Battery monitoring device

Abstract

To provide a switched capacitor amplifier and a battery monitoring device that uses a telescopic type fully differential amplifier to significantly reduce output errors caused by common mode noise and achieve a high CMRR.SOLUTION: A telescopic type fully differential amplifier 14b includes an input portion 20 including input a transistor M1-M2. A bias generating portion 21 generates a bias Vbn1. A cascode portion 22 is cascode-connected to the input portion 20 of the fully differential amplifier 14b and applies the bias Vbn1 to the cascode portion 22. The bias generating section 21 generates the bias Vbn1 so as to depend on the source potentials of the input transistor M1-M2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention electric Regarding pond monitoring equipment. [Background technology]

[0002] Conventionally, the applicant has proposed a battery monitoring device as shown in Patent Document 1. According to the technology described in Patent Document 1, the voltage detection device is composed of an RC filter, a multiplexer, a differential switched capacitor amplifier comprising a sampling capacitor and a feedback capacitor, and an AD converter. The battery monitoring device receives input from multiple battery voltages switched by a multiplexer and detects them using a set of differential switched capacitor amplifiers and an AD converter. This makes it possible to reduce the size and power consumption. Because battery voltages have a lot of noise, an RC filter with a cutoff frequency set to a low frequency is placed at the input of the battery monitoring device.

[0003] Some switched-capacitor differential amplifier circuits are equipped with a leak cancellation circuit. The leak cancellation circuit is provided to improve the accuracy of voltage detection by canceling errors caused by the leakage current flowing through the sampling capacitance and the voltage drop determined by the resistance value of the RC filter during the operation of the switched-capacitor amplifier. Conventionally, for the purpose of miniaturization, the leak cancellation circuit is provided as a buffer amplifier on only one side of the differential amplifier circuit. In such a configuration where the leak cancellation circuit is differentially asymmetric, the CMRR deteriorates, and the accuracy deteriorates. CMRR is an abbreviation for Common Mode Rejection Ratio. Common mode noise is superimposed on the input voltage of the differential amplifier circuit, and the detection accuracy deteriorates. For example, when used for battery monitoring, the common mode noise is large and this problem is particularly noticeable. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 10429447 [Overview of the project] [Problems that the invention aims to solve]

[0005] While employing a typical folded cascode amplifier or a two-stage amplifier configuration allows for a wider tolerance range for the input common-mode voltage, it results in higher power consumption. Furthermore, when using a telescopic amplifier, which consumes relatively little power, there are concerns that impedance mismatch of the input transistors or fluctuations in the input common-mode voltage can cause the bias state to move outside the input transistor's saturation region, leading to degraded linearity.

[0006] If the input common-mode noise exceeds the allowable range of the amplifier's input common-mode voltage, the amplifier's gain decreases, leading to larger errors. This problem becomes particularly pronounced when common-mode noise is high, especially in applications such as battery monitoring.

[0007] The objective of the present invention is to significantly reduce output errors due to common-mode noise and achieve a high CMRR using a telescopic all-differential amplifier. taden The objective is to provide a pond monitoring device. [Means for solving the problem]

[0008] The invention described in claim 1 relates to a switched-capacitor amplifier equipped with a fully differential amplifier circuit. The telescopic fully differential amplifier includes an input section containing an input transistor. A bias generation section generates a bias. A cascode section is cascode-connected to the input section of the fully differential amplifier and a bias is applied to it. The bias generation section generates the bias applied to the cascode section so as to depend on the source potential of the input transistor. With this configuration, the bias state can be configured without deviating from the saturation region of the input transistor, and good linearity can be maintained. 。 A chopper switch is further provided on the input side of the input section of the fully differential amplifier. Chop Switch On the input side of ...leaks from the battery pack through the multiplexer to the input of the fully differential amplifier. It is configured by connecting a leakage canceling circuit that cancels leakage current. The leakage canceling circuit To create a compensation current A DA converter that inputs a digital command value and differentially outputs a command voltage, two single-ended buffers that input the differential output of the DA converter, and switches the outputs of the two buffers to Leak cancellation Charge and discharge a capacitor and output Leak cancellation A switch, and by switching the chopper switch sampling A sampling period for sampling the capacitor, sampling The hold period for inputting the holding voltage of the capacitor to the differential input terminal of the fully differential amplifier is switched Replace It is configured. The leakage canceling circuit This mechanism is designed to improve the accuracy of voltage detection by canceling errors caused by leakage current flowing through the sampling capacitor during the operation of a switched-capacitor amplifier. It cancels the leakage current by supplying a compensation current to the input of the entire differential amplifier via a chop switch. During both the sampling period and the hold period Cancel leakage current So as to During the sample and hold periods, the leak cancellation switch is toggled to activate the leak cancellation capacitor. By applying charge to A compensatory current is applied. As a result, the output error due to common-mode noise is significantly reduced when using a telescopic all-differential amplifier, enabling a high CMRR and thus achieving excellent characteristics.

Brief Description of Drawings

[0009] [Figure 1] Electrical configuration diagram schematically showing a battery monitoring device according to an embodiment [Figure 2] Circuit configuration example of a fully differential amplifier circuit according to an embodiment [Figure 3] Circuit configuration example of a fully differential amplifier circuit showing a comparative example [Figure 4] Electrical configuration diagram 1 of a leakage canceling circuit according to an embodiment [Figure 5] Electrical configuration diagram 2 of a leakage canceling circuit according to an embodiment [Figure 6] Diagram schematically showing the sample / hold signal and the operating state of the leakage canceling circuit in an embodiment [Figure 7] Diagram schematically showing the flow of charge during leakage cancellation in the hold period of an embodiment [Figure 8] Diagram schematically showing the flow of charge during leakage cancellation in the sampling period of an embodiment

Best Mode for Carrying Out the Invention

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The battery monitoring device 1 shown in FIG. 1 monitors a battery pack 4 or the like mounted on a vehicle, and is constituted by, for example, an ASIC. The battery pack 4 is a plurality of battery cells 4a, 4b,... which are secondary batteries such as lithium ion batteries, and are connected in series in multiple stages. Therefore, a common mode voltage is superimposed on the plurality of battery cells 4a, 4b,....

[0011] The common mode voltage becomes higher as the battery cell 4a connected to the upper stage side, that is, the high potential side of the battery pack 4 is higher. In FIG. 1 and the like, only two battery cells 4a, 4b and the corresponding configuration are shown. The negative terminal P9 of the battery cell (not shown) provided at the lowermost stage, that is, the lowermost potential side of the battery pack 4 is connected to the ground line Lg. The battery monitoring device 1 has a function of detecting and voltage-amplifying the voltage between each terminal of the battery pack 4, that is, the battery cells 4a, 4b. The battery monitoring device 1 also has a function of detecting the current flowing through the battery cells 4a, 4b.

[0012] The battery monitoring device 1 includes terminals P1, P2 corresponding to each terminal of the battery cell 4a, terminals P3, P4 corresponding to each terminal of the battery cell 4b, and a terminal P9 for supplying a ground potential (0 V).

[0013] Between each terminal of the battery cell 4a and the terminals P1, P2, they are connected via a filter 3a. The filter 3a is an RC filter and includes resistors R1, R2 and a capacitor C1. Between each terminal of the battery cell 4b and the terminals P3, P4, they are connected via a filter 3b. The filter 3b is an RC filter configured similarly to the filter 3a or the like, and includes resistors R3, R and a capacitor C2. The terminal P9 is configured as the negative terminal of the lowermost potential battery cell (not shown) to which the ground line Lg is connected.

[0014] The battery monitoring device 1 comprises a leak cancellation circuit 5, a control circuit 13, an integrator 14a, a subtractor 15, a DA converter 16, and an AD converter 17, all of which are configured using a switched-capacitor type fully differential amplifier circuit 14. The control circuit 13 is configured using a predetermined logic circuit. Figure 1 mainly illustrates the components of the switched-capacitor amplifier 18 according to the present invention. For this reason, the digital circuit downstream of the AD converter 17 is omitted from Figure 1.

[0015] The multiplexer MUX selects one of the voltages from terminals P1 and P2, terminals P3 and P4, etc., and outputs it to the next stage by switching switches S1, S2, S3, S4, etc. on and off. The differential analog signal selected by the multiplexer MUX is input to the integrator 14a via the subtractor 15.

[0016] The integrator 14a receives a differential analog signal, integrates it, and outputs an integrated voltage corresponding to the stored charge in capacitors C11 to C16 to the higher-level AD converter 17. When the AD converter 17 receives the integrated voltage as input, it quantizes it into multiple levels and outputs it digitally. The digital output undergoes predetermined digital processing and is output digitally again, and is also input to the DA converter 16.

[0017] The DA converter 16 converts the digital output of the AD converter 17 into an analog signal and feeds the converted output VR back into the subtractor 15. The subtractor 15 subtracts the converted output VR from the input differential analog signal and feeds the result into the integrator 14a. The integrator 14a integrates the difference signal input from the subtractor 15 and outputs it to the AD converter 17, which then quantizes the integrated output and outputs it digitally.

[0018] The fully differential amplifier circuit 14 includes a fully differential amplifier 14b with differential output, and also includes capacitors C11-C18 and switches S11-S30 as a switched capacitor block to form an integrator 14a. The fully differential amplifier circuit 14 receives two voltage outputs from the multiplexer MUX as input.

[0019] The two output voltages of the multiplexer MUX can be switched between forward and reversed inputs to nodes Np and Nm by the control circuit 13, which controls chop switches S7a, S7b, S7c, and S7d. The voltages at nodes Np and Nm are referred to as input voltages Vip and Vim.

[0020] The input voltages Vip and Vim can be switched between forward and inverted input to the sampling capacitance capacitors C11 and C12 by the control circuit 13, which controls the chop switches S12a, S12b, S12c, and S12d.

[0021] The fully differential amplifier circuit 14 samples the input voltages Vip and Vim using capacitors C11 and C12, and transfers the sampled charge via capacitors C13 to C16, which correspond to the feedback capacitance. The fully differential amplifier circuit 14 is a differential sample-and-hold circuit that outputs a detection voltage corresponding to the input voltages Vip and Vim. The fully differential amplifier circuit 14 also performs level shifting, stepping down a high common-mode voltage to a low reference voltage Vcm. Furthermore, the fully differential amplifier circuit 14 has a configuration that allows switching of its amplification factor (gain).

[0022] The common voltage of the fully differential amplifier 14b is set to be equal to the reference voltage Vcm, which serves as the reference for voltage detection. The reference voltage Vcm is the intermediate voltage (e.g., +2.5V) of the power supply voltages (e.g., +5V) of each circuit. The fully differential amplifier 14b outputs output voltages Vop and Vom from its inverting output terminal and non-inverting output terminal, respectively.

[0023] The output voltages Vop and Vom correspond to the detection voltages corresponding to the input voltages Vip and Vim, and are converted into digital data by the differential input type AD converter 17. This digital data represents the detection values ​​of the input voltages Vip and Vim and is acquired by a higher-level control device (not shown). The fully differential amplifier circuit 14 is configured to apply an offset so that the output voltages Vop and Vom fall within the input voltage range of the AD converter 17 (for example, +2.5V to -2.5V).

[0024] <Example of circuit configuration for the fully differential amplifier 14b> The fully differential amplifier circuit 14 includes a low-power fully differential amplifier 14b. As shown in Figure 2, the fully differential amplifier 14b is configured as shown by connecting a cascode section 22, an input section 20 including differential input transistors M1-M2, and a MOS transistor M9 between the power supply and ground. The fully differential amplifier 14b is also configured as a telescopic type with two pairs of MOS transistors M5-M6 and M7-M8 connected as an active load 23 between the power supply and output terminals. The gates of the two pairs of MOS transistors M5-M6 and M7-M8 are connected in common, and appropriate predetermined bias voltages Vbp2 and Vbp1 are applied to the common-connected gates, respectively.

[0025] The sources of input transistors M1 and M2 are connected in common and are connected to a bias generation unit 21 that generates a predetermined bias. As shown in Figure 2, the bias generation unit 21 is configured by connecting the drain and source of a current source CI1, a diode-connected n-channel MOS transistor M11, and an n-channel MOS transistor M10 in series. The same bias voltage Vbn2 is applied to the gates of MOS transistors M9 and M10.

[0026] The current source CI1 applies a predetermined current to the drain of MOS transistor M11, thereby generating a bias voltage Vbn1 at the common connection point of MOS transistors M11 and M9 and M10. This bias voltage Vbn1 is then supplied to the sources of the differential input transistors M1-M2.

[0027] The fully differential amplifier 14b includes a cascode section 22 connected to input transistors M1 and M2. The cascode section 22 is configured between the input section 20 and the active load 23, and its output has a high output impedance.

[0028] The cascode section 22 is composed of MOS transistors M3-M4 that are cascode-connected to the differential input transistors M1-M2. The gates of MOS transistors M3 and M4 are connected in common, and the aforementioned bias voltage Vbn1 is also applied to this common gate.

[0029] Here, the bias voltage Vbn1 of the gates of the MOS transistors M3-M4 in the cascode section 22 is shown to be set to the same potential as the bias voltage Vbn1 applied to the source potential of the input transistors M1-M2, but this is not limited to this configuration. It is preferable that the potential depends on the source potential of the input transistors M1-M2. That is, it should change in the same way as the source potential of the input transistors M1-M2.

[0030] In this configuration, the bias generation unit 21 generates the bias voltage Vbn1 by providing a diode-connected MOS transistor M11. Therefore, the threshold voltage V of the input transistors M1-M2 t、M1 or common-mode voltage V in,cm A bias voltage Vbn1 that depends on can be generated.

[0031] The circuit will be described below along with the relationship between the voltages at each node. The input common-mode voltage when no differential signal is input is V. in,cm (Equivalent to VCMIN). The total differential amplifier circuit 14 has a change ΔV due to input impedance mismatch. t,M1 Even if it exists, the input common-mode voltage V in,cm It is necessary to operate so that it falls within the lower and upper limits. The change due to input impedance mismatch ΔV t,M1 There exists an input common-mode voltage V in,cm This is because fluctuations cause the bias state to move outside the saturation region of input transistors M1-M2, resulting in a deterioration of linearity.

[0032] <Comparative Example> For example, a circuit without a bias generation unit 21 composed of a current source CI1, MOS transistors M11, and M10 is shown in FIG. 3 as a comparative example. In the case of the configuration of FIG. 3, a bias generation unit 121 is provided instead of the bias generation unit 21. The bias generation unit 121 includes a current source CI1 and a diode-connected MOS transistor M111, and generates the voltage at the common connection point of the current source CI1 and the MOS transistor M111 as a predetermined bias voltage Vbn1. According to the configuration shown in FIG. 3, the bias voltage Vbn1 is not applied to the gates of the MOS transistors M3 and M4 in a form that depends on the source potential of the MOS transistor M111. When a predetermined bias voltage Vbn1 is applied to the gates of the MOS transistors M3 and M4 as in the configuration of FIG. 3, the lower and upper limit conditions of the input common-mode voltage V in,cm change depending on the change ΔV t,M1 due to the mismatch of the input impedance. Let the threshold voltage of the MOS transistor M111 be V t,M111 , and the overdrive voltage be V od,M111 . In this case, the bias voltage Vbn1 is determined by the threshold voltage V t,M111 + the overdrive voltage V od,M111 . When the input impedance is mismatched, the allowable range of the input common-mode voltage V in,cm becomes narrower accordingly.

[0033] <In the case of the configuration of the present embodiment> On the other hand, consider the case where the bias generation unit 21 is provided as in the present embodiment. When the bias generation unit 21 is provided, a bias voltage Vbn1 that depends on the source potential of the MOS transistor M11 can be applied to the gates of the MOS transistors M3 and M4. In this case, the drain potential of the input transistors M1 - M2 is the potential obtained by subtracting (the overdrive voltage V od、M3 + the threshold voltage V t、M3 ) of the MOS transistors M3 and M4 from the bias voltage Vbn1. Also, the source potential of the input transistors M1 - M2 is the potential obtained by subtracting (the overdrive voltage V od、M11 + the threshold voltage V t、M11This results in a potential obtained by subtracting (). From this, both the drain potential and source potential of input transistors M1-M2 change depending on the bias voltage Vbn1.

[0034] If the input voltages Vinp and Vinm are adjusted so that input transistors M1-M2 operate in the saturation region, the change due to input impedance mismatch ΔV t,M1 It will change stably with almost no dependence on it.

[0035] According to this embodiment, a bias voltage Vbn1 dependent on the source potential of input transistors M1-M2 is applied to the gates of MOS transistors M3-M4 in the cascode section 22. As a result, the common-mode voltage V is input to the fully differential amplifier 14b. in,cm It is possible to obtain a robust output that can handle such fluctuations without being dependent on those fluctuations.

[0036] This fully differential amplifier 14b is used as a fully differential amplification circuit 14 that acts as a switched-capacitor amplifier. The common-mode voltage V transiently occurs due to the sample / hold operation of the switched-capacitor. in,cm Even when the bias fluctuates, the bias state of the input section 20 of the fully differential amplifier 14b can be maintained in the saturation region. As a result, the bias state can be configured without deviating from the saturation region of input transistors M1-M2. Linearity can be maintained well, and operation can be performed with high precision and high speed.

[0037] <Explanation of the peripheral configuration of the 14b differential amplifier> As shown in Figure 1, a pair of capacitors C11 and C12 are provided at the differential input of the fully differential amplifier 14b. Capacitors C11 and C12 have the same capacitance value Cs. In this specification, "same capacitance value" includes not only capacitors with perfectly identical capacitance values, but also capacitors with slight differences in capacitance values ​​that are not strictly identical, as long as they achieve the desired effect.

[0038] One terminal of capacitors C11 and C12 is connected to the side of the multiplexer MUX. The other terminal of capacitors C11 and C12 is connected to the non-inverting input terminal and the inverting input terminal of the differential amplifier 14b. Switches S12e and S12f are connected in series between the non-inverting input terminal and the inverting input terminal of the differential amplifier 14b, and the common connection point of switches S12e and S12f is connected to the input common-mode potential line LIN (for example, the input common-mode potential VCMIN = 2.1V).

[0039] The paired feedback capacitors C13 and C14 have the same capacitance value Cf. Also, the paired capacitors C15 and C16 in the differential configuration have the same capacitance value Cf2. Capacitor C13 is connected in series between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 14b. Capacitor C14 is connected in series between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier 14b.

[0040] One terminal of capacitor C15 is connected to the non-inverting input terminal of the all-differential amplifier 14b via switch S17, and also to the input common-mode potential line LIN (for example, input common-mode potential VCMIN = 2.1V) via switch S18. The other terminal of capacitor C15 is connected to the inverting output terminal of the all-differential amplifier 14b via switch S19, and also to the output common-mode potential line LO (for example, output common-mode potential VCMO = 2.5V) via switch S20.

[0041] One terminal of capacitor C16 is connected to the inverting input terminal of the all-differential amplifier 14b via switch S21, and also to the input common-mode potential line LIN (for example, input common-mode potential VCMIN = 2.1V) via switch S22. The other terminal of capacitor C16 is connected to the non-inverting output terminal of the all-differential amplifier 14b via switch S23, and also to the output common-mode potential line LO (for example, output common-mode potential VCMO = 2.5V) via switch S24. The input common-mode potential line LIN and the output common-mode potential line LO are at different potentials from each other.

[0042] In this configuration, when switches S17, S19, S21, and S23 are off, capacitor C13 is connected between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 14b. Also, capacitor C14 is connected between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier 14b. In this case, the capacitance value of the feedback capacitance is the capacitance value Cf of capacitors C13 and C14.

[0043] In contrast, when switches S17, S19, S21, and S23 are ON, capacitors C13 and C15 are connected in parallel between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 14b. Capacitors C14 and C16 are connected in parallel between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier 14b. In this case, the capacitance value of the feedback capacitance is the capacitance value Cf of capacitors C13 and C14 plus the capacitance value Cf2 of capacitors C15 and C16 (=Cf+Cf2).

[0044] In this embodiment, a feedback capacitance switching unit is configured to switch the capacitance value of the feedback capacitance using switches S17, S19, S21, and S23. In this case, the feedback capacitance switching unit increases the capacitance value of the feedback capacitance when switches S17, S19, S21, and S23 are switched from off to on. The amplification factor of the differential amplifier circuit 14 changes according to the capacitance value of the feedback capacitance. Therefore, in this embodiment, the differential amplifier circuit 14 is configured to have a switchable amplification factor by switching the capacitance value using the feedback capacitance switching unit.

[0045] On the other hand, the DA converter 16 receives the digital output value from the AD converter 17. The DA converter 16 switches switches S25 to S30 on and off based on the control of the control circuit 13. The DA converter 16 inputs the converted output VR, which corresponds to the digital processing of the digital output of the AD converter 17, as a reference voltage (one of Vrp, Vcm, or Vrm) to the capacitors C17 and C18, which become the DAC capacitance. The converted output VR corresponds to the analog voltage obtained by D / A conversion processing of the output value of the AD converter 17, and has a relationship such as Vrp > Vcm > Vrm.

[0046] One terminal of capacitor C17 is connected to one terminal of capacitor C15. The other terminal of capacitor C17 can be used to apply a reference voltage Vrp (e.g., +5V) via switch S25, a reference voltage Vcm via switch S26, and a reference voltage Vrm (e.g., 0V) via switch S27.

[0047] One terminal of capacitor C18 is connected to one terminal of capacitor C16. The other terminal of capacitor C18 can be used to apply a reference voltage Vrp via switch S28, a reference voltage Vcm via switch S29, and a reference voltage Vrm via switch S30.

[0048] In the above configuration, capacitors C11 and C12, and the circuit elements arranged on the battery pack 4 side of capacitors C11 and C12, are subjected to a high common-mode voltage superimposed on battery cells 4a to 4c. For this reason, capacitors C11 and C12 and the circuit elements on the battery pack 4 side use high-voltage components capable of withstanding this voltage. Other circuit elements use low-voltage components. In this embodiment, at least capacitors C11 and C12 are composed of inter-wiring capacitance, thereby achieving high voltage resistance.

[0049] When detecting the terminal voltage of battery cell 4a or 4b, the control circuit 13 controls the operation of the multiplexer MUX to output the terminal voltage of each battery cell 4a or 4b, and controls the amplification operation of the differential amplifier circuit 14 to switch the amplification ratio to a predetermined amplification ratio. Furthermore, at this time, the control circuit 13 controls the amplification operation of the differential amplifier circuit 14 to apply an offset.

[0050] Furthermore, the control circuit 13 controls the amplification operation of the fully differential amplifier circuit 14 so that sampling is performed twice for each voltage detection. That is, in one of the two samplings, the control circuit 13 samples the input voltage Vip using capacitor C11 and the input voltage Vim using capacitor C12. In this way, the control circuit 13 controls the amplification operation of the multiplexer MUX and the fully differential amplifier circuit 14.

[0051] Furthermore, in the other of the two samplings, the control circuit 13 samples the input voltage Vip using capacitor C12 and the input voltage Vim using capacitor C11. This allows the control circuit 13 to control the amplification operation of the multiplexer MUX and the fully differential amplifier circuit 14. With this configuration, the control circuit 13 can cancel the offset that occurs in the fully differential amplifier circuit 14 when detecting terminal voltages between battery cells 4a, 4b, etc., by switching the switch on or off according to predetermined rules.

[0052] <Explanation of the Leak Cancellation Circuit 5 Configuration> Next, an example configuration of the leakage cancellation circuit 5 shown in Figure 1 will be explained with reference to Figures 4 and 5. In this configuration, chop switches S12a to S12d are provided on the input side of the fully differential amplifier 14b. Since these chop switches S12a to S12d, together with capacitors C11 and C12, constitute an RC filter, the input impedance of the fully differential amplifier 14b is increased. Therefore, it becomes susceptible to the influence of leakage current flowing in from the multiplexer MUX side, and thus the leakage cancellation circuit 5 is provided.

[0053] The leak cancellation circuit 5 is connected to the input nodes of the input voltages Vip and Vim of the fully differential amplifier circuit 14. The leak cancellation circuit 5 is constructed by connecting the switched capacitor blocks 8 and 9 shown in Figures 4 and 5 in parallel with the DA converter 6 and amplifier 7.

[0054] As shown in Figure 4, the leak cancellation circuit 5 comprises a DA converter 6, an amplifier 7, and switched capacitor blocks 8 and 9 as voltage generation circuits. The DA converter 6 is configured to receive a digital command value for creating a compensation current, convert it to an analog signal, output two command voltages, and input them to the amplifier 7.

[0055] The DA converter 6 is configured as a fully differential DAC. A fully differential DAC outputs two command voltages: a first voltage that is directly proportional to the digital command value with a positive slope, and a second voltage that is directly proportional to the digital command value with a negative slope. The DA converter 6 may also be configured as a pseudo-differential DAC. A pseudo-differential DAC outputs two command voltages: a first voltage that is constant regardless of the digital command value, and a second voltage that is directly proportional to the digital command value.

[0056] Amplifier 7 consists of two single-ended buffers 7a and 7b, each configured as a voltage follower. Amplifier 7 receives the outputs of two command voltages from the DA converter 6, performs impedance conversion using the voltage followers, and outputs voltages Vdp and Vdm, respectively.

[0057] As shown in Figures 4 and 5, the switched-capacitor blocks 8 and 9 are configured to switch the outputs of two buffers 7a and 7b to charge and discharge capacitors C8a, C8b, C9a, and C9b and output the result, and they have the same configuration. Therefore, we will mainly describe the configuration of switched-capacitor block 8. In addition, each component of switched-capacitor blocks 8 and 9 is given the same reference numerals for the switches S8 and S9 and the capacitors C8 and C9, and the corresponding components are indicated by subscripts a, b, c, d, aa, ba, ca, da, etc.

[0058] As shown in Figure 5, the switched-capacitor block 8 comprises switches S8a to S8d, capacitors C8a and C8b, and switches S8aa, S8ba, S8ca, and S8da. The switched-capacitor block 9 comprises switches S9a to S9d, capacitors C9a and C9b, and switches S9aa, S9ba, S9ca, and S9da.

[0059] Switches S8a to S8d receive voltages Vdp and Vdm and, based on the control of the control circuit 13, switch between straight and cross connections to energize capacitors C8a and C8b. Similarly, switches S9a to S9d receive voltages Vdp and Vdm and, based on the control of the control circuit 13, switch between straight and cross connections to energize capacitors C9a and C9b.

[0060] Furthermore, the control circuit 13 can switch the energizing paths of capacitors C8a and C8b to closed paths by turning on switches S8ca and S8da and turning off switches S8aa and S8ba. The control circuit 13 can switch the energizing paths of the outputs of capacitors C8a and C8b to the input voltage Vip and Vim node sides by turning off switches S8ca and S8da and turning on switches S8aa and S8ba.

[0061] Furthermore, the control circuit 13 can switch the energizing paths of capacitors C9a and C9b to closed paths by turning on switches S9ca and S9da and turning off switches S9aa and S9ba. The control circuit 13 can switch the energizing paths of the outputs of capacitors C9a and C9b to the input voltage Vip and Vim node sides by turning off switches S9ca and S9da and turning on switches S9aa and S9ba.

[0062] <Operation of Leak Cancellation Circuit 5> Next, we will explain the leak cancellation by the leak cancellation circuit 5. Figure 6 shows the operating states of the switched capacitor blocks 8 and 9 during the hold period and sample period, respectively. In this configuration, the leak cancellation circuit 5 is designed to cancel the effect of offset caused by leakage current flowing in from the multiplexer MUX side during the hold period shown in Figure 7 and the sample period shown in Figure 8.

[0063] The control circuit 13 switches switches S8a~S8d, S9a~S9d, S8aa, S8ba, S8ca, S8da, S9aa, S9ba, S9ca, S9da, and S12a~S12f on or off. This results in the connection shown in Figure 7 for the hold period and Figure 8 for the sample period. During the sample period, the chop switches 12a~12d are switched to sample the voltages of capacitors C11 and C12. During the hold period, the holding voltages of capacitors C11 and C12 are input to the differential input terminals of the differential amplifier 14b.

[0064] Switched capacitor blocks 8 and 9 repeat their operation during the hold and sample periods. The integrator 14a outputs an integrated voltage, and the AD converter 17 performs AD conversion. The control circuit 13 alternately operates the two switched capacitor blocks 8 and 9 during correlated double sampling. As a result, the leakage cancellation circuit 5 cancels the leakage current by supplying a compensation current during both the hold and sample periods.

[0065] In the steady state during the hold period shown in Figure 7, capacitors C8a and C8b hold charge based on the voltages Vdp and Vdm of the switched capacitor block 8, and the intermediate potential (Vip + Vim) / 2 of the differential input terminals of the fully differential amplifier 14b into which the leakage current flows.

[0066] At this time, the non-inverting and inverting input terminals of the differential amplifier 14b are connected to be short-circuited when switches 12e and 12f are turned on. The differential input terminals of the differential amplifier 14b are each held at the input common-mode potential VCMIN. During the hold period shown in Figure 7, the switched capacitor block 9, conversely, flows a current based on the charge Qlc through capacitors C9a and C9b to the input side of the differential amplifier 14b. This cancels the charge Qsh caused by the leakage current flowing during the hold period.

[0067] Furthermore, in the steady state of the sampling period shown in Figure 8, capacitors C9a and C9b hold charges based on the voltages Vdp and Vdm, and the intermediate potential (Vip + Vim) / 2 of the differential input terminals into which the leakage current flows. Also, the non-inverting and inverting input terminals of the full differential amplifier 14b are open, creating an imaginary short circuit. Conversely, during the sampling period shown in Figure 8, the switched capacitor block 8 flows a current based on the charge Qlc through capacitors C8a and C8b to the input side of the full differential amplifier 14b, canceling the charge Qsh caused by the leakage current flowing during the sampling period.

[0068] When the sampling capacitance is constant, using a MOS transistor with a low threshold voltage Vt allows for a larger leakage cancellation voltage ΔVd relative to the input voltage ΔVi, enabling the use of a smaller capacitance value for leakage cancellation. Reducing the value of the leakage cancellation capacitance allows for a reduction in circuit area.

[0069] According to this embodiment, the leak cancellation circuit 5 generates a compensation current by performing correlated double sampling based on the command voltage from the DA converter 6, so that the leak current can be canceled during the hold period and sample period when correlated double sampling is performed.

[0070] <Summary of this embodiment> The objectives, problems, and technical significance of this embodiment will be described below. <Purpose and problems of this embodiment> In telescopic amplifiers, impedance mismatch between input transistors M1 and M2, or input common-mode fluctuations, can cause the bias state of input transistors M1 and M2 to move outside the saturation region, resulting in poor linearity. While employing folded cascode or two-stage amplifiers widens the tolerance range for input common-mode voltage, it tends to increase power consumption.

[0071] When using a fully differential amplifier 14b in a switched-capacitor type fully differential amplifier circuit 14, if common-mode noise is introduced into the input, the input common-mode voltage of the fully differential amplifier 14b may fluctuate, potentially exceeding the allowable range of the input common-mode voltage. Exceeding the allowable range reduces the gain of the fully differential amplifier 14b, resulting in a larger error. This problem is particularly pronounced when used as a battery monitoring device 1, where common-mode noise is high.

[0072] <Technical significance of this embodiment> According to this embodiment, the bias voltage Vbn1 is applied to the gates of the MOS transistors M3-M4 of the cascode section 22, and this bias voltage Vbn1 changes depending on the source potential of the input transistors M1-M2. Therefore, a robust output can be obtained in response to fluctuations in the reference voltage Vcm input to the fully differential amplifier 14b.

[0073] When this fully differential amplifier 14b is used in a switched-capacitor type fully differential amplifier circuit 14, even if the reference voltage Vcm on the input side of the fully differential amplifier 14b transiently fluctuates due to the sample / hold operation described above, the operating state of the input transistors M1-M2 based on the state of the bias voltage Vbn1 can be maintained in the saturation region. As a result, it can be operated with high precision and high speed.

[0074] In this embodiment, the battery monitoring device 1 is equipped with chop switches S12a to S12d on the input side of the fully differential amplifier 14b. The chop switches S12a to S12d and capacitors C11 and C12 act as an RC filter when the voltage of the battery pack 4 is input. As a result, the input impedance of the fully differential amplifier 14b becomes high in the region of cutoff frequency 1kHz or lower. When the input impedance is high, it becomes more susceptible to the influence of leakage current leaking from the multiplexer MUX side.

[0075] Therefore, it is desirable to provide a separate leak cancellation circuit 5, as in this embodiment. The leak cancellation circuit 5 is also configured as a fully differential type, and is composed of an amplifier 7 consisting of a DA converter 6 and two single-ended buffers 7a and 7b. Therefore, even if the input impedance is high, the effect of leakage current can be suppressed.

[0076] When the leak cancellation circuit 5 is operating, common-mode noise is applied to the input of the all-differential amplifier 14b. Even in this case, by applying the configuration of the all-differential amplifier 14b of this embodiment, accuracy is not degraded, and a low-power, high-precision switched-capacitor type all-differential amplifier circuit 14 can be constructed. This allows for the construction of a switched-capacitor amplifier with a high CMRR.

[0077] This disclosure has been written in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure. [Explanation of Symbols]

[0078] In the diagram, 4 is a battery pack, 4a and 4b are battery cells, 5 is a leak cancellation circuit, 6 is a DA converter, 7a and 7b are buffers, C8aa, C8ba, C9aa, and C9ba are capacitors, S8a to S8d, S8aa to S8da, S9a to S9d, and S9aa to S9da are switches, 12a to 12d are chop switches, 14 is a fully differential amplifier circuit, M1 and M2 are input transistors, 20 is the input section, 21 is the bias generation section, and 22 is the cascode section.

Claims

1. A battery monitoring device (1) equipped with a switched-capacitor amplifier, used for monitoring the state of a battery pack (4) made up of battery cells (4a, 4b), A switched-capacitor amplifier is, A telescopic all-differential amplifier (14b) having an input section (20) including input transistors (M1, M2), and an all-differential amplifier circuit (14) having sampling capacitors (C11, C12) and a switched capacitor including a switch for switching the sampling capacitors, A bias generation unit (21) that generates a bias (Vbn1), The cascode section (22) is connected in cascode to the input of the all-differential amplifier and to which the bias is applied, The bias generation unit generates the bias applied to the cascode section in such a way that it depends on the source potential of the input transistor. The input side of the input section of the aforementioned fully differential amplifier is further equipped with chop switches (12a to 12d). It is configured by connecting a leakage cancellation circuit (5) to the input side of the chop switch and canceling the leakage current that leaks from the battery pack to the input section of the all-differential amplifier via the multiplexer, The aforementioned leak cancellation circuit is A DA converter (6) takes a digital command value as input to create a compensation current and outputs a command voltage differentially, Two single-ended buffers (7a, 7b) receive the differential output of the aforementioned DA converter, A leak cancellation switch (S8a-S8d, S8aa-S8da, S9a-S9d, S9aa-S9da) switches the outputs of the two buffers to charge and discharge the leak cancellation capacitors (C8a, C8b, C9a, C9b) and outputs the result, Equipped with, The configuration is such that by switching the chop switch, the sampling period for sampling with the sampling capacitors (C11, C12) and the hold period for inputting the holding voltage of the sampling capacitors to the differential input terminals of the differential amplifier are switched. The aforementioned leak cancellation circuit is This device is provided to cancel errors based on the leakage current flowing through the sampling capacitor during the operation of the switched-capacitor amplifier and to improve the accuracy of voltage detection, and cancels the leakage current by supplying the compensation current to the input of the full differential amplifier through the chop switch. A battery monitoring device that generates the compensation current by switching the leak cancellation switch during the sample period and the hold period to apply charge to the leak cancellation capacitor, thereby canceling the leakage current during either the sample period or the hold period.

2. The battery monitoring device according to claim 1, wherein the switched-capacitor amplifier is used to amplify the voltage between the terminals of the battery cells of the battery pack.

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