Display panel and method for manufacturing the same

Abstract

The display panel includes a substrate, buffer layer, semiconductor layer, gate insulation layer, gate, common wiring, interlayer insulation layer, pixel electrode, source, drain, passivation layer, and common electrode. A first through-hole is provided, penetrating the interlayer insulation layer and exposing the common wiring. A second through-hole is provided in the passivation layer at a position corresponding to the first through-hole and is sleeve-connected to the first through-hole. The display panel further includes a metal pad provided within the first through-hole, provided on the same layer as the source and drain, provided on the bottom and side walls of the first through-hole and around the opening of the first through-hole, and in contact with the common wiring. The second through-hole exposes a portion of the metal pad, and the common electrode is in contact with the metal pad through the second through-hole. [Effect] By adding a metal pad between the passivation layer and the sleeve connection hole of the interlayer insulation layer, the yield of display panels was improved.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application with application number 202510839555.3 filed with the Chinese Patent Office on June 20, 2025, and incorporates by reference all the content described in that application.

[0002] This application relates to the field of display technologies, and more particularly to display panels and methods for manufacturing the same.

Background Art

[0003] Low temperature poly-silicon (LTPS) thin film transistors (TFTs) are important components of display panels such as liquid crystal display (LCD) panels and organic light-emitting diode (OLED) display panels. In order to reduce manufacturing costs and product costs, the industry has always been striving to simplify the process.

[0004] Currently, nine mask processes are usually used in the manufacture of display panels. This process is mature and reliable, but it has relatively many process steps and relatively high manufacturing costs. In order to simplify the process flow and reduce costs, a six-mask process has been proposed in the industry. This process omits the manufacturing process of the light-shielding layer and the manufacturing process of the planarization layer, and uses a halftone mask technology to form the pixel electrode and the interlayer insulating layer in the same process, thereby saving the number of photomasks.

[0005] In the six-mask process, in order to make the common voltage in the display panel more uniform, usually, a common wiring installed in the same layer as the gate is used to provide a common voltage signal to the common electrode. However, since there may be a situation where the common wiring and the common electrode cannot be normally connected, this technical problem has reduced the yield of display panel products.

[0006] Therefore, in order to solve the above technical challenges, it is necessary to submit a new technical proposal. [Overview of the project] [Problems that the invention aims to solve]

[0007] The objective of the embodiments of this application is to provide a display panel and a method for manufacturing the same, thereby improving the yield of the display panel. [Means for solving the problem]

[0008] Embodiments of the present application provide a display panel, the display panel comprising: a gate; common wiring located in the same film layer as the gate; an interlayer insulating layer installed on the gate, wherein a first through-hole is provided in the interlayer insulating layer, the first through-hole penetrates the interlayer insulating layer and exposes at least a portion of the common wiring; a pixel electrode, a source and a drain installed on the interlayer insulating layer; a passivation layer installed on the source, the drain, the pixel electrode and the interlayer insulating layer, wherein a second through-hole is provided in the passivation layer at a position corresponding to the first through-hole, and the second through-hole is sleeve-connected to the first through-hole; a common electrode installed on the passivation layer; and a metal pad installed in the first through-hole, located in the same film layer as the source and the drain, and installed on the bottom surface and side wall of the first through-hole and around the opening of the first through-hole, and in contact with the common wiring. Here, the second through-hole exposes a portion of the metal pad, and the common electrode contacts the metal pad through the second through-hole.

[0009] In the display panel, the display panel further includes an annular metal member, the annular metal member being installed around the opening of the first through-hole, surrounding the opening of the first through-hole, and installed on the interlayer insulating layer, and the portion of the metal pad located outside the first through-hole being installed on the annular metal member.

[0010] In the display panel, the ratio of the area of ​​the annular metal member to the area of ​​the portion of the metal pad located outside the first through-hole is less than 1.

[0011] In the display panel, the inner edge of the annular metal member is flush with the edge of the opening of the first through-hole.

[0012] In the display panel, the annular metal member is located in the same film layer as the pixel electrode, and the material of the pixel electrode and the annular metal member is the same.

[0013] In the display panel, the metal pad is placed on the interlayer insulating layer around the opening of the first through-hole.

[0014] In the aforementioned display panel, the source, the drain, and the metal pad are located in the same film layer, and the source, the drain, and the metal pad are made of the same material.

[0015] In the display panel, when viewed from above, the metal pad is located between the main body of the common wiring and the gate wire electrically connected to the gate.

[0016] In the display panel, when the display panel is viewed from above, the dimensions of the metal pad in a direction perpendicular to the longitudinal direction of the common wiring are greater than half the width of the gap between the main body of the common wiring and the gate wire, and less than the width of the gap.

[0017] In the display panel, when the display panel is viewed from above, the dimensions of the metal pad in a direction perpendicular to the longitudinal direction of the common wiring are greater than the width of the main body of the common wiring or the width of the gate wire.

[0018] Embodiments of the present application further provide a method for manufacturing a display panel, the manufacturing method comprising: forming a gate and common wiring on a gate insulating layer; forming an interlayer insulating layer on the gate insulating layer, the gate and the common wiring; forming a pixel electrode on the interlayer insulating layer; forming a first through-hole in the interlayer insulating layer, the first through-hole penetrating the interlayer insulating layer and exposing the common wiring; forming a source, a drain and a metal pad in the first through-hole and on the interlayer insulating layer, the metal pad being installed on the bottom surface and side wall of the first through-hole and around the opening of the first through-hole, the metal pad being in contact with the common wiring; forming a passivation layer on the source, the drain, the metal pad, the pixel electrode and the interlayer insulating layer; forming a second through-hole on the passivation layer at a position corresponding to the first through-hole, the second through-hole exposing a portion of the metal pad; and forming a common electrode on the passivation layer, the common electrode being in contact with the metal pad via the second through-hole.

[0019] In the above manufacturing method, the step of forming a source, drain and metal pad in the first through-hole and on the interlayer insulating layer includes forming a source-drain metal layer in the first through-hole and on the interlayer insulating layer, and performing a patterning process on the source-drain metal layer to form the source and drain and metal pad.

[0020] The manufacturing method further includes forming an annular metal member located on the same layer as the pixel electrode during the process of forming the pixel electrode, and placing the annular metal member on the interlayer insulating layer around the opening of the first through-hole.

[0021] In the above manufacturing method, the step of forming a first through-hole in the interlayer insulating layer includes etching the interlayer insulating layer in the perforated portion of the annular metal member used as a mask to form the first through-hole.

Advantages of the Invention

[0022] In the display panel and its manufacturing method of the present application, a metal pad is installed in the first through-hole provided in the interlayer insulating layer. This metal pad is located in the same layer as the source and the drain, and they are manufactured with the same material. With such a structural design, the metal pad is formed together with the source and the drain in the same process step, eliminating the need for additional process steps. At the same time, since the metal pad is installed on the bottom surface and side wall of the first through-hole and around the opening of the first through-hole, it completely covers and protects the lower common wiring, avoiding the etching of the common wiring when wet-etching the source-drain metal layer, and thus ensuring a highly reliable electrical connection between the common wiring and the common electrode.

[0023] The display panel and its manufacturing method provided in the present application, by means of the technical solution of adding a metal pad between the passivation layer and the sleeve connection hole of the interlayer insulating layer, maintain the advantage of simplifying the six mask processes, effectively solve the problem that the common wiring is etched in the wet-etching process, ensure a highly reliable electrical connection between the common wiring and the common electrode, improve the yield of the display panel manufacturing and the product reliability, and achieve the goals of reducing manufacturing costs, improving production efficiency and display quality.

Brief Description of the Drawings

[0024] [Figure 1] It is a schematic diagram showing the phenomenon that the common wiring was etched in the conventional display panel. [Figure 2] It is a block diagram of the display panel provided in the present application. [Figure 3] It is a schematic diagram showing the first embodiment of the display panel provided in the present application. [Figure 4] It is a layout diagram of a part of the region of the first embodiment of the display panel provided in the present application. [Figure 5] It is a schematic diagram showing the second embodiment of the display panel provided in the present application. [Figure 6] It is a schematic diagram showing a method for manufacturing a display panel provided in the present application. [Figure 7] It is a schematic diagram showing a method for manufacturing a display panel provided in the present application. [Figure 8] It is a schematic diagram showing a method for manufacturing a display panel provided in the present application. [Figure 9] It is a schematic diagram showing a method for manufacturing a display panel provided in the present application. [Figure 10] It is a schematic diagram showing a method for manufacturing a display panel provided in the present application. [Figure 11] It is a schematic diagram showing a method for manufacturing a display panel provided in the present application.

Embodiments for Carrying out the Invention

[0025] Hereinafter, specific embodiments of the present application will be described in detail while referring to the drawings.

[0026] The terms "first", "second" and similar terms thereof do not indicate order, quantity or importance, but are merely used to distinguish different technical features. The term "plurality" and similar terms thereof indicate two or more unless specifically and clearly limited.

[0027] Examples of the present application can be combined.

[0028] The display panel provided in the examples of the present application is, for example, a liquid crystal display panel.

[0029] As shown in Figure 2, the display panel includes a display area and a non-display area. The display area contains m × n pixels arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used for arranging the drive circuit and various signal lines. The display panel further includes multiple gate lines, multiple data lines, and a gate drive circuit. The multiple gate lines extend along a first direction and are arranged along a second direction, while the multiple data lines extend along a second direction and are arranged along a first direction, with the first direction being perpendicular to the second direction. The gate drive circuit is installed in the non-display area and is electrically connected to the multiple gate lines. The source drive circuit is electrically connected to the multiple data lines by a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit, respectively.

[0030] The display panel includes a thin-film transistor array substrate, a counter substrate, and a liquid crystal layer placed between the thin-film transistor array substrate and the counter substrate. The thin-film transistor array substrate includes a glass substrate, a first metal layer placed on the glass substrate, a gate insulating layer placed on the first metal layer, a semiconductor layer placed on the gate insulating layer, a second metal layer placed on the semiconductor layer, a passivation layer placed on the second metal layer, and pixel electrodes placed on the passivation layer. The first metal layer includes gate lines, gates, etc. The second metal layer includes data lines, sources, drains, etc. The counter substrate includes a glass substrate, a black matrix placed on the glass substrate, a color filter layer placed on the black matrix, and common electrodes placed on the color filter layer.

[0031] Each pixel includes at least one thin-film transistor and a pixel electrode. The thin-film transistor has its gate electrically connected to the corresponding gate line, its source electrically connected to the corresponding data line, and its drain electrically connected to the corresponding pixel electrode. When a high-level scan signal is output from the gate line, the thin-film transistor is turned on, and the data signal on the data line is transmitted by the thin-film transistor to the pixel electrode. When a low-level scan signal is output from the gate line, the thin-film transistor is turned off, and the pixel electrode holds the voltage corresponding to the data signal.

[0032] The gate drive circuit includes n-stage gate drive subcircuits connected in cascade order, with each stage's gate drive subcircuit electrically connected to a single gate line. The gate drive subcircuits sequentially output scanning signals under the control of a timing controller, scanning each row of pixels in the display area one row at a time.

[0033] In one embodiment of the present invention, a display panel is provided which is manufactured in six masking steps. Compared to the conventional nine masking steps, the manufacturing steps for the light shielding layer (LS) and the planarization layer (PLN) are omitted, and the pixel electrodes and interlayer insulating layer are formed in the same step using halftone mask technology, thereby reducing the number of photomasks and lowering manufacturing costs.

[0034] Specifically, as shown in Figures 3, 4, and 5, the thin-film transistor array substrate of this display panel includes a substrate 301, a buffer layer 302, a semiconductor layer 303, a gate insulating layer 304, a gate 305, a common wiring 307, an interlayer insulating layer 306, a pixel electrode 312, a source 313, a drain 314, a passivation layer 315, and a common electrode 317. Here, the substrate 301 is a glass substrate, and the buffer layer 302 is placed on the substrate 301. The semiconductor layer 303 is placed on the buffer layer 302 and is made of low-temperature poly-silicon (LTPS) material. After doping, the semiconductor layer 303 forms a source region, a drain region, and a channel region. The gate insulating layer 304 is placed on the semiconductor layer 303 and the buffer layer 302 and is used to insulate the semiconductor layer 303 from the gate 305. The gate 305 and common wiring 307 are installed on the gate insulating layer 304. The common wiring 307 is located on the same film layer as the gate 305 and is made of the same material (molybdenum (Mo)) as the gate 305. The interlayer insulating layer 306 is installed on the gate 305 and the gate insulating layer 304 and is used to insulate the gate 305 from the source 313 and drain 314.

[0035] The source 313, drain 314, and pixel electrode 312 are placed on an interlayer insulating layer 306, where the source 313 and drain 314 are made of a molybdenum-aluminum-molybdenum (MoAlMo) multilayer metallic material. The pixel electrode 312 is made of a transparent conductive material, such as indium tin oxide (ITO), and in this embodiment, the pixel electrode 312 is a bottom transparent electrode (BITO). The passivation layer 315 is placed on the source 313, drain 314, pixel electrode 312, and interlayer insulating layer 306. The common electrode 317 is placed on the passivation layer 315 and is made of a transparent conductive material, such as indium tin oxide, and in this embodiment, the common electrode 317 is a top transparent electrode (TITO).

[0036] In this display panel, a first through-hole 309 is provided in the interlayer insulation layer 306, and the first through-hole 309 penetrates the interlayer insulation layer 306, exposing at least a portion of the protrusion 3072 of the common wiring 307. A second through-hole 316 is provided in the passivation layer 315 at a position corresponding to the first through-hole 309, and the second through-hole 316 is sleeve-connected to the first through-hole 309 to form a sleeve connection hole. The display panel further includes a metal pad 308 installed in the first through-hole 309, the metal pad 308 is located in the same film layer as the source 313 and drain 314, and is installed on the bottom surface and side wall of the first through-hole 309 and around the opening of the first through-hole 309, and is in contact (electrically connected) with the protrusion 3072 of the common wiring 307. The second through-hole 316 exposes a portion of the metal pad 308, and the common electrode 317 contacts the metal pad 308 through the second through-hole 316, thereby achieving an electrical connection between the common electrode 317 and the common wiring 307. The metal pad 308 here protects the protrusion 3072 of the common wiring 307, preventing the protrusion 3072 of the common wiring 307 from being etched during the wet etching process.

[0037] In this display panel, the drain 314 is electrically connected to the pixel electrode 312, and since the pixel electrode 312 is formed before the source 313 and drain 314, at least a portion of the drain 314 overlaps and is connected to at least a portion of the pixel electrode 312. The source 313 is electrically connected to the semiconductor layer 303 via a third through-hole 310 that penetrates the gate insulating layer 304 and the interlayer insulating layer 306, and the drain 314 is electrically connected to the semiconductor layer 303 via a fourth through-hole 311 that penetrates the gate insulating layer 304 and the interlayer insulating layer 306. The first through-hole 309, the third through-hole 310 and the fourth through-hole 311 are formed in the same manufacturing process.

[0038] To make the common voltage within the display panel more uniform, the present invention provides a common voltage signal to the common electrode 317 via a common wiring 307 installed on the same layer as the gate 305 in the display panel. This design reduces the signal transmission path diameter, reduces signal delay, and improves display quality. However, in the actual manufacturing process, as shown in Figure 1, when the source and drain metals (made of MoAlMo) are wet-etched to form the source and drain, the common wiring 101 (made of Mo) under the through-hole 102 is also etched, resulting in the inability to properly connect the common wiring 101 and the common electrode. This is because the wet etching solution used to etch MoAlMo also etches the Mo material, and when the two materials are in direct contact and exposed to the same etching environment, it becomes impossible to selectively etch only MoAlMo without affecting Mo.

[0039] To solve the above problems, as shown in Figures 3, 4, and 5, the display panel of the present invention adds a metal pad 308 between the passivation layer 315 and the sleeve connection hole of the interlayer insulation layer 306. This metal pad 308 is located on the same layer as the source 313 and drain 314 and is made of the same material (MoAlMo). The metal pad 308 is installed on the bottom and side walls of the first through-hole 309 and around the opening of the first through-hole 309. The metal pad 308 is in contact with the projection 3072 of the common wiring 307, and a portion of the passivation layer 315 is installed on this metal pad 308, while the second through-hole 316 exposes a portion of the metal pad 308 but does not expose a portion of the projection 3072 of the common wiring 307. The common electrode 317 is electrically connected to the projection 3072 of the common wiring 307 by contacting the metal pad 308 through the second through-hole 316. During the wet etching process in which the source 313 and drain 314 are formed, the metal pad 308 covers and protects the protrusions 3072 of the common wiring 307, thereby preventing the etching of the protrusions 3072. Furthermore, because the metal pad 308 is located on the same layer as the source 313 and drain 314 and is made of the same material, they can be formed in the same process step, thus avoiding an increase in additional manufacturing costs and process complexity.

[0040] When the display panel is viewed from above, the metal pad 308 is located between the main body 3071 of the common wiring 307 and the gate line electrically connected to the gate 305. Specifically, the main body 3071 of the common wiring 307 extends along a first direction, the gate line extends along the first direction and is installed parallel to the main body 3071 of the common wiring 307, and the metal pad 308 is installed in the gap area between the main body 3071 of the common wiring 307 and the adjacent gate line. This makes full use of the space between the gate line and the common wiring 307 in the display panel, prevents the metal pad 308 from occupying the aperture area of ​​the pixel, and consequently does not affect the transmittance and display effect of the display panel. At the same time, this allows the metal pad 308 to form an effective and reliable electrical connection with the protrusion 3072 of the common wiring 307, ensuring stable transmission of the common voltage signal and improving the electrical performance and display uniformity of the display panel.

[0041] When the display panel is viewed from above, the dimension W1 of the metal pad 308 in the direction perpendicular to the longitudinal direction of the common wiring 307 is greater than half the width W2 of the gap between the main body 3071 of the common wiring 307 and the gate wire, and less than the width W2 of the gap. This ensures that the metal pad 308 has sufficient area to form good electrical contact with the protrusion 3072 of the common wiring 307, reducing contact resistance, and avoiding the risk of short circuits with adjacent gate wires by not occupying excessive space in the gap. Furthermore, this is advantageous in maintaining good process margins during the manufacturing process, and even if there is a slight deviation in the alignment of the photoresist, a reliable connection between the metal pad 308 and the common wiring 307 can be ensured, improving the manufacturing yield and product reliability of the display panel.

[0042] When the display panel is viewed from above, the dimension W1 of the metal pad 308 in the direction perpendicular to the longitudinal direction of the common wiring 307 is larger than the width W3 of the main body 3071 of the common wiring 307 or the width W4 of the gate wire. This ensures that the metal pad 308 has a sufficiently large contact area, effectively reducing contact resistance with the common wiring 307 and improving the reliability of the electrical connection. The relatively large dimensions of the metal pad 308 also provide better current load performance, avoiding electromigration due to excessively high current density and extending the service life of the display panel. At the same time, this also enhances the protective effect of the metal pad 308 on the common wiring 307, more comprehensively covering and protecting the protruding portion 3072 of the common wiring 307 during the wet etching process, preventing penetration of the etching solution and unintended etching of the common wiring 307.

[0043] The present invention provides two embodiments. As shown in Figures 3 and 4, in the first embodiment, the display panel further includes an annular metal member 318, which is positioned around the opening of the first through-hole 309, surrounding the opening of the first through-hole 309, and is positioned on the interlayer insulating layer 306, with the portion of the metal pad 308 located outside the first through-hole 309 positioned on the annular metal member 318, that is, the annular metal member 318 is positioned between the metal pad 308 and the interlayer insulating layer 306, and is located on the same film layer as the pixel electrode 312. The ratio of the area of ​​the annular metal member 318 to the area of ​​the portion of the metal pad 308 located outside the first through-hole 309 is less than 1. Specifically, the ratio of the area of ​​the annular metal member 318 to the area of ​​the portion of the metal pad 308 located outside the first through-hole 309 is between 0.3 and 0.9. This ensures that the annular metal member 318 provides the necessary support and positioning functions for the metal pad 308 without excessively occupying space in the pixel area. Since the annular metal member 318 is made of a transparent conductive material, it has a certain degree of light transmittance, but if its area is too large, it will affect the light transmittance of that area. By controlling the area of ​​the annular metal member 318 to be less than or equal to a predetermined ratio of the area of ​​the surrounding portion of the metal pad 308, the effect on the transmittance of the pixel aperture is minimized, ensuring that the brightness and display effect of the display panel are not significantly affected, guaranteeing the reliability of the electrical connection, and maintaining the high transmittance and excellent optical performance of the display panel. The inner edge of the annular metal member 318 is flush with the edge of the opening of the first through-hole 309; that is, the annular metal member 318 is not installed on the side wall or bottom surface of the first through-hole 309. The annular metal member 318 is located in the same film layer as the pixel electrode 312, and the material of the pixel electrode 312 and the annular metal member 318 is the same, a transparent conductive material, such as indium tin oxide. The annular metal member 318 is formed using the same manufacturing process as the pixel electrode 312 and serves as a mask for forming the first through-hole 309. When the first through-hole 309 is formed, the annular metal member 318 allows the etching solution to etch the interlayer insulating layer 306 only at the location where the first through-hole 309 should be formed, thereby improving the positional accuracy and dimensional controllability of the through-hole. Consequently, the shape and position of the through-hole can be controlled with high precision.

[0044] The second embodiment of the present invention is similar to the first embodiment, but the differences are as follows. As shown in Figure 5, in the second embodiment, the metal pad 308 is directly placed on the interlayer insulating layer 306 around the opening of the first through-hole 309, and there is no annular metal member 318 located on the same layer as the pixel electrode 312 between the metal pad 308 and the interlayer insulating layer 306. The source 313, drain 314 and metal pad 308 are located on the same film layer, and the materials of the source 313, drain 314 and metal pad 308 are the same, all of which are MoAlMo multilayer metals. Such a design is relatively simplified, the number of layers is reduced, and the complexity of manufacturing is reduced.

[0045] This invention further provides a method for manufacturing a display panel. As shown in Figures 6 to 11, this method includes the following steps.

[0046] In the first step, a buffer layer 302 is formed on the substrate 301. The substrate 301 is a glass substrate, and the buffer layer 302 may be made of silicon nitride (SiNx) or silicon oxide (SiOx) material and deposited by plasma-enhanced chemical vapor deposition (PECVD).

[0047] In the second step, a semiconductor layer 303 is formed on the buffer layer 302. The semiconductor layer 303 uses a low-temperature polysilicon material, in which an amorphous silicon thin film is first deposited, and then the amorphous silicon is converted to polysilicon by an excimer laser annealing (ELA) process.

[0048] In the third step, the semiconductor layer 303 is treated so that it includes a channel region, a low-concentration doping region, and a high-concentration doping region, where the high-concentration doping region includes a source region and a drain region. This step is achieved by an ion implantation process, using different types, amounts, and energies of dopants depending on the doping requirements of the different regions.

[0049] In the fourth step, a gate insulating layer 304 is formed on the semiconductor layer 303 and the buffer layer 302. The gate insulating layer 304 may be made of silicon nitride or silicon oxide material and deposited by the PECVD method.

[0050] In the fifth step, the gate 305 and common wiring 307 are formed on the gate insulating layer 304. This step is achieved by depositing a metal layer (e.g., a molybdenum layer), photolithography, and dry etching. The gate electrode 305 and common wiring 307 are formed in the same metal layer, thereby ensuring that the common wiring 307 has the same electrical properties as the gate electrode 305.

[0051] In the sixth step, an interlayer insulating layer 306 is formed on the gate insulating layer 304, the gate 305, and the common wiring 307. The interlayer insulating layer 306 may be made of silicon nitride or silicon oxide material and may also be deposited by the PECVD method.

[0052] In the seventh step, pixel electrodes 312 are formed on the interlayer insulating layer 306, and through-holes are formed within the interlayer insulating layer 306. This step uses halftone mask technology to simultaneously complete the formation of the pixel electrodes 312 and etching of the first through-holes 309 in the interlayer insulating layer 306 in a single photolithography process. A halftone mask is a special photomask whose patterned areas have different transmittances and are usually divided into fully transparent, semi-transparent, and fully opaque areas. During the exposure process, the photoresist receives different amounts of exposure depending on the area of ​​different transmittance, forming photoresist patterns of different thicknesses after development. Specifically, the photoresist corresponding to the fully transparent area is completely removed after development and used to form through-holes. The photoresist corresponding to the semi-transparent area remains partially after development, is thin, and is used to form the pattern of the pixel electrodes 312. The photoresist corresponding to the fully opaque area remains completely after development and is used to protect other areas.

[0053] In this step, a transparent conductive material (e.g., ITO) layer is first deposited on the interlayer insulating layer 306, then a photoresist is applied, and exposure is performed using a halftone mask. After development, photoresist patterns of different thicknesses are formed. Next, the first etching is performed to etch the transparent conductive material layer and form the pattern of the pixel electrode 312. Then, an ashing process is performed to remove the thin photoresist corresponding to the semi-transparent region, exposing the underlying interlayer insulating layer 306. Finally, the second etching is performed to etch the interlayer insulating layer 306 and form through-holes. This method completes the formation of the pixel electrode 312 and the etching of the through-holes in the interlayer insulating layer 306 in a single photolithography process, saving one photomask and corresponding process steps.

[0054] In this embodiment, the pixel electrode 312 is formed by halftone mask technology, and at the same time, an annular metal member 318 located on the same layer as the pixel electrode 312 is also formed, and a first through-hole 309, a third through-hole 310, and a fourth through-hole 311 are formed in the interlayer insulating layer 306. The first through-hole 309 penetrates the interlayer insulating layer 306 and exposes the common wiring 307. The third through-hole 310 and the fourth through-hole 311 penetrate the gate insulating layer 304 and the interlayer insulating layer 306 and expose the high-concentration doping region of the semiconductor layer 303. When using the design of the first embodiment, the first through-hole 309 can be formed by using the annular metal member 318 located on the same layer as the pixel electrode 312 as a mask and etching the interlayer insulating layer 306 in the perforated portion of the annular metal member 318.

[0055] In the eighth step, a source 313, a drain 314, and a metal pad 308 are formed inside the first through-hole 309 and on the interlayer insulating layer 306. This step includes two substeps. First, a source-drain metal layer is formed inside the first through-hole 309 and on the interlayer insulating layer 306, using a MoAlMo multilayer metal structure, which may be deposited by methods such as magnetron sputtering. Then, the source-drain metal layer is patterned to form the source 313, drain 314, and metal pad 308. The metal pad 308 is installed on the bottom and side walls of the first through-hole 309 and around the opening of the first through-hole 309, and plays a role in protecting the common wiring 307 by contacting it.

[0056] In the ninth step, a passivation layer 315 is formed on the source 313, drain 314, metal pad 308, pixel electrode 312, and interlayer insulating layer 306. The passivation layer 315 may be made of silicon nitride or silicon oxide material and may also be deposited by the PECVD method.

[0057] In the tenth step, a second through-hole 316 is formed on the passivation layer 315 at a position corresponding to the first through-hole 309, and the second through-hole 316 exposes a portion of the metal pad 308. This step is achieved by photolithography and dry etching processes. Because the metal pad 308 covers the common wiring 307, the second through-hole 316 only needs to expose the metal pad 308, eliminating the need to directly expose the common wiring 307, thereby avoiding the possibility of damage to the common wiring 307 in subsequent processes.

[0058] In the 11th step, a common electrode 317 is formed on the passivation layer 315, and the common electrode 317 contacts the metal pad 308 through the second through-hole 316. This step includes two substeps. First, a common electrode layer is formed on the surface of the passivation layer 315 and within the second through-hole 316, which may be deposited using a transparent conductive material, such as ITO, by a method such as magnetron sputtering. Then, the common electrode layer is patterned to form a common electrode 317 pattern that meets the requirements.

[0059] The above-described technology effectively solves the problem of common wiring 307 being etched when the source-drain metal layer is wet-etched by adding a metal pad 308 between the passivation layer 315 and the sleeve connection hole of the interlayer insulation layer 306 in the display panel of the present invention. This ensures a highly reliable electrical connection between the common wiring 307 and the common electrode 317, improving the manufacturing yield and product reliability of the display panel. At the same time, the display panel of the present invention reduces the number of photomasks and process steps by using six masking processes, thereby reducing manufacturing costs and improving production efficiency.

[0060] In actual applications, if the contact area between the metal pad 308 and the common wiring 307 is insufficient, the contact resistance becomes too high, affecting the uniform distribution of the common voltage, which in turn causes display defects such as uneven display and flicker.

[0061] To solve the above technical problems, in the embodiment of the present application, the first through-hole 309 is set to be elongated or to be a combination of multiple small through-holes, thereby maximizing the contact area between the metal pad 308 and the common wiring 307. In addition, the contact area with the metal pad 308 may be increased by installing a convex structure on the common wiring 307.

[0062] During prolonged operation or in high-temperature environments, metal interdiffusion or oxidation may occur at the interface between the metal pad 308 (MoAlMo) and the common wiring 307 (Mo), leading to increased contact resistance and impacting the reliability of the electrical connection.

[0063] To solve the above technical problems, a transition layer, for example, a thin layer of titanium (Ti) or titanium nitride (TiN), is added between the metal pad 308 and the common wiring 307 to act as a diffusion prevention layer, thereby preventing interdiffusion between the two types of metals. Specifically, before the source-drain metal layer is formed, a thin layer of titanium or titanium nitride is first deposited in the first through-hole 309, and then a MoAlMo multilayer metal is deposited.

[0064] During the wet etching process of the source drain metal layer, if the etching solution penetrates through the tiny gap between the metal pad 308 and the sidewall of the first through-hole 309, it can still cause etching of parts of the common wiring 307, affecting the reliability of the electrical connection.

[0065] To solve the above technical problems, multi-angle deposition technology is used to ensure that the metal pad 308 uniformly covers the sidewall of the first through-hole 309. At the same time, the thickness of the metal pad 308 may be appropriately increased to enhance its protective ability against the common wiring 307. Furthermore, the wet etching process may be optimized, for example by adjusting the composition of the etching solution, controlling the etching time and temperature, thereby reducing the etching rate for Mo material and increasing selectivity for MoAlMo. In addition, after the metal pad 308 is formed, a short heat treatment is performed to promote interfacial bonding between the metal pad 308 and the common wiring 307, thereby reducing the possibility of etching solution penetration.

[0066] In actual applications, if the contact area between the metal pad 308 and the common wiring 307 is insufficient, the contact resistance becomes too high, affecting the uniform distribution of the common voltage, which in turn causes display defects such as uneven display and flicker.

[0067] To solve the above technical problems, in the embodiments of the present invention, three to five small circular through-holes with a diameter of 2 μm to 3 μm are provided in the common wiring 307, with a spacing of 5 μm to 10 μm between the small through-holes, thereby ensuring that the metal pads 308 in each small through-hole can form a continuous electrical connection. Furthermore, in the embodiments of the present invention, protrusions are provided in the common wiring 307, with a height of 50 nm to 100 nm and a width of 1 μm to 3 μm, and one protrusion is provided every 10 μm to 15 μm along the length of the common wiring 307, thereby allowing the metal pads 308 to form closer contact with the common wiring 307 at the protrusions, increasing the contact area and reducing contact resistance. Such protrusions can be realized by using a specially designed mask pattern during the process of forming the common wiring 307, without requiring any additional process steps.

[0068] During prolonged operation or in high-temperature environments, metal interdiffusion or oxidation may occur at the interface between the metal pad 308 (MoAlMo) and the common wiring 307 (Mo), leading to increased contact resistance and impacting the reliability of the electrical connection.

[0069] To solve the above technical problems, a transition layer, for example, a thin layer of titanium (Ti) or titanium nitride (TiN), is added between the metal pad 308 and the common wiring 307 to act as a diffusion prevention layer, thereby preventing interdiffusion between the two types of metals. The thickness of this transition layer is 5 nm to 20 nm, which prevents metal interdiffusion and does not significantly increase contact resistance. Specifically, before the source-drain metal layer is formed, a thin layer of titanium or titanium nitride is first deposited in the first through-hole 309, and then a MoAlMo multilayer metal is deposited. The titanium layer may be deposited by magnetron sputtering in an argon atmosphere, with a deposition time of 30 to 60 seconds. The titanium nitride layer may be deposited by reactive magnetron sputtering in a mixed argon and nitrogen atmosphere, with a flow rate ratio of argon to nitrogen of 4:1 to 2:1, and a deposition time of 40 to 80 seconds. Such a transition layer not only prevents metal interdiffusion, but also enhances adhesion between the metal pad 308 and the common wiring 307, strengthens the interfacial bonding strength, and improves the reliability and stability of the electrical connection.

[0070] During the wet etching process of the source drain metal layer, if the etching solution penetrates through the tiny gap between the metal pad 308 and the sidewall of the first through-hole 309, it can still cause etching of parts of the common wiring 307, affecting the reliability of the electrical connection.

[0071] To solve the above technical problems, the embodiments of the present invention use multi-angle deposition technology to ensure that the metal pad 308 uniformly covers the sidewalls of the first through-holes 309. Specifically, when depositing the source-drain metal layer, the substrate 301 is rotated and deposited at an inclination angle of 15° to 30°, with rotation angles in four directions: 0°, 90°, 180°, and 270°. The deposition thickness in each direction is 1 / 4 of the total thickness, thereby ensuring that the coverage rate of the metal pad 308 on the sidewalls of the first through-holes 309 reaches 95% or more, forming a continuous and gapless protective layer. In addition, the embodiments of the present invention appropriately increase the thickness of the metal pad 308 from the conventional 200nm to 300nm to 300nm to 500nm, thereby enhancing its protective ability against common wiring 307 and strengthening its resistance to etching solution penetration.

[0072] Furthermore, in the embodiments of this application, the wet etching process was optimized and the composition of the etching solution was adjusted by adding 0.5% to 1% of a corrosion inhibitor, such as benzotriazole or thiourea, to the conventional mixture of phosphoric acid, nitric acid, and acetic acid to selectively reduce the etching rate for Mo material and selectively increase the etching rate for MoAlMo, thereby improving the etching rate ratio of MoAlMo to Mo from the original 3:1 to 8:1 or higher. At the same time, the etching temperature was reduced from the conventional 40°C to 25°C to 30°C, and the etching time was extended from 60 seconds to 90 seconds to 120 seconds, thereby improving the precision of process control by reducing the etching rate and reducing unintended etching of the common wiring 307.

[0073] Furthermore, in the embodiments of this application, after the metal pad 308 was formed, a short-time heat treatment was performed to promote interfacial bonding between the metal pad 308 and the common wiring 307, thereby reducing the possibility of etching solution penetration. This heat treatment was carried out in a nitrogen or argon protective atmosphere at a temperature of 250°C to 350°C for a duration of 10 to 30 minutes. This appropriate heat treatment formed a closer bond at the interface between the metal pad 308 and the common wiring 307, while avoiding the problem of metal interdiffusion caused by excessively high temperatures.

[0074] The display panel of this invention can be applied to various types of liquid crystal display panels, such as FFS (Fringe Field Switching) liquid crystal display panels or IPS (In-Plane Switching) liquid crystal display panels. Furthermore, this technology can be further applied to other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels.

[0075] Although embodiments of this application have been described in detail above, the contents of this specification should not be understood as limiting the scope of protection of this application.

Claims

1. The gate, A common wiring located in the same film layer as the aforementioned gate, An interlayer insulating layer installed on the gate, wherein a first through-hole is provided in the interlayer insulating layer, the first through-hole penetrates the interlayer insulating layer and exposes at least a portion of the common wiring, The pixel electrodes, source, and drain are installed on the interlayer insulating layer, A passivation layer installed on the source, the drain, the pixel electrode, and the interlayer insulating layer, wherein a second through-hole is installed at a position corresponding to the first through-hole of the passivation layer, and the second through-hole is sleeve-connected to the first through-hole of the passivation layer, A common electrode installed on the passivation layer, The device includes a metal pad installed within the first through-hole, located in the same film layer as the source and the drain, and installed on the bottom surface and side walls of the first through-hole, and around the opening of the first through-hole, which is in contact with the common wiring. Here, the second through-hole exposes a portion of the metal pad, and the common electrode contacts the metal pad through the second through-hole. Display panel.

2. The display panel further includes an annular metal member, which is positioned around the opening of the first through-hole, surrounds the opening of the first through-hole, and is positioned on the interlayer insulating layer, and the portion of the metal pad located outside the first through-hole is positioned on the annular metal member. The display panel according to claim 1.

3. The ratio of the area of ​​the annular metal member to the area of ​​the portion of the metal pad located outside the first through-hole is less than 1. The display panel according to claim 2.

4. The inner edge of the annular metal member is flush with the edge of the opening of the first through-hole. The display panel according to claim 2.

5. The annular metal member is located in the same film layer as the pixel electrode, and the material of the pixel electrode and the annular metal member is the same. The display panel according to claim 2.

6. Around the opening of the first through-hole, the metal pad is placed on the interlayer insulating layer. The display panel according to claim 1.

7. The source, the drain, and the metal pad are located in the same film layer, and the source, the drain, and the metal pad are made of the same material. The display panel according to claim 1.

8. When the display panel is viewed from above, the metal pad is located between the main body of the common wiring and the gate wire electrically connected to the gate. The display panel according to claim 1.

9. When the display panel is viewed from above, in a direction perpendicular to the longitudinal direction of the common wiring, the dimensions of the metal pad are greater than half the width of the gap between the main body of the common wiring and the gate wire, and less than the width of the gap. The display panel according to claim 8.

10. When the display panel is viewed from above, the dimensions of the metal pad are greater than the width of the main body of the common wiring or the width of the gate wire in a direction perpendicular to the length direction of the common wiring. The display panel according to claim 8.

11. The gate and common wiring are formed on the gate insulation layer, The gate insulating layer, the gate and the common wiring are formed on the interlayer insulating layer, The pixel electrodes are formed on the interlayer insulating layer, A first through-hole is formed in the interlayer insulating layer, the first through-hole penetrates the interlayer insulating layer and exposes the common wiring, Source, drain, and metal pad are formed in the first through-hole and on the interlayer insulating layer, the metal pad is installed on the bottom surface and side wall of the first through-hole and around the opening of the first through-hole, and the metal pad is in contact with the common wiring, A passivation layer is formed on the source, the drain, the metal pad, the pixel electrode, and the interlayer insulating layer, A second through-hole is formed on the passivation layer at a position corresponding to the first through-hole, and the second through-hole exposes a portion of the metal pad. The common electrode is formed on the passivation layer, and the common electrode is in contact with the metal pad through the second through-hole, A method for manufacturing a display panel.

12. The step of forming the source, drain, and metal pad in the first through-hole and on the interlayer insulating layer is as follows: A source-drain metal layer is formed inside the first through-hole and on the interlayer insulating layer, This includes performing a patterning process on the source-drain metal layer to form the source, the drain, and the metal pad, A method for manufacturing a display panel according to claim 11.

13. The process of forming the pixel electrode further includes forming an annular metal member located on the same layer as the pixel electrode, and placing the annular metal member on the interlayer insulating layer around the opening of the first through-hole. A method for manufacturing a display panel according to claim 11.

14. The step of forming the first through-hole in the interlayer insulating layer is, The process includes etching the interlayer insulating layer in the perforated portion of the annular metal member used as a mask to form the first through-hole, A method for manufacturing a display panel according to claim 13.

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