Inkjet head unit and inkjet printer

Abstract

To provide an inkjet head unit which interrupts a power supply line involving all the routes where penetration current generated in a driver IC by latch-up flows.SOLUTION: An inkjet head unit includes: a driver IC for driving an actuator; first and second power source supply lines for supplying a different power source to the driver IC; a first fuse of first fusion current provided on the first power source supply line; and a second fuse of second fusion current smaller than the first fusion current provided on the second power source supply line. When latch-up is generated in the driver IC, and a first route where the penetration current relating to the first power source supply line flows and a second route where the penetration current relating to the second power source supply line flows are established, the second fuse is fused and the second route is interrupted, simultaneously or with a delay, the first fuse is fused and the first route is interrupted, the first power source supply line and the second power source supply line are electrically separated from one another relative to the driver IC.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to an inkjet head unit having a protection circuit and an inkjet printer.

Background Art

[0002] As an image forming apparatus, an inkjet printer that discharges ink onto a printing medium to form an image is known. The inkjet printer includes, for example, an inkjet head and a head control unit that controls the inkjet head. The inkjet head includes an actuator having a capacitive load connected with a plurality of capacitive elements, and a driver IC that drives the actuator. The driver IC includes a logic circuit and a semiconductor switch. Based on the control of the head control unit, the driver IC switches the semiconductor switch by the output of the logic circuit to generate a drive signal from a drive power source, and supplies this drive signal to each capacitive element of the actuator.

[0003] In order to improve the quality of ink discharge, the inkjet printer generates a plurality of types of drive signals with different potentials and different waveforms by the driver IC. Since the above-described driver IC is formed by a CMOS process, there are often parasitic circuits. Therefore, when latch-up occurs, a structure in which a plurality of through-current paths due to parasitic circuits are likely to occur. The inkjet printer instantaneously supplies a drive signal in order to drive the actuator at high speed. When latch-up occurs due to external noise or the like and a plurality of through-current paths are formed, even if only the main drive power source is disconnected, there is a risk that all the through-current paths due to other drive power sources cannot be disconnected. Therefore, in order to prevent an overcurrent from flowing through the driver IC due to latch-up and causing burnout due to heating, a protection circuit including a fuse is provided in the power supply line so that the power supply to the driver IC can be cut off.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] Japanese Patent Publication No. 2017-53236 [Overview of the project] [Problems that the invention aims to solve]

[0005] The aforementioned protection circuit fuses are provided for each power supply line with a certain degree of tolerance to prevent them from blowing due to the current flowing through the power supply line during the normal operation of the driver IC. These fuses have a large capacity (rated current) and are designed to allow for some tolerance.

[0006] When latch-up creates multiple paths for through-current, depending on the circumstances, not all fuses involved in the through-current may blow. For example, in a power supply line with different potentials, if fuses of the same capacity are provided for each, the fuse on the higher potential side may blow first, reducing the through-current. This may cause the other fuse to not blow, thus maintaining the path of the through-current.

[0007] Therefore, the objective is to provide an inkjet head and inkjet printer that have a protection circuit that shuts off the power supply line involved in all paths, even if multiple paths are created through which through-current flows due to latch-up. [Means for solving the problem]

[0008] An inkjet head unit according to one embodiment comprises: an actuator having a capacitive load connected to a plurality of capacitive elements that eject ink; a driver IC that drives the capacitive elements of the actuator; a first capacitor provided in a first power supply line that supplies power of a first potential to the driver IC; a second capacitor provided in a second power supply line that supplies power of a second potential smaller than the first potential to the driver IC; a first fuse with a first blowing current provided in the first power supply line between the first capacitor and the driver IC; and a second fuse with a second blowing current smaller than the first blowing current provided in the second power supply line between the second capacitor and the driver IC. When latch-up occurs in the driver IC, and a first path through which a through current related to the first power supply line flows and a second path through which a through current related to the second power supply line flows are generated, the second fuse blows to interrupt the second path, and simultaneously or with a delay, the first fuse blows to interrupt the first path, electrically isolating the driver IC from the first power supply line and the second power supply line. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is an explanatory diagram showing an example configuration of an inkjet printer according to one embodiment. [Figure 2] Figure 2 shows an example of the configuration of an inkjet head unit and a head control unit. [Figure 3] Figure 3 shows an example of the configuration of a driver IC. [Figure 4] Figure 4 shows an example configuration of a driver IC and actuator. [Figure 5] Figure 5 shows an example of a driver configuration. [Figure 6] Figure 6 shows the stacked structure and equivalent circuit of the driver together. [Figure 7] Figure 7 shows the flow of trigger current generated in the equivalent circuit of a parasitic circuit. [Figure 8]Figure 8 shows the flow of through-current during latch-up in the equivalent circuit of a parasitic circuit. [Figure 9] Figure 9 shows the flow of through-current during latch-up in the equivalent circuit of the parasitic circuit when a drive power supply V2 is supplied in addition to the drive power supply V1. [Figure 10] Figure 10 shows the fuse blowing line and the line where the fuse is less likely to blow. [Figure 11] Figure 11 shows the fuse blowing line. [Modes for carrying out the invention]

[0010] The inkjet printer and inkjet head unit according to the first embodiment will be described below with reference to the drawings. Figure 1 is an explanatory diagram showing an example of the configuration of the inkjet printer 1 according to one embodiment.

[0011] The inkjet printer 1 transports the printing medium, which is the recording medium, and forms an image on the printing medium. The inkjet printer 1 comprises a control unit 11, a display 12, an operation unit 13, a communication interface 14, a transport motor 15, a motor drive circuit 16, a pump 17, a pump drive circuit 18, an inkjet head unit 19, a head control unit 20, and a power supply 21. Furthermore, the inkjet printer 1 comprises a transport mechanism, a paper feed cassette, and an output tray (not shown).

[0012] The control unit 11 comprises a processor 22 and a memory 23, and performs various controls on the inkjet printer 1. The processor 22 is an arithmetic element that performs calculations. For example, the processor 22 performs various processes based on the program and the data used in the program stored in the memory 23. The memory 23 stores the program and the data used in the program in a rewritable manner.

[0013] The display 12 is a display device such as a liquid crystal display, and displays an image according to a video signal input from the processor 22 or a graphic controller (not shown) for performing image processing.

[0014] The operation unit 13 has an operation unit that generates an operation signal based on a user's operation. The operation unit 13 is, for example, a touch sensor, a numeric keypad, a power key, a paper feed key, various function keys, or a keyboard. The touch sensor is, for example, a resistive film type touch sensor or a capacitive touch sensor. The touch sensor acquires information indicating a specified position within a certain area. Also, the touch sensor may be used as a touch panel disposed on the upper surface of the display 12 and integrally configured. In this case, the touch sensor generates a signal indicating the touched position on the screen displayed on the display 12.

[0015] The communication interface 14 is an interface for communicating with an external device. In the present embodiment, the communication interface 14 is used, for example, for communication with at least one host PC 2 that transmits print data to the inkjet printer 1. The communication interface 14 communicates with the host PC 2 via a network 24 configured by wire or wirelessly, for example, a LAN (Local Area Network).

[0016] The conveyance motor 15 serves as a drive source for a conveyance mechanism (not shown) that conveys the print medium by rotating. The conveyance mechanism includes a conveyance belt that conveys the print medium, a plurality of rollers (drive roller and driven roller) around which the conveyance belt is looped, and guides and the like. The conveyance motor 15 rotates the drive roller to move the conveyance belt. The print medium moves along a conveyance path defined by a guide disposed near the conveyance belt.

[0017] The motor drive circuit 16 drives the conveyance motor 15 in accordance with the conveyance control signal input from the control unit 11. The motor drive circuit 16, the conveyance motor 15, and the conveyance mechanism convey the print medium taken out from a paper feed cassette (not shown) via the inkjet head unit 19 to a paper discharge tray (not shown). Incidentally, the paper feed cassette is a cassette that houses a plurality of print media. The paper discharge tray is a tray that houses the print media discharged from the inkjet printer 1.

[0018] The pump 17 supplies ink from the ink tank to the ink chamber of the inkjet head unit 19 through the ink supply path. The pump 17 is disposed on an ink supply path composed of a tube (not shown) that connects the ink tank and the ink chamber (the pressure chamber of a capacitive element described later) of the inkjet head unit 19. The pump drive circuit 18 drives the pump 17 in accordance with the ink supply control signal input from the processor 22.

[0019] The inkjet head unit 19 forms an image by discharging ink onto the print medium. The inkjet head unit 19 forms an image by discharging ink onto the print medium conveyed by the conveyance mechanism based on the drive power supply and the control signal supplied from the head control unit 20. A plurality of inkjet head units 19 are provided corresponding to each color of ink, for example, colors such as cyan, magenta, yellow, and black.

[0020] The head control unit 20 operates the inkjet head unit 19 to discharge ink from the actuator in the inkjet head unit 19 and form an image on the print medium. The head control unit 20 is a circuit that is connected to the control unit 11, the power supply 21, and the host PC 2 and controls the inkjet head unit 19. The head control unit 20 supplies a plurality of drive power supplies with different potentials to the inkjet head unit 19. Further, the head control unit 20 generates a control signal based on the print data input via the communication interface 14.

[0021] The power supply [main power supply] 21 converts AC power supplied from the commercial power supply into DC power (DC voltage DCV). The power supply 21 supplies the DC power as a driving power source to each component in the inkjet printer 1.

[0022] The inkjet head unit 19 and head control unit 20 will be described with reference to Figure 2. Figure 2 is a diagram showing an example configuration of the inkjet head unit 19 and head control unit 20. The inkjet head unit 19 and the head control unit 20 are electrically connected by a transmission I / F cable 35. The I / F cable 35 is preferably made of FFC or FPC. If the connection distance is long, a harness assembly may also be used. As a result, the head control unit 20 supplies drive power and control signals, including a common GND used by the inkjet head unit 19, through the I / F cable 35.

[0023] First, let's explain the head control unit 20. The head control unit 20 includes a drive power supply V1 generation circuit 31, a drive power supply V2 generation circuit 32, a logic circuit power supply VDD generation circuit 33, and a control signal generation circuit 34.

[0024] The drive power supply V1 generation circuit 31 and the drive power supply V2 generation circuit 32 use the DC voltage DCV supplied from the power supply 21 to generate the drive power necessary for the operation of the inkjet head unit 19 and the actuator 42. For example, the drive power supply V1 generation circuit 31 uses the DC voltage DCV to generate drive power supply V1 (power supply at the first potential) to be supplied to the level shift circuit 52 and the driver circuit 53 of the driver IC 43, which will be described later. The drive power supply V2 generation circuit 32 also uses the DC voltage DCV to generate drive power supply V2 (power supply at the second potential) to be supplied to the driver circuit 53 and the actuator 42. In this embodiment, drive power supply V1 and drive power supply V2 have a potential difference, and the relationship is that the voltage value of drive power supply V1 > the voltage value of drive power supply V2. As an example, drive power supply V2 is set to 50 percent of drive power supply V1. Here, when drive power supply V1 is 30V, drive power supply V2 is set to 15V.

[0025] The logic circuit power supply VDD generation circuit 33 generates the logic circuit power supply VDD that is supplied to the logic circuit 51 and level shift circuit 52 of the driver IC 43. The control signal generation circuit 34 generates control signals based on print data input from the host PC2 via the communication interface 14. These control signals include a clock signal CK, a reset signal RST, an initialization signal INIT, and print data SDI, etc. The control signals generated by the control signal generation circuit 34 are output to the logic circuit 51 of the driver IC 43, which will be described later.

[0026] Next, we will describe the inkjet head unit 19. The inkjet head unit 19 consists of a head PC board 41, an actuator 42, and a driver IC 43. Furthermore, a heat sink (heat dissipation fin) 46 is installed inside the inkjet head unit 19 to dissipate heat from the driver IC 43.

[0027] The actuator 42 has a capacitive load, as shown in Figure 4, which will be described later, with multiple capacitive elements connected to eject ink. These capacitive elements include, for example, two piezoelectric members sandwiched between two electrodes formed in a groove. The two piezoelectric members and a nozzle plate (not shown) form a pressure chamber into which ink is filled. These piezoelectric members deform the pressure chamber by the potential difference between the two electrodes, ejecting ink from a nozzle provided on the nozzle plate. The driver IC 43 drives the multiple capacitive elements of the actuator 42.

[0028] The head PC board 41 relays the drive power supply V1, drive power supply V2, logic circuit power supply VDD, control signals, and GND potential transmitted from the head control unit 20 via the I / F cable 35 to the driver IC and actuator 42. The GND potential is the ground potential for the drive power supplies V1 and V2, the logic circuit power supply VDD, and the control signals. The head PC board 41 also includes a protection circuit 47, described later, on each power supply line of the drive power supply V1 and drive power supply V2. The control signals include the clock signal CK, reset signal RST, initialization signal INIT, and print data SDI.

[0029] Next, we will describe the driver IC 43 with reference to Figure 3. Figure 3 shows an example configuration of the driver IC 43. This driver IC 43 consists of a logic circuit 51, a level shift circuit 52, and a driver circuit 53. These circuits are formed on a semiconductor chip using a CMOS process. This driver IC 43 is configured in the form of a COF (Chip On Film) package 45. In this COF package 45, the driver IC 43 chip is mounted on the film surface of a film made of a resin material on which wiring is formed, for example, a polyimide film 44, and then sealed with resin.

[0030] The logic circuit 51 operates using the logic circuit power supply VDD generated by the logic circuit power supply VDD generation circuit 33. Based on the input control signals, the clock signal CK, reset signal RST, initialization signal INIT, and print data SDI, the logic circuit 51 generates drive signals to control the operation of the switching elements of the drivers 53a to 53n described later in the driver circuit 53. The logic circuit 51 outputs these drive signals to the level shift circuit 52.

[0031] The level shift circuit 52 converts the voltage level of the drive signal input from the logic circuit 51 using the drive power supply V1. The level shift circuit 52 outputs the converted voltage level drive signal to the driver circuit 53.

[0032] The driver circuit 53 will be described with reference to Figures 4 and 5. Figure 4 shows an example configuration of the driver IC and actuator. Figure 5 shows an example configuration of the driver. The driver circuit 53 is composed of multiple drivers 53a to 53n. The number of these drivers 53a to 53n is determined by the number of nozzles (or capacitive elements) provided on the actuator 42.

[0033] Each driver 53a to 53n is connected to one electrode of a series-connected capacitive element within each actuator 42. Each driver 53a to 53n receives drive power supplies V1 and V2 as input and outputs drive signals DRV1 to DRVn to drive the actuator 42. When drive signals DRV1 to DRVn are input from each driver 53a to 53n to the electrodes of the capacitive element, the volume of the pressure chamber changes. This changes the pressure in the pressure chamber, causing the ink inside the pressure chamber to be ejected from the ejection nozzle. As mentioned above, the drivers 53a to 53n are formed using a CMOS process.

[0034] Furthermore, a capacitor C1 (first capacitor) is placed before the driver IC 43 on the power supply line (first power supply line) of the drive power supply V1 for bypass purposes, and similarly, a capacitor C2 (second capacitor) is placed before the driver IC 43 on the power supply line (second power supply line) of the drive power supply V2.

[0035] In order to drive the actuator 42 at high speed, it is necessary to supply drive signals DRV1 to DRVn to each driver 53a to 53n instantaneously. Therefore, by pre-charging capacitors C1 and C2, drive power supplies V1 and V2 are supplied instantaneously to drivers 53a to 53n. Ceramic capacitors are preferred for these capacitors C1 and C2, and their capacitance values ​​are determined based on conditions such as assuming the voltage drop due to maximum power from the design value and satisfying the rise and fall time requirements of the drive waveform. In this embodiment, capacitors C1 and C2 are preferably of a capacitance of about 12 [μF].

[0036] In this embodiment, a protection circuit 47 is provided in the power supply line. Specifically, a fuse F1 (first fuse) is provided on the power supply line of the drive power supply V1 between capacitor C1 and driver IC 43. Similarly, a fuse F2 (second fuse) is provided on the power supply line of the drive power supply V2 between capacitor C2 and driver IC 43. These fuses F1 and F2 function as a protection circuit that, in the event of latch-up in driver IC 43, cuts off the power supply line, preventing drive power supplies V1 and V2 from being supplied to driver IC 43. The capacity and blowing timing of fuses F1 and F2 will be described later.

[0037] Next, we will explain drivers 53a to 53n with reference to Figure 5. The following explanation will use driver 53a as an example. The driver 53a uses transistors M1 and M3, which are made of PMOSFETs, and transistors M2 and M4, which are made of NMOSFETs. These are configured as switches using transistors M1 and M2, and switches using transistors M3 and M4. Of these, transistor M1 is configured as a switch connected to the drive power supply V1, transistor M2 is configured as a switch connected to GND, and transistors M3 and M4 are configured as switches connected to the drive power supply V2.

[0038] This driver 53a has four output patterns for the drive signal DRV. The first pattern outputs the voltage of the drive power supply V1 (first potential level), the second pattern outputs the voltage of the drive power supply V2 (second potential level), and the third pattern outputs the potential level of GND (ground) (voltage 0V), which are all different potential levels of the drive signal DRV. In addition, the fourth pattern puts the driver 53a into a high-impedance state where it does not output any drive signal.

[0039] The connection relationships between transistors M1 to M4 will be explained below. Transistor M1 has a drive power supply V1 applied to its source, a drive signal DRV output from its drain, and its back gate connected to the N-well region of a P-type semiconductor substrate. The drive power supply V1 is also applied to the N-well region. Transistor M2 has its source connected to GND, a drive signal DRV output from its drain, and its back gate connected to a P-type semiconductor substrate. The P-type semiconductor substrate is connected to GND.

[0040] Transistor M3 has the drive power supply V2 applied to its source, outputs the drive signal DRV from its drain, and its back gate is connected to the N well. The N well is supplied with the drive power supply V1. Transistor M4 has the drive power supply V2 applied to its source, outputs the drive signal DRV from its drain, and its back gate is connected to the P-type substrate. The P-type semiconductor substrate is connected to GND. The drains of the output terminals of transistors M1 to M4 are connected to the electrodes of the series-connected capacitive elements of their respective actuators. The drive power supply V2 is applied to these series-connected capacitive elements. The drive power supply V2 here is the potential of the common electrode of the actuator.

[0041] In the driver 53a configured in this way, when outputting voltage V1 (drive power supply V1) as the first drive signal DRV, transistor M1 is turned on and transistors M2, M3, and M4 are turned off. Similarly, when outputting voltage V2 (drive power supply V2) as the second drive signal DRV, transistors M3 and M4 are turned on and transistors M1 and M2 are turned off. When outputting GND (0V) as the drive signal DRV as the third drive signal DRV, transistor M2 is turned on and transistors M1, M3, and M4 are turned off. When setting the drive signal DRV to high impedance as the fourth drive signal DRV, all transistors M1 to M4 are turned off.

[0042] Referring to Figure 6, the stacked structure and equivalent circuit of drivers 53a to 53n will be explained. Figure 6 is a diagram showing the stacked structure and equivalent circuit of the drivers together.

[0043] An N-well region is formed on the P-type semiconductor substrate. A switching circuit consisting of transistors M1 to M4 is formed on the main surface of the P-type semiconductor substrate. A drive power supply V1 is applied to the N-wells, and the P-type semiconductor substrate is connected to GND.

[0044] In addition to the switching circuits of transistors M1 and M3 in these PMOSFETs, parasitic circuits exist in the vertical direction of the PMOSFET, which is the depth direction relative to the main surface of the P-type semiconductor substrate. These parasitic circuits are PNP-type transistors with the P-type diffusion layer as the emitter, the N-well region as the base, and the P-type substrate as the collector. Here, we will refer to these as transistors Q1, Q2, Q3, and Q4.

[0045] Similarly, in addition to the switching circuit of transistors M2 and M4 of the NMOSFET, a parasitic circuit exists in the vertical direction. This parasitic circuit is an NPN transistor with an N-type diffusion layer as the emitter, a P-type semiconductor substrate as the base, and an N-well region as the collector. Here, we will refer to these as transistors Q5, Q6, Q7, and Q8. Note that the sheet resistance of the N-well region is denoted as Rwell, and the sheet resistance of the P-type semiconductor substrate is denoted as Rsub.

[0046] Next, referring to Figures 7 and 8, we will explain the process of latch-up occurring, triggered by the output terminal DRV of drivers 53a to 53n. The following explanation will use driver 53a as an example. Figure 7 shows the flow of trigger current generated in the equivalent circuit of the parasitic circuit shown in Figure 6. Figure 8 shows the flow of current during latch-up in the equivalent circuit of the parasitic circuit. Figure 9 shows the flow of through-current during latch-up in the equivalent circuit of the parasitic circuit when a drive power supply V2 is supplied in addition to the drive power supply V1.

[0047] First, we will explain the generation of trigger current by referring to Figure 7. If the voltage of the drive signal DRV output from driver 53a exceeds the drive power supply V1 by 0.6V or more (for example, due to noise interference), the emitter-base junctions of transistors Q2 and Q4 are forward-biased. This bias causes a through-current i1 to flow from the output terminal side (drive signal DRV) through the bases of transistors Q2 and Q4 to the drive power supply V1 terminal side. Simultaneously, a through-current i2 flows through the collectors of transistors Q2 and Q4 to the GND side, which is the P-type semiconductor substrate. If the through-current i2 flowing to the GND side becomes large, the base-emitter junction of transistor Q8 is forward-biased.

[0048] As shown in Figure 8, a through-current i3 flows from the base of transistor Q8 to GND due to the bias. This through-current i3 forms the first A path. This through-current i3 acts as a trigger current, and a through-current i4 also flows through transistor Q1. This through-current i4 forms the first B path. The state in which these through-currents i3 and i4 are flowing is called latch-up. Once these through-currents i3 and i4 are flowing and the first A and first B paths are established, even if the voltage at the output terminal (drive signal DRV) drops, the first A and first B paths of the through-currents i3 and i4 flowing from the drive power supply V1 to GND are maintained, and the through-currents will continue to flow unless the supply of the drive power supply V1 is stopped. The first A and first B paths together are referred to as the first path.

[0049] Furthermore, in the state shown in Figure 8, if a drive power supply V2 is also supplied in addition to the drive power supply V1, then, as shown in Figure 9, after two first A and first B paths are established between the drive power supply V1 and GND through which through-currents i3 and i4 flow, a voltage drop occurs at the base of transistor Q3, and the emitter-base of transistor Q3 is forward-biased, establishing a second path through-current i5 flowing from the drive power supply V2 to GND. If latch-up is maintained in this state, the through-currents i3, i4, and i5 may become overcurrents.

[0050] When latch-up occurs in this way, and a first and second path are established between the drive power supply V1 and the drive power supply V2 due to the through-currents i3, i4, and i5, these through-currents i3, i4, and i5 can overcurrent and destroy or burn out the driver IC. Therefore, in this embodiment, first, the fuse F2 of the protection circuit 47 installed in the power supply line of the delayed-generating drive power V2 is blown. Subsequently, if the fuse F1 installed in the power supply line that supplies the drive power V1, which is a factor that maintains latch-up, is blown and the power supply of the drive power V1 is stopped, then all fault factors can be isolated (disconnected), and a situation that would lead to burnout due to overheating of the driver can be avoided.

[0051] Next, we will explain the arrangement of fuses F1 and F2 in the protection circuit 47 and capacitors C1 and C2 located in the power supply line, as well as the blowing current of fuses F1 and F2. As mentioned above, capacitor C1 is placed upstream of driver IC 43 on the power supply line of drive power supply V1. Similarly, capacitor C2 is placed upstream of driver IC 43 on the power supply line of drive power supply V2. The purpose of these capacitors C1 and C2 is, as mentioned above, to supply drive power supplies V1 and V2 to drivers 53a to 53n instantaneously by pre-charging them with charge in order to drive actuator 42 at high speed.

[0052] In this embodiment, as shown in Figure 3, fuses F1 and F2 are placed on the power supply line between capacitors C1 and C2 and driver IC 43. This arrangement, viewed from the head control unit 20 side, connects capacitors C1 and C2, fuses F1 and F2, and driver IC 43 in that order.

[0053] Conversely to this arrangement, for example, fuses F1 and F2 are placed before capacitors C1 and C2 on the power supply line. That is, as seen from the head control unit 20 shown in Figure 1, the fuses F1 and F2, capacitors C1 and C2, and driver IC 43 are connected in that order. In this opposite arrangement, when the normal drive power is turned on, the charging current flows to capacitors C1 and C2 after passing through fuses F1 and F2. In this case, there is a risk that the Joule integral value flowing through capacitors C1 and C2 will exceed the value that blows fuses F1 and F2. In other words, the arrangement of fuses F1 and F2, and capacitors C1 and C2 is not desirable.

[0054] Therefore, in this embodiment, as shown in Figure 3, fuses F1 and F2 are placed downstream of capacitors C1 and C2. This arrangement prevents the charging current to capacitors C1 and C2 that occurs when the drive power is turned on from passing through fuses F1 and F2, thus avoiding the blowing of fuses F1 and F2 due to the Joule integral value.

[0055] Next, with reference to Figures 10 and 11, we will explain the current flowing through fuses F1 and F2 and the blowing current. In the following explanation, driver 53a will be used as an example among drivers 53a to 53n. Figure 10 shows the blowing line L1 where the fuse blows, the line L2 where the fuse is less likely to blow due to its inrush current resistance, and the line L3 where the Joule integral (I^2*t) curve is less than 25% and the fuse is less likely to blow, with the Joule integral value on the vertical axis and time on the horizontal axis.

[0056] The specifications for fuses F1 and F2 define the burnout current as the current at which overcurrent flows through the power supply wiring of driver IC43 and causes burnout. A guideline is set for the current at which fuses F1 and F2 blow out, so as not to reach this burnout current, and this is defined as the dangerous current.

[0057] In the head control unit 20 and inkjet head unit 19 of this embodiment, the burnout current at which the driver 53a burns out is 3.5[A], as determined by experiment, so a dangerous current of approximately 3[A] is set. Furthermore, for the normal drive current, a fuse is selected that is 25% or less of the Joule integral (I^2*t) curve used for fuse selection, and is used in the region below the lines L2 and L3, which are less likely to blow.

[0058] Here, fuse F1 is used, which has a rated current of 1.25[A] and is designed to blow within 5 seconds when 250% of its rated current flows through it. With this fuse F1, the design value of the blowing current (first blowing current) is 3.125[A], which is sufficient to avoid burnout.

[0059] Next, the critical current setting for fuse F2 is the same as for fuse F1. However, under normal circumstances, the drive current for drive power supply V2 is set to a smaller value than that for the main drive power supply V1. Therefore, under normal circumstances, it would be considered acceptable to select fuse F2 with the same specifications as fuse F1. However, considering the possibility of latch-up, selecting the same specifications is not necessarily the best option for the following reasons.

[0060] As shown in Figure 9, when latch-up occurs, a path for through-current due to the drive power supply V1 is created in the parasitic circuit, and then, after a delay of about 5 [μs], a new path for through-current due to the drive power supply V2 is created in the same parasitic circuit. At this time, if fuses F1 and F2 are of the same specifications, when fuse F1 first blows, the overcurrent due to through-currents i3 and i4 decreases, and subsequently, fuse F2 does not blow. If fuse F2 does not blow, the through-current i5 continues to flow, and it is conceivable that the parts involved in the path of this through-current i5, for example, the switching element of the driver 53a shown in Figure 5, may be damaged or burned out due to overcurrent or temperature rise.

[0061] Furthermore, with the aforementioned dangerous current setting, it has been confirmed that if a latch-up occurs, the driver 53a will be damaged but not burned out if the time is approximately 30 [μs]. Therefore, the specifications of fuse F1 are selected so that it blows at the blowing position Fa indicated by the circle in Figure 10.

[0062] Furthermore, the capacitance of capacitor C1 (the charge to be charged) is set so that 20 μs after latch-up occurs, the through-current flowing through the power supply line becomes the Joule integral value on the blunt line L1 shown in Figure 10.

[0063] Fuse F2 can blow simultaneously with or before fuse F1 by selecting one with a small rated current and blowing current (second blowing current), taking into account that the initial voltage of the drive power supply V2 is 50% of the voltage of the drive power supply V1, the amount of charge stored in capacitor C2 is small, and the current flow is delayed by 5 [μs]. In other words, the timing of fuses F1 and F2 blowing can be adjusted by adjusting the magnitude of the Joule integral values ​​leading to the blowing of each fuse. Basically, it is set so that fuse F1 blows after or at the same time as fuse F2 blows. Of course, the selection of fuse specifications should ensure that the dangerous current at which blowing occurs and the normal drive current at which blowing does not occur are properly set, but if both conditions cannot be met, the capacitance of capacitor C2 may be changed.

[0064] Next, we will explain the blowing status of fuses F1 and F2 with reference to Figure 11. Figure 11 has the Joule integral value on the vertical axis and time on the horizontal axis, showing the blowing line L1 where fuse F1 blows and the blowing line L4 where fuse F2 blows.

[0065] When the driver IC latches up while power supplies V1 and V2 are supplied, a path for through-current (overcurrent) is established within the driver IC by power supplies V1 and V2, respectively. The overcurrent flowing through this path will destroy or burn out the driver IC.

[0066] To prevent this, first, if the fuse F2 located in the path of the through-current from the delayed-generating drive power supply V2 can be blown, and then the fuse F1 can be blown, the risk of destruction or burnout due to overheating can be avoided. In other words, if the fuse F1 located on the power supply line to which the drive power supply V1, which causes damage or burnout due to latch-up, is applied can be blown, all fault factors can be isolated, and thus the danger can be avoided.

[0067] Therefore, as shown in Figure 11, in this embodiment, fuse F1 is set to the position Fa indicated by the circle as the current that blows out, and fuse F2 is set to the position Fb indicated by the circle as the current that blows out. Specifically, fuse F1 has a rated current of 1.25[A] and is designed to blow out within 5 seconds when 250% of the rated current flows through it. With this fuse F1, the design value of the current that blows out is 3.125[A], which can be considered as not leading to burnout.

[0068] First, as an example of setting the blowing current for fuses F1 and F2, fuse F1 has a rated current of 1.25[A] and is designed to blow within 5 seconds when 250% of its rated current is applied. Fuse F2 has a rated current of 1[A] and is designed to blow within 5 seconds when 250% of its rated current is applied.

[0069] Fuse F1 blows 20 [μs] after latch-up occurs, with a Joule integral value of 0.004 [A^2*sec]. At this time, the effective value of the current IF1rms [A] is: IF1rms[A]=√(0.004[A^2*sec] / 20[μs]), IF1rms[A]=√(200)=14.1[A], This is the result. Furthermore, the amount of charge q1[C] discharged from capacitor C1 is, q1 = 14.1[A] * 20[μs] = 282[μC]. The amount of charge q1init[C] discharged from capacitor C1, which was initially charged, is q1init = 12[μF] * 30[V] = 360[μC]. Fuse F2 blows within 15 μs, effectively because the fuse blows 5 μs after the current is generated by the drive power supply V1, resulting in a Joule integral of 0.0015 A² sec. Therefore, the effective value of the current, IF2rms [A], is: IF1rms[A]=√(0.0015[A^2*sec] / 15[μs]), IF1rms[A]=√(100)=10[A], This is the result. Furthermore, the amount of charge q2[C] discharged from capacitor C2 is, q2 = 10[A] * 15[μs] = 150[μC].

[0070] The amount of charge q2init[C] discharged from capacitor C2, which was initially charged, is q1init = 12[μF] * 15[V] = 180[μC]. Thus, after latch-up occurs, the fuse F2 on the power supply line to which the drive power supply V2 is supplied is blown first, and simultaneously or with a delay, the fuse F1 on the power supply line to which the drive power supply V1 is supplied is blown. The aforementioned delay time (delay time) is determined during circuit design and is set appropriately according to the circuit configuration so that fuse F1 blows after fuse F2 blows. One method for determining the delay time is to make fuse F1 more difficult to blow than fuse F2. For example, a margin is added to the current that interrupts the circuit before burnout occurs, relative to the burnout current that causes the driver IC to burn out, to determine the critical current. By selecting the specifications of fuse F1 so that it blows at this critical current, the delay time until blowing can be maximized. In other words, the delay time is determined by selecting the specifications of fuse F1. Another method for determining the delay time is to make fuse F2 more easy to blow than fuse F1. For example, by selecting fuse 2, which melts at the minimum current value among those that do not melt under normal current, the melting time can be accelerated. In other words, by selecting the specifications of fuse F2, the timing of the melting of fuses F1 and F2 can be measured to determine the delay time.

[0071] To implement this sequence of fuse blowing, the rated current of fuse F2 is selected to be lower than that of fuse F1. This selection ensures that when latch-up occurs and a through-current flows from drive power supply V1, followed by a through-current from drive power supply V2, fuse F2 on the power supply line supplied by drive power supply V2 blows first, and simultaneously or with a delay, fuse F1 on the power supply line supplied by drive power supply V1 blows. This sequence of blowing isolates all potential fault factors and avoids the risk of burnout of components of driver IC43, including drivers 53a to 53n, due to the heat generated by the overcurrent caused by the through-current.

[0072] Furthermore, this embodiment of the present invention is presented as an example and is not intended to limit the scope of the invention. This embodiment can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. This embodiment and its variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0073] 1...Inkjet printer, 2...Host PC, 11...Control unit, 12...Display, 13...Operation unit, 14...Communication interface, 15...Transport motor, 16...Motor drive circuit, 17...Pump, 18...Pump drive circuit, 19...Inkjet head unit, 20...Head control unit, 21...Power supply, 22...Processor, 23...Memory, 24...Network, 31...Drive power supply V1 generation circuit, 32...Drive power supply V2 generation circuit, 33...Logic circuit power supply VDD generation circuit, 34...Control signal generation circuit, 35...I / F cable, 41...Head PC board, 42...Actuator, 43...Driver IC, 44...Polyimide film, 45...COF package, 46...Heat sink, 47...Protection circuit, 51...Logic circuit, 52...Level shift circuit, 53...Driver circuit, 53a~53n...Driver.

Claims

1. An actuator having a capacitive load with multiple capacitive elements connected to eject ink, A driver IC that drives the capacitive element of the actuator, A first capacitor is provided in the first power supply line that supplies power to the driver IC at a first potential, A second capacitor is provided in the second power supply line that supplies power to the driver IC at a second potential lower than the first potential, A first fuse with a first blown current is provided in the first power supply line between the first capacitor and the driver IC, A second fuse having a second blowing current smaller than the first blowing current is provided in the second power supply line between the second capacitor and the driver IC, It is equipped with, An inkjet head unit that, when latch-up occurs in the driver IC and a first path through which a through-current related to the first power supply line flows, and a second path through which a through-current related to the second power supply line flows, blows the second fuse to interrupt the second path, and simultaneously or with a delay blows the first fuse to interrupt the first path, thereby electrically isolating the driver IC from the first power supply line and the second power supply line.

2. The inkjet head unit according to claim 1, wherein the driver IC has a structure formed by a CMOS process.

3. A transport motor for transporting printing media, An actuator that ejects ink onto the printing medium being transported by the transport motor, A head control unit that supplies drive power and control signals to the actuator, It is equipped with, A driver IC for driving the capacitive element of the actuator, A first capacitor is provided in the first power supply line that supplies power to the driver IC at a first potential, A second capacitor is provided in the second power supply line that supplies power to the driver IC at a second potential, which is also smaller than the first potential. A first fuse with a first blown current is provided in the first power supply line between the first capacitor and the driver IC, A second fuse having a second blowing current smaller than the first blowing current is provided in the second power supply line between the second capacitor and the driver IC, It is equipped with, An inkjet printer in which, when latch-up occurs in the driver IC, and a first path through which a through-current related to the first power supply line flows and a second path through which a through-current related to the second power supply line flows, the second fuse blows to interrupt the second path, and simultaneously or after a set time delay, the first fuse blows to interrupt the first path, thereby electrically isolating the driver IC from the first power supply line and the second power supply line.

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