Design and manufacturing of improved power devices

Abstract

To provide design of an improved power device and a manufacturing method of the same.SOLUTION: A device comprises a unit cell on a SiC substrate 102, which is a part of a pattern within a semiconductor that is repeated within the semiconductor. The unit cell comprises a first source region 108 of a first conductivity type, a second source region 110 of the first conductivity type, a well region 106 of a second conductivity type, a silicide layer 120, a gate insulating film 114. The second source region of the first conductivity type has a thickness smaller than the thickness of the first source region of the first conductivity type.SELECTED DRAWING: Figure 48A

Description

[Technical Field]

[0001] Cross-reference of related applications This application is a continuation of U.S. Patent Application No. 16 / 431,655, titled "DESIGN and MANUFACTURE OF IMPROVED POWER DEVICES," filed on March 13, 2019, and U.S. Patent Application No. 17 / 2019, titled "DESIGN and MANUFACTURE OF SELFALIGNED POWER DEVICES," filed on June 9, 2021. U.S. Patent Application No. 17 / 231,301, titled "Design AND MANUFACTURE OF ROBUST, HIGH-PERFORMANCE DEVICES," filed on August 25, 2020; "IMPROVED PERFORMANCE SIC SCHOTTKY DIODES," filed on April 28, 2021; "IMPROVED PERFORMANCE SIC SCHOTTKY DIODES," filed on January 31, 2020; "IMPROVED PERFORMANCE SIC SCHOTTKY DIODES," filed on November 16, 2020; U.S. Patent Application No. 16 / 670,963, filed on October 31, 2019; "SILICON CARBIDE POWER DEVICES," filed on January 14, 2020; U.S. Patent Application No. 16 / 741,800, titled "Design AND MANUFACTURE OF POWER DEVICES HAVING INCREASED CROSS OVER," filed on July 31, 2020. "current"; U.S. Patent Application No. 17 / 227,897, filed April 12, 2021, "Design AND MANUFACTURE OF POWER DEVICES" "HAVING INCREASED CROSS OVER current"; U.S. Patent filed April 12, 2021. U.S. Patent Application No. 17 / 227,936, Title of Invention, "Design and Manufacture of a Power Device Having Increased Crossover Current," and U.S. Patent Application No. 17 / 227,951, filed on April 12, 2021, The invention is titled "Design and manufacture of a power device with increased crossover current," and U.S. Patent Application No. 17 / 007,014, filed on August 31, 2020, titled "Polycrystalline orientation This includes “inverting channel devices”. This application claims priority to U.S. Provisional Application No. 63 / 072,473, “POWER DEVICES,” filed on 31 August 2020, and the foregoing application and its disclosures are incorporated herein by reference in their entirety.

[0002] This invention relates to vertical silicon carbide (SiC) double implantation metal oxide semiconductor field effect This relates to power semiconductor devices using transistors (DMOSFETs). A MOSFET is a specific type of MOSFET designed to handle considerable power levels.

[0003] Furthermore, the present invention relates to interdigitated N-type and P-type diodes such as JBS (Junction Barrier Schottky) diodes, MPS (Merged PiN / Schottky) diodes, MOSFETs (Metal oxide semiconductor field effect transistors), and JFETs (Junction field effect transistors). This relates to 4H-SiC devices, including diodes and transistors having regions. [Background technology]

[0004] Silicon-based power devices have long dominated applications in power electronics and power systems. Meanwhile, SiC (SiC) has a band gap of Eg = 1.1 eV. SiC has a relatively wide bandgap (Eg = 3.3 eV) and has a higher blocking voltage than Si. SiC has a higher dielectric breakdown electric field (3 × 10⁻¹⁰) compared to Si. 6 V / cm ~ 5 × 10 6(V / cm) (The dielectric breakdown electric field of Si is 0.3 × 10⁻⁶) 6 SiC has a better thermal conductivity (3.7 W / cm-K) than Si (1.6 W / cm-K). SiC has been chosen as the material for power MOSFETs. However, although the introduction of SiC power MOSFETs to the commercial market has been successful, several major reliability issues have not been fully resolved. It has not been decided. [Source: SiC Power MOSFET, A. Lelis, D. Habersat, R. Green, and E.] Mooro of US Army Research Laboratory, Publisher: ECS Transactions, 58(4)87-93(2013), DOI: 10.1149]

[0005] SiC has polymorphic crystal structures known as polytypes such as 3C-SiC, 4H-SiC, and 6H-SiC. It exists as a type of [unclear]. Figure 1A shows the structure of a conventional SiC DMOSFET reported by BJ Baliga in Advanced High-Voltage Power Device Concepts (Springer Press, 2011). Figure IB shows the simulated electric field contour for the conventional SiC DMOSFET structure shown in Figure 1A. Figure IB shows the electric field distribution near the surface of the 5kV shielded 4H-SiC inversion-mode power MOSFET structure. The electric fields in the junction-gate field-effect transistor (JFET) region and the gate region were investigated. A sharp peak in the electric field at the edge of the P+ shielding region can be observed in this prior art device, which results in a high electric field in the gate oxide, thereby leading to insufficient performance of this MOSFET device. Figure 1C shows the electric field distribution of a shielded 4H-SiC inverted-mode MOSFET. The simulation results in the figure show an electric field with a height of 4 MV / cm in the gate oxide of the prior art SiC DMOSFET structure shown in Figure 1A.

[0006] A typical SiC MOSFET device structure, as shown in Figure 1A, is particularly suitable for high drain bias ( During rocking mode operation, a high electric field is introduced within the gate oxide layer, resulting in high electric field concentration at the corners of the p-well region. High critical electric field for fracture in 4H-SiC (3MV / cm) This results in a very high electric field (>5 MV / cm) in the gate oxide. Fowler-Nordheim tunneling currents are observed in the gate oxide at such high electric fields, This can result in trapped charges in the gate oxide, which leads to insufficient device reliability.

[0007] Si manufacturing processes use techniques such as dopant diffusion, but these conventional manufacturing processes are not feasible for producing SiC devices because the diffusion coefficient in SiC is negligible at temperatures below 1800°C. SiC devices are manufactured by ion implantation in both the source and p-well regions, but ion implantation and deep ion implantation are difficult in SiC. Therefore, improved power devices to address the reliability issues of SiC power MOSFETs There has been a long-standing need for this.

[0008] Furthermore, the limited (10-25 cm² / Vs) MOS channel achievable on conventional SiC planar DMOSFETs To prevent a significant degradation of the overall on-resistance of the power MOSFET due to the mobility, it is necessary to form a MOS channel with a submicron channel length. If the N+ source regions are formed using different masks, the alignment of the two masks will be impaired. Good results in different channel lengths on both sides of the cell. This avoids a drop in threshold voltage (Vth). To reduce the breakdown voltage (Vbr), the N+ mask is self-aligned with respect to the P-well. Ru. [Source: Design and Fabrication of 1.2kV 4H-SiC DMOSFET by R. Huang et al. published in 2016 13th China International Forum on Solid State Lighting: International Forum on Wide Bandgap Semiconductors C] The MOSFET channel region is formed as a result of the offset between the p-well and the N+ source region in the DMOSFET structure. The p-well and the N+ source region are two separate masking regions. When formed by steps, a certain amount of lithographic misalignment inevitably exists between these levels, resulting in different (or asymmetrical) MOS channel lengths on the two sides of the unit cell. Lithographic misalignment between two masking levels using projection lithography techniques, which are typically used in the manufacturing of high-capacity semiconductors, ranges from + / -0.05 μm to + / -0.2 μm. This can be in the range of μm or more, which sets a lower limit for MOS channel lengths that are actually achievable without significant asymmetry. If the target channel length is 0.5 μm, a misalignment (alignment error) of + / - 0.2 μm between the N+ source and the p-well masking step is within the unit cell. This can result in a MOS channel length of 0.3 μm on one side and a MOS channel length of 0.7 μm on the other side of the unit cell. The on-resistance of the MOSFET increases with higher MOS channel lengths, A MOS channel length shorter than the optimal length can lead to undesirable degradation of the gate threshold voltage (Vth). This can lead to undesirable effects and other short-channel effects such as drain-induced barrier reduction (DIBL).

[0009] Self-alignment techniques to eliminate misalignment between P-wells and N+ source regions This has been proposed in the literature. It is defined by sidewall spacer deposition and etching. Self-aligned MOS channel formation with a channel length is one such technique. Figure 9 shows R. Huang et al. reported in "Design and Fabrication of 1.2 kV 4H-SiC DMOSFET" This is a conventional process flow of a self-aligned injection technique having a channel length defined by sidewall spacer deposition and etching.

[0010] Furthermore, if SiC power MOSFETs share many similarities with silicon MOSFETs, then many problems arise. There are still some significant differences. In particular, the wide bandgap properties of 4H-SiC (EG=3.26 eV) present challenges regarding inversion layer mobility and reliability in the passivated dielectric layer, while also resulting in low intrinsic carrier concentration and a high critical electric field, which is both an advantage and a disadvantage." [Source: GE] Challenges in SiC Power MOSFET Design by Kevin Matocha of the Global Research Center Niskayuna, NY, USA, Semiconductor Technology Laboratory, December 12-14, 2007, MD, College Park, USA, 2007

[0011] In the typical SiC planar MOSFET structure shown in Figure 1A, the metal oxide semiconductor (MOS) channel is made of SiC Formed on the horizontal or 0001 crystal plane. Channel mobility or electric field on the 0001 crystal plane of SiC. The effect mobility tends to be lower compared to vertical sidewalls or so-called 11-20 or 10-10 crystal planes. The channel mobility or field-effect mobility on the 0001 crystal plane of SiC is in the range of 15-25 cm² / V-sec, compared to silicon MOSFETs, which can exceed 350 cm² / V-sec. When fabricating planar SiC DMOSFETs, the on-resistance tends to be higher, and the MOSFET's field-effect channel This is limited by channel mobility. Therefore, there has been a long-standing need for improved power devices that address the low channel mobility and high on-resistance in SiC MOSFETs.

[0012] Furthermore, the threshold voltage of a power MOSFET is a critical design parameter from the application site. In most system applications, the minimum threshold voltage is maintained above 1 volt to reduce noise. It must provide resistance (immunity) to turn-on caused by voltage spikes resulting from this. At the same time, the voltage available to generate charge in the channel inversion layer is determined by (VG-VT), where VG is the applied gate bias and VT is the threshold voltage. [Source: BJ Baliga, Silicon Carbide Power Devices, Springer Press (2005), Page 234]

[0013] Figure 22 [Source: BJ Baliga, Silicon Carbide Power Devices, Springer Press (2005), Page 235] shows the threshold voltage of 4H-SiC planar MOSFETs with a gate oxide film thickness of 0.1 microns. The results obtained for silicon power MOSFETs with the same gate oxide film thickness are also provided in the figure for comparison.

[0014] To achieve a lower RDS, planar gate SiC MOSFETs with high withstand voltage ratings are used. In this design, the channel length (LCH) is kept as short as possible, and most of the conduction losses associated with the channel are reduced. Reducing this is a common practice. The trade-off in this process is that as the channel length decreases, the threshold voltage (VTH) roll-off at high drain bias and Drain leak under high drain bias (I L This includes, but is not limited to, an increase in, This makes the system more susceptible to undesirable phenomena such as the DIBL effect (drain-induced barrier reduction effect), which can cause poor vice performance. A conventional approach to mitigate this problem is to uniformly increase the doping concentration in the channel region, but this approach suffers from being higher than the optimal gate threshold voltage and on-resistance, which can offset the gain achieved from reducing the channel length.

[0015] Furthermore, there has been a continuing trend toward higher operating frequencies, particularly in motor control and switch-mode power supplies. In power supplies, high-frequency operation is attractive due to the reduction of passive component size (inductors and capacitors) and power loss, resulting in more efficient and compact system designs. To achieve higher frequency operation, modifications are necessary. It is essential to use power transistors and rectifiers with improved switching performance. The superior electronic parameters of SiC allow for dramatic improvements in this regard.

[0016] Figure 27 shows an MPS (Multi-Purpose System) consisting of parallel-connected alternating mating pins and Schottky diodes. This is the structure of the prior art diode. [T. Kimoto and JA Cooper, Fundamentals of Silicon Carbide Technology, IEEE Press (2014), page 296]. The prior art MPS diode shown in Figure 27 has a metal layer on top that forms an ohmic contact to the P+ region and a Schottky contact to the n region, and thus the entire device consists of alternating mated Schottky and pin diodes connected in parallel. The P+ anode regions are positioned far enough apart so that their depletion regions do not contact under zero or forward bias. This leaves a conductive path through the drift region between each Schottky or non-Schottky contact and the N+ substrate. When a forward bias is applied, the Schottky or non-Schottky region conducts first because the current density of the Schottky barrier diode is orders of magnitude higher than that of the pin diode at the same forward voltage. Thus, the Schottky or non-Schottky region effectively clamps the voltage drop across the pin region, which does not conduct. As a result, virtually all forward current is due to electrons injected from the n-drift region via Schottky or non-Schottky contact to the metal. The P+ region is Since no holes are injected into the lift region, minority carrier charge does not accumulate, the turn-off transient is fast, and switching losses are minimized. In the absence of conductivity modulation, the series resistance of the drift region is determined by its thickness and doping. This relatively high resistance results in a voltage drop VDR that dominates the total voltage drop at high currents. In Schottky diodes, pure This is problematic under high-surge current events because Schottky diodes can overheat and potentially have catastrophic consequences.

[0017] Furthermore, [A] A silicon carbide (SiC) device may include a gate electrode disposed on a SiC semiconductor layer, the SiC semiconductor layer having a drift region having a first conductivity type, and a well region disposed adjacent to the drift region, the well region having a second conductivity type, and It includes a source region having a first conductivity type, which is located adjacent to the source region It includes a contact region and a pinch region, the pinch region being partially located below the gate electrode, and the sheet doping density in the pinch region is 2.5 × 10⁻¹⁶ 14 cm -2 The pinch region is less than the nominal current density of the SiC device, which increases the resistance of the source region. It is configured to deplete with current density. [Source: Silicon Carbide Device and Method for Manufacturing the Same] [Peter Almem Losee, Ljubisa Dragoljub Stevanovic, Gregory Thomas Dunne, Alexander Viktorovich Bolotnikov, published February 20, 2018 as US9899512B2] ,

[0018] US20190013312A1 discloses body regions numbered 3 and 5, respectively, which house the first and second source regions 4 and 6 of type N and extend from the upper surface 2A into the interior of the body regions 3 and 5, and "the first metal The crystalline layer extends onto the first surface and comes into direct contact with the injected structure and JFET region to form a JBS diode. [Source: Silicon Carbide MOSFET Devices with Integrated Diodes and Their Manufacturing Processes, Mario Giuseppe Saggio, Simone RASCUNA, published at the USPTO on January 10, 2019].

[0019] "The n-MOSFET device (11) has an n-type channel (2) between the substrate (1) and the gate structure (7, 8)." Channel (2) is formed by a layer of n-doped germanium of a thickness such that channel (2) is completely depleted without an applied gate voltage, thereby causing device (11) to operate in storage mode. [Source: Germanium n-MOSFET device and method of fabrication, Daniele Caimi, Athanasios Dimoulas, Jean Fompeyrine, Chiara Marchiori, Christophe P. Rossel, Marilyne Sousa, Axelle M. Tapponnier, David J. Webb, published as WO2011013042A]

[0020] US9318597B2 discloses a semiconductor device including a vertical field-effect transistor (FET) and a bypass diode. Furthermore, the vertical FET device comprises a substrate and a drill formed on the substrate. A drift layer, a gate contact, and a first surface of the drift layer opposite the substrate are arranged on the first surface. The invention includes multiple source contacts, a drain contact located on the surface of the substrate opposite the drift layer, and multiple junction implants, each of which is laterally separated on the surface of the drift layer opposite the substrate and extends downward toward the substrate, and each of one or more bypass diodes is formed by placing a Schottky metal contact on the first surface of the drift layer, with each Schottky metal contact running between two of the multiple junction implants. [Source: Published as US9318597B2 by the USPTO on April 19, 2016. Power transistor by Vipindas Paia, Edward Robert Van Brunt, Lin Cheng, and John Williams Palmour] [Layout configuration for integrating Schottky contacts into the device]

[0021] US9876104B2 is a multi-cell MOSFET containing a MOSFET cell with integrated Schottky diodes. A device is disclosed, wherein the MOSFET includes an n-type source region formed within a p-type well region formed within an n-type drift layer, a p-type body contact region formed around the MOSFET, and the source metallization of the device is adjacent to the p-type body contact region of the device. It forms a Schottky contact with an n-type semiconductor region. [Source: Published on January 23, 2018 as US9876104B2, by Kevin Matocha, Kiran Chatty, and Sujit Ban]

[0022] US8436367B1 is a "muted" channel conduction, a negative temperature coefficient for channel mobility, and Field-effect (MOSFET, IGBT, etc.) SiC power MOSFETs with "stabilized" source resistance in the field (in situ) and optimized thermal management of the cell for an increased safe operating area. A semiconductor device is disclosed. Control of the location of the zero-temperature crossover point (ZTCP) related to drain current is achieved by partitioning between "active" and "inactive" channels, and by adjusting the carrier mobility within the channel over a temperature range of interest. [SiC Power Vertical DMOS with Increased Safe Operating Area, Dumitru Sdrulla, Marc Vandenberg, published at the USPTO on May 7, 2013, as US8436367B1]

[0023] Considering the knowledge of those skilled in the art, in order to overcome performance and reliability issues, an increased third element Power devices with limited crossover current have been needed for many years.

[0024] Furthermore, Figure 67A shows two implementation forms of power MOSFETs: vertical planar DMOSFETs and vertical trench UMOSFETs. The term DMOSFET is derived from the silicon device of the same name, and here The n+ source region and p-base region are formed by the diffusion of n-type and p-type impurities through the same mask opening (hence, a "double diffusion" MOSFET). In SiC, the same structure is formed by double implantation. The term UMOSFET derives from its U-shaped geometric form, although the term trench MOSFET is also used. Historically, the first SiC power MOSFETs were UMOSFETs, but they were quickly joined by ion-implanted DMOSFETs. [Source: T. Kimoto, JA Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press (2014), pages 320-324.]

[0025] Due to its trench shape, UMOSFETs present both opportunities and challenges compared to planar devices such as DMOSFETs. Because the MOS channel is oriented perpendicular to the surface, UMOSFETs can be fabricated with a smaller surface area than DMOSFETs. Since it is determined by the gate acid, it is also easy to form short submicron channels. However, MOS channels are formed on etched nonpolar surfaces of the crystal, and the gate acid The properties of the ionized material differ from those on the (1000) plane. Channel mobility or field-effect mobility on the 0001 crystal plane tends to be lower compared to vertical sidewalls or the so-called 11-20 or 10-10 crystal planes. Channel mobility can range from 15 to 25 cm² / Vs on the 1000 plane, but can reach heights of 60 to 80 cm² / Vs on the 11 to 20 or 1010 crystal planes of SiC [SOURCE: T. Kimoto, JA Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press (2014), pages 320-324].

[0026] Figures 67B and 67C show the main resistances in the vertical DMOSFET and UMOSFET, respectively, clearly demonstrating that the device geometry effectively eliminates the JFET resistance present in the DMOSFET. Figure 67(D) shows the electric field in a blocking UMOSFET, where the trench corners are key locations for significant electric field concentration. Since the oxide electric field is approximately 2.5 times higher than the semiconductor peak electric field (according to Gauss's law of electrostatics), this is a serious problem inherent to UMOSFET device design. [Source: T. Kimoto, JA Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press (2014), pages 320-324]

[0027] Therefore, there has been a long-standing need to combine the desirable features of planar DMOSFETs and trench UMOSFETs into a single device that can be advantageously and flexibly designed to leverage the specific advantages of each device structure for a given application. Furthermore, there has long been a need to incorporate junction barrier Schottky (JBS) or combined PiN Schottky (MPS) rectifier elements into hybrid DMOSFET / UMOSFET device geometries. [Overview of the project]

[0028] One or more aspects of the present invention are disclosed herein.

[0029] In one embodiment, the device is described herein. The device has unit cells on a SiC substrate. The unit cell comprises a gate insulating film, a trench in the well region, and a second conductivity type It comprises a first sinker region having a second conductivity type and a second sinker region having a second conductivity type. The first sinker region has a depth equal to or greater than the depth of the well region. Each of the sinker region and the second sinker region is in contact with the region having the first conduction type to form a pn junction.

[0030] In one embodiment, the device comprises a semiconductor metal-insulator semiconductor transistor component.

[0031] In another embodiment, the well region is adjacent to the insulator-semiconductor interface, and the first conduction-type source region It is formed within the well region.

[0032] In yet another embodiment, the depth of the trench is greater than or equal to the thickness of the source region.

[0033] In yet another embodiment, the first sinker region is located below the trench.

[0034] In yet another embodiment, the depth of the second sinker region is smaller than the depth of the first sinker region.

[0035] In yet another embodiment, the depth of the second sinker region is greater than the depth of the well region.

[0036] In yet another embodiment, the device has a gate insulating film of 4 milliohms / cm². 2 It has an on-resistance of less than 1.5 volts, a gate threshold voltage greater than 1.5 volts, a breakdown voltage greater than 500 volts, and an electric field of less than 3.5 megavolts / cm.

[0037] In another embodiment, a device including a unit cell is described on a SiC substrate. The unit cell is The device comprises a gate insulating film, a trench in the well region, a first sinker region of the second conductivity type, a second sinker region of the second conductivity type, and a source region. The source region is the second sinker It is in direct contact with the region.

[0038] In one embodiment, the device comprises a semiconductor metal-insulator transistor component.

[0039] In another embodiment, the unit cell comprises a first conductive semiconductor body having a drift zone. The device further comprises a second conduction-type well region adjacent to the insulator-semiconductor interface, and a first conduction-type source region formed within the well region.

[0040] In yet another embodiment, the depth of the trench is equal to or greater than the thickness of the source region.

[0041] In yet another embodiment, the trench depth is greater than the depth of the source region.

[0042] In yet another embodiment, the device calculates the avalanche energy in joules by dividing it by the total die area in centimeters squared, which is 10 joules / cm². 2 It possesses avalanche energy exceeding that.

[0043] In yet another embodiment, the avalanche defect is located within the unit cell.

[0044] In another embodiment, a device comprising a unit cell on a SiC substrate is disclosed. The device comprises a gate insulating film, a trench within the well region, a first sinker region of a second conductivity type, a second sinker region of a second conductivity type, and a source region. The first sinker region has a depth greater than the depth of the second sinker region. The second sinker has a width greater than the width of the first sinker.

[0045] In another embodiment, the first sinker region is located below the trench.

[0046] In yet another embodiment, the depth of the second sinker region is smaller than the depth of the first sinker region.

[0047] In yet another embodiment, the depth of the second sinker region is greater than the depth of the well region.

[0048] In yet another aspect, a device including a unit cell on a silicon carbide (SiC) substrate is disclosed. The unit cell includes a first source region of a first conductivity type, a second source region of the first conductivity type, a well region of a second conductivity type, and a silicide layer. The device includes a vertical silicon carbide (SiC) double implantation (dual implantation) metal oxide semiconductor field effect transistor (DMOSFET) having a drain terminal on the back surface of the SiC substrate and a source terminal on the top surface of the SiC substrate. The second source region of the first conductivity type has a thickness thinner than that of the first source region of the first conductivity type. The second source region of the first conductivity type is interspersed between the well region of the second conductivity type and the silicide layer. The second source region of the first conductivity type includes a sheet of the source region located between the recessed SiC trench region and the well region of the second conductivity type.

[0049] In one embodiment, the sheet of the source region includes a thin sheet of the source region.

[0050] In another embodiment, the second source region of the first conductivity type includes at least one of (a) a target thickness and (b) a target doping concentration.

[0051] In yet another embodiment, the target thickness of the second source region of the first conductivity type ranges from 1 nm to 1 μm, and the target doping concentration ranges from 10 cm 15 cm -3 to 10 21 cm -3 .

[0052] In yet another embodiment, the second source region of the first conductivity type includes a sheet of the source region located between the silicide layer and the well region of the second conductivity type.

[0053] In yet another embodiment, the device can carry a drain current of less than negative 500 milliamperes with a drain voltage of negative 3 volts.

[0054] In yet another embodiment, a device is provided that includes a unit cell on a silicon carbide (SiC) substrate. The unit cell comprises a first conductivity type source region, a second conductivity type well region, and a second conductivity type seed region. It comprises a rud region. The second conductivity type shield region is confined within the second conductivity type well region.

[0055] In one embodiment, the second conductivity type shielding region is located within the metal oxide semiconductor field-effect transistor (MOSFET) channel.

[0056] In another embodiment, the second conductive shield region is positioned opposite the edge of the second conductive well region. And it will be located closer.

[0057] In yet another embodiment, the doping concentration in the second conductivity type well region is non-uniform in the lateral direction. be.

[0058] In yet another embodiment, the doping concentration in the second conductive shield region is higher than the doping concentration in the second conductive well region.

[0059] In yet another embodiment, the second conductive shielding region extends beyond the vertical range of the second conductive well region.

[0060] In yet another embodiment, the device further trenches within a second conductive well region. The trench region has a depth greater than or equal to the thickness of the first conductivity type source region.

[0061] In yet another embodiment, the device comprises a gate oxide layer in contact with a second conductivity type well region and a first conductivity type source region. The device is a double implantation metal acid It is equipped with a monoxide field-effect transistor (DMOSFET).

[0062] In yet another embodiment, the device comprises a plurality of second conductivity type shielding regions within a metal oxide semiconductor field-effect transistor (MOSFET) channel.

[0063] In yet another embodiment, a plurality of second conductive shield regions are located closer to the edge of the second conductive well region.

[0064] In yet another embodiment, a plurality of second conductive shielding regions extend beyond the vertical extent of the second conductive well region.

[0065] In yet another embodiment, a second conductive shield region is embedded within a second conductive well region.

[0066] In yet another embodiment, a device comprising a unit cell on a silicon carbide (SiC) substrate is disclosed. The device comprises a first conductive type source region, a second conductive type well region, and a second conductive type It comprises a shielding region. The second conductivity type shielding region is confined and incorporated within the second conductivity type well region. The second conductivity type shielding region shields the MOSFET (metal oxide semiconductor field-effect transistor) channel from the high potential applied to the drain terminal.

[0067] In one embodiment, the device further comprises a trench region within a second conductive well region. The inch region has a depth equal to or greater than the thickness of the first conductive source region.

[0068] In another embodiment, the device has a gate threshold voltage greater than 2.5 volts and a gate of 0 volts. Breakdown voltage exceeding 3300 volts at source-to-source voltage and resistance of 15 milliohms / cm² 2It features an on-resistance of less than 1500 volts and a short-circuit tolerance time of more than 4 microseconds at a drain voltage of 1500 volts.

[0069] In yet another embodiment, the device has a gate threshold voltage exceeding 2 volts, a breakdown voltage exceeding 1200 volts with a gate-source voltage bias of 0 volts, and a resistance of 4.5 milliohms / cm². 2 Less than 2.5 microseconds on-resistance and short-circuit tolerance at 800 volts drain voltage. It is equipped with the following.

[0070] In yet another embodiment, the device has a gate threshold voltage of 2.5 volts or more, a gate-source voltage of 0 volts, a dielectric breakdown voltage of more than 6500 volts, and resistance of 50 milliohms / cm². 2 It features an on-resistance of less than 3600 volts and a short-circuit withstand time of more than 4 microseconds at a drain voltage of 3600 volts.

[0071] In yet another embodiment, the device has a gate threshold voltage of 2.5 volts or more, a breakdown voltage of over 10,000 volts at a gate-source voltage of 0 volts, and a resistance of 100 milliohms / cm². 2 It features an on-resistance of less than 5000 volts and a short-circuit withstand time of more than 4 microseconds at a drain voltage of 5000 volts.

[0072] In yet another embodiment, the device has a gate threshold voltage of 2.5 volts or more, a breakdown voltage of over 13,000 volts at a gate-source voltage of 0 volts, and a resistance of 400 milliohms / cm². 2 It features an on-resistance of less than 10,000 volts and a short-circuit withstand time of more than 4 microseconds at a drain voltage of 10,000 volts.

[0073] In yet another embodiment, the second conductive shielding region is in the off state and blocking operation. Between the two, the metal oxide semiconductor field-effect transistor (MOSFET) channel is shielded from the high potential applied to the drain terminal.

[0074] In yet another embodiment, the following method is described herein. This method involves silicon carbide (SiC) A metal oxide semiconductor field-effect transistor (MOSFET) is formed, and a second conductivity type well region is formed. This completes the process, forming a first conductive source region within the second conductive well region, and a second conductive seal This includes forming a shield region. The second conductivity type shield region is located outside the first conductivity type source region.

[0075] In one embodiment, the second conductivity type shield region is located within the second conductivity type well region.

[0076] In another embodiment, the second conductive shield region extends beyond the second conductive well region.

[0077] In yet another embodiment, the SiC MOSFET is 10 14 ~10 18 cm -3 It is manufactured on SiC epitaxial wafers, including doping in the range of 1 micrometer (μm) to 300 micrometers (μm).

[0078] In yet another embodiment, the second conductive well region is formed by a silicon dioxide layer, nitrogen Silicon oxide layer, polysilicon layer, silicon oxynitride layer, 50 nanometers to 5 micrometers Depositing a hard mask containing at least one of a metal layer having a total thickness in the range of, patterning the hard mask, and etching the hard mask. This involves using a second conductive ion for ion implantation and epitaxial growth. This includes performing one of the following steps: The step of performing ion implantation is performed in the range of 10 keV to 1000 keV. With the surrounding energy, and 10 12 cm -2 ~10 15 cm -2 With injection doses in the range of, the second conductive type io This includes injecting a second conductive ion, which comprises one of aluminum and boron.

[0079] In one embodiment, forming a second conductive shield region includes forming a second conductive shield region that is closer to the edge of the second conductive well region.

[0080] In another embodiment, forming a second conductivity type shield region includes forming a second conductivity type shield region confined within a second conductivity type well region.

[0081] In yet another embodiment, this method further includes forming a metal oxide semiconductor field-effect transistor (MOSFET) channel.

[0082] In yet another embodiment, the formation of a second conductive shielding region is a metal oxide semiconductor. Forms a second conductive shielding region that contacts the field-effect transistor (MOSFET) channel. This includes the following.

[0083] In yet another embodiment, the formation of a second conductive shielding region is a metal oxide semiconductor. Multiple second conductive seals that contact the field-effect transistor (MOSFET) channel. This includes forming a domain.

[0084] In yet another embodiment, the first conductivity type source region is formed by nitrogen ions and This includes using one of the ions to form a first conductivity type source region.

[0085] In yet another embodiment, this method forms a gate oxide layer, a polysilicon gate layer, an interlayer insulating film (ILD) layer, and a silicide region. This further includes doing so and forming an interconnect metal layer.

[0086] In yet another embodiment, forming the gate oxide layer involves performing either thermal oxidation and / or a stacked combination of chemical vapor deposition (CVD) of one dielectric layer from among silicon dioxide, silicon nitride, and silicon oxynitride layers. The gate oxide layer is formed with a thickness ranging from 10 nanometers to 100 nanometers.

[0087] In yet another embodiment, forming a polysilicon gate layer involves depositing a polysilicon layer via in-situ doping and subsequent drive-in doping using one of plasma chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD).

[0088] In yet another embodiment, the formation of the interlayer dielectric (ILD) layer is a silicon dioxide layer, a nitride layer. At least one of a silicon dioxide layer and a silicon oxynitride layer, as well as a silicon dioxide layer, nitride The process involves depositing one of the following stacking combinations: a silicon layer and a silicon oxynitride layer. The ILD layer has a thickness of 50 nanometers or more.

[0089] In yet another embodiment, the silicide region is formed on the exposed SiC surface by nickel This includes forming a lucilicide region.

[0090] In yet another embodiment, forming a second conductive shield region includes forming a second conductive shield region that extends beyond the vertical extent of the second conductive well region. nothing.

[0091] In yet another embodiment, the following method is described herein. This method involves silicon carbide (SiC) Forming a metal oxide semiconductor field-effect transistor (MOSFET) and a second conductivity type well The process includes forming a region, forming a first conductivity type source region within a second conductivity type well region, and forming a second conductivity type shield region. The second conductivity type shield region is located outside the first conductivity type source region. The doping concentration in the second conductivity type well region within the MOSFET (metal oxide semiconductor field-effect transistor) channel is non-uniform. At least a portion of the second conductivity type shield region is located within the second conductivity type well region.

[0092] In one embodiment, the doping concentration profile of the second conductive shield region at different locations Il is different.

[0093] In another embodiment, the doping concentration of the second conductive shield region at different locations The files are not different.

[0094] In yet another embodiment, a semiconductor component is described herein. The semiconductor component comprises a semiconductor body of a first conductivity type including a voltage blocking layer and a contact surface It comprises a second conductive island on top and a metal layer on the voltage blocking layer. The voltage blocking layer is located between the Schottky contact and the second conductive island. It includes a first conductive layer that is not in contact with scattered Schottky contacts.

[0095] In one embodiment, the vertical extent of the first conductive layer is smaller than the bottom of the island of the second conductive layer.

[0096] In another embodiment, the vertical extent of the first conductive layer is greater than the bottom of the island of the second conductive layer.

[0097] In yet another embodiment, the doping concentration in the first conductive layer is Schottky contact It is non-uniform in the direction perpendicular to it.

[0098] In yet another embodiment, the vertical extent of the first conductive layer is higher or lower than the bottom of the island of the second conductive layer.

[0099] In yet another embodiment, the first conductive layer does not change in any direction along the contact surface. It has a ping concentration.

[0100] In yet another embodiment, the first conductive layer has a first doping concentration that is higher than the second doping concentration in the drift region.

[0101] In yet another embodiment, the first conductive layer has a first doping concentration lower than the second doping concentration in the drift region.

[0102] In yet another embodiment, the Schottky contact is made of a metal including Al, Ag, Au, Mo, Ni, Ti, W, TixWy, TixNy, or a combination thereof.

[0103] In yet another embodiment, P+ islands are scattered within the N+ region, and N+ is in contact with the Schottky layer. It is a diode that includes a region.

[0104] In one embodiment, the vertical extent of the N+ region is smaller than the bottom of the P+ island.

[0105] In another embodiment, the vertical extent of the N+ region is greater than the bottom of the P+ island.

[0106] In yet another embodiment, the doping concentration within the N+ region is non-uniform in the direction perpendicular to the Schottky layer.

[0107] In yet another embodiment, the vertical extent of the N+ region is higher or lower than the bottom of the P+ island.

[0108] In yet another embodiment, the diode includes N+ islands scattered within a P+ region and a pre-ion contact having a Schottky layer.

[0109] In one embodiment, the vertical extent of the P+ region is smaller than the bottom of the N+ island.

[0110] In another embodiment, the vertical extent of the P+ region is greater than the bottom of the N+ island.

[0111] In yet another embodiment, the doping concentration within the P+ region is non-uniform in the direction perpendicular to the Schottky layer.

[0112] In yet another embodiment, the vertical extent of the P+ region is either higher or lower than the bottom of the N+ island.

[0113] In one embodiment, a metal-insulating semiconductor field-effect transistor is disclosed herein. The metal-insulating semiconductor field-effect transistor comprises a unit cell on a SiC substrate. This comprises a trench in a well region having a second conduction type, a source region of a first conduction type, and a second It comprises a first sinker region having a conduction type and a second sinker region having a second conduction type. The first sinker region has a depth equal to or greater than the depth of the well region. Each of the first sinker region and the second sinker region is a region having the first conduction type. It comes into contact with the other and forms a pn junction.

[0114] In one embodiment, the first sinker region has a depth greater than the depth of the second sinker region. The second sinker has a width greater than the width of the first sinker.

[0115] In another embodiment, a metal-insulating semiconductor field-effect transistor is disclosed herein. The metal-insulating semiconductor field-effect transistor comprises a unit cell on a silicon carbide (SiC) substrate. The knit cell comprises a first conductivity type source region, a second conductivity type well region, and a second conductivity type shield region. It comprises a second conductivity type shielding region, which is located outside the first conductivity type source region.

[0116] In one embodiment, the second conductive shielding region extends beyond the vertical extent of the second conductive well region.

[0117] In another embodiment, the device further comprises a trench region within a second conductive well region. The trench region has a depth equal to or greater than the thickness of the first conductivity type source region. .

[0118] In yet another embodiment, the device is located directly beneath the trench region in a first type of thin Further enhancements to the automotive sector.

[0119] In yet another embodiment, a semiconductor component is disclosed herein. The semiconductor component comprises a semiconductor body of a first conductivity type including a voltage blocking layer and a contact surface It comprises a second conductive island on top and a metal layer on a voltage blocking layer. The layer and voltage blocking layer consist of Schottky contacts and a second conductive island. It includes a first conductive layer that is not in contact with Schottky contacts scattered between them.

[0120] In one embodiment, the vertical extent of the first conductive layer is smaller than the bottom of the island of the second conductive layer.

[0121] In another embodiment, the doping concentration in the first conductive layer is perpendicular to the Schottky contact. It is uneven in all directions.

[0122] In yet another embodiment, a silicon carbide diode is disclosed herein. The silicon carbide diode has first conduction islands scattered within a second region of a first conduction type, and contacts a metal layer. It comprises a first conduction type first region. [Brief explanation of the drawing]

[0123] This patent or application document includes at least one drawing prepared in color. Copies of this patent or patent application publication accompanied by color drawings are available from the Patent and Trademark Office upon request and payment of the required fees.

[0124] Figure 1A shows a conventional SiC DMOS as reported by BJ Baliga in Advanced High-Voltage Power Device Concepts, Springer Press, 2011.

[0125] Figure IB shows the simulated electric field contour for the conventional SiC DMOSFET structure shown in Figure 1A.

[0126] Figure IC shows the electric field distribution of the conventional SiC DMOSFET structure shown in Figure 1A.

[0127] Figure 2A shows an embodiment of a SiC DMOSFET having a p+ plug region for grounding a p-well region having an N+ source contact.

[0128] Figure 2B shows a fracture simulation of the SiC DMOSFET structure shown in Figure 2A.

[0129] Figure 3 shows an implementation of a SiC DMOSFET in which the P+ plug region of Figure 2A is replaced with a deep P-type Sinker #1 region. It shows the form.

[0130] Figures 4A to 4R are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 3.

[0131] Figure 5A shows that in addition to the deep P-type Sinker#l region, a P-type Sinker#2 region is formed below the N+ source region. An embodiment of the SiC DMOSFET is shown.

[0132] Figure 5B shows the breakdown of a SiC DMOSFET structure designed according to the embodiments shown in Figures 3 and 5A. The simulation is shown.

[0133] Figures 6A to 6J are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 5A.

[0134] Figure 7A shows an embodiment of a SiCDMOSFET in which a trench is etched into the N+ source region before the P-type Sinker #1 region is injected.

[0135] Figure 7B shows a fracture simulation of the SiC MOSFET structure shown in Figure 7A.

[0136] Figures 8A to 8BB are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 7A.

[0137] Figure 9 shows the process flow of a conventional SiC DMOSFET for self-aligned MOS channel formation.

[0138] Figure 10 shows an embodiment of a SiC DMOSFET structure for removing parasitic N+ source regions formed around the periphery.

[0139] Figures 11A to 11GG are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 10.

[0140] Figure 12 shows a dedicated tool used to mask the injection of N+ source regions around the device. An embodiment of a SiC DMOSFET having process steps is shown.

[0141] Figures 13(A) to 13(G) are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 12.

[0142] Figure 14 shows a dedicated process for masking the injection of N+ source regions around the device. This shows an embodiment of a SiC DMOSFET having a step, and an N+ source region in the active region for enabling ohmic contact to the p-well region.

[0143] Figures 15A to 15FF are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 14.

[0144] Figure 16 shows that the polysilicon gate metallization layer is segmented in the surrounding region. An embodiment of the SiC DMOSFET is shown.

[0145] Figures 17A to 17FF are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 16.

[0146] Figure 18 shows an embodiment of a SiC DMOSFET having a portion of the MOS channel on the (1000) plane and a second portion on the (11-20) or (11-00) crystal plane.

[0147] Figures 19A to 19U are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 18.

[0148] Figure 20 shows an embodiment of a SiC DMOSFET having a portion of the MOS channel on the (1000) plane, a second portion on the (11-20) or (11-00) crystal plane, a deeper p-well trench, and the formation of a second p-well region below the N+ source region.

[0149] Figures 21A to 21V are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure shown in Figure 20.

[0150] Figure 22 shows the prior art, specifically the threshold voltage versus p-base doping for a 4H-SiC planar MOSFET. The concentration of the globulin is plotted.

[0151] Figures 23A to 23D show embodiments of SiC DMOSFET structures for field shielding within the p-well region.

[0152] Figures 24A to 24U show the process steps for manufacturing the SiC DMOSFET structure shown in Figure 23A. This is a cross-section.

[0153] Figures 25A to 25D show embodiments of SiC DMOSFET structures for field shielding that are embedded and formed within a p-well structure.

[0154] Figures 26A to 26U are cross-sectional views showing the process steps for manufacturing the SiC DMOSFET structure shown in Figure 25A.

[0155] Figure 27 is a schematic cross-sectional view of a conventional SiC MPS diode.

[0156] Figure 28A shows an embodiment of an MPS diode structure having an embedded N+ region.

[0157] Figure 28B shows the IV characteristic of the embodiment described in Figure 28A.

[0158] Figure 28C shows a comparison of the cross-sections of the devices in Figure 28A.

[0159] Figures 29A to 29L are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 28A.

[0160] Figure 30 shows an embodiment of an MPS diode structure in which the bottom of the N+ region is higher than the bottom of the P+ region.

[0161] Figures 31A to 31L are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 30.

[0162] Figures 32A to 32F show MPS diodes having multiple N subregions, P subregions, or both. This is an embodiment of the structure.

[0163] Figures 33AA to 33AL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 32A.

[0164] Figures 33BA to 33BL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 32B.

[0165] Figures 33EA to 33EL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 32E.

[0166] Figures 33FA to 33FL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 32F.

[0167] Figure 34 shows two different types of P+ wells depending on their depth, compared to the depth of the N+ layer. This is an embodiment of the MPS diode structure.

[0168] Figures 35A to 35P are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in Figure 34.

[0169] Figure 36A shows the blocking performance of the device of the present invention with various Wl / Dl ratios.

[0170] Figure 36B shows the blocking IV curves of the device of the present invention having various Wl / Dl ratios.

[0171] Figure 36C shows the forward IV curve of the device of the present invention having various Wl / Dl ratios.

[0172] Figure 36D shows the differential ratio on-resistance performance of the devices of the present invention with various Wl / Dl ratios.

[0173] Figure 37A shows the device structure of a DMOSFET according to an embodiment.

[0174] Figure 37B shows the device structure of a junction field effect transistor (JFET) according to an embodiment.

[0175] Figure 38 shows an example of an n-type layer formed using ion implantation according to an embodiment.

[0176] Figures 39A to 39C show the spread of the N layer in the vertical direction with respect to the P+ gate layer in a JFET according to various embodiments. of the spread.

[0177] Figures 40A to 40C show the vertical range of the N layer with respect to the p-well layer in a DMOSFET according to various embodiments. surrounding.

[0178] Figures 41A to 41E are schematic cross-sectional views of a vertical JFET showing the process steps for the device shown in Figure 37B. is a schematic cross-sectional view.

[0179] Figures 42A to 42D are schematic cross-sectional views of a power MOSFET structure showing the process steps for the device shown in Figure 37A.

[0180] Figures 43A and 43B show the output and breakdown I-V characteristics of a 1200 V SiC DMOSFET manufactured using the teachings of the present invention.

[0181] Figures 44A and 44B show the transfer (ID V / s VGS) characteristics of a 1200 V SiC MOSFET manufactured using the teachings of the present invention.

[0182] Figure 45 is the single pulse avalanche energy measured for a 1200 V SiC MOSFET manufactured using the teachings of the present invention.

[0183] Figure 46 is a photograph showing a SiC DMOSFET fabricated using the teachings of these inventions and tested for a single-pulse avalanche energy test.

[0184] Figures 47A and 47B show the output characteristics of two 3.3 kV SiC MOSFETs fabricated using the teachings of these inventions.

[0185] Figure 47C shows the transfer characteristics of two 3.3 kV SiC MOSFETs fabricated using the teachings of these inventions. be.

[0186] Figure 47D shows measurements taken for two 3.3 kV SiC MOSFETs fabricated using the teachings of this invention. This is a short-circuit test.

[0187] Figure 48A shows a first conductivity type with a second source region of the first conductivity type within a first source region of the first conductivity type. Cross-sectional structure of a unit cell of a double-injection metal-oxide-semiconductor field-effect transistor (DMOSFET) Embodiments are illustrated.

[0188] Figure 48B illustrates an embodiment of the cross-sectional structure of one or more unit cells of a DMOSFET, which includes one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell including a second source region of a first conductivity type within a first source region of a first conductivity type.

[0189] Figure 48C illustrates an embodiment of the cross-sectional structure of one or more unit cells of a trench gate MOSFET, which includes one or more unit cells of an integrated Schottky diode, and each MOSFET unit cell is , including a second source region of the first conductivity type within a first source region of the first conductivity type.

[0190] Figures 49A to 49T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 48A.

[0191] Figure 50A shows one embodiment of the voltage-current characteristics of a conventional SiC DMOSFET having a pn junction relative to a SiC DMOSFET having a deactivated pn junction (i.e., a second source region of the first conductivity type). vinegar.

[0192] Figure 50B is a perspective view showing a side view embodiment of a DMOSFET with respect to the die.

[0193] Figures 50C and 50D show the MOSFET and intrinsic antiparallel diode regions in the H-bridge circuit, respectively. This shows the current path through the region.

[0194] Figure 51A shows a first conductivity type with a second source region of the first conductivity type within a first source region of the first conductivity type. Cross-sectional structure of a unit cell of a double-injection metal-oxide-semiconductor field-effect transistor (DMOSFET) Embodiments are illustrated.

[0195] Figure 51B illustrates an embodiment of the cross-sectional structure of one or more unit cells of a DMOSFET, which includes one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell including a second source region of a first conductivity type within a first source region of a first conductivity type.

[0196] Figures 52A to 52T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 51A. .

[0197] Figure 53A shows a double metal region including a first metal region that is in direct contact with a second conductive well contact region. Implementation of the cross-sectional structure of a unit cell of an injected metal oxide semiconductor field-effect transistor (DMOSFET). The form is illustrated.

[0198] FIG. 53B illustrates an embodiment of a cross-sectional structure of one or more unit cells of a DMOSFET including one or more unit cells of an integrated Schottky diode, and each DMOSFET unit cell has a respective first metal region that is in direct contact with a second conductivity type well contact region.

[0199] FIG. 53C shows an embodiment of third quadrant current conduction through a true p-n junction diode region connected in parallel with a DMOSFET to a Schottky diode region.

[0200] FIG. 53D shows an embodiment of third quadrant current conduction through a DMOSFET after connecting one or more Schottky diode regions in series with one or more body diode regions of the DMOSFET.

[0201] FIGS. 54A to 54X show an embodiment of a process for manufacturing the DMOSFET structure shown in FIG. 53A .

[0202] FIGS. 55A, 55B, and 55C show embodiments of cross-sectional structures of unit cells of a dual-injected metal oxide semiconductor field effect transistor (DMOSFET) having a second conductivity type well contact region that meanders at three different positions, respectively. tact region. FIGS. 55D, 55E, and 55F show embodiments of cross-sectional structures of one or more unit cells of a diode integrated DMOSFET, and each DMOSFET unit cell has a second conductivity type well contact region that meanders at three different positions, respectively.

[0203] FIGS. 56A to 56T show an embodiment of a process for manufacturing the DMOSFET structure shown in FIG. 55A .

[0204] FIGS. 56A to 56T show an embodiment of a process for manufacturing the DMOSFET structure shown in FIG. 55A .

[0205] Figures 57A to 57T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 55B.

[0206] Figures 58A to 58T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 55C.

[0207] Figures 59A, 59B, and 59C show a second conductive well contour that meanders at three different positions. A unit of a double-injection metal oxide semiconductor field-effect transistor (DMOSFET) equipped with a tactile region. An embodiment of the cross-sectional structure of the cell is shown, where the second conductive type well region is the second conductive type well This allows contact with the source metal only through the contact area.

[0208] Figures 59D, 59E, and 59F show cross-sections of one or more unit cells of a diode-integrated DMOSFET. An embodiment of the structure is shown, in which each DMOSFET unit cell comprises a second conductivity type well contact region that meanders at three different positions, and the second conductivity type well region is the second conductivity type well This allows contact with the source metal only through the contact area.

[0209] Figure 59G shows an embodiment of the cross-sectional structure of one or more unit cells of a diode-integrated trench gate MOSFET, which comprises one or more unit cells of integrated Schottky diodes. The MOSFET unit cell is provided with a second conductivity type well contact region at a first position, allowing the second conductivity type well region to contact the source metal only through the second conductivity type well contact region.

[0210] Figures 60A to 60T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 59A. .

[0211] Figures 61A to 61T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 59B.

[0212] Figures 62A to 62T show one embodiment of the process for manufacturing the DMOSFET structure shown in Figure 59C.

[0213] Figure 63 shows an embodiment of the cross-sectional structure of one or more unit cells of a power MOSFET, where the first unit cell of the one or more unit cells is a first metal oxide semiconductor (MOS) on the horizontal plane of a semiconductor substrate. The unit cell comprises an interface and a trench sidewall, and one or more unit cells have a second metal-oxide-semiconductor (MOS) interface formed only on the trench sidewall.

[0214] Figures 64A to 64AB are cross-sectional views showing one embodiment of the manufacturing process for the MOSFET structure shown in Figure 63. .

[0215] Figure 65 shows an embodiment of the cross-sectional structure of one or more unit cells of a power MOSFET, where the first unit cell of the one or more unit cells comprises a first metal oxide semiconductor (MOS) interface and a trench sidewall on the horizontal plane of the semiconductor substrate, and the second unit of the one or more unit cells The tocell comprises a metallic region formed adjacent to the first conductive drift layer of the MOSFET.

[0216] Figures 66A to 66AA are cross-sectional views showing one embodiment of the manufacturing process of the MOSFET structure shown in Figure 65. ru.

[0217] Figure 67A shows two implementation configurations of power MOSFETs: a vertical planar DMOSFET and a vertical trench UMOSFET.

[0218] Figures 67B and 67C show the main resistances in the vertical DMOSFET and UMOSFET, respectively, clearly demonstrating that the device geometry effectively eliminates the JFET resistance present in the DMOSFET.

[0219] Figure 67D shows the electric field in a UMOSFET in a blocking state, and the trench corners are important locations for significant electric field concentration.

[0220] Other features of this embodiment will become apparent from the accompanying drawings and the following detailed description. [Modes for carrying out the invention]

[0221] Definitions and general techniques Unless otherwise defined herein, scientific and technical terms used in connection with the present invention shall have meanings generally understood by those skilled in the art. Furthermore, unless otherwise required by context, singular terms shall include plural forms, and plural terms shall include singular forms. Generally, the nomenclature and techniques used in connection with the semiconductor processing described herein are well known and commonly used in the art.

[0222] The methods and techniques of the present invention generally follow conventional methods well known in the art, and otherwise Unless otherwise indicated, the procedures and techniques described in the various general and more specific references cited and discussed throughout this specification shall be implemented as described herein. The nomenclature used in relation to semiconductor device technology, semiconductor processing, and other related fields described herein, as well as the procedures and techniques of semiconductor device technology, semiconductor processing, and other related fields, are well known and commonly used in the art.

[0223] For simplicity and clarity, the drawings illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring this disclosure. In addition, elements in the drawings are not necessarily drawn to a consistent scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to others to aid in understanding embodiments of this disclosure. The same reference numeral in different drawings indicates the same element.

[0224] The terms “first,” “second,” “third,” “fourth,” etc., in this specification and the claims are used to distinguish similar elements, if any, and are not necessarily used to describe a specific sequential or chronological order. It should be understood that such terms are interchangeable under appropriate circumstances, such as when the embodiments described herein may operate in an order other than that illustrated or otherwise described herein. Furthermore, the terms “include” and “have,” Furthermore, any variations thereof are intended to cover non-exclusive inclusions, and therefore, a process, method, system, article, device, or apparatus comprising a list of elements is not necessarily limited to those elements, but may include other elements that are not expressly enumerated or that are specific to such process, method, system, article, device, or apparatus.

[0225] Terms such as “left,” “right,” “front,” “rear,” “up,” “down,” “up,” and “down” in this specification and in the claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. Terms used in this way refer to embodiments of the apparatus, methods, and / or products described herein, for example, as illustrated herein. It should be understood that they are interchangeable under appropriate circumstances so that they can operate in orientations other than those described in other ways.

[0226] Any element, action, or instruction used herein should not be construed as important or essential unless expressly stated otherwise. Furthermore, when used herein, the articles “a” and “an” are intended to include an item and may be used interchangeably with “one or more.” Additionally, when used herein, the term “set” is intended to include items (e.g., related items, unrelated items, combinations of related items, and unrelated items) and may be used interchangeably with “one or more.” When only one item is intended, the term “one” is used. Or similar language is used. Also, when used herein, the term "has" Terms such as "have" and "having" are intended to be open-ended. Furthermore, unless otherwise specified, the phrase "based on" means "based at least partially on."

[0227] The following terms and phrases shall be understood to have the following meanings unless otherwise indicated.

[0228] As used herein, the term "unit cell" refers to a portion of a repeating pattern within a semiconductor.

[0229] As used herein, the term "SiC" refers to silicon carbide, a compound semiconductor and a mixture of silicon and carbon having the chemical formula SiC. Silicon is covalently bonded to carbon. Here, in 4H-SiC, 4H is written in the Ramsdell classification scheme, the numbers indicate layers, and the letters Bravai It shows an s-lattice. This means that in the 4HSiC structure, there are four hexagonal layers of SiC. SiC is a polymorphic crystalline structure known as polytype, such as 3C-SiC, 4H-SiC, and 6H-SiC. It exists as a type of material. Currently, 4H-SiC is used in the manufacture of power devices. [Source: Complete Analytical Possibility-Based Solutions for Nanoscale 4HSiC MOSFETs, MK Yadav, K Pradhan and PK Sahu, Published 24 May 2016 · (c) 2016 Vietnam Academy of Science] [& Technology]

[0230] As used herein, the term “substrate” refers to the support material on which the components of an integrated circuit are manufactured or mounted.

[0231] As used herein, the term "JFET" refers to a junction gate field-effect transistor, which is a three-terminal semiconductor device that can be used as an electronically controlled switch, amplifier, or voltage-controlled resistor. This refers to a FET (field-effect transistor). A FET is a unipolar transistor, and it is a current-generating transistor. Carriers are injected into the source terminal and pass through a channel in the semiconductor material, whose conductivity largely depends on the electric field applied to the semiconductor from the control electrode, to the drain terminal. There are two main types of FETs: junction FETs and insulated-gate FETs. In a junction FET, the gate is a pn junction. It is insulated from the channel. In an insulated-gate FET, the gate is insulated from the channel by an insulating layer. As a result, the gate and channel form a capacitor having an insulating layer as a capacitor dielectric.

[0232] As used herein, the term "MOSFET" refers to source (S), gate (G), drain (D), and This refers to a metal oxide semiconductor field-effect transistor, which is a four-terminal device with a body (B) terminal. The body of a MOSFET is often connected to the source terminal, making it a three-terminal device like a field-effect transistor.

[0233] As used herein, the term "DMOSFET" refers to a double-injection gold This refers to a field-effect transistor made of a type oxide semiconductor. The typical physical structure of a SiC MOSFET is a planar structure in 4H-SiC (SiC-DMOSFET). It is a double-injection MOSFET.

[0234] As used herein, the term “dopant” refers to an impurity added to a material from an external source by diffusion, coating, or injection into a substrate, for example, by altering its properties. In semiconductor technology, impurities can be added to a semiconductor to alter its electrical properties, or added to a material to produce a semiconductor with desired electrical properties. N-type (negative) dopants (e.g., phosphorus in Group IV semiconductors) are typically derived from Group V of the periodic table. When added to a semiconductor, n-type dopants create a material containing conduction electrons. P-type (positive) dopants (e.g., Boron (for Group IV semiconductors, etc.) typically originates from Group III, and conduction holes (i.e., electron chains) This creates voids within the shell.

[0235] As used herein, the term "drain" refers to the electrode of a field-effect transistor that receives charge carriers from the source electrode through the transistor channel.

[0236] As used herein, the term “source” refers to the active region / ectrod within a field-effect transistor to which the source of charge carriers is connected.

[0237] As used herein, the term “gate” refers to a control electrode or control region that affects a semiconductor region directly associated with it, such that the conductive properties of that semiconductor region are temporarily altered, often resulting in an on-off switching action. In a field-effect transistor, the control electrode or control region is located between the source electrode and the drain electrode, and in the region between them.

[0238] As used herein, the term “impurity” refers to foreign substances present in a semiconductor crystal, such as boron or arsenic in silicon, that are added to a semiconductor to produce either a p-type or n-type semiconductor material, or otherwise to result in a material whose electrical properties depend on the impurity dopant atom.

[0239] As used herein, the term "PN junction" refers to the interface and region of the transition between a p-type semiconductor and an n-type semiconductor.

[0240] As used herein, the term "polysilicon" refers to silicon in a polycrystalline form.

[0241] As used herein, the term "P-type" refers to an exogenous semiconductor in which the hole density exceeds the conduction electron density. It refers to the body.

[0242] As used herein, the term “band gap” refers to the difference between the energy levels of electrons bound to the nucleus (valence electrons) and the energy levels that allow electrons to move freely (conduction electrons). The band gap depends on the specific semiconductor involved.

[0243] As used herein, the term “yield” refers to a sudden change in dynamic electrical resistance from high to very low in a reverse-biased semiconductor device (e.g., a reverse-biased junction between a p-type semiconductor material and an n-type semiconductor material), where a slight increase in the reverse applied voltage causes a rapid increase in the reverse current, and the device behaves as if it had negative electrical resistance.

[0244] As used herein, the term "channel" refers to the path for conducting electric current between the source and drain of a field-effect transistor.

[0245] As used herein, the term “chip” means one or more active or passive solid-state electronic devices. This refers to a single-crystal substrate of semiconductor material on which a chip is formed. The chip may contain an integrated circuit. The chip is typically not ready for use until it is packaged and an external connector is provided.

[0246] As used herein, the term “contact” refers to a point or portion of a conductor that makes contact with another conductor or electrical component in order to carry an electric current between them.

[0247] As used herein, the term “die” means one or more separated from a semiconductor slice. This refers to a tiny piece of semiconductor material on which several active electronic components are formed. It is also called a chip. N+ substrate.

[0248] When used herein, the term "sinker" refers to a key position within the DMOSFET structure. This refers to the deep injection area.

[0249] As used herein, the term "plug" refers to a well and source contact that are grounded. This refers to the structure used.

[0250] As used herein, the term “drift layer” refers to a low-concentration doped region in a power MOSFET that supports high voltages.

[0251] As used herein, the term "well" refers to the well within a metal oxide semiconductor (MOS) transistor. This refers to a specific region. MOS transistors are always formed in the "well" region. PMOS (Po Negative channel MOS transistors are fabricated within an N-doped region called an "N-well" region. Similarly, NMOS transistors (negative channel MOS) are fabricated within a "P-type" region called a "p-well" region. This is formed in the region. This ensures low leakage between the two transistors passing through the lower side due to the reverse bias between the transistor region and the well region.

[0252] As used herein, the term “source interconnects metallization” refers to interconnect metallization, which interconnects thousands of MOSFETs using a fine wire metal pattern.

[0253] As used herein, the term “self-alignment” refers to a processing step in the manufacturing of semiconductor devices. Achieving precise alignment between structures manufactured at different lithography stages in integrated circuit manufacturing is often necessary. Strict requirements regarding lithography alignment tolerances can be relaxed when structures are “self-aligned,” meaning that one structure is forced to a specific position relative to the other for a wide range of positions defined by lithography.

[0254] As used herein, the term “device” refers to the physical realization of individual electrical elements within a physically independent body that cannot be further divided without destroying its described function.

[0255] As used herein, the term “surface” refers to the outer surface or outer boundary of an object.

[0256] As used herein, the term “trench” refers to the electrical isolation of electronic components within a monolithic integrated circuit by using grooves or other recesses on the surface of a substrate, which may or may not be filled with an electrically insulating (i.e., dielectric) material.

[0257] As used herein, the term “dielectric” refers to an electrical nonconductor, otherwise known as an insulator.

[0258] As used herein, the term “mobility” refers to the movement of carriers through a semiconductor when exposed to an applied electric field. Electrons and holes typically have different mobilities in the same semiconductor.

[0259] As used herein, the term "RIE" refers to etching techniques used in microfabrication. This refers to reactive ion etching. RIE has different properties from wet etching. RLE is a type of lye etching. RLE uses chemically reactive plasma to deposit on a wafer. The material is removed. Plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the plasma attack the wafer surface and react with it.

[0260] As used herein, the term "ILD" is used to electrically isolate densely spaced interconnection lines located at several levels (multilayer metallization) within an advanced integrated circuit. This refers to interlayer dielectrics and dielectric materials.

[0261] As used herein, the term "CVD" refers to chemical vapor deposition, typically performed under vacuum, resulting in high quality This is a method used to produce high-performance solid materials. This process is often used in the semiconductor industry to manufacture thin films. In a typical CVD, a wafer (substrate) is used as the substrate The material is exposed to one or more volatile precursors that react and / or decompose on the surface to produce the desired deposit. Often, volatile byproducts are also produced, which are removed by a gas flow through the reaction chamber.

[0262] As used herein, the term "PECVD" refers to the process of transferring a substance from a gaseous (vapor) state to a solid state on a substrate. This refers to the plasma-enhanced chemical deposition process used to deposit thin films. The chemical reaction is: It is involved in the process that occurs after the generation of a plasma from the reactive gas.

[0263] As used herein, the term "LPCVD" refers to the process of using heat to reverse the reaction of a precursor gas on a solid substrate. This refers to low-pressure chemical vapor deposition (DEV) technology used to initiate the reaction. This reaction on the surface forms a solid-phase material.

[0264] As used herein, the term "DIBL" refers to drain-induced barrier reduction, initially referring to the short-channel effect in MOSFETs, which is the reduction of the transistor's threshold voltage at higher drain voltages. In classical planar field-effect transistors with long channels, the bottleneck in channel formation occurs far enough away from the drain contacts that it is electrostatically shielded from the drain potential by the substrate-gate combination; therefore, classically, the threshold voltage was independent of the drain voltage. In short-channel devices, this is no longer true: the drain potential can gate the channel, and therefore, high drain voltages are bottlenecks. The torneck can be opened, allowing the transistor to be turned on prematurely.

[0265] As used herein, the term "ICP" refers to the specialized semiconductor market for device manufacturing. This refers to the inductively coupled plasma etching technique that is frequently used. This technique can combine both chemical reactions and ion-induced etching. Independent control of the ion flux allows for high process flexibility. ICP etching is based on the use of an inductively coupled plasma source. The ICP source generates a high-density plasma through inductive coupling between an RF antenna and the plasma. The antenna, located in the plasma generation region, generates an alternating RF magnetic field, which induces an RF electric field that energizes electrons involved in the ionization of gas molecules and atoms at low pressure. Since there is no electric field near the reactor wall, there is virtually no ion bombardment or erosion of the wall.

[0266] As used herein, the term “p-shield” refers to a carefully designed p-type doped region strategically placed near or within the MOSFET channel region, in the off state or blocking state. The purpose is to shield the MOSFET channel from the high potential applied to the drain terminal during operation.

[0267] When used herein, the terms “first conductivity type region” and “second conductivity type region” are used to describe the n-type and p-type regions, respectively, for N-type devices. For P-type devices, “first conductivity type region” and “second conductivity type region” are used to describe the p-type and n-type regions, respectively.

[0268] As used herein, the term “IV characteristic curve” refers to the current-voltage characteristic curve or simply IV curve of an electrical device or component, and refers to a set of graphical curves used to define its operation within an electrical circuit.

[0269] As used herein, the term "MV / cm" refers to megavolts per centimeter and is a unit of electric field.

[0270] As used herein, the term “avalanche defect” refers to a phenomenon that can occur in both insulating and semiconductor materials. It is a form of current multiplication that can enable very large currents in a material that is otherwise a good insulator. It is a type of electron avalanche. This avalanche process occurs when carriers in a transition region are accelerated by an electric field to have enough energy to generate movable or free electron-hole pairs through collisions with coupled electrons. The voltage at which breakdown occurs is called the breakdown voltage. Avalanche breakdown can cause structural damage to semiconductor devices.

[0271] When used herein, the term "avalanche energy" refers to the setting of avalanche mode. It is defined as the amount of energy that a MOSFET can withstand when it is subjected to a certain voltage, or when its breakdown voltage is exceeded.

[0272] As used herein, the term "upper side" refers to the outer / upper side of a DMOSFET. The upper surface of a vertical SiC DMOSFET may include a source terminal.

[0273] As used herein, the term "bottom" refers to the underside / bottom of a DMOSFET. The bottom of a vertical SiC DMOSFET may include a drain terminal.

[0274] As used herein, the term "front" refers to the surface visible to the front of the DMOSFET.

[0275] As used herein, the term "backside" refers to the backside of a DMOSFET. The backside of a vertical SiC DMOSFET may include a drain terminal.

[0276] As used herein, the term "plus" refers to a specific region within a metal-oxide-semiconductor (MOS) transistor where the doping concentration is excessive.

[0277] As used herein, the term “active region” refers to the region of a DMOSFET where current conduction occurs. .

[0278] As used herein, the term “depletion region” refers to a region in which the flow of charged carriers decreases over a given time.

[0279] As used herein, the term “thermal budget” refers to the total amount of thermal energy transferred to a wafer during a given high-temperature operation.

[0280] As used herein, the term “work function” refers to the minimum amount of energy required to infinitely remove electrons from the surface of a given metal.

[0281] As defined herein, two or more elements are fields in which they are composed of the same material piece. In this specification, two or more elements are, each distinct. When composed of separate material pieces, it is considered "non-integrated."

[0282] As used herein, the term "trench sidewall" refers to the wall that forms the side of the trench area.

[0283] As used herein, the term "bottom" refers to the bottom of the trench area.

[0284] As used herein, the term "crystal plane" refers to a virtual plane within the crystal of a semiconductor substrate where a high atomic concentration exists.

[0285] As used herein, the term "MOS interface" refers to a region / path that electrically interconnects two regions.

[0286] As used herein, the term “horizontal surface” refers to an unetched surface on the upper surface of a semiconductor substrate.

[0287] As used herein, the term "RF" refers to radio frequency. Radio frequency is the oscillation speed of alternating current or voltage, or of a magnetic, electric, electromagnetic, or mechanical field.

[0288] The embodiment relates to a SiC DMOSFET power device, and the p-well region in particular effectively protects the gate oxide, which is sensitive to the high electric field present in the SiC, during high drain bias or blocking mode operation. It effectively shields.

[0289] One embodiment involves using a p+ plug to ground the p-well region with an N+ source contact. Regarding.

[0290] One embodiment relates to creating a lateral spacing between p-well regions that is sufficiently narrow to suppress the electric field within the gate oxide, while ensuring that the on-resistance is not high.

[0291] One embodiment involves replacing the P+ plug region of the DMOSFET with a deep P-type Sinker #1 region. To relate to.

[0292] The embodiment is a MOSFET unit whose depth may be equal to or greater than the depth of the p-well region. This relates to the formation of one or more deeply injected sinker regions at specific locations within a MOSFET device structure, such as a first P-type sinker region at the center of a MOSFET cell.

[0293] The embodiment relates to forming a second P-type sinker region below the N+ source region, the depth of which may be equal to or greater than the p-well region, but equal to the depth of the first P-type sinker region. It may be less than or equal to less than that.

[0294] The embodiment relates to boron injection, which can be advantageously used to form a deep sinker region because boron has a larger injection range than aluminum, which can result in a deeper injection profile.

[0295] The embodiment relates to the formation of a first trench having a desired shape that can be etched within an N+ source region before the formation of a first P-type sinker region, wherein the first P-type sinker region is a first P-type sinker This can increase the depth of the Kerr region. The depth of the first trench may range from 0.01 μm to 2 μm. The resulting depth of the first sinker region may be 0% to 100% greater than the depth of the p-well region. The depth of the first P-type sinker region may be the same as the entire epitaxial layer.

[0296] Embodiments relating to forming a first trench in the N+ source region include a first P-type sinker region The need for expensive, ultra-high energy injection steps to form the region can be reduced or eliminated.

[0297] The embodiment relating to the first trench removes N+ source injection from the first P-type sinker region. This can be used to its advantage, which may be desirable to prevent compensation of the first P-type sinker region by N+ source injection. This is because the N+ source region is relative to the p-well region. It is particularly useful when it is self-aligned.

[0298] The embodiment uses first and second P-shaped sinker regions instead of a box-shaped injection profile. Regarding the gradually decreasing injection concentration that can be used to form, this may be advantageous for properly shaping the electric field under a high drain bias. Doping in the P-type sinker region The doping concentration can be linearly varied from a maximum value near the SiC surface to a value equal to or slightly higher than the doping concentration of the drift layer at the other end of the P-type sinker region.

[0299] The first and second thinker region design embodiments simplify the design of the p-well region. The p-well region can be designed to support metal-oxide-semiconductor (MOS) channel formation and can be advantageously designed to achieve low on-resistance without compromising other performance metrics such as reverse leakage current and electric field in the gate oxide.

[0300] SiC devices in power electronics offer high switching times and high blocking It features high voltage capability and the ability to operate at high temperatures. These characteristics, along with recent advances in manufacturing processes, make SiC a successor to conventional silicon-based (Si) devices for power electronics. This suggests that it has the potential to revolutionize electronics. SiC has a wide bandgap. The band gap material is (3.3 eV), and the band gap of Si is 1.1 eV, and the dielectric breakdown field of Si is 1.1 eV. Compared to 0.3 × 10⁶ V / cm, it has a high dielectric breakdown field (3 × 10⁶ V / cm). 6 V / cm ~ 5 × 10 6 It has V / cm). SiC is a superior thermal conductor with 3.7 (W / cm-K) compared to 1.6 (W / cm-K) of SiC. SiC enables operation at extremely high power levels while still dissipating the large amount of excess heat generated. These material properties of SiC offer several advantages to using SiC instead of Si in power devices. SiC and Si semiconductor devices with identical structure and dimensions In the comparison, the SiC die exhibits lower specific ON resistance and higher breakdown voltage than the Si die.

[0301] The embodiments disclosed herein provide novel technologies for the design and manufacture of SiC DMOSFETs. This provides a way to shape the electric field on the device structure and reduce the concentration of the electric field at singularities. Embodiments of this specification reduce the electric field in the gate oxide region to less than 3.5 MV / cm, improving the reliability of the device.

[0302] Manufacturing processes in Si utilize techniques such as dopant diffusion, but these conventional manufacturing processes are not feasible for producing SiC devices because the diffusion coefficient in SiC is negligible at temperatures below 1800°C. SiC devices are manufactured by ion implantation in both the source and p-well regions, but ion implantation, and especially deep ion implantation, is difficult in SiC. Yes. In embodiments of this specification, ion implantation of the source and p-well regions is a novel technique. It is used and carried out in depth.

[0303] Compared to silicon devices, the SiC devices of the embodiments described herein offer high reliability and high dynamic range. Operating temperature, high efficiency, and high voltage capability make them highly desirable in the electric vehicle and renewable energy industries. Traction inverters in electric vehicles are exposed to high temperatures (>150°C), and load cycling and renewable energy converters are exposed to extreme environmental conditions. Embodiments described herein for SiC devices can achieve, for example, power conversion up to >98%. Maximizing conversion efficiency while providing high reliability, and therefore minimizing high costs, maintenance, and downtime for electric vehicle operators, makes it an ideal candidate for electric vehicles.

[0304] The disclosed embodiments describe a SiC power DMOSFET device that is particularly high drain bias (blocking) During gate mode operation, the sensitive gate oxide is effectively shielded from the high electric field present in 4H-SiC. Change the way it can be done.

[0305] In embodiments of this specification, the trade-off between achieving low on-resistance in a SiC power DMOSFET device and achieving robust blocking performance that implies a low electric field within a structure close to the gate oxide is overcome.

[0306] Embodiments herein include a unit cell of a SiC power DMOSFET comprising a vertical MOSFET. A specific region of the power DMOSFET device is the p-well region formed by the injection, N+ source region, N-drift layer, and N+ substrate. In the embodiments herein, during the ON state, The flow flows vertically from the drain through the inversion layer formed at the top of the p-well layer, and the gate electricity Pressure is applied to this device through the N+ source region and through source metallization. When exiting, the voltage is applied to this device. In the off or blocking state, the voltage is supported across the p-well and N-drift layer junction in the embodiments herein. A PN junction is formed between the N-drift layer and the N-drift layer. The voltage applied to the structure is reverse via This PN junction is supported across the junction.

[0307] In the embodiments described herein, the power MOSFET has a pitch of a unit cell which is the repeating unit of the MOSFET, a channel length which is the portion of the p-well where the inversion channel is formed, and a junction gate field effect. It has several physical dimensions, including the distance between two consecutive p-wells called the transistor (JFET) region or JFET gap, the thickness of the gate oxide, and the interlayer dielectric (ILD) layer used to insulate the source interconnect metallization from the polysilicon gate. .

[0308] In embodiments of this specification, the advantage of using SiC over Si is that, for similar chip sizes, SiC can support a much higher power density. The amount of voltage that can be transmitted is more than 10 times that of Si, and SiC chips can carry it through MOSFETs. The current is 10 to 50 times that of Si. The performance advantage lies in the trade-off between voltage and current. Voltage blocking and current conduction capabilities are approximately 200 times better in the case of SiC compared to Si.

[0309] In embodiments of this specification, the P+ plug at the center of the SiC DMOSFET unit cell is replaced by a PS#1 region. In embodiments, the PS#1 region extends below the p-well region. During blocking conditions, the electric field or main region where breakdown may occur is essentially the PS#1 region and the Ndrift region. It is located at the center of the SiC DMOSFET unit cell between the layers. The SiC structure has p-wells and Ndrift There is a tendency for fracture between layers, particularly at the curvature of the p-well region. In the embodiments described herein, The structure is broken between the PS#1 region and the Ndrift layer. Here, the location of dielectric breakdown is in the unit It is moved toward the center of the cell, resulting in a lower electric field closer to the gate oxide region. Due to the PS#1 region, a reduced electric field exists closer to the gate oxide region in this embodiment. This should create a more robust device.

[0310] The embodiments described herein describe differences in structure, manufacturing method, device function, and manufacturing results compared to prior art SiC devices. It has. The simulation data of the embodiments herein shows the differences in structural performance and results. In addition to the PS#1 region, the devices of the embodiments herein also have an N+ source region. It has a PS#2 region located on the side. This is because during the blocking mode of operation, the voltage is The electric field profile in the embodiment is improved so that it is dropped across a larger area of ​​the unit cell, resulting in more robust operation. In the embodiments herein, the PS#2 region can be deeper than the p-well region and shallower than the PS#1 region. This is possible. In all p-type regions in the SiC DMOSFET structure according to the embodiments herein, the deepest of these is the PS#1 region, the intermediate is the PS#2 region, and the shallower is the p-well region. The embodiments herein are derived from these PS#1 and PS#2 structures. This demonstrates more appropriate field shaping.

[0311] In embodiments of this specification, another advantage of including the PS#2 region is that PS#2 functions as a secondary p-well region. The design of the p-well region must satisfy several different constraints. The electrical dose of the p-well region can be large enough to achieve the desired breakdown voltage, while at the same time, the doping of the p-well region near the gate oxide region where the MOS channel is formed can be low enough to achieve a reasonably low threshold voltage.

[0312] In this embodiment, the p-well region can satisfy conflicting requirements. By placing PS#2 below the N+ source region, it relaxes the design of the p-well region, and its purpose is now , simply for channel definition and channel formation. In the embodiments herein, p-we The p-well region does not need to be designed to support the breakdown voltage. The embodiments herein give designers more flexibility in designing the p-well region appropriately solely for MOS channel formation.

[0313] In embodiments of this specification, PS#1 is formed after a trench is etched into the N+ source region in the center of the SiC DMOSFET unit cell. The advantage of this trench is that it moves the electric field position further away from the gate oxide interface to the center of the SiC DMOSFET unit cell. In this embodiment, a deeper PS#1 region is effectively generated by etching a recess trench in the N+ source region. The electric field moves further away from the gate oxide region. This results in more robust blocking capabilities. In the embodiments described herein, one reason for forming trenches is the difficulty of ion implantation into SiC, particularly deep ion implantation. Deep PS#1 sinker regions can be created for source trenches. In this embodiment, it is possible to create a deeper PS#1 region by etching the trench and then performing ion implantation, which is effective and achieves functionality.

[0314] In the embodiments herein, the trench forms a deeper PS#1 due to the source trench. By reducing the oxide, a thinner oxide region can be formed, which helps prevent SiC DMOSFETs from being destroyed in the dielectric field. It requires an object. In the embodiments of this specification, by introducing a P-type sinker region, Thinner oxides can be used.

[0315] In embodiments of this specification, a SiC DMOSFET device undergoes a series of masking steps and The units are fabricated using either subsequent ion implantation or etching and deposition steps. In embodiments of this specification, a unit cell is fabricated by using photolithography, which is used to mask a specific portion of a wafer or a specific portion of a device, perform a specific step, then remove the mask, and perform other steps, thereby fabricating a series of structures. Minimizing the number of steps is crucial for achieving cost-effectiveness; that is, if the number of steps can be reduced in any way, the cost structure will be lower. Also, certain steps in the production of SiC are expensive, and embodiments of this specification address this. Minimize the number of these expensive steps. For example, ion implantation is relatively high in SiC. This is a valuable step. The p-well, p-plug, and N+ source region use ion implantation. It is manufactured by [method]. Ion implantation is an expensive step, and deeper ion implantation is even more expensive. Therefore, it is important to minimize deep ion implantation. Furthermore, in contrast to N-type implantation, which can be done at room temperature, P-type implantation requires a higher temperature (400°C). Because it needs to be performed at ~1000℃, it is 5 to 10 times more expensive than N-type injection. Minimizing the size of the P-type implant is also important.

[0316] In the embodiments described herein, the wafer first undergoes a series of ion implantation steps, which are typically referred to as the process front end, followed by high-temperature annealing, which is note It is used to anneal the injector and electrically activate the injection. The trailing end of the process typically consists of forming a gate oxide, ILD, and other metallization steps.

[0317] In embodiments herein for fabricating SiC DMOSFET structures, photolithography is used. Then, a specific portion of the wafer is masked to create a p-well region, and then the N+ source region is implemented. The following masking step can be used to reveal the p+ plug region, and then another masking step can be used to realize the p+ plug region. The wafer needs to be annealed to activate the injected region. After this, the gate oxide or gate dielectric can be grown by thermal oxide or using deposited oxide. Gate metallization can be formed using polysilicon or other heat-resistant metals. This can be done. Next, gate metallization is selectively patterned and etched to access the N+ source region, then ILD is deposited, and then the N+ source The wafer is patterned to create windows for generating these ohmic contacts for the regions. The ohmic contacts for the drain region can be realized on the back surface of the wafer, which is the drain. At the end of the process, the various unit cells are connected using source interconnection metallization.

[0318] SiC MOSFETs are typically fabricated using several masking steps. Some of these masking steps may be for forming injection regions, while others are for forming structures such as gate oxides and ILDs. All morphologies are carried out in 11 masking steps without increasing the number of masking steps for any additional features such as PS#1, PS#2, source trench formation, or other structures in the embodiments.

[0319] Because diffusion does not work well in SiC, ion implantation is a method of introducing dopants. Therefore, higher implantation energy is required to make the PS#1 region deeper than the p-well region. In the embodiments herein, typically either aluminum or boron is used to realize the P-type region in SiC. Thus, in the embodiments herein, boron implantation is used instead of aluminum implantation to realize the PS#1 region and the deep PS#1 region, because, for a given energy, boron implantation can result in a deeper region compared to aluminum implantation. Another method for realizing the deep PS#1 region is It uses much higher energy and still uses aluminum as a P-type dope. And so it is.

[0320] In one embodiment of this specification, a p-well region is formed, and then an N+ source region is formed. The PS#2 region is realized by performing ion implantation while forming the N+ source region. The same masking step is used to form the region and the PS#2 region. In the embodiment of this book, this makes it possible to realize the PS#2 region exactly below the N+ source region. do.

[0321] In embodiments of this specification, N+ source injection is achieved in two regions using different masking steps. To reduce or eliminate the inconsistencies that may occur when this is done, self-injection of p-wells It will be aligned.

[0322] In the embodiments described herein, a channel length of sub-0.5 microns or sub-1 micron is used. To achieve this, the first p-well region is formed using a conventional implantation masking step. A dielectric layer of sufficient thickness is deposited, and then this layer is selectively patterned using photolithography, and then ion implantation is performed to realize the p-well region. Once this is done, a second dielectric layer is deposited on top of this patterned first dielectric layer and then subjected to blanket etching. This is N+ source injection This provides a dielectric spacer region that defines the receiving area. Therefore, the suitability of the second dielectric layer The MOS channel length can be defined by selecting a specific thickness.

[0323] In embodiments of this specification, in order to realize a channel with a width of 0.5 microns, first, p-well regions are created using conventional photolithography techniques, and for example, silicon dioxide layers are piled up. After stacking and pattern formation, a second silicon dioxide layer with a thickness equal to 0.5 microns is then stacked. It can be deposited. Etching this layer downwards will result in a 0.5 micron spacer. N+ When source injection is performed, the MOS channel length is effectively 0.5 microns.

[0324] In this embodiment, the channel length is not limited by the lithography technique, but rather by the dielectric layer, e.g. For example, by the ability to deposit silicon dioxide, the dielectric layer has much better control. Dielectric layers or silicon dioxide layers can be deposited with a resolution far superior to that made possible by lithography.

[0325] In one method called the subtractive method, this process first produces N+ sources. Next, a dielectric layer is deposited, and then a P+ layer is formed through a polysilicon variation. Embodiments herein first perform p-wells, and then control the channel length. A deposition method is performed in which a dielectric of a certain thickness is deposited, and then an N+ source is placed. Therefore, the order of N+ and p-wells is compared to how conventional SiC DMOSFETs are formed. In the embodiments described herein, however, the opposite is true.

[0326] Embodiments herein avoid injecting the N+ source region into the gate region. In SiC MOSFET structures, parasitic NPN transistors exist, which are not present during normal operation but at very high speeds. This can be triggered when switching this device from off to on or on to off.

[0327] In the embodiments of this specification, a trench into the N+ source region is formed before injection into the PS#1 region. This results in a deeper PS#1 region. However, another advantage of doing this is that N+ source regions are injected. It is also possible to remove the N+ source region from the part of the device that you do not want to be treated. Therefore, this is the second of having trenches etched in the N+ source region. This is an advantage. The same masking step is used to perform SiC dry etching and then to inject the PS#1 region. This is achieved with just one masking step. In one embodiment, the PS#2 region is masked together with the N+ source region in the same masking step. The SiC trenches and PS#1 regions are formed. The SiC trenches and PS#1 regions are formed again using the same masking step. In this embodiment, four features are created using two masking steps.

[0328] In the embodiments described herein, deep ion implantation is not required, so the PS#1 sinker Streak is reduced. High-dose deep ion implantation is expensive. Also, having deep P+ in the periphery is beneficial to prevent the formation of fracture regions. In the embodiments herein, a single step is used to generate PS#1 and trenches, thus preventing fracture in the periphery. Avoid the region. When forming a self-aligned MOS channel, the N+ source region is the device Formed in any location having a p-well region extending to the periphery. This configuration avoids damage in the surrounding area due to the formation of trenches and PS#1.

[0329] The embodiment shown in Figure 2A is a unit cell of the cross-sectional structure of a SiC DMOSFET. The important areas are ion implantation or epitaxy of p-type species such as aluminum or boron. This is the p-well region 203 formed by regrowth, N+ source region 204, N-drift layer 202 , and the N+ substrate 201 are present. In the ON state when the gate voltage is applied to the polysilicon gate 206, current flows from the drain 201 through the inversion layer formed on top of the p-well layer 203, and through the N+ substrate. It flows vertically, passing through region 204 and exiting through source metallization 208. In the off or blocking state, the voltage is supported across the p-well 203 and the N-drift layer 202 junction, with a PN junction formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. The power MOSFET has a pitch of the unit cell, which is the repeating unit of the MOSFET, and a p-well where the inversion channel is formed. There are several important characteristics, including the channel length, which is the well portion; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 205. A key feature is the ILD layer 207, used to isolate the source interconnect metallization 208 from the polysilicon gate 206. At the very center of the unit cell is a P+ plug layer 209 grounded with an N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region using the N+ source contact. Typically, p+ plug injection is The depth is made shallower than the p-well region, as shown in Figure 2A. The DMOSFET device structure is In particular, during high drain bias (blocking mode) operation, a high electric field is present within the gate oxide layer 205. This can result in high electric field concentration at the corners of the p-well region 203. A high critical electric field for breakdown in 4H-SiC (~3MV / cm) results in a very high electric field (>5MV / cm) in the gate oxide. Fowler-Nordheim tunneling current can lead to such a high electric field in the gate oxide. This is observed, and can result in trapped charge in the gate oxide, which degrades the reliability of the device. In embodiments herein, the lateral spacing between p-well regions (JFET regions) suppresses the electric field in the gate oxide while ensuring that the on-resistance of the MOSFET is sufficiently low. It is made narrow enough.

[0330] Figure 2B shows a breakdown simulation of the SiC MOSFET shown in Figure 2A. The simulation shows a peak electric field located at the corner of the p-well region, which is a specific high electric field within the gate oxide layer. This creates a field. The electric field is strongly concentrated at the corners of the p-well region because it is the region of maximum curvature. (This embodiment has limitations.)

[0331] The embodiment shown in Figure 3 is a cross-sectional unit cell of a SiC DMOSFET. A key area of ​​this device is ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. This is the p-well region 303 formed by the following. An N+ source region 304, an N-drift layer 302, and an N+ substrate 301 are present. In the ON state when the gate voltage is applied to the polysilicon gate 306, The current flows perpendicularly from the drain 301, through the inversion layer formed on top of the p-well layer 303, through the N+ source region 304, and out through the source metallization 308. Power MOSFETs have several important characteristics, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 305. A key feature is the ILD layer 307 used to isolate the source interconnect metallization 308 from the polysilicon gate 306. Here, the P+ plug region 209 of the SiC DMOSFET from Figure 2A is replaced by a deep P-type sinker #1 (PS#1) region 309. The depth of the PS#1 region is greater than the depth of the p-well region. During the off-state or blocking state, the structure shown in Figure 2A is broken between the p-well 203 and the N-drift layer 202, particularly in the curvature of the p-well region. However, in the state where PS#1 region 309 is introduced in Figure 3, the electric field in which destruction is likely to occur is also The main region is located in the middle of the diagram, essentially between the PS#1 region 309 and the N-drift layer 302. The presence of a deeper PS#1 region indicates a peak electric field from the corner of the p-well region 303 to the PS#1 region 309. The position is shifted. In 4H-SiC during high-drain bias operation, the peak electric field is located further away from the gate oxide 305. The electric field within the gate oxide 305 is lower than the electric field of the device in Figure 2A.

[0332] Figures 4A to 4R illustrate the process for manufacturing the structure shown in Figure 3. The manufacturing process for the SiC DMOSFET is on a SiC substrate 401, and appropriate doping (10) is applied to the epitaxial layer 402 shown in Figure 4A. 14 ~10 18 cm -3 It starts with the use of 4H-SiC Si-plane epitaxial wafers having a thickness (1 μm to 300 μm). Blanket hard mask 403 (silicon dioxide, silicon nitride, silicon oxynitride, or nickel A CVD deposition layer of metal layers such as KEL (with a thickness in the range of 50 nm to 5 μm) is deposited in Figure 4B, then patterned using photolithography as shown in Figure 4C, followed by dry etching (e.g., using reactive ion etching). In Figure 4D, P-type implantation 404 (with an energy in the range of 10 keV to 800 keV, 10 12 cm -2 ~10 15 cm -2In injection doses ranging from boron to aluminum, p-well 405 is shown in Figure 4E. Mask 403 is removed, and another hard mask layer 406 is deposited (CVD deposited silicon dioxide, silicon nitride, acid). It contains a metal layer such as silicon nitride or nickel, with a thickness in the range of 50 nm to 5 μm, as shown in Figure 4F. Turned to define the N+ source region. For source (SRC) injection, within the unit cell. Please note that the mind is masked. As shown in Figure 4G, SRC(n + source region)407 is n Type (n+) impurity 408 (containing nitrogen or phosphorus) is ionized at energies in the range of 10 keV to 500 keV. 13 cm -2 ~10 16 cm -2 It is formed by injecting in amounts within the range of hard mask 406. After removal, another hard mask layer 409 is deposited and patterned in Figure 4H. The PS#1 region 411 is formed by implanting p-type impurities 410 in Figure 4H. Deep PS#1 regions are formed using ion implantation of aluminum or boron, which are p-type dopants commonly used in 4H-SiC. It can be formed. Boron has a significantly higher injection range compared to aluminum, so it can be advantageously used to form this deep P-type sinker region, and boron can be used The deep implantation used allows for formation with lower ion implantation energies. For example, the PS#1 region can be formed by boron implantation with a depth 20-50% greater than that of the p-well region. This can be done. Boron injection is 10 12 cm -2 ~10 15 cm -2 Injection volume within the range of 10 keV to 800 keV It may contain energy. In related embodiments of the present invention, doping of the PS#1 region A profile is formed on the SiC surface by gradually decreasing the doping concentration, which has a peak value. This gradient doping profile for the PS#1 region can prevent the formation of sharp angles in the three-dimensional landscape, which is beneficial for spreading the peak electric field over a larger area during high-drain bias operation, resulting in a higher breakdown voltage. In one example, the PS#1 region is close to the SiC surface. 19 cm -3 ~I0 20 cm -3 It can be formed with peak doping in the range of (10) as a function of depth into silicon carbide, background N-drift layer doping (10 14 ~10 16 cm -3 It decreases linearly up to the range of PS#1. The gradient doping profile is supported by a sufficient portion of the drain potential within the PS#1 region. This is not limited to the N-drift region. As a result, a pseudo-charge equilibrium structure is created, which is larger This promotes dielectric breakdown across the SiC region, resulting in a lower critical electric field at the time of dielectric breakdown. As a result, the electric field inside the gate insulator is reduced. Subsequently, in Figure 41, the hard mask 409 is removed (using either dry etching or wet etching techniques, which are commonly practiced by those skilled in the art). Next, in Figure 4J, the gate oxide is The oxide layer 412 is thermally grown or deposited using chemical vapor deposition (CVD). The gate oxide thickness may be in the range of 10 nm to 100 nm. Dry or wet hot acid is used for oxide growth. Either of the following methods can be used: Plasma-enhanced CVD (PECVD) or low-pressure CVD (LPCVD) can be used for gate oxide deposition. Next, in Figure 4K, a polysilicon gate layer is deposited on the upper 413. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerate-doped in situ or in a subsequent step using boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon depositing chemical. Post-deposition doping of polysilicon may be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700-900°C. As shown in Figure 4L, a hard mask 414 is deposited on top, and Turning is performed. The polysilicon gate layer 413 is etched using the patterned mask layer 414 in Figure 4M. Next, the mask layer 414 is removed from the top in Figure 4N. An interlayer insulating film (ILD) layer 415 (containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof with a thickness of 50 nm to 1000 nm) is deposited on the wafer, a hard mask 416 is deposited and patterned on top to define the ILD opening, and the ILD layer is patterned using the hard mask 416 as shown in Figure 40. Furthermore, the gate oxide is etched using the same mask 416 in Figure 4P. Next, the mask 416 is removed, and nickel silicide regions 417 are formed on the exposed SiC surface in Figure 4Q. Interconnecting metal layer 418 (Al or Ag or Au Either of the above is deposited and patterned on the top and bottom of the chip in Figure 4R.

[0333] The main problem in the prior art device shown in Figure 1A, as recognized by the authors of this invention, is pwe The problem is that the PS#1 region does not effectively shield the sensitive gate oxide from the high electric field present in 4H-SiC, especially during high drain bias (blocking mode operation). This shifts the peak electric field position from the corner of the p-well region to the PS#1 region. In other words, the peak electric field position in 4H-SiC during high-drain bias operation shifts further away from the gate oxide.

[0334] The advantage of this embodiment is that the dielectric breakdown location is from the corner of the p-well region to the gate oxide interface. It is moved to the base of the newly formed PS#1 region, which is further away and deeper within the semiconductor. The result is that the electric field in the gate oxide of the device structure incorporating the PS#1 region is significantly lower than that of the conventional device, as shown by the device simulation using SILVACO ATLAS in Figure 5B.

[0335] The embodiment shown in Figure 5A is a cross-sectional unit cell of a vertical power DMOSFET. The important areas are ion implantation or epitaxy of p-type species such as aluminum or boron. This is the p-well region 503 formed by gal regrowth. An N+ source region 504, an N-drift layer 502, and an N+ substrate 501 are present. The gate voltage is applied to the polysilicon gate 506. In this state, the current flows from the drain 501 through the inversion layer formed on top of the p-well layer 503, and N+ The current flows perpendicularly, passing through the source region 504 and exiting through the source metallization 508. Power MOSFETs have several key features, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 505. Another feature is the ILD layer 507, which is used to insulate the source interconnect metallization 508 from the polysilicon gate 506. Here, the second P below the N+ source region 504 The type sinker #2 (PS#2) region 510 is formed in addition to the PS#1 region 509, which has already been described in the embodiment shown in Figure 3. The PS#2 region is formed to be deeper than the p-well region 503 and shallower than the PS#1 region 509. For example, the PS#2 region 510 can be 20% deeper than the p-well region 503, and PS Region #1 509 can be 20% deeper than PS#2 region 510.

[0336] The presence of the PS#2 region is peaked under high-drain bias operation between the PS#1 and PS#2 regions. This results in the sharing of the electric field. The presence of the PS#2 region is beneficial for the device under high drain bias conditions. This mitigates the peak electric field maxima in the structure. In the conventional SiC MOSFET shown in Figure 1A, p-wave The design of the region must satisfy conflicting requirements. The electrical dose in the p-well region must be high enough to prevent reach-through breakdown under off-state (high drain bias) operation. However, at the same time, the p-well region The surface doping must be low enough to maintain a moderately low gate threshold voltage and device on-resistance. In this context, the PS#2 region introduced in this embodiment is It can be considered a secondary p-well region, preventing reach-through breakdown and high dray The design can be primarily aimed at properly shaping the electric field profile under non-biased operation. The presence of the PS#2 region frees up constraints in the design of the primary p-well region, which can be used for on-state related device metrics such as gate threshold voltage and on-resistance. The introduction of the PS#2 region gives designers more flexibility in designing a p-well region suitable solely for MOS channel formation, as the p-well region does not need to be designed for the purpose of supporting breakdown voltage.

[0337] Failure simulation of a SiC DMOSFET designed according to the two embodiments described in Figures 3 and 5A. Figure 5B shows that the peak electric field position has shifted from the corner of the p-well region to the center of the unit cell. This demonstrates that a lower electric field is produced in the gate oxide layer.

[0338] Figures 6A to 6J illustrate the process for manufacturing the structure shown in Figure 5a. SiC DMOSFET Manufacturing The process is carried out on the SiC substrate 601, and appropriate doping (10) is performed for the epitaxial layer 602 shown in Figure 6A. 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-plane epitaxial wafer having a thickness (1 μm to 300 μm). A blanket hard mask 603 (containing a CVD deposited layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, with a thickness ranging from 50 nm to 5 μm) is deposited in Figure 6B, then patterned using photolithography as shown in Figure 6C, followed by dry etching (e.g., using reactive ion etching). In Figure 6D, P Type 604 injection (with energies in the range of 10 keV to 800 keV, 10 12 cm -2 ~10 15 cm -2 Injection dose within the range Perform a procedure (containing boron or aluminum) to form the p-well 605 in Figure 6E. Mask 603 The first layer is removed, and another hard mask layer 606 is deposited (CVD deposited silicon dioxide, silicon nitride). A metal layer, such as silicon oxynitride or nickel, with a thickness ranging from 50 nm to 5 μm, is formed in Figure 6F to define the N+ source region. Note that the center of the unit cell is masked for source (SRC) injection. As shown in Figure 6G, the SRC (n+ source region) 607 contains n-type (n+) impurities 608 (containing nitrogen or phosphorus) at energies ranging from 10 keV to 500 keV. In terms of energy, 10 13 cm -2 ~10 16 cm -2It is formed by implanting with an implantation dose within the range. The PS#2 region 609 is formed by implanting a p-type impurity 610, as shown in Figure 6(h). Deep PS#2 regions can be formed using ion implantation of aluminum or boron, which are p-type dopants commonly used in 4H-SiC. Boron has a significantly higher implantation range compared to aluminum, making it advantageous for forming this deep p-type sinker region. It can be used for deep implantation with boron, and can be formed with lower ion implantation energies. When using aluminum, the PS#2 region is in the range of 100 keV to 1 MeV. The energy injected around, and 10 13 cm -2 ~10 16 cm -2 This can include injection doses in the range of 50 keV to 800 keV. When using boron, the PS#2 region can include injection energies in the range of 50 keV to 800 keV, and 10 13 cm -2 ~10 16 cm -2 This can include an implantation dose in the range of . The same hard mask 606 used to form the N+ source region is used to define the ion-implanted PS#2 region. In this case, the PS#2 region is self-aligned below the N+ source region. See Figure 61. Then, the hard mask 606 is removed, another hard mask layer 612 is deposited and patterned. The PS#1 region 611 is formed by implanting P-type impurities 613, which may contain aluminum or boron. Boron has a significantly higher implantation range compared to aluminum, so it can be advantageously used to form the PS#1 region, and deeper implantation using boron is more It can be formed with low ion implantation energy. When using aluminum, the PS#1 region can be formed with implantation energy in the range of 100 keV to 1 MeV, and 10 13 cm -2 ~10 16 cm -2 Note on the scope It can include an input dose. When using boron, the PS#1 region has an injection energy in the range of 50 keV to 800 keV, and 10 13 cm -2 ~10 16 cm -2 It can include injection doses in the range of [range]. The PS#2 region can be formed deeper than the p-well region, but deeper than the PS#1 region. This can be achieved. As a second example of this embodiment, the PS#2 region can be made 20% deeper than the p-well region, and the PS#1 region can be made 20% deeper than the PS#2 region. Related embodiments of the present invention In this state, the doping profiles in the PS#1 and PS#2 regions have peak values ​​on the SiC surface. This can be achieved by gradually decreasing the doping concentration. This gradient doping profile for PS#1 and PS#2 regions prevents the formation of sharp angles in the 3D landscape. This allows for spreading the peak electric field over a larger area during high-drain bias operation, resulting in a higher breakdown voltage. For example, PS#1 The PS#2 region is closer to the SiC surface and the PS#2 region is closer to the N+ source region, respectively. 19 cm -3 ~10 20 cm -3 Peak doping in the range can be formed. The doping concentration in the PS#1 and PS#2 regions is a function of depth into silicon carbide, relative to the background N-drift layer doping (10 14 ~10 16 cm -3 It can decrease linearly within the range of PS#1 / PS#2. The gradient doping profile results in a sufficient portion of the drain potential being supported not only in the N-drift region but also within the PS#1 / PS#2 region. This results in a pseudo-charge equilibrium structure, which promotes dielectric breakdown across a larger SiC region, and consequently the critical field at dielectric breakdown is The voltage decreases, resulting in a lower electric field within the gate insulator. Following the formation of the PS#1 region, the hard mask 612 (dry etching or wet etching) shown in Figure 6J is removed. The remaining steps in the process to create the structure shown in Figure 5A follow exactly the same steps as shown in Figures 4J to 4R.

[0339] This "staircase" arrangement of PS#1 and PS#2 regions with specific depths can result in even lower electric fields within the gate oxide under high drain bias operation. The advantage is that the p-well region can be created more shallowly and with a lower injection dose. This can reduce the on-resistance of the device and simultaneously increase the gate threshold voltage, both of which are desirable from an application standpoint. Therefore, between off-state performance and on-state performance A better trade-off becomes possible through the teachings of this invention.

[0340] The embodiment shown in Figure 7A is a cross-sectional unit cell of a SiC DMOSFET. The key areas are ion implantation or epitaxial implantation of p-type species such as aluminum or boron. This is the p-well region 703 formed by regrowth. N+ source region 704, N drift layer 702, And an N+ substrate 701 is present. In the ON state when the gate voltage is applied to the polysilicon gate 706, current flows from the drain 701 through the inversion layer formed on top of the p-well layer 703, and into the N+ saw The current flows perpendicularly through the PS#1 region 704 and exits through the source metallization 708. Power MOSFETs have several key features, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 705. Another feature is the interlayer dielectric (ILD) layer 707 used to insulate the source interconnect metallization 708 from the polysilicon gate 706. Here, the trench 711 is etched into the N+ source region 704 before the PS#1 region 709 is injected. Here, in addition to the PS#1 region 709, the PS#2 region 710 is formed beneath the N+ source region 704. The PS#2 region is the p-well region It is formed deeper than region 703 and shallower than PS#1 region 709. This improves the reliability of the device. For robust blocking capability of the device operation, it is desirable to move the electric field position far from the gate oxide interface. In the unit cell furthest from the gate oxide 705 Shifting the yield position to the center is one embodiment, in which etching the reset trench 711 into the N+ source region 704 effectively creates a deeper PS#1 region than those shown in Figures 3 and 5A, further moving the electric field away from the gate oxide region.

[0341] The PS#1 region is designed to be the deepest in the P-type sinker region. In SiC technology, Boron implantation is one technique for forming deep P-type regions, but commercially available ion implantation devices... Considering the maximum range, ion implantation into SiC is not an easy process, and deep ion implantation is required. This proved to be particularly difficult. The functionality of the N+ source region, also called the source trench, can be realized in the PS#1 region with lower ion implantation energies, without compromising implantation depth. The goal is to reduce the cost and time of this injection step without any further work. In the embodiments herein, the trenches can be dry-etched to SiC after the injection of the N+ source region, but before the injection of the PS#1 region. The same hard mask layer used for PS#1 injection can be used to etch the source trenches to SiC. In this embodiment, the hard mask layer is first patterned, and then the trenches are dry-etched to SiC. Immediately afterward, the PS#1 region is ion-implanted. The formation of the source trench naturally extends to the depth of the PS#1 region. Therefore, the PS#1 region is realized with a lower ion implantation energy. This allows for a reduction in the cost / time of this injection step without compromising the injection depth. The formation of the source trench also removes the N+ source region and the P well region and the N+ source region. This enables direct connection with the mixed contact, thereby grounding the p-well and short-circuiting the p-well region with the N+ source region.

[0342] Figure 7B is a dielectric breakdown simulation of a SiC MOSFET designed according to the embodiment shown in Figure 7A, where the peak electric field position is moved from the corner of the p-well region to the center of the unit cell. This demonstrates that a lower electric field is produced in the oxide layer.

[0343] Figures 8A to 8BB illustrate the process for manufacturing the SiC DMOSFET structure shown in Figure 7A. The SiC DMOSFET manufacturing process is carried out on a SiC substrate 801, and appropriate doping (10) is performed for the epitaxial layer 802 shown in Figure 8A. 14 ~10 18 cm -3 ) and thickness (1 μm to 300 μm) of 4H-SiC Si plane epitaxial wafers It starts with use. A blanket hard mask 803 (including a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, with a thickness in the range of 50 nm to 5 μm) is deposited as shown in FIG. 8B, and then, as shown in FIG. 8C, it is patterned using photolithography, and then dry etching (for example, using reactive ion etching) follows. In FIG. 8D, a P-type implantation 804 (using an energy in the range of 10 keV to 800 keV and an implantation dose in the range of 10 12 cm -2 ~10 15 cm -2 and containing boron or aluminum) is performed to form a p-well 805 in FIG. 8E. The mask 803 is removed, and another hard mask layer 806 is deposited (CVD deposited and containing a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, with a thickness in the range of 50 nm to 5 μm), patterned in FIG. 8F to define an N+ source region. As shown in FIG. 8G an n+ source region 807 is formed by implanting an n-type (n+) impurity 808 (containing nitrogen or phosphorus) with an energy in the range of 10 keV to 500 keV and an implantation amount in the range of 10 13 cm -2 ~10 16 cm -2 . The PS#2 region 809 is formed by implanting a P-type impurity 810 in FIG. 8H. The deep PS#2 region can be formed using ion implantation of aluminum or boron, which are p-type dopants commonly used in 4H-SiC. Boron can be advantageously used to form this deep P-type sinker region because it has a significantly higher implantation range compared to aluminum, and deep implantation using boron can be formed at a lower ion implantation energy. The patterned hard mask 806 is removed from the top in FIG. 8I. Another hard mask layer 811 is formed on the top in FIG. 8J and patterned in FIG. 8K. The patterning ... ... The applied mask 811 is used to etch the substrate in FIG. 8L by etching 812 to form a recess region. The source trench, which is the recess region 813, penetrates the source region in FIG. 8(M) and is formed in the substrate. The P-type implant 814 in FIG. 8N is performed to create the PS#1 region. When aluminum is used, the PS#1 region can include an implantation energy in the range of 100 keV to 1 MeV, and an implantation dose in the range of 10 cm 13 to 10 -2 cm 16 to 10 -2 cm 13 When boron is used, the PS#1 region can include an implantation energy in the range of 50 keV to 800 keV, and an implantation dose in the range of 10 -2 cm 16 to 10 -2 cm 14 The PS#1 815 is formed by self-aligned implantation of p-type impurities in FIG. 8O. As more fully described in the above embodiments, it is preferable to use a linear gradient doping profile for the PS#1 / PS#2 regions instead of a uniform (abrupt) doping profile. As a result, a sufficient portion of the drain potential is supported within the PS#1 / PS#2 regions, not just in the Ndrift region. As a result, a pseudo charge balance structure is generated, which promotes breakdown over a larger SiC region, resulting in a lower critical electric field at breakdown and, as a result, a lower electric field within the gate insulator. The PS#1 region is designed to be the deepest within the P-type sinker region using boron implantation, and the formation of the trench naturally extends the depth of the PS#1 region. The same hard mask used to etch the source trench 811 is used to define the PS#1 region. In the field of the present invention the resulting

[0344] PS#1 region is designed to be the deepest within the P-type sinker region using boron implantation, and the formation of the trench naturally extends the depth of the PS#1 region. The same hard mask used to etch the source trench 811 is used to define the PS#1 region. In the field of the present invention As is evident to those familiar with the subject, SiC trenches can be formed using dry etching techniques, including reactive ion etching and inductively coupled plasma (ICP)-RIE. While Figure 7A shows a 90° sidewall inclination for this trench region, forming trench regions with lower sidewall angles (60-90°) reduces the curvature of the PS#1 region, thus improving the device's performance. This is advantageous because it improves the blocking performance.

[0345] The patterned hard mask 811 is removed from the top of Figure 8P. In Figure 8Q, An oxide layer 816 for the oxide is grown. The polysilicon gate layer is the upper part 817 in Figure 8R. It is deposited on top. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerate-doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon can be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700-900°C. As shown in Figure 8S, a hard mask 818 is deposited on top, and the pattern is applied. The polysilicon gate layer 817 is etched using the patterned mask layer 818 in Figure 8T. Next, the mask layer 818 is removed from the top in Figure 8U. An interlayer dielectric (ILD) layer 819 (containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof, with a thickness of 50 nm to 1000 nm) is deposited on the wafer in Figure 8V. A hard mask 820 is deposited and patterned thereon to define the ILD openings in Figure 8W. As shown in Figure 8X, it is patterned using hard mask 820. Furthermore, The oxide 816 is etched using the same mask 820 in Figure 8Y. Next, the mask 820 In Figure 8Z, it is removed. In Figure 8AA, a nickel silicide region 821 is formed on the exposed SiC surface. The interconnection metal layer 822 (either Al, Ag, or Au) is the chip in Figure 8BB. It accumulates and forms patterns on the upper and lower parts of the pu.

[0346] An advantage of the embodiments described herein is that the source trench region is etched before injection of the PS#1 region. This causes the dielectric breakdown location to move further into the semiconductor, further away from the gate oxide layer. Due to the inherent hardness of silicon carbide, the observed range (depth) of ion-implanted dopants is significantly lower than in silicon. For example, forming deep (>0.3 pm) ion-implanted layers in silicon carbide requires extremely high implantation energy (>300 keV), which necessitates double or triple ion-implanted species, dramatically reducing throughput and increasing the cost of these ion-implantation steps. By forming source trenches as described in this embodiment, the double / triple ion-implantation steps become unnecessary, and low-cost use of high-throughput single ion implantation can be utilized to achieve the PS#1 region.

[0347] The embodiment relates to a SiC DMOSFET power device that can be used to manufacture a self-aligned power MOSFET.

[0348] One embodiment relates to increasing the MOS channel density.

[0349] One embodiment relates to increasing the effective field effect mobility.

[0350] One embodiment relates to improved device reliability.

[0351] One embodiment relates to reducing the ON resistance for a given chip size.

[0352] One embodiment relates to the design and manufacture of a self-aligning power device.

[0353] One embodiment relates to the design and manufacture of MOS channels having a submicron channel length. .

[0354] One embodiment relates to the removal of parasitic N+ source regions inadvertently formed around a device.

[0355] The embodiment shows a p-well having source ohmic contact in the active region of the device. Regarding proper grounding of the area.

[0356] One embodiment relates to the removal of parasitic NPN transistors formed in the active region and peripheral region of a self-aligned power device.

[0357] The embodiment relates to a combination of appropriately positioned source trenches and ion-implanted p+ plug regions, with proper grounding of the p-well region within the main active MOSFET region and the formation around the MOSFET This enables the removal of parasitic N+ source regions.

[0358] One embodiment relates to forming a highly doped P+ plug region around the MOSFET, particularly below the gate pad and gate bus region.

[0359] One embodiment relates to suppressing false turn-on of a MOSFET during high-speed switching transitions at vulnerable locations due to a decrease in threshold voltage caused by the body bias effect.

[0360] One embodiment relates to improving the maximum dV / dt rating of a MOSFET.

[0361] One embodiment relates to an improvement in the maximum avalanche energy rating of a MOSFET.

[0362] One embodiment relates to a dedicated process step used to mask the injection of N+ source regions in the peripheral area of ​​a device. In this embodiment, the P+ plug region is formed first, and the source trench is formed later in the process of the ILD etching step.

[0363] One embodiment relates to a dedicated hard mask that is applied after the sidewall spacer is formed and before N+ source injection. This layer prevents the formation of N+ source regions in the peripheral part of the device, and thus parasitic NPN structures in the peripheral part of the device are avoided.

[0364] One embodiment relates to a p-well region (P-well #2) located below the N+ source region and electrically connected to the main p-well region. P-well #2 is particularly important for reach-through fracture after source trench formation. To prevent damage, an additional electrical dose is provided below the N+ source injection.

[0365] One embodiment involves injecting an N+ source region in the peripheral part of the device and masking the N+ source region in the central part of the unit cell in the active region, thereby enabling ohmic contact with the p-well region. A special process step is used to enable contact.

[0366] One embodiment relates to forming segmented polysilicon gate metallization around the device instead of a continuous gate bus that reduces the gate body capacitance of the MOSFET.

[0367] One embodiment relates to reducing the gate capacitance of a MOSFET.

[0368] One embodiment relates to increasing the switching speed of a MOSFET.

[0369] The embodiments described herein are for the design and manufacture of self-aligned SiC DMOSFET power devices. This demonstrates a novel technology. Due to the limited mobility achievable on a SiC planar DMOSFET, a submicron-length n-welt is used so as not to degrade the overall power and on-resistance of the MOSFET. It is necessary to form a flannel.

[0370] In a MOSFET, the channel region is due to the offset between the p-well and the N+ source region. The p-well and N+ source region are formed by two separate masking steps, which may result in lithographic mismatches, leading to asymmetric MOSFET channel lengths on two sides of the unit cell. In the embodiments described herein, MOS To minimize this asymmetry in channel length, p-well and N+ source injection are used. This is done using a self-alignment method. To achieve a self-aligned MOSFET, several methods are used, including one that uses an oxide spacer approach to form a self-aligned p-well and N+ source region. That technique has been proposed in the literature, and N+ source injection is under p-well injection.

[0371] Embodiments of this specification describe several innovative techniques in self-aligned channel formation that not only enable the elimination of misalignment errors during the manufacturing of SiC MOSFETs but also allow for the possibility of reducing channel length. The channel length can be made smaller using narrow spacers. The self-aligning process offers the advantage of creating arbitrarily short channel lengths and eliminating misalignment, but because the n+ region is co-incident with the p-well region, This creates several other problems regarding the structure of the outer device of the knit cell.

[0372] In conventional MOSFETs where the p-well and N+ source region do not self-align, N+ source injection is formed. There is a dedicated masking step used for this purpose. In the embodiments described herein, there is no dedicated masking step for performing N+ source injection in the self-alignment process. p-well injection is performed, followed by spacer deposition, then spacer etching, and so on. There is a dedicated masking step for injection to realize the N+ source region. N+ source injection exists wherever p-well regions exist. It is undesirable to have N+ source injection at the periphery of the device. It is important to terminate the device with p-type injection alone. The various embodiments described herein introduce techniques that can eliminate N+ source injection around the device and replace it with several other regions.

[0373] The active region of a MOSFET is where current conduction occurs, while the peripheral region of the MOSFET is where the device edge terminations are provided to block any voltage. The gate pad and gate bus regions are also considered part of the peripheral region of the MOSFET to illustrate the innovations described herein. In the embodiments described herein, the combination of appropriately positioned source trenches and ion-implanted p+ plug regions is the primary active MOSFET region. This enables proper grounding of the casing region and removal of parasitic N+ source regions formed around the MOSFET.

[0374] In conventional MOSFETs without self-alignment, source injection can be performed whenever necessary, and then a region for grounding the p-well can be created. In self-aligned DMOSFETs, source injection is self-aligned to the p-well, so not only the p-well extends to the periphery, but the N+ source region also extends to the periphery.

[0375] A parasitic NPN transistor is a MOSFET unit formed by an N+ source region acting like an N+ emitter, a p-well region forming a P-base, and an N+ source ohmic contact. It is present in the active region of the cell. Even under peripheral and gate pad metallization of the device, N+ source ohmic contacts are absent, and as a result, parasitic NPN transistors The emitter and base regions are not short-circuited in this region. Parasitic NPN transistor Although it is not activated under the normal DC or switching operation of the MOSFET, operating the device under extreme conditions may trigger the parasitic NPN transistor. ru.

[0376] In the active region, the emission of this parasitic NPN transistor is reduced by forming a source trench. The dent and base are short-circuited, ensuring that this parasitic transistor does not turn on in the active region of the device. Around the device without a source trench, the parasitic NPN transistor The transistor exists despite being short-circuited in the active region. Parasitic NPN transistors are present in the surrounding region. It may turn on in the edge region, which is undesirable.

[0377] In embodiments of this specification, a source trench is formed around the device, and a p-type injection plug area is formed. By creating a region, it is guaranteed that parasitic NPN transistors will be completely eliminated. Since the emitter of this transistor is completely removed, any kind of parasitic BJT structure There is no possibility of this. Typically, a separate masking step is performed to mask the formation of N+ source regions at these locations, but in the embodiments herein, the source trench removes parasitic N+ source regions and makes them self-aligned with the source trench and p-we It can be advantageously used to replace the p+ plug area that is electrically connected to the p+ area.

[0378] The doping concentration of the P+ plug region located around the device can be advantageously very high. This helps to avoid the other parasitic effects described here. In a typical power MOSFET device structure, a moderately doped P-well region is as described above. It exists in the peripheral area of ​​the device, regardless of the presence or absence of parasitic N+ source regions. When co-incident with the p-well region at the periphery of the device (i.e., when the n+ source region is not intentionally masked from the periphery region), this results in partial compensation of the p-type electrical dose in the p-well region. In either case, the p-well region around the device is extremely resistant from an electrical standpoint. This can be the case. During switching of a power MOSFET from the off state to the on state, or vice versa, the extremely high rate of change (or dV / dt) of the drain voltage is within the active region of the MOSFET. The volume collected through this resistant peripheral p-well region is collected only by sohmic contact. This can result in a quantitative current flow. In other words, high dV / dt during device switching Therefore, the capacitive current generated must traverse an extremely long distance from the periphery of the device to the source ohmic contact within the active region. High resistivity in the void region can lead to a significant body bias effect, which results in a decrease in the device threshold voltage in those regions. Therefore, these parts of the device may exhibit false turn-on, leading to device failure / destruction. This may be the case. The highly doped P+ plug region in this embodiment can mitigate the aforementioned effect by reducing the amount of body bias generated in the peripheral region of the MOSFET, which makes the MOSFET described in this embodiment more resilient to dV / dt induced faults. In other words, the MOSFET structure described in this embodiment has a higher dV / dt rating than conventional MOSFETs. This reduces switching losses and improves circuit efficiency.

[0379] In one embodiment of this specification, a dedicated process step is used to mask the injection of N+ source regions in the peripheral area of ​​the device. In this embodiment, the P+ plug region is formed first, and the source trench is formed later in the process of the ILD etching step. ru.

[0380] In the embodiments described herein, a source trench exists in the active region of the device, but no source trench exists around the device. A dedicated masking step is dispersed between the formation of the sidewall spacer after p-well injection and before N+ source injection to mask N+ source injection from the peripheral region of the MOSFET. The masking layer protects the periphery of the device from the source injection region. A second, deeper p-well region (P-Well #2) is used for N+ source injection and The same masking step is used to form the P+ plug region. The P+ plug region is formed in a later step in both the active region and the peripheral region of the device. The trenches are then etched through the N+ source region at discrete locations within the active region to contact the P+ plug region and short-circuited to the N+ source region by ohmic or silicide metallization.

[0381] In one embodiment of this specification, source region injection is masked from the periphery of the device. A dedicated process step is used to mask the injection of N+ source regions in the peripheral part of the device, and the N+ source region in the central part of the unit cell in the active region is used to enable ohmic contact to the p-well region.

[0382] In one embodiment of this specification, polysilicon metallization is segmented around the device, rather than being a single continuous layer as is commonly seen. After p-well injection, N+ Prior to the source injection, there is a dedicated masking step dispersed during the formation of the sidewall spacers to mask the N+ source region from both the peripheral region of the device and selected regions within the active region.

[0383] In one embodiment of this specification, segmenting polysilicon metallization reduces parasitic gate-to-body or gate-to-source capacitance, which is a parasitic capacitance. The polysilicon islands are not cut but connected at positions perpendicular to the plane of the drawing. Reducing parasitic capacitance allows the device to switch faster, which increases circuit efficiency by reducing switching losses.

[0384] The embodiment shown in Figure 10 shows the unit cell and device peripheral portions of the cross-sectional structure of the SiC DMOSFET. Yes. A key area of ​​this device is the ion injection of p-type species such as aluminum or boron. This is the p-well region 203 formed by input or epitaxial regrowth. An N+ source region 204, an N-drift layer 202, and an N+ substrate 201 are present. In the ON state, when a gate voltage is applied to the polysilicon gate 208, current flows vertically from the drain 201, through the inversion layer formed on top of the p-well layer 203, through the N+ source region 204, and out through the source metallization 211. In the OFF or blocking state, the voltage flows through the p-well 203, the N-drift layer 202, and the substrate 201. The PN junction is supported across the lift layer 202 junction and is formed between the p-well and the N-drift layer. A PN junction exists. The voltage applied to the structure is supported across this PN junction in reverse bias. Power MOSFETs have a pitch of the unit cell, which is the repeating unit of the MOSFET; a channel length, which is the portion of the p-well where the inversion channel is formed; a junction gate field-effect transistor (JFET) region, or the distance between two consecutive p-wells, called the JFET gap; and a gate acid. There are several important features, including the thickness of the 207 material. Another feature is the source interconnect metallizer. This is the ILD layer 209 used to insulate the emission 211 from the polysilicon gate 208.

[0385] The source trench region 205 is dry through the N+ source layer at a selected location in the device. This is achieved by etching and a subsequent p-type ion implantation step to realize the p+ plug region 206 below the source trench. At the very center of the unit cell is a p+ plug layer 206 grounded by N+ source metallization. The purpose of the p+ plug in the SiC DMOSFET is to ground the p-well region using the N+ source contact.

[0386] The formation of the source trench 205 device structure enables proper grounding of the p-well region within the main active MOSFET region and the removal of the parasitic N+ source region 204 formed around the MOSFET. When the region is formed in a self-consistent manner with the p-well region, the source trend after the formation of the N+ source region Chi formation removes parasitic N+ source regions from the periphery of the chip device and from below the gate pad region.

[0387] In embodiments of this specification, the combination of a source trench and an ion-implanted P+ plug region provides three important functions. First, it provides proper grounding of the p-well region having source ohmic contact in the active region of the device; second, it helps remove parasitic N+ source regions inadvertently formed around the device; and third, it provides a highly doped P+ plug. The region increases the dV / dt rating of the MOSFET. In the embodiments described herein, both of the above are If not present, ensure the removal of parasitic NPN transistors that would otherwise form in these regions. .

[0388] Parasitic NPN transistors also exist within the MOSFET unit cell, but their shape is determined by the N+ source region. The N+ emitter (formed by the p-well region) and the P-base (formed by the p-well region) are N+ source emitters. It is short-circuited by a contact. However, even under device periphery and gate pad metallization, there is no N+ source ohmic contact, and as a result, the emitter and base regions of the parasitic NPN transistor are not short-circuited in this region. This parasitic NPN transistor is activated under the normal DC or switching operation of the MOSFET. However, operation of the device under extreme conditions such as short circuits or avalanche modes results in the simultaneous presence of very high junction temperatures, high dV / dt, and high current densities, which can trigger parasitic NPN transistors. Typically, a separate masking step is performed to mask N+ source regions so that they do not form at these locations. However, in embodiments herein, source trenches eliminate parasitic N+ source regions and replace them with p+ plug regions that are self-aligned with the source trenches and electrically connected to the p-well regions. It can be used to its advantage for that purpose.

[0389] Figures 11A to 11FF illustrate the process for manufacturing the structure shown in Figure 10. The manufacturing process for the SiC DMOSFET is carried out on a SiC substrate 301, and appropriate doping (10) is performed for the epitaxial layer 302 shown in Figure 11A. 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-plane epitaxial wafer having a thickness (1 μm to 300 μm). A blanket hard mask 303 containing a chemical vapor deposition (CVD) layer with a metal layer thickness of 50 nm to 5 μm, such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, is deposited on Figure 1 IB and then patterned using photolithography, and then, for example, on Figure 11C. As shown, dry etching is performed using reactive ion etching (RIE). Next First, ion implantation or epidural implantation is performed using aluminum or boron as the p-type impurity. By axial growth, p-well regions are formed. In ID in Figure 1, 10 12 cm -2 ~10 15 cm -2 With injection doses in the range of 10 keV to 800 keV, p-type injections 304 containing boron or aluminum are performed to create p-wells 305 in the IE shown in Figure 1.

[0390] The second hard mask layer 306 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, with a thickness in the IF range of 50 nm to 5 μm in Figure 1, and is located on top of the patterned first hard mask layer 303. This is followed by the anisotropy in Figure 11G. Etching 307 is performed to form the side wall spacer 306 as shown in Figure 11H.

[0391] In Figure 11 J, in order to generate the n+ source region 309, n-type injection 308 is performed in Figure 1 II. The n+ source region is affected by ion implantation or epitaxy due to n-type impurities such as nitrogen and phosphorus. It is formed by regrowth. As a result, the source region 309 self-aligns with the p-well region 304. The first and second hard mask layers 303 and 306 are formed together. It is removed in the above-described series of process steps for the self-aligned p-well and N+ source region. One method constitutes forming a region, but other methods are used to achieve the same result. For example, the N+ source region 309 may be formed first after the deposition and patterning of the first hard mask layer, and then further etch-back of the first hard mask layer may be performed. Next, a p-well region 304 is formed.

[0392] Another mask layer 310 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, etc. The metal layer is deposited by CVD deposition and has a thickness ranging from 50 nm to 5 μm in the upper part of Figure 11L. The mask layer 310 is patterned in Figure 11M. The patterned mask 310 is Using the Lye etching method, the substrate 311 in Figure 1 is etched to form a recess region within the SiC. It is used for this purpose. The recessed area penetrates the source area in Figure 11O and is formed in the substrate. The trench is 312. The entire N+ source area is at these selected locations on the device. It is removed by live etching. Using the same hard mask 310, a p+ plug layer is formed in Figure 11Q by injecting a controlled dose of p-type impurities 313, such as aluminum or boron, in Figure 11P. The depth of the p+ plug layer 314 may preferably exceed the depth of the N+ source injection, and in certain mounting configurations, it may exceed the depth of the p-well region. In Figure 11D... 10 13 cm -2 ~10 17 cm -2 With injection doses in the range of 10 keV to 800 keV, P-type injection containing porosin or aluminum is performed to form the P+ plug region. Region 314 is formed beneath a source trench 312 electrically connected to the p-well region 304. The mask layer is removed in Figure HR. The wafer is annealed to activate the implanted impurities.

[0393] The oxide layer 315, which is the gate oxide, undergoes thermal oxidation or silicon dioxide nitridation in Figure 1 IS. It is formed using CVD (Chemical Vapor Deposition) on dielectric layers such as silicon and silicon oxynitride. The thickness of the gate oxide is The wavelength can be in the range of 5 nm to 100 nm. For oxide growth, either dry or wet thermal oxidation can be used. Plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 11T, polysilicone A gate layer 316 is deposited. The polysilicon layer is deposited using PECVD or LPCVD. Obtain. The polysilicon layer is obtained using boron or phosphorus, either in situ or in subsequent steps. Therefore, degenerate doping can be performed. In-situ doping can be carried out by adding a PH3 precursor to the polysilicon deposit chemical. Post-deposition doping of polysilicon may be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 600-900°C. Hard mask 317 is silicon dioxide, silicon nitride, silicon oxynitride Alternatively, a CVD deposition layer of a metal layer such as nickel is deposited and patterned, with a thickness ranging from 50 nm to 5 μm, as shown in Figure 11U. The polysilicon layer 316 is etched using the patterned mask layer 317 in Figure 11V. Next, in Figure 11W, the mask layer 317 is removed. Silicon dioxide, silicon nitride, silicon oxynitride with a thickness of 50 nm to 1000 nm. In Figure 11X, the ILD layer 318, which includes an elementary layer or a stacked combination thereof, is on the wafer. It is deposited there.

[0394] Hard mask 319 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, among other materials. The layer is deposited by a CVD deposition layer, with a thickness ranging from 50 nm to 5 μm at the top, and a pattern is formed at the top to define the ILD opening in Figure 11Y. The ILD layer 318 is as shown in Figure 11Z. The hard mask 319 is used for etching. Furthermore, the gate oxide 315 is the same as shown in Figure 11 AA. The mask 319 is then used for etching. Next, the mask 319 is removed in Figure 1 IBB. In Figure 11CC, a nickel silicide region 320 is formed on the exposed SiC surface. The mask layer 321 is formed by a CVD deposited layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and its thickness ranges from 50 nm to 5 pm at the top, as shown in Figure 11DD. It is being etched. The ILD layer 318 is etched using the mask 321 in Figure 11EE. Layer 321 is removed in Figure 11FF. Either aluminum, silver, or gold phase. The interconnecting metal layers 322 are deposited and patterned on the upper and lower parts of the substrate. Figure 11GG.

[0395] In embodiments of this specification, the same final structures for forming the source trench region and the P+ plug region may be realized alternatively using slightly different approaches. Similar to the methods described above, the p-well region and the N+ source region are realized using a self-aligning process. However, in this embodiment, a P-plug layer may first be formed as an embedded layer located below the N+ source region using deep boron or aluminum implantation. Dry etching for trench realization may be performed after the process. N+ source trenches may preferably be realized after the high-temperature annealing process in one embodiment.

[0396] The embodiment shown in Figure 12 illustrates the unit cell and device periphery of the cross-sectional structure of a SiC DMOSFET. This is the part. The important area of ​​this device is p-type ions such as aluminum or boron. This is a p-well region 403 formed by injection or epitaxial regrowth. An N+ source region 404, an N-drift layer 402, and an N+ substrate 401 are present. In the ON state, when a gate voltage is applied to the polysilicon gate 407, current is formed from the drain 401 to the top of the p-well layer 403. The voltage flows perpendicularly through the inversion layer, through the N+ source region 404, and out through the source metallization 412. In the off or blocking state, the voltage is supported across the p-well 403 and the N-drift layer 402 junction, where a PN junction is formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. The power MOSFET has a pitch of the unit cell, which is the repeating unit of the MOSFET, a channel length which is the portion of the p-well where the inversion channel is formed, and a JFET region or JFET gap. The distance between two consecutive p-wells, and several other factors including the thickness of the gate oxide 407. It has an important feature. Another feature is source interconnection metallization 412 polysilico This is the ILD layer 409 used to insulate from the gate.

[0397] A dedicated masking step is distributed between the formation of the sidewall spacer after p-well injection and before N+ source injection to mask N+ source injection from the peripheral region of the MOSFET. The second, deeper p-well region (P-well #2) 405 is masked using the same masking as that used for N+ source injection. It is formed using a step. The P+ plug area 406 is activated in a later step. It is formed in both the vital region and the peripheral area of ​​the device. The P+ plug layer 406 is N+ source metal It is grounded by the fusion. The purpose of the p+ plug in SiC DMOSFET is the N+ source capacitor. This involves using a tact to ground the p-well region.

[0398] Trench 410 subsequently contacts the P+ plug region, with N+ sources at discrete locations within the active region. Etched through the region, N+ by ohmic silicide 411 metallization The source region is short-circuited. The source trench 410 is etched to SiC in the selected region using the same hard mask used to pattern the interlevel dielectric layer (ILD). It is applied. In the embodiments described herein, the source trench 410 performs two functions. Firstly, Secondly, the source trench exposes the surface of a P+ plug layer pre-embedded beneath the N+ source region for subsequent contact with the ohmic silicide metal, and the source trench is ohmic silicide - Reveals the sidewalls of the N+ source region for subsequent contact with the mic silicide metal.

[0399] In the embodiments described herein, a dedicated hard mask or photoresist layer is applied after the sidewall spacers are formed and before N+ source injection. This layer prevents the formation of N+ source regions around the device, thus avoiding parasitic NPN structures around the device.

[0400] In embodiments of this specification, a second p-well region (P-well #2) 405 is located below the N+ source region 404 and is electrically connected to the main p-well region, particularly in relation to the reaching after source trench formation. - To prevent breakdown, provide an additional electrical dose under N+ source injection. Etching of the source trench inadvertently etches a portion of the primary p-well region beneath the N+ source region. This is done to locally reduce the p-well dose in this region, and these This could result in an undesirable reach-through breakdown at that location.

[0401] Figures 13A to 13GG show the manufacturing process of the structure shown in Figure 12. SiC DMOSFET Manufacturing Process The SiC substrate 501 is suitable for doping (10) for the epitaxial layer 502 shown in Figure 13A. 14 ~10 18 cm -3It starts with the use of 4H-SiC Si-plane epitaxial wafers having a thickness (1 μm to 300 μm). Includes a CVD deposited layer of metal such as silicon oxide, silicon nitride, silicon oxynitride, or nickel. A blanket hard mask 503 with a thickness in the range of 50 nm to 5 μm is deposited in Figure 13B, then patterned using photolithography, and then, for example, as shown in Figure 13C. The p-well regions are then dry-etched using RIE. Next, the p-well regions are first grown by ion implantation or epitaxial growth using aluminum or boron as the p-type impurity. It forms. In Figure 13D, 10 12 cm -2 ~10 15 cm -2 With injection doses in the range of 10 keV to 800 keV, p-type injections 504 containing boron or aluminum are performed to generate p-wells 505 in Figure 13E.

[0402] The second hard mask layer 506 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and in Figure 13F, the patterned first hard A patterned mask layer 503 has a thickness ranging from 50 nm to 5 μm. Subsequently, anisotropic etching 507 is performed as shown in Figure 13G to form sidewall spacers 506 as shown in Figure 13H. The mask layer 508 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, etc. A hard mask layer 508 is deposited by a CVD deposition layer of metal layers and has a thickness ranging from 50 nm to 5 μm above it, alongside a patterned mask layer with sidewall spacers as shown in Figure 131. The pattern is applied to the area surrounding the chair.

[0403] In Figure 13 J, in order to generate the n+ source region 510, n-type injection 509 is performed in Figure 13 J. The n+ source region is subjected to ion implantation or epitaxy by n-type impurities such as nitrogen and phosphorus. It is formed by schall regrowth. The N+ source region 510 is self-aligned with the p-well region 504. The source region is formed in a self-aligned manner with the p-well region, while the peripheral region of the device The edge region is masked. The deep second p-well region (P-Well #2) 511 may be formed simultaneously with the N+ source region in Figure 13K. The embedded P-well #2 region may be formed using aluminum or boron and may be located below the N+ source region within the active region of the device. The P-well #2 region is formed using p-type species boron, which has a larger ion implantation range compared to aluminum in SiC. It is preferable to form it. It is not necessary to mask the p-well region #2 from the peripheral region of the device.

[0404] In Figure 13L, the first and second hard mask layers 503 and 506 have been removed, respectively. The mask layer 512 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, among other materials. The CVD deposition layer of the parent layer has a thickness ranging from 50 nm to 5 μm in the upper part of Figure 13M. The mask layer 512 is patterned in Figure 13N. In Figure 130, aluminum or By injecting p-type impurities such as boron in controlled doses, N+ is produced in Figure 13P. A p+ plug region 514 is realized embedded beneath the source region 510. The p+ plug region 514 is electrically connected to the P well region 504 and the p well #2 region 511. The p+ plug region is P The injection may be formed deeper than the vel region and the p-well #2 region. Next, the mask layer 512 is removed in Figure 13Q, and the injection is activated by high-temperature annealing.

[0405] The gate oxide layer 515 is formed in Figure 13R by thermal oxidation or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The oxide thickness may be in the range of 10 nm to 100 nm. For oxide growth, dry or wet methods are used. Either thermal oxidation can be used. PECVD or LPCVD may be used for gate oxide deposition. Next, in Figure 13S, the polysilicon gate layer 516 is deposited. The polysilicon layer may be deposited using PECVD or LPCVD. The polysilicon layer can be degenerate-doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon may be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700-900°C. The hard mask 517 is made of silicon dioxide, silicon nitride, silicon oxynitride, or gold such as nickel. A polysilicon layer is deposited by a CVD deposition layer, and as shown in Figure 13T, it has a thickness ranging from 50 nm to 5 μm and is patterned. The polysilicon layer 516 is etched using the patterned mask layer 517 in Figure 13U. Next, the mask layer 517 is removed in Figure 13V. An ILD layer 518 containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof, with a thickness of 50 nm to 1000 nm is deposited on the wafer in Figure 13W. Hardmass Layer 519 is deposited by CVD deposition of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and has a thickness ranging from 50 nm to 5 μm on top to define the ILD opening in Figure 13X, with a pattern formed on top. The ILD layer 518 is constructed using a hard mask as shown in Figure 13Y. It is then etched. Furthermore, the gate oxide 515 is etched using the same mask 519 in Figure 13Z. The hard mask used to pattern the ILD layer 519 is used to create the source trench region 520 by etching completely through the N+ source layer to the P+ plug layer, as shown in Figure 13AA. Next, in Figure 13BB, the mask 519 is removed. In Figure 13CC, a nickel silicide region 521 is formed on the exposed SiC surface. The mask layer 522 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, etc. The metal layer is formed by a CVD deposition layer, and its thickness is patterned in Figure 13DD, The range is 50 nm to 5 pm above. The ILD layer 518 is etched in Figure 13EE. Mask Layer 522 is removed in Figure 13FF. The interaction of either aluminum, silver, or gold. The connecting metal layer 523 is deposited and patterned on the upper and lower parts of the substrate. Figure 13GG. N+SO In contrast to the horizontal plane of the N+ source region in conventional MOSFETs, ohmic contact to the source region in this embodiment is performed via the etched sidewall of the source trench region.

[0406] The embodiment shown in Figure 14 illustrates the unit cell and device periphery of the cross-sectional structure of a SiC DMOSFET. This is the part. The important area of ​​this device is p-type ions such as aluminum or boron. This is a p-well region 603 formed by injection or epitaxial regrowth. An N+ source region 604, an N-drift layer 602, and an N+ substrate 601 are present. In the ON state, when a gate voltage is applied to the polysilicon gate 607, current flows vertically from the drain 601, through the inversion layer formed on top of the p-well layer 603, through the N+ source region 604, and out through the source metallization 610. In the OFF or blocking state, the voltage is supported across the p-well 603, N-drift layer 602 junction, and a PN junction is formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. Power MOSFETs have a pitch of the unit cell, which is the repeating unit of the MOSFET; a channel length, which is the portion of the p-well where the inversion channel is formed; and a JFET region or JFET gap. Several factors, including the distance between two consecutive p-wells and the thickness of the gate oxide 606. It has an important feature. Another feature is that the source interconnect metallization 610 is polysilicon. This is the ILD layer 608 used to insulate from the gate 607. At the very center of the unit cell is the P+ plug layer 605, which is grounded with N+ source metallization. p+ in SiC DMOSFET The purpose of the plug is to ground the p-well region using an N+ source contact.

[0407] In one embodiment of this specification, a dedicated masking step is performed on the side wall space after p-well injection. The formation of the p-well and the subsequent N+ source injection are interspersed between the formation of the p-well and the injection of N+ source from the peripheral region of the MOSFET to mask the injection of N+ source from the peripheral region. This also masks the injection of N+ source from selected regions within the active region of the device, which allows for ohmic contact to the p-well or p+ plug region. This embodiment eliminates the need for a source trench, which is present in the previous embodiment.

[0408] In the embodiments of this specification, a dedicated hard mask or photoresist layer is applied after the sidewall spacer is formed and before N+ source injection, thereby avoiding the formation of N+ source regions and parasitic NPN structures in the peripheral regions of the device. Injection is avoided in selected regions within the active area, which allows ohmic contact to the p-well or p+ plug region without the intervening N+ source region.

[0409] Figures 15A to 15F show the manufacturing process of the structure shown in Figure 14. The manufacturing process of the SiC DMOSFET is on the SiC substrate 701, and appropriate doping (10) for the epitaxial layer 702 shown in Figure 15A. 14 ~10 18 cm -3 It starts with the use of 4H-SiC Si-plane epitaxial wafers having a thickness (1 μm to 300 μm). It includes a CVD deposited layer of metal such as silicon, silicon nitride, silicon oxynitride, or nickel. A blanket hard mask 703 with a thickness in the range of 50 nm to 5 μm is deposited in Figure 15B, then patterned using photolithography, and then shown, for example, in Figure 15C. As such, dry etching is performed using RIE. Next, the p-well regions are formed by ion implantation or epitaxial growth using aluminum or boron as the p-type impurity. To accomplish. In Figure 15D, 10 12 cm -2 ~10 15 cm -2 Injection doses within the range of 10 keV to 800 keV A p-type implantation 704 containing boron or aluminum is performed with energy to form a p-well 705 in Figure 15E.

[0410] The second hard mask layer 706 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and in Figure 15F, the patterned first hard The code mask layer 703 has a thickness ranging from 50 nm to 5 pm. Following this, the anisotropy shown in Figure 15G Etching 707 is performed to form sidewall spacers 706 as shown in Figure 15H. The hard mask layer 708 is a CVD deposition of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel. The layers are deposited and have a thickness ranging from 50 nm to 5 pm, and are patterned in Figure 151. The patterned mask layer has sidewall spacers 706. It is formed at the top, alongside the above. In Figure 15K, in order to generate the n+ source region 710, in Figure 15J n-type implantation 709 is performed in the n+ source region. It is formed by epitaxial regrowth due to impurities. Therefore, the source region 710 is While masked from the peripheral region of the device and selected regions of the active region of the device, the p-well region 705 is formed self-aligned with the device, allowing contact with source ohmic metallization. In Figure 15L, the first and second hard mask layers 703 and 708 Each of these is removed. Another mask layer 711 is made of silicon dioxide, silicon nitride, and oxynitride. The mask layer 711 is deposited by CVD deposition of a metal layer such as ion or nickel, and has a thickness ranging from 50 nm to 5 μm in the upper part of Figure 15M. The mask layer 711 is patterned in Figure 15N.

[0411] Using a hard mask 711, the p+ plug region is realized in Figure 15P by injecting a controlled dose of p-type impurities 712 such as aluminum or boron in Figure 150. The depth of the lag layer 713 may preferably exceed the depth of the N+ source injection, and in certain implementation configurations, it may exceed the depth of the p-well region. The mask layer 711 is removed in Figure 15Q. The wafer is annealed to activate the injected impurities.

[0412] The gate oxide layer 714 is formed in Figure 15R by thermal oxidation or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The thickness of the material can range from 10 nm to 100 nm. Dry or wet heat is used for oxide growth. Either oxidation can be used. PECVD or LPCVD can be used for gate oxide deposition. Next, in Figure 15S, the polysilicon gate layer 715 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ or in a subsequent step using boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon can be performed by depositing a layer in a pool, followed by a drive-in step at a temperature in the range of 700-900°C. The hard mask 716 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, having a thickness in the range of 50 nm to 5 μm, as shown in Figure 15T. The polysilicon layer 715 is patterned. The patterned mask layer 716 in Figure 15U The material is then etched using the following method. Next, in Figure 15V, the mask layer 716 is removed. An ILD layer 717, containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof, with a thickness of 50 nm to 1000 nm, is deposited on the wafer in Figure 15W.

[0413] Hard Mask 718 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, among other materials. The layer is deposited by a CVD deposition layer, with a thickness ranging from 50 nm to 5 μm, to define the ILD opening in Figure 15X, and a pattern is formed on top. The ILD layer 717 is etched using a hard mask as shown in Figure 15Y. Furthermore, the gate oxide 714 is etched using the same mask 718 in Figure 15Z. It is etched using [this method]. Next, in Figure 15A, mask 718 is removed. In Figure 15B, Then, a nickel silicide region 719 is formed on the exposed SiC surface. The mask layer 720 is In CVD deposits of metal layers such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel Thus, it is formed, and its thickness is patterned in Figure 15C, with a range of 50 nm to 5 μm above it. The ILD layer 717 is etched in Figure 15D. The mask layer 720 is etched in Figure 15E. Removed. An interconnected metal layer 721 of either aluminum, silver, or gold is deposited. This is patterned on the upper and lower parts of the substrate in Figure 15F.

[0414] The embodiment shown in Figure 8 is a cross-sectional structure of a SiC DMOSFET, specifically the unit cell and the peripheral region of the device. A key area of ​​this device is ion implantation of p-type species such as aluminum or boron. Alternatively, it is a p-well region 803 formed by epitaxial regrowth. An N+ source region 804, an N-drift layer 802, and an N+ substrate 801 are present. The gate voltage is set to the polysilicon gate 807. In the ON state, when applied to the current, current flows from the drain 801 to the top of the p-well layer 803. The voltage flows perpendicularly through the inversion layer, through the N+ source region 804, and exits through the source metallization 810. In the off or blocking state, the voltage is in the p well 803, N-d A PN junction is formed between the p-well and the N-drift layer, supported across the lift layer 802 junction. A PN junction exists. The voltage applied to the structure is supported across this PN junction in reverse bias. Power MOSFETs have a pitch of the unit cell, which is the repeating unit of the MOSFET; a channel length, which is the portion of the p-well where the inversion channel is formed; and a JFET region or JFET gap. The distance between two consecutive p-wells, and several weights including the thickness of the gate oxide 806. It has key features. Another feature is that the source interconnect metallization 810 is polysilicon gel The ILD layer 808 is used to insulate from layer 807. At the very center of the unit cell is N+ There is a grounded P+ plug layer 805 in the source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region using the N+ source contact.

[0415] In one embodiment of this specification, a dedicated masking step is used for the side wall spacer after p-well injection. The formation of these structures is interspersed between the formation of these structures and the pre-injection of N+ source injection to mask N+ source injection from the peripheral region of the MOSFET. This also masks N+ source injection from selected regions within the active region of the device, which allows ohmic contact to the p-well or p+ plug region. This embodiment eliminates the need for a source trench, which is present in some of the earlier embodiments.

[0416] In the embodiments of this specification, a dedicated hard mask or photoresist layer is applied after the sidewall spacer is formed and before N+ source injection, thereby avoiding the formation of N+ source regions and parasitic NPN structures in the peripheral regions of the device. Injection is avoided in selected regions within the active area, which allows ohmic contact to the p-well or p+ plug region without the intervening N+ source region.

[0417] In the embodiments described herein, polysilicon metallization in the peripheral region of device 807 The gates are segmented and not continuous layers. In embodiments of this specification, the gate body capacitance of the MOSFET can be significantly reduced by forming segmented gate metallization on the periphery of the device instead of adjacent gate buses. This can result in a significant increase in the switching speed of the MOSFET.

[0418] Figures 17A to 17F show the manufacturing process of the structure shown in Figure 8. The manufacturing process of SiC DMOSFETs is SiC The process begins with the use of a 4H-SiC Si-plane epitaxial wafer on a substrate 901, having appropriate doping (10¹⁴–10¹⁸ cm'³) and thickness (1 pm–300 pm) for the epitaxial layer 902 shown in Figure 17A. It includes a CVD deposited layer of metal such as silicon, silicon nitride, silicon oxynitride, or nickel. A blanket hard mask 903 with a thickness in the range of 50 nm to 5 μm is deposited in Figure 17B, then patterned using photolithography, and then shown, for example, in Figure 17C. As such, dry etching is performed using RIE. Next, the p-well regions are formed by ion implantation or epitaxial growth using aluminum or boron as the p-type impurity. To accomplish. In Figure 17D, 10 12 cm -2 ~10 15 cm -2 At injection doses in the range of 10 keV to 800 keV, p-type injection 904 containing boron or aluminum is shown in p-well 905 in Figure 17E. This is executed to generate it.

[0419] The second hard mask layer 906 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, with a thickness ranging from 50 nm to 5 μm in Figure 17F, and is located on top of the patterned first hard mask layer 903. This is followed by the anisotropy shown in Figure 17G. Hard mask Layer 908 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, has a thickness in the range of 50 nm to 5 μm, and is patterned in Figure 171. The patterned mask layer 908 has a patterned mask with side wall spacers. It is formed above the layer alongside the cubic layer. In Figure 17K, n-type implantation 909 is performed in Figure 17J to generate the n+ source region 910. The n+ source region is formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen and phosphorus. Therefore, the source region 910 While masked from the peripheral region of the device and selected regions of the active region of the device, the p-well region 905 is formed self-aligned with the p-well region 905, allowing contact with source ohmic metallization. In Figure 17L, the first and second hard mask layers 903 and 908 are removed, respectively. Another mask layer 911 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and has a thickness ranging from 50 nm to 5 μm at the top of Figure 17M. The mask layer 911 is patterned in Figure 17N.

[0420] Using a hard mask 911, a p+ plug region 913 is realized in Figure 17P by implanting a controlled dose of p-type impurities 912, such as aluminum or boron, in Figure 170. The mask layer 911 is removed in Figure 17Q. The wafer is annealed to activate the implanted impurities.

[0421] The gate oxide layer 914 is formed in Figure 17R by thermal oxidation or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The thickness of the material can range from 10 nm to 100 nm. Dry or wet heat is used for oxide growth. Either oxidation can be used. PECVD or LPCVD may be used for gate oxide deposition. Next, in Figure 17S, the polysilicon gate layer 915 is deposited. The polysilicon layer may be deposited using PECVD or LPCVD. The polysilicon layer can be degenerate-doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon may be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700-900°C. The hard mask 916 is a metal such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel. The polysilicon layer 915 is deposited by CVD deposition and has a thickness ranging from 50 nm to 5 μm, as shown in Figure 17T, and is patterned. The polysilicon layer 915 is etched using the patterned mask layer 916 in Figure 17U. In the embodiments described herein, the polysilicon gate The masking step used to pattern the metal results in a partially segmented polysilicon pattern. Although not evident in the cross-sectional schematic, the separated gate fingers are connected at positions perpendicular to the plane of the drawing. In Figure 17V, the patterned The gate insulator 914 is etched using the mask 916. Next, in Figure 17W, the mask Layer 916 is removed. Silicon dioxide, silicon nitride, and silicon oxynitride layers with a thickness of 50 nm to 1000 nm. Alternatively, an ILD layer 917 containing a stacked combination thereof is deposited on the wafer in Figure 17X. It will be done.

[0422] Hard Mask 918 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, among other materials. The layer is deposited by a CVD deposition layer, with a thickness ranging from 50 nm to 5 μm at the top, and a pattern is formed at the top to define the ILD opening in Figure 17Y. The ILD layer 917 is etched using a hard mask as shown in Figure 17Z. Next, in Figure 17AA, the mask 918 is removed. In Figure 17BB, a nickel silicide region 919 is formed on the exposed SiC surface. The mask layer 920 is formed by a CVD deposited layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and its thickness is in the range of 50 nm to 5 μm above the patterned area in Figure 17CC. The ILD layer 917 is etched in Figure 17DD. The mask layer 920 is etched in Figure 17EE. The interconnecting metal layer 921, which is either aluminum, silver, or gold, is removed from the substrate. It accumulates and forms patterns in the upper and lower layers.

[0423] The embodiment relates to a SiC DMOSFET power device, and the p-well region in particular effectively protects the gate oxide, which is sensitive to the high electric field present in the SiC, during high drain bias or blocking mode operation. It effectively shields.

[0424] One embodiment involves using a p+ plug to ground the p-well region with an N+ source contact. Regarding.

[0425] In one embodiment, the p-well injection region immediately before source region formation is formed by dry etching. With respect to the p-welt trench, the portion formed on the (0001) or horizontal plane of the MOS channel and the (11-20 / 10-10) or perpendicular crystal plane of SiC have the advantage of increasing the mobility of the MOS channel. This results in another portion of the MOS channel formed above.

[0426] One embodiment is formed by completely etching the p-well region, Regarding deep vertical MOS channels. Subsequently, after the formation of the N+ source region, reach-through destruction is suppressed. To control this, a second p-well region (PW#2) is ion-implanted below and around the N+ source region. ru.

[0427] The embodiment relates to the formation of a p-welt trench, which provides a device designer with the flexibility to either increase the effective channel length for a given on-resistance target or decrease the on-resistance for a given chip size.

[0428] SiC devices in power electronics offer high switching times and high blocking It features high voltage capability and the ability to operate at high temperatures. These characteristics, along with recent advances in manufacturing processes, make SiC a successor to conventional silicon-based (Si) devices for power electronics. This suggests that it has the potential to revolutionize electronics. SiC has a wide bandgap. The band gap material is (3.3 eV), and the band gap of Si is 1.1 eV, and the dielectric breakdown field of Si is 1.1 eV. Compared to 0.3 × 10⁶ V / cm, it has a high dielectric breakdown field (3 × 10⁶ V / cm). 6 V / cm ~ 5 × 10 6 It has V / cm). SiC is a superior thermal conductor with 3.7 (W / cm-K) compared to 1.6 (W / cm-K) of SiC. SiC enables operation at extremely high power levels while still dissipating the large amount of excess heat generated. These material properties of SiC offer several advantages to using SiC instead of Si in power devices. SiC and Si semiconductor devices with identical structure and dimensions In the comparison, the SiC die exhibits lower specific ON resistance and higher breakdown voltage than the Si die.

[0429] The embodiments disclosed herein provide novel technologies for the design and manufacture of SiC DMOSFETs. This may be advantageous for providing a higher channel density and reducing the on-resistance of the device.

[0430] In a typical SiC planar MOSFET structure, also known as a DMOSFET, the MOS channel is formed on the horizontal or 0001 crystal plane of the SiC. Channel mobility or field effect on the 0001 crystal plane of SiC. Mobility tends to be lower compared to vertical sidewalls or so-called 11-20 or 10-10 crystal planes. When fabricating planar SiC DMOSFETs, on-resistance tends to be high, and the DMOSFET is limited by the field-effect channel mobility.

[0431] The channel mobility or field-effect mobility on the 0001 crystal plane of SiC is 350 cm⁻¹. 2 Compared to silicon MOSFETs which can exceed / V-sec, 15-25cm² 2 The range is / V-sec. One way to design a SiC MOSFET with lower resistance is to create a very small channel length. The goal is to find such a channel, and as a result, this inversion layer mobility is active only in a smaller region of the current conduction path of the device, which can lead to the problem of short channel effects. Therefore, simply reducing the channel does not solve the low channel mobility on the 0001 crystal plane, which introduces short channel effects, resulting in poor reliability and robustness of the device. In one embodiment of this specification, one way to address this problem is by introducing a trench MOSFET in SiC. In a trench MOSFET, instead of forming the MOS channel on the horizontal or 0001 crystal plane, the channel is formed on the vertical side They are formed on walls, or on the so-called A-plane or M-plane, or also called the 10-10 plane or 11-20 plane. Both of these planes have a remarkably high channel shift of nearly five times compared to the horizontal plane. It has mobility, and the vertical channel is 110-120 cm. 2 This results in / V-sec

[0432] Trench MOSFETs can offer higher channel density compared to planar MOSFETs, and therefore, increased packing density. Higher channel mobility enables devices with lower on-resistance. Conventional trench MOSFETs have advantages over DMOSFETs. Although it has points, the problem with conventional trench MOSFET structures in SiC is the base of the trench. A high electric field exists in the trench, and a portion of the gate oxide within the trench is subjected to this high electric field in blocking modes of operation. This is a typical failure point in trench MOSFET structures, and to overcome this problem, the gate oxide needs to be shielded at the base of the trench. P-type injection and W-trench MOSFETs are approaches used to shield the gate oxide.

[0433] However, forming these shielding regions increases the on-resistance. DMOSFET and In comparison, trench MOSFETs allow for higher channel mobility and thus lower on-resistance, but they generate a high electric field at the trench corners. To counteract this, a shielding region is introduced, but this increases on-resistance. Some of the advantages gained from the reduced on-resistance of trench MOSFETs are now lost due to the shielding, which is a trade-off when designing conventional trench MOSFETs.

[0434] In the embodiments described herein, the device is not a pure DMOSFET, but a pure trench MOSFET. There is none. In this device, the MOS channel is formed on both the 0001 plane and the vertical sidewall or 11-20 (or 10-10) plane, and therefore it is a hybrid between a DMOSFET and a trench MOSFET.

[0435] In the embodiments described herein, the device has a shorter overall channel length compared to a pure DMOSFET. However, it has the same effective channel mobility. By increasing the channel length in this way, some of the robustness and reliability problems associated with the fabrication of short-channel DMOSFETs are overcome. This is possible. In the embodiments described herein, the device completely surrounds the p-type injection area. It has trenches that are either embedded in or surrounded by the structure. This provides natural shielding against high electric fields. Since the trenches are formed entirely within the p-well, there are no areas where the trenches are exposed to the n-type epitaxial layer, which mitigates the problem of high electric fields in trench combers.

[0436] In the embodiments described herein, the structure of this device is etched into a trench in the p-well region. This trench is distinguished by and is called a p-welt trench. In the first embodiment, p A well region is formed, and then the trench is etched into the p-well region, therefore All sides of this trench are contained within this p-well region. This trench is N+ It also exists immediately before the formation of the source region. As described in this embodiment, in this process the device has a portion of the MOS channel formed on the 0001 phase, and another portion of the channel is formed on the 11-20 or 10-10 plane.

[0437] The main process for forming the device described in this embodiment involves using aluminum as a p-type impurity. Alternatively, the p-well region can be formed by either ion implantation using boron or epitaxial growth. The goal is to form a region. Then, reactive ion etching (RIE), or this trench, is performed. A higher power inductively coupled plasma (ICP) source having a suitable hard mask layer for forming By using either of these methods, a p-well trench is formed by controlled etching of the p-well region.

[0438] In the embodiments described herein, the trench may be formed with a side wall angle of 70° to 90°, that is, the approximate angle at which the trench is formed. For example, the depth of the trench may be in the range of 0.1 μm to 0.5 μm. The depth of the p-welt trench is the p-welt trench The bottom of the structure may be adjusted to be smaller than the depth of the p-well region in which it is completely enclosed within the p-well region.

[0439] In this embodiment, after forming a p-welt trench, an ion using impurities such as nitrogen and phosphorus is used. N+ source regions are formed by injection or epitaxial regrowth. The N+ source is pW The N+ source is completely contained within the p-well region and does not extend beyond the p-well region. Morphologically, one option is that a p-well trench region is not required, but can be formed using the same masking steps that can be used to form the N+ source region. Then, a p+ plug layer for grounding the p-well is made of either aluminum or boron. It is formed by injection. The depth of the p+ plug layer may exceed the depth of the source injection layer, and as a result, the source injection layer can be short-circuited by the ohmic layer placed on top, and also p This can provide grounding for the well region. The remainder of the process consists of thermal treatment of the wafer for electrical activation, electrical formation, gate metal formation, interlayer dielectric (ILD), patterning ILD, ohmic metallization, and thick pad metallization.

[0440] In embodiments of this specification, either thermal oxidation or chemical vapor deposition (CVD) of a dielectric layer such as silicon dioxide, silicon nitride, or oxynitride is used to form the gate insulator. In SiC, the oxidation rate differs at the 0001 plane compared to the 11-20 or 10-10 plane, meaning that the oxidation rate differs between the horizontal and vertical sidewalls. This can result in a thicker gate oxide on the vertical sidewalls compared to the horizontal sidewalls. In embodiments of this specification, CVD silicon dioxide Silicon can be deposited, and it can be ensured that the thickness is the same on both the horizontal and vertical sides.

[0441] In one embodiment using the SiC DMOSFET described herein, the p-well trench is formed before the source region is formed and after the p-well region is formed. Here, a portion of the MOS channel in the device is formed parallel to the 0001 plane, and another portion is formed parallel to the 11-20 plane. In this embodiment... Consequently, the fabricated MOSFETs have a higher channel density compared to planar devices for the same lateral footprint, thus allowing for tighter packing. In addition to geometrically increasing the channel density, the embodiments herein can also take advantage of the higher channel mobility of the vertical sidewalls.

[0442] In embodiments of this specification, the device has a higher channel density, higher channel mobility, and lower on-resistance. For a specific on-resistance target, the effective channel length can be increased. Comparing the device described in one embodiment with a typical planar DMOSFET In comparison, for the same on-resistance target, the channel length of the device can be made longer in this embodiment. Short channel effects can degrade reliability and robustness characteristics, while longer channel lengths can mitigate short channel effects. Another way to use the device in the embodiment is for the same channel length as a planar DMOSFET This allows for smaller chips, which means lower-cost devices.

[0443] The device in this embodiment can have the same channel length as a planar DMOSFET. For higher channel mobility in the 11-20 and 10-10 directions, longer channels can be provided in the vertical sidewalls, while still having shorter horizontal channels. For higher channel mobility, the device in this embodiment has lower on-resistance. This allows for a smaller chip size for the same on-resistance, enabling the design of a device with longer vertical channels and shorter horizontal channels, and creating a MOSFET with lower on-resistance.

[0444] The embodiments described herein are based on U.S. Patent Application US 2018 / 0331174 Al, published in November 2018. In this regard, distinguishing it from prior art disclosed by Hitachi, Ltd. by Tega et al. This is possible. The prior art structure described in the U.S. patent by Hitachi's Tega et al. describes a SiC MOSFET structure in which MOS channels are formed on both the horizontal and vertical p-well surfaces, and no continuous p-well trenches forming these MOS channels are formed on the vertical and horizontal sidewalls. The welt trench is formed only at orthogonal positions within the 3D landscape. If formed sequentially, the cross-section at any point within the device will show the same structure. However, in the case of the prior art, the cross-section through these types of trenches will show the same structure in the device where the p-well trench is not present. Since there are many regions within the chair, each location exhibits a different cross-section. However, the p-welt trench in the device described in the embodiments herein is essentially continuous. Therefore, it differs from the structure of the prior art described by Tega et al. from Hitachi, Ltd.

[0445] The second difference is that the structure of the MOS channel in the prior art structure described by Tega et al. from Hitachi, Ltd. is completely different when compared to that described in the embodiments herein. The prior art MOS channel is formed between an N+ source region and another N+ storage region In the devices of the embodiments described herein, the p-well region is initially formed. Subsequently, a trench is formed within the p-well region, followed by the formation of a source injection. However, in the prior art structure described by Tega et al. from Hitachi, Ltd., the p-well region A region is formed, followed by source injection, accumulation region, heat treatment, and then the formation of a p-welt trench. The difference lies in how and when the MOS channels are formed during the process. It depends on whether it is done.

[0446] The third difference is the trench formation process for realizing MOS channels on the perpendicular SiC crystal plane. In the prior art described by Tega et al. of Hitachi, Ltd., all injection stages This is done after the p-well injection is complete. As a result, the N+ source region is higher compared to the MOS channel formed on the vertical sidewall. In the devices described herein, the p-well trench is etched immediately after the p-well injection and before the N+ source injection formed on the recess region created by etching the p-well trench.

[0447] The structure proposed by Tega et al. includes an N+ storage region and a p+ shielding region, along with a p+ plug region, an N+ source region, and a p well region.

[0448] Embodiments described herein enable the formation of extremely long channels on vertical sidewalls. The p-welt trench has a bottom that extends beyond the p-well region. It can be formed to a remarkably deep extent, enabling this.

[0449] In one embodiment of this specification, a p-well region is formed, followed by a deep p-well trench and source injection. After source injection, a second p-well region is formed. The region extends below the source region, has a cover around the corners, and has sharp edges, preventing any reliability issues.

[0450] In embodiments of this specification, gradient injection is used to extend the p-well region beyond the lateral extent of the p-well region, shielding the gate oxide from any drain-induced electric field. The structure in the embodiment provides a natural way to shield the drain potential from the channel region by extending the second p-well region beyond the source region.

[0451] The device formation method described in this embodiment includes forming p-well regions by ion implantation or epitaxial growth using aluminum or boron. , shaping by controlled etching of the p-well region by RIE or ICP-based etching A p-welt trench is formed. The p-welt trench may be formed with a side wall angle between 75° and 90°. The depth of the p-welt trench region may be in the range of 0.1 μm to 2 μm. Next, the n+ source region is implanted with n-type elements such as nitrogen or phosphorus by ion implantation. It is formed by epitaxial regrowth due to impurities. In the embodiments herein, p The bottom of the welt trench does not need to be completely sealed within the p-well region, so the second p-well A region is formed. The second p-well is formed to a sufficient depth below the N+ source region, ensuring that the lateral extent of the p-well region is greater than that of the original p-well region.

[0452] Two methods for forming a second p-well are described in the embodiments herein. In one case, a dedicated hard mask layer is deposited to a degree slightly larger than the original p-well region. The pattern may be created, and then ion implantation for PW#2 may be performed. In the second case, gradient ion implantation may be advantageously used to realize PW#2. In the embodiments described, the same hard mask is used with gradient ion implantation of p-type impurities, lateral The directional spread is made larger than the original PW region, p welt trench, N+ source region, next This can then be used to generate the PW#2 region. The rest of the process is the injected impurities. Thermal treatment of the wafer for electrical activation, gate insulator formation, gate electrode formation, interlevel dielectric formation, source / drain ohmic metallization, and finally, diprobing and This constitutes the formation of pads or interconnecting metals suitable for packaging. The gate insulator is formed by thermal oxidation of silicon carbide or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0453] The device described in this embodiment is a robust device often encountered in the case of SiC power MOSFETs. This allows for greater flexibility in on-resistance, overcoming the trade-off between on-resistance and short-circuit performance. Longer channels allow for better short-circuit performance, and on-resistance is lower due to the inherent characteristics of SiC. High due to channel mobility.

[0454] The embodiment shown in Figure 18 is a unit cell of the cross-sectional structure of a SiC DMOSFET. The important areas are ion implantation or epitaxy of p-type species such as aluminum or boron. This is the p-well region 203 formed by regrowth, N+ source region 204, N-drift layer 202 , and the N+ substrate 201 are present. In the ON state when the gate voltage is applied to the polysilicon gate 206, current flows from the drain 201 through the inversion layer formed on top of the p-well layer 203, and through the N+ substrate. The voltage flows perpendicularly, passing through the p-well region 204 and exiting through the source metallization 208. In the off or blocking state, the voltage is supported across the p-well 203 and the N-drift layer 202 junction, where a PN junction is formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. The power MOSFET has a pitch of the unit cell, which is the repeating unit of the MOSFET, and a p-well where the inversion channel is formed. There are several important features, including the channel length, which is the part of the well; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 205. A key feature is the ILD layer 207, which is used to isolate the source interconnect metallization 208 from the polysilicon gate 206. At the very center of the unit cell is a P+ plug layer 209 grounded with an N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region using the N+ source contact.

[0455] First, ion implantation or epitaxy using aluminum or boron as p-type impurities. A p-well region 203 is formed by gal growth. Next, a p-well trench 210 is formed by controlled etching of the p-well region 203 by either RIE or ICP etching using a properly patterned hard mask layer. The p-well trench may be formed with a sidewall angle between 70° and 90°. The depth of the p-well trench region 210 may be in the range of 0.1 μm to 0.5 μm. The depth of the p-well trench is shallower than the depth of the p-well region. It can be adjusted so that the bottom of the p-well trench can be sealed within the p-well region. The n+ source region is then injected by ion implantation, or by n-type sources such as nitrogen or phosphorus. It is formed by epitaxial regrowth due to impurities. The p-welt trench region is N+ sol The same mask used to perform the ion implantation necessary to form region 204. It is preferable to form using a molding step. The p+ plug layer 209 is made of aluminum Alternatively, it can be formed by injecting a controlled dose of p-type impurities such as boron. The depth of the p+ plug layer may exceed the depth of the N+ source injection, and in certain implementations, p-wells are used. The depth of the region may be exceeded. The remainder of the process involves the electrical activation of the injected impurities, gate insulator formation, gate electrode formation, interlevel dielectric formation, and source / drain ohmic metallurgy. The process involves heat treatment of the wafer for diploving and the formation of pads or interconnect metals suitable for packaging. The gate insulating film 205 is Shaped by thermal oxidation or CVD of dielectric layers such as silicon dioxide, silicon nitride, or silicon oxynitride. It will be accomplished.

[0456] In this embodiment, the p-well region immediately before the formation of the N+ source region A of the MOS channel is A wrench is formed, and the rest of the MOS channel is parallel to the (1120) or (1-100) crystal planes of SiC. It is formed parallel to the (0001) crystal plane. A DMOSFET manufactured according to this embodiment has a higher channel density, which reduces the on-resistance of the device. This may be advantageous. It is well known to those in the art of the present invention that MOS channels formed on vertical sidewalls parallel to the (11-20) or (10-10) crystal planes of 4H-SiC can achieve much higher field-effect mobility compared to MOS channels formed on flat (0001) crystal planes. In one embodiment described herein, in addition to increasing channel density, the effective channel mobility of a DMOSFET manufactured according to this embodiment is expected to be higher than that of a DMOSFET manufactured using MOS channels always parallel to the (0001) crystal plane of 4H-SiC. Desirable features can be utilized for either increasing the effective channel length for a given on-resistance target or decreasing the on-resistance for a given chip size, which may be of interest to the device designer.

[0457] The embodiments described in this application can be distinguished from the apparatus disclosed by Tega et al. in U.S. Patent Application No. 2018 / 0331174 [hereinafter referred to as Reference 1]. Its application is MOS channel The diagram describes the SiC MOSFET structure formed on the vertical and horizontal p-well surfaces.

[0458] (1) In Reference 1, MOS channels are not formed continuously on the vertical SiC crystal plane, but only at discrete orthogonal positions within the active region. Therefore, there exists a cross-section of the MOSFET in Reference 1 that does not include MOS channel formation on the vertical SiC sidewall.

[0459] (2) The MOS channel configuration in Reference 1 is completely different from that described in the embodiments of this specification. In Reference 1, the MOS channel is formed between the N+ source region and a separate N+ storage region that connects the MOS channel to the JFET region.

[0460] (3) In Reference 1, the process of creating trenches to realize MOS channels on a vertical SiC crystal plane is performed after all injection steps are completed. As a result, the N+ source region is higher compared to the MOS channels formed on the vertical sidewalls. In the embodiments described herein, the p-well trench is etched immediately after p-well injection and before N+ source injection is formed on the recess region created by etching the p-well trench.

[0461] Figures 19A to 19U illustrate the process for manufacturing the structure shown in Figure 18. (SiC DMOSFET manufacturing) The fabrication process is carried out on the SiC substrate 301, and appropriate doping is performed for the epitaxial layer 302 shown in Figure 19A. G (10 14 ~10 18 cm -3 ) and use of 4H-SiC Si-plane epitaxial wafers having a thickness (1 μm to 300 μm) It begins with a blanket hard mask 303 containing a CVD deposited layer of metal such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, with a thickness in the range of 50 nm to 5 μm, as shown in Figure 19B. The material is deposited, then patterned using photolithography, and then dry-etched using RIE, for example, as shown in Figure 19C. Next, the p-type impurities are first processed. The p-well region is formed by ion implantation or epitaxial growth using aluminum or boron as the material. In Figure 19D, 10 12 cm -2 ~10 15 cm -2 Injection doses within the range of 10 keV At energies in the ~800 keV range, p-type implantation 304 containing boron or aluminum is shown in Figure 19E. This is done to generate p-well 305. Mask 303 is removed and another hard mass is generated. The hard mask layer 306 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, having a thickness in the range of 50 nm to 5 pm, and is then patterned as shown in Figure 19F. The welt trench 308 is then etched by a controlled etching process 307 using RIE or ICP etching with the properly patterned hard mask layer 306 as shown in Figure 19G. This is formed in the p-well region. The p-well trench 308 is formed with a side wall angle of 70° to 90°. The depth of the p-welt trench region is in the range of 0.1 μm to 0.5 μm. The depth of the p-welt trench may be adjusted to be shallower than the depth of the p-well region 305. The bottom of the p-welt trench 308 can be sealed within the p-well region 305. n-type implantation 309 is performed to generate the n+ source region 310 in Figure 19H. The n+ source region is formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen and phosphorus. The p-welt trench is etched. The same hard mask layer 306 used for this purpose is used to pattern N+ source injection. It can be used to its advantage, and as a result, the source injection is perfectly aligned below the p-well trench. The masking layer 306 is removed in Figure 191. Another hard mask layer 311 is deposited in Figure 19J. In Figure 19K, the hard mask layer 311 is patterned. In Figure 19L, a controlled dose of p-type impurities 312, such as aluminum or boron, is injected into the p+ plug layer. It can be formed by the following. The depth of the p+ plug layer 313 preferably exceeds the depth of the N+ source injection. This may also exceed the depth of the p-well region in a particular embodiment of Figure 19M. This is followed by either a dry or wet etching technique, which is commonly practiced by those skilled in the art, as shown in Figure 19N. The hard mask 311 is removed using [a specific method]. Next, in Figure 190, the oxide layer 314, which is the gate oxide, is removed by thermal oxidation or by an induction agent such as silicon dioxide, silicon nitride, or silicon oxynitride. The electrochemical layer is formed using CVD. The thickness of the gate oxide can be in the range of 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. Plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 19P, the polysilicon gate layer 315 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ or in a subsequent step using boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon may be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700 to 900°C. As shown in Figure 19Q, a hard mask 316 is deposited on top and patterned. The polysilicon gate layer 315 is etched using the patterned mask layer 316. Next, in Figure 19R, the mask layer 316 is removed. An ILD layer 317, containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof, with a thickness of 50 nm to 1000 nm, is deposited on the wafer, a hard mask is deposited, and a pattern is applied on top to define the ILD openings. Then, the ILD layer 317 is patterned using a hard mask, as shown in Figure 19S. Furthermore, the gate oxide 314 is etched using the same mask. Next, the mask After removal, a nickel silicide region 318 is formed on the exposed SiC surface in Figure 19T. An interconnecting metal layer 319, either aluminum, silver, or gold, is deposited and patterned on the top and bottom of the chip in Figure 19U.

[0462] The embodiment shown in Figure 20 is a unit cell of the cross-sectional structure of a SiC DMOSFET. The important areas are ion implantation or epitaxy of p-type species such as aluminum or boron. This is the p-well region 403 formed by regrowth, N+ source region 404, N-drift layer 402 , and the N+ substrate 401 are present. In the ON state when the gate voltage is applied to the polysilicon gate 406, current flows from the drain 401 through the inversion layer formed on top of the p-well layer 403, and through the N+ substrate 401. It flows vertically, passing through region 404 and exiting through source metallization 408. In the reverse bias or blocking state, the voltage is supported across the p-well 403 and the N-drift layer 402 junction, and a PN junction is formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. The power MOSFET has a pitch of the unit cell, which is the repeating unit of the MOSFET, and a p-well where the inversion channel is formed. There are several important features, including the channel length, which is the part of the well; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 405. A key feature is the ILD layer 407, which is used to isolate the source interconnect metallization 408 from the polysilicon gate 406. At the very center of the unit cell is a P+ plug layer 409 grounded with an N+ source metallization. The purpose of the p+ plug in the SiC DMOSFET is to ground the p-well region using the N+ source contact.

[0463] The p-well trench 410 is formed by dry etching in the p-well injection region immediately before the formation of the source region 404, resulting in a portion of the MOS channel formed on the (0001) or horizontal plane and another portion of the MOS channel formed on the (11-20 / 10-10) or vertical crystal plane of SiC. However, in the embodiment shown in Figure 20, by completely etching the p-well region, a much deeper A vertical MOS channel is formed. Subsequently, after the formation of the N+ source region, a reach-through bracket is formed. To suppress downgrade, the second p-well region, indicated by PW#2411, is ion-implanted below and around the N+ source region.

[0464] First, ion implantation or epitaxy using aluminum or boron as p-type impurities. By random growth, the p-well region 403 is formed. Next, controlled etching of the p-well region is performed by RIE or ICP etching using a properly patterned hard mask layer. Then, a p-welt trench 410 is formed. The p-welt trench 410 may be formed with a side wall angle of 75° to 90°. The depth of the p-welt trench region may be in the range of 0.1 μm to 2 μm. Compared to the device shown in Figure 18, the device in Figure 20 has a p-welt trench depth. This can be adjusted to be the same depth as the p-well region or slightly deeper than the p-well region. In the embodiment shown in Figure 20, the bottom of the p-well trench does not have to be completely enclosed within the p-well region. The n+ source region is then formed by ion implantation or by epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. Next, a second p-well region (PW#2) 411 is formed to a sufficient depth below the N+ source region such that the lateral extent of the PW#2 region is greater than the lateral extent of the original p-well region. Two methods for forming the PW#2 411 region are identified: (1) dedicated hard mass (2) A layer can be deposited and patterned to a degree slightly larger than the original p-well region, and then ion implantation of PW#2 can be performed. In this embodiment, the same hard mask is used for the trench, the N+ source region, and then the PW#2 region. It can be used to form, and its lateral spread is achieved using gradient ion implantation of p-type impurities. This makes the p-well region larger than the original p-well region 403. The rest of the process involves the electrical activation of the injected impurities, gate insulator formation, gate electrode formation, inter-level dielectric formation, and source / dray The process involves heat treatment of the wafer for anomic metallization and, finally, for the formation of pads or interconnect metals suitable for diprobing and packaging. The gate insulator 405 is formed by thermal oxidation of silicon carbide, or silicon dioxide, silicon nitride, or nitrate. It is formed by CVD (Chemical Vapor Deposition) of a dielectric layer such as silicon dioxide.

[0465] The apparatus described in this embodiment of Figure 20 is an improvement on the apparatus described in the embodiment of Figure 18 and has several additional functions and advantages. The vertical portion of the MOS channel in the embodiment of Figure 20 For the deeper p-welt trench 410 for the MOSFET in Figure 20, it can be much larger than the device shown in Figure 18. A larger percentage of the MOS channel is water Compared to a plane, it can be realized on a vertical sidewall where higher channel mobility is possible. For example, for a total channel length of 1 μm, 0.25 μm of the MOS channel can be realized on a horizontal plane. This makes it possible to realize a MOS channel of 0.75 μm on the vertical sidewall. Therefore, the effective channel mobility of the device described in the embodiment shown in Figure 20 is the same as the MOS channel length. In contrast, it can be larger than the device described in the embodiment shown in Figure 18. Therefore, for the same effective channel mobility, a longer channel MOSFET can be manufactured using the embodiment in Figure 20 compared to a MOSFET manufactured using the embodiment in Figure 18. Longer channel MOSFETs offer lower drain saturation current, higher short-circuit robustness, lower Vth roll-off due to drain voltage, and immunity from drain-induced barrier drop (DIBL) effects. It provides higher device robustness, including [mention specific feature / feature].

[0466] In the embodiment shown in Figure 20, a larger range for PW#2 411 is observed compared to the original p well 403. This is necessary and beneficial for reducing the channel length of the horizontal portion of the MOS channel. By forming PW#2, which has a larger lateral spread than the original p-well, high-voltage blocks The drain potential during the King state is effectively shielded from the original p-well region by the PW#2 region. This allows for extension beyond the p-well trench without the risk of reach-through breakdown. This significantly reduces the lateral spread (electrical dose) of the original p-well region. When the lateral spread of the p-well region beyond the p-well trench is reduced, the portion of the MOSFET channel formed on the horizontal plane becomes smaller.

[0467] Figures 21A to 21V illustrate the process for manufacturing the structure shown in Figure 20. (SiC DMOSFET manufacturing) The fabrication process is carried out on the SiC substrate 501, and appropriate doping is performed for the epitaxial layer 502 shown in Figure 21A. G (10 14 ~10 18 cm -3 ) and use of 4H-SiC Si-plane epitaxial wafers having a thickness (1 μm to 300 μm) The process begins with the deposition of a blanket hard mask 503 in Figure 2 IB, which includes a CVD deposited layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and has a thickness in the range of 50 nm to 5 μm. This is then patterned using photolithography and then dry-etched using RIE, for example, as shown in Figure 21C. Next, the p-type impurities are first removed. The p-well region is formed by ion implantation or epitaxial growth using aluminum or boron as the material. In Figure 21D, 10 12 cm -2 ~10 15 cm -2 With injection doses in the range of 10 keV to 800 keV, p-type injection 504 containing boron or aluminum is performed, as shown in Figure 2 IE This is performed to generate p-wells 505. Mask 503 is removed, and another hard mask layer 506 is deposited by a CVD deposition layer of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel with a thickness of 50 nm to 5 μm, and then patterned as shown in Figure 21F. The deep p-well trench 508 is then subjected to a controlled etching process to the p-well region by RLE or ICP etching using the properly patterned hard mask layer 506 as shown in Figure 21G. Formed by S507. The p welt trench 508 is formed with a side wall angle of 75° to 90°. Good. The depth of the p-well trench region may be, for example, in the range of 0.5 μm to 2 μm. The depth of the p-well trench 508 may be the same depth as the p-well region or slightly deeper than the p-well region. It can be adjusted to increase the depth. The bottom of the p-well trench is sealed within the p-well region. It is not necessary for it to be included.

[0468] N-type implantation 509 is performed to generate the N+ source region 510 in Figure 21H. The n+ source region is formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen and phosphorus. Next, the second p-well region (PW#2) 511 is formed to a sufficient depth below the N+ source region, and as a result, the lateral extent of the PW#2 region is the same as the lateral extent of the original p-well region in Figure 211. It becomes larger than the original p-well region. Two methods are identified for forming the PW#2 region 511: (1) Deposit a dedicated hard mask layer and pattern it to be slightly larger than the original p-well region. Next, ion implantation of PW#2 can be performed. (2) Gradient ion implantation realizes PW#2 It can be used advantageously for this purpose. In this implementation, the same hard mask 506 uses gradient ion implantation of p-type impurities so that the lateral spread is larger than the original p-well region. To create the p welt trench 508, the N+ source area 510, and then the PW#2 area 511, It can be used.

[0469] The masking layer 506 is removed in Figure 21 J. Another hard mask layer 512 is applied in Figure 21 K. It is deposited. The hard mask layer 512 is patterned in Figure 21L. The p+ plug layer is a controlled dose of p-type impurities 513 such as aluminum or boron in Figure 21M. It can be formed by injection. The depth of the p+ plug layer 514 is preferably the depth of the N+ source injection. This may exceed, and in a particular embodiment of Figure 21N, it may exceed the depth of the p-well region. This is followed by dry or wet etching techniques commonly practiced by those skilled in the art of Figure 21O. Remove the hard mask 512 using either method. Next, in Figure 21P, remove the oxide layer 515, which is the gate oxide, by thermal oxidation, or by silicon dioxide, silicon nitride, or silicon oxynitride. Dielectric layers such as are formed using CVD. The thickness of the gate oxide can be in the range of 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. PECVD or LPCVD can be used for gate oxide deposition. Next, in Figure 21Q... Then, a polysilicon gate layer 516 is deposited. The polysilicon layer is deposited using PECVD or LPCVD. It can be deposited using [a specific method]. The polysilicon layer can be degenerately doped in situ or in a subsequent step using boron or phosphorus. Insitol doping uses a PH3 precursor. This can be carried out by adding to the polysilicon deposition chemical. Post-deposition doping of polysilicon can be performed by depositing a layer of POCL followed by a drive-in step at a temperature in the range of 700-900°C. As shown in Figure 21R, a hard mask 517 is deposited and patterned. The polysilicon gate layer 516 is patterned. Etching is performed using the mask layer 517. Next, in Figure 21S, the mask layer 517 is removed. An ILD layer 518 containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof with a thickness of 50 nm to 1000 nm is deposited on the wafer, a hard mask is deposited and patterned on top to define the ILD openings, and the ILD layer 518 is as shown in Figure 2IT. It is patterned using a hard mask. Furthermore, the gate oxide 515 uses the same mask. It is then etched using the following method. Next, the mask is removed, and a nickel silicide region 519 is formed on the exposed SiC surface in Figure 21U. An interconnect metal layer 520 is deposited, and a pattern is formed on the top and bottom of the chip in Figure 21V. It will be converted to n.

[0470] This invention relates to the design and manufacture of short-channel SiC MOSFETs.

[0471] The embodiments described herein relate to minimizing the DIBL effect of high-voltage short-channel SiC MOSFETs.

[0472] The embodiments described herein relate to the design of MOS channels having submicron channel lengths and Regarding manufacturing.

[0473] The embodiments described herein achieve a device having both sufficiently low on-resistance and sufficiently high short-circuit endurance.

[0474] Embodiments described herein relate to locally increasing the channel doping concentration in a specific region of the channel. Non-uniformly doped channels for SiC MOSFETs offer a better trade-off between on-resistance, threshold voltage, and short-circuit withstand time.

[0475] The embodiments described herein relate to locally increasing the doping concentration within the channel to achieve a better trade-off by not significantly increasing the threshold voltage while simultaneously reducing the DIBL effect.

[0476] In one embodiment described herein, a p-type shield layer called a p-type shield is located in the p-well region. It is formed within the p-well region. The p-shield always occurs within the p-well region, but it can extend beyond the vertical range of the p-well region.

[0477] In the embodiments described herein, the bottom of the p-type shield region can extend below the p-type well.

[0478] In one embodiment described herein, a plurality of p-shield regions may exist. Doping concentrations in the p-shield region can vary from one another.

[0479] The present invention relates to a device in which a p-shield region is embedded within a p-well structure. The p-shield region always occurs within the p-well region, but can extend beyond the vertical range of the p-well region.

[0480] In one embodiment of this specification, the device structure may have a plurality of p-shield regions. In these cases, the doping concentration profiles in different p-shield regions are not necessarily the same. They don't have to be that way; they can be different from each other.

[0481] In the competition to achieve lower on-stage resistance in planar gate SiC MOSFETs, particularly with high breakdown voltage ratings, a large portion of the conduction losses associated with the SiC channel are reduced. Therefore, it is common practice to make the channel length as short as possible. SiC MOS structure The MOS mobility in this device is significantly smaller compared to that of silicon MOSFETs, and as a result To achieve sufficiently low on-resistance, the channel length needs to be extremely short, sometimes even in the submicron range.

[0482] As channel length decreases, short-channel effects become a problem in SiC power MOSFETs. This causes a drain-induced barrier reduction effect (also known as the DIBL effect), which is the cause of many reliability problems in SiC MOSFETs.

[0483] One related issue is that the designed device only works at very low drain bias. This is the roll-off of the threshold voltage at a high drain bias to achieve a specific desired threshold voltage. However, as the drain bias approaches its blocking value, the threshold voltage drops substantially, which is undesirable because the channel may be inadvertently turned on.

[0484] Furthermore, devices affected by the DIBL effect have extremely large saturation currents under high drain bias, resulting in excessive power loss under short-circuit load conditions. This shortens the short-circuit endurance time. The limited MOS channel mobility of SiC MOSFETs can be overcome with short channel lengths, however This relates to problems caused by the DIBL effect.

[0485] One approach to mitigate this problem is to uniformly increase the threshold voltage of the device. This involves increasing the doping concentration in the channel region. While this approach can reduce the saturation drain current, it also increases the on-resistance of the device.

[0486] The embodiments described herein can help achieve devices having both sufficiently low on-resistance and sufficiently high short-circuit withstand time. While the conventional approach simply increases the doping concentration uniformly in the channel region, the embodiments described herein increase the doping concentration locally in specific regions of the channel, rather than uniformly increasing the doping concentration in other channels. Non-uniformly doped channels for SiC MOSFETs offer a better trade-off between on-resistance, threshold voltage, and short-circuit withstand time.

[0487] In the embodiments described herein, the doping concentration does not significantly increase the threshold voltage, but at the same time, DIBL The effect is reduced, and therefore increased to achieve a better trade-off.

[0488] In one embodiment of this specification, a p-type shield layer, called a p-type shield, is formed within the p-well region. The p-shield always occurs within the p-well region, but in certain examples of this embodiment, it can extend beyond the vertical range of the p-well region.

[0489] In one embodiment of this specification, the bottom of the p-shield region can extend further downward and reach below the p-well. In one embodiment of this specification, multiple p-shield regions A region may exist. Doping concentrations in different p-shield regions can differ from one another.

[0490] In one embodiment of this specification, a p-type shield layer, called a p-type shield, is embedded within the p-well region. It is formed by being embedded. The p-shield always occurs within the p-well region, but in certain examples of this embodiment, it can extend beyond the vertical range of the p-well region.

[0491] In one embodiment of this specification, the bottom of the p-shield region can extend further downward and reach below the p-well. In one embodiment of this specification, the p-well region can be embedded Multiple p-shield regions can be present in different p-shield regions. Doping concentrations can vary from one another.

[0492] The p-shield region is formed by embedding it within the p-well structure, locally re-enhancing the doping of the p-well region and providing better shielding of the MOSFET channel on the surface while minimizing the DIBL effect. In the embodiments described herein, the p-shield is directly connected to the channel. Since there is no connection, the p-shield does not change VTH.

[0493] The embodiment shown in Figure 23A is a half-unit cell of the cross-sectional structure of a SiC DMOSFET. The key areas of the vice are ion implantation or epidural implantation of p-type species such as aluminum or boron. This is the p-well region 203 formed by taxial regrowth. An N+ source region 205, an N-drift layer 202, and an N+ substrate 201 are present. A gate voltage is applied to the polysilicon gate 207. In the ON state, current flows from the drain 201 through the inversion layer formed on top of the p-well layer 203. The voltage flows perpendicularly, passing through the N+ source region 205 and exiting through the source metallization 210. In the off or blocking state, the voltage is supported across the p-well 203 and the N-drift layer 202 junction, where a PN junction is formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. The power MOSFET has a pitch of the unit cell, which is the repeating unit of the MOSFET, a channel length which is the portion of the p-well where the inverting channel is formed, and a junction gate field-effect transistor (JFET) region. This is the distance between two consecutive p-wells called the JFET gap, and the thickness of the gate oxide 206. It has several important features, including [missing text]. Another feature is the ILD layer 208 used to insulate the source interconnect metallization 210 from the polysilicon gate 207.

[0494] In the embodiments of this specification, a p-type shield layer called p-shield 204a is located within the p-well region. A p-shield is formed. The p-shield can be located inside the p-well such that the lateral position of the point with the highest doping concentration, compared to the average background doping concentration of the p-well, lies within the boundary of the p-well. The p-shield region always occurs within the p-well region. Point A And point B shows how the doping profile of the injected p-shield region looks. It is given as a reference point for explaining the reason.

[0495] The embodiment shown in Figure 23B is similar to the embodiment in Figure 23A, except that the bottom of the p-shield region extends further downward into the p-well and can reach the outside of the p-well region. ru.

[0496] In the embodiments shown in Figures 23C and 23D, the device is similar to that in Figure 23A. The device in Figure 23D illustrates the case where there are multiple p-shield regions. In these cases, The doping concentration profiles in different p-shield regions do not necessarily have to be the same. They may be different from one another.

[0497] When the drain is biased with a high voltage, the p-shield formed in the center of the channel can help mitigate the expansion of the drain bias-induced depletion region, which eliminates the DIBL effect. In addition to mitigating the DIBL effect, the p-shield region is a simple way to control the VTH of the MOSFET. It also provides a method that makes it possible to improve the short-circuit time (TSC). P-Shield is P-Welding In contrast to a uniform increase in doping concentration, this allows for a localized increase in the doping concentration of the p-well at critical locations within the device structure, resulting in lower Vth, ON resistance, and short channel effects. A better trade-off in terms of better immunity is obtained by the method described in the embodiment. When the depth of the p-shield region is greater than that of the p-well region, i.e., when the p-shield extends vertically beyond the p-well region, the p-shield can also provide better shielding of the electric field to the channel region, which further mitigates the DIBL effect in the channel. Device structures having multiple p-shield regions can be designed with different doping concentrations in different p-shield regions. In the embodiment described herein, a higher doping concentration is applied to the p-shield region closer to the edge of the p-well (POINT A). This can be applied to the p-shield region, while the p-shield region closer to POINT B can be fabricated with a lower doping concentration. This structure has the advantages of a lower gate threshold voltage and excellent resistance to short-channel effects for a given channel length.

[0498] Figures 24A to 24U illustrate the process for manufacturing the structure shown in Figure 23A. SiC DMOSFET The manufacturing process is carried out on the SiC substrate 301, and appropriate doping (10) is performed for the epitaxial layer 302 shown in Figure 24A. 14 ~10 18 cm -3 ) and use of 4H-SiC Si-plane epitaxial wafers having a thickness (1 μm to 300 μm) It begins with a blanket hard mask 303 containing a chemical vapor deposition (CVD) layer with a metal layer thickness of 50 nm to 5 μm, such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, which is shown in Figure 24B. The material is then deposited, patterned using photolithography, and then dry-etched using reactive ion etching (RIE), for example, as shown in Figure 24C. First, ion implantation or epitaxy using aluminum or boron as p-type impurities is performed. Through shal growth, p-well regions are formed. In Figure 24D, 10 12 cm -2 ~10 15 cm -2 With an injection dose in the range of 10 keV to 1000 keV, p-type injection 304 containing boron or aluminum is performed to generate p-wells 305. The patterned mask layer 303 is removed in Figure 24E.

[0499] The hard mask layer 306 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, etc. The metal layer is deposited by CVD deposition, with a thickness ranging from 50 nm to 5 μm in Figure 24F. The mask layer 306 is patterned using photolithography and then dry-etched using RTE, for example, in Figure 24G.

[0500] As shown in Figure 24H, the p-type injection 307 creates a p-type region within a p-well called the p-type shield 308. This is done to form. Using aluminum or boron as a p-type impurity, a p-type shield region 308 can be formed. The doping concentration in the p-shield region may be in the range of 1E16 cm⁻³ to 1E21 cm⁻³. In Figure 241, the patterned mask layer 306 is removed. They are being taken away.

[0501] Figure 24J shows a blanket hard mask 309 containing a chemical vapor deposition (CVD) layer with a metal layer thickness of 50 nm to 5 μm, such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel. It is deposited in such a way, then patterned using photolithography, and then, for example For example, as shown in Figure 24K, dry etching is performed using RIE.

[0502] The N+ source region 311 is formed in Figure 24L by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen and phosphorus 310. The patterned mask layer 309 is removed as shown in Figure 24M.

[0503] The gate oxide layer 312 is formed by thermal oxidation or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride, as shown in Figure 24N. The thickness of the oxide can be in the range of 10 nm to 100 nm. For oxide growth, dry or Either wet thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD) can be used. Alternatively, low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 240, a polysilicon gate layer 313 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be deposited in situ using boron or phosphorus. Alternatively, degenerate doping can be performed in a subsequent step. In-situ doping can be carried out by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon may be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700–900°C. In Figure 24P, the polysilicon layer 313 is patterned. An ILD layer 314 containing silicon dioxide, silicon nitride, silicon oxynitride layers or stacked combinations thereof with a thickness of 50 nm–1000 nm is deposited on the wafer in Figure 24Q. The ILD layer 314 is patterned as shown in Figure 24R. In Figure 24S, the gate oxide 312 is patterned.

[0504] In Figure 24T, a nickel silicide region 315 is formed on the exposed SiC surface. The interconnected metal layer 316, which is either nium, silver, or gold, is based as shown in Figure 24U. It is deposited and patterned on the top and bottom of the board.

[0505] The embodiment shown in Figure 25A is a half-unit cell of the cross-sectional structure of a SiC DMOSFET. A key area of ​​this device is ion implantation or epitaxial of p-type species such as aluminum or boron. This is the p-well region 403 formed by axial regrowth. An N+ source region 405, an N-drift layer 402, and an N+ substrate 401 are present. A gate voltage is applied to the polysilicon gate 407. In the ON state, current flows from the drain 401 through the inversion layer formed on top of the p-well layer 403. The voltage flows perpendicularly, passing through the N+ source region 405 and exiting through the source metallization 410. In the off or blocking state, the voltage is supported across the p-well 403 and the N-drift layer 402 junction, where a PN junction is formed between the p-well and the N-drift layer. The voltage applied to the structure is supported across this PN junction in reverse bias. The power MOSFET has a pitch and an inverting channel formed in the unit cell, which is the repeating unit of the MOSFET. The p-well portion is the channel length, and the junction gate field-effect transistor region (JFET region) is also a part of the transistor. Alternatively, the distance between two consecutive p-wells, called the JFET gap, and the gate oxide 406 It has several important features, including its thickness. Another feature is the ILD layer 408 used to insulate the source interconnect metallization 410 from the polysilicon gate 407.

[0506] A p-shield region 404a is formed embedded within the p-well structure. In other words, the p-shield region The rudd is formed beneath the SiC surface where the MOSFET channel is located. The p-shield region always occurs within the p-well region, as seen in Figure 25A, but in certain examples of this embodiment, it may extend beyond the vertical extent of the p-well region, as shown in Figure 25B.

[0507] The embodiment shown in Figure 25B is similar to the embodiment in Figure 25A, except that the bottom of the p-shield region extends further downward into the p-well and can reach the outside of the p-well region. ru.

[0508] The device structures shown in Figures 25C and 25D are similar to those of the device in Figure 25A, but with multiple p-series Let's take an example where there is a shield region. In these cases, the doping concentration of different p-shield regions is different. The degree profiles do not necessarily have to be the same and may differ from one another. Points A and B in each of these figures are given as reference points to illustrate what the doping profile of the injected p-shield region looks like.

[0509] The p-shields in Figures 25A to 25D locally "re-enhance" the doping in the p-well region, providing better shielding of the MOSFET channel on the surface while minimizing the DIBL effect. Since the p-shield is not directly connected to the channel, in this case, the p-shield does not change the threshold voltage. The device shown in Figure 25A provides homogeneous field shielding to mitigate DIBL. However, this does not require changing the threshold voltage value, which is unavoidable for the device in Figure 23A.

[0510] Figures 26A to 26U illustrate the process for manufacturing the structure shown in Figure 25A. The manufacturing process for the SiC DMOSFET is carried out on a SiC substrate 501, and appropriate doping (10) is performed for the epitaxial layer 502 shown in Figure 26A. 14 ~10 18 cm -3From the use of 4H-SiC Si-plane epitaxial wafers having ) and thickness (1 μm to 300 μm) The process begins. A blanket hard mask 503 containing a chemical vapor deposition (CVD) layer with a metal layer thickness of 50 nm to 5 μm, such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, is shown in Figure 26B. The material is deposited in such a manner, then patterned using photolithography, and then dry-etched using reactive ion etching (RIE), for example, as shown in Figure 26C. Next, first, ions using aluminum or boron as p-type impurities are applied. The p-well region is formed by injection or epitaxial growth. In Figure 26D, 10 12 cm -2 ~10 15 cm -2 With an injection dose in the range of 10 keV to 1000 keV, p-type injection 504 containing boron or aluminum is performed to generate p-wells 505. The patterned mask layer 503 is removed in Figure 26E.

[0511] The hard mask layer 506 is made of silicon dioxide, silicon nitride, silicon oxynitride, or nickel, etc. The metal layer is deposited by CVD deposition, with a thickness ranging from 50 nm to 5 μm in Figure 26F. The mask layer 506 is patterned using photolithography and then dry-etched using RIE, for example, in Figure 26G.

[0512] In Figure 26H, the p-type injection 507 forms a p-type region within the p-well called the p-type shield 508. This is done using aluminum or boron as a p-type impurity in the p-type shield region 508. A p-shield region can be formed. A p-shield region is formed embedded within the p-well structure. In other words, the p-shield is formed beneath the SiC surface where the MOSFET channel is located. The p-shield region always occurs within the p-well region. The location of the p-shield region is controlled by careful adjustment of the injection energy used to realize the p-shield region.

[0513] The p-type shield area is 10¹² cm². -2 ~10 15 cm -2 With an implantation dose in the range of 25 keV to 800 keV, it is produced by a p-type ion implantation step containing boron or aluminum. This may be done. In Figure 261, the patterned mask layer 506 is removed.

[0514] Figure 261 shows a blanket hard mask 509 containing a chemical vapor deposition (CVD) layer with a metal layer thickness of 50 nm to 5 μm, such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel. The material is deposited, then patterned using photolithography, and then dry-etched using RIE, for example, as shown in Figure 26K.

[0515] The N+ source region 511 is formed in Figure 26L by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen and phosphorus 510. The patterned mask layer 509 is It is removed in Figure 26M.

[0516] The gate oxide layer 512 is formed in Figure 26N by thermal oxidation or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The thickness of the material can range from 10 nm to 100 nm. Dry or wet heat is used for oxide growth. Either oxidation can be used: plasma-enhanced chemical vapor deposition (PECVD) or low pressure Chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 260, a polysilicon gate layer 513 is deposited. The polysilicon layer is deposited using PECVD or LPCVD. Polysilicon layers can be deposited in this manner. The polysilicon layer can be degenerate-doped in situ or in a subsequent step using boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemical. Post-deposition doping of polysilicon can be performed by depositing a layer in a pool, followed by a drive-in step at a temperature in the range of 700-900°C. In Figure 26P, the polysilicon layer 513 is patterned. An ILD layer 514 containing silicon dioxide, silicon nitride, silicon oxynitride layers, or stacked combinations thereof, with a thickness of 50 nm to 1000 nm, is deposited on the wafer in Figure 26Q. The ILD layer 514 is patterned in Figure 26R. The gate oxide 512 is patterned in Figure 26S.

[0517] In Figure 26T, a nickel silicide region 515 is formed on the exposed SiC surface. The interconnected metal layer 516, which is either nium, silver, or gold, is based as shown in Figure 26U. It is deposited and patterned on the top and bottom of the board.

[0518] The embodiments described herein relate to SiC transistors.

[0519] A device described in one embodiment of this specification has an embedded N+ region located between its P+ islands. The embedded N+ region is formed to be physically separated from the wafer surface so as not to contact the Schottky layer. A portion of the N-drift layer is in contact with the Schottky surface. Physical separation of the N+ region from the wafer surface is achieved in Schottky metals, and SiC devices are also involved. Since the concentration of S has an N doping concentration rather than an N+ doping concentration, this embodiment is an important feature. This is a characteristic feature. The silicon carbide surface in contact with the Schottky metal is at the Schottky metal boundary with SiC. It has an important N-doping concentration to reduce the electric field intensity on the surface. In one embodiment described herein, the vertical extent of the embedded N+ region is lower than the bottom of the P+ region and covers the bottom of the P+ region. Compared with conventional MPS diodes, the spacing between P+ islands is The P+ islands are narrower and deeper. The presence of N+ regions allows for narrower spacing between P+ islands. The P+ islands shield the electric field generated during high-voltage operation from the Schottky interface. In embodiments herein, the P+ regions, interspersed with N+ regions, are designed to achieve a certain level of charge balance between the P+ islands and the N+ regions, which further reduces the ON resistance of the device and also provides the advantage of maintaining a low electric field.

[0520] In one embodiment of this specification, the bottom of the N+ region is higher than the bottom of the P+ region. The bottom of the P+ region is N It is in contact with the drift layer, which is a trade-off as it allows for lower leakage current but also higher on-resistance. Better on-resistance can be achieved in embodiments of devices where lower leakage current can be achieved, in embodiments of devices where the N+ region located between the P+ islands is embedded and the N+ region does not completely enclose the bottom of the P+ island. In embodiments described herein, both embedded N+ regions located between the P+ islands and N+ regions that do not completely enclose the bottom of the P+ island can be present on the same device.

[0521] In one embodiment described herein, the N+ region is formed from several sub-N regions, and P+ is multi Formed from a sub-P region, doping in each of these different layers or slices The concentrations may vary. In one embodiment of this specification, the final slice of the N+ region is below the P+ island and completely covers the periphery of the P+ island, or the bottom of the N+ slice is below the P+ region It is higher than the bottom. The doping concentration in the N+ type subregions further away from the silicon carbide surface can gradually increase, which may have the advantage of lower conduction loss. In another embodiment, the SiC surface This allows for a gradual reduction in the doping concentration of p-type subregions further from the plane, thereby This allows for better blocking characteristics. The doping concentration variations described in the embodiments herein provide the freedom to appropriately adjust the device design toward lower leakage current, better conduction loss, lower resistance, and so on. In contrast to having only one P+ layer and one N+ layer, better trade-offs can be achieved in layered and differently doped N+ and P+ regions, which can be achieved by using multiple ion implantation steps or multiple epitaxial growths.

[0522] In one embodiment of this specification, N+ regions scattered between sets of multiple P+ wells are physically separated from the wafer surface and formed to extend entirely within the N-drift region. The physical separation of the N+ region from the SiC wafer surface in this embodiment is compared to other similar inventions. To distinguish.

[0523] In one embodiment of this specification, a Schottky metal (METAL 1) is in contact with an n-type semiconductor SiC. In part of the operation of the SiC MPS diode, the doping concentration of the n-type SiC semiconductor in direct contact with the Schottky metal (METAL 1) during the high-voltage blocking mode of operation is affected by the electric field on the wafer surface. The doping concentrations for N-drift are the same because it is important to reduce the intensity of [the substance].

[0524] The device of the embodiment shown in Figure 28A is a schematic cross-sectional view of a SiC MPS diode. A critical region of this device is the bottom N+ substrate 201, which provides mechanical support for the wafer and has a thickness of ~350 μm. Typically, this is the epitaxial layer, and above the N+ substrate is the N-drift region 202. Linear stripe Alternatively, there are multiple P+ wells 204 that are formed as more complex circular or hexagonal patterns. The device is a Schottky metal into the n-type SiC semiconductor region, and into the n-type region beneath it. It has a first metal layer 205, indicated as METAL 1, which forms a Schottky contact. The wafer has a second metal layer 206, indicated as metal 2, on the front surface of the wafer in contact with metal 1. Metal 2 is often called "power metal" and is usually aluminum. A silicide layer 207 is located beneath the bottom of the plate. Below the back surface of the wafer that is in contact with the silicide layer. There is a third metal layer 208, which is shown as metal 3.

[0525] The device shown in Figure 28A has N+ regions 203 scattered among multiple sets of P+ wells 204. The N+ region 203 is physically separated from the wafer surface and extends completely within the N-drift region 202. It is formed in such a way. The physical separation of the N+ region from the SiC wafer surface is described herein. This is an important feature of the embodiment and distinguishes it from other similar inventions. Among the SiC wafers, METAL The portion in contact with the Schottky metal 205, referred to as 1, and which is an n-type semiconductor, is N-drift 202. The doping concentrations are the same. In the embodiments described herein, labeled METAL 1 The doping concentration of the n-type SiC semiconductor in direct contact with the embedded Schottky metal 205 is important for reducing the electric field strength at the wafer surface during the high-voltage blocking mode of operation of the SiC MPS diode. The vertical extent of the N+ region 203 is smaller than the bottom of the P+ region 204. The embedded N+ region completely surrounds the P+ region, which provides a conductive migration path for Schottky-injected majority carriers and reduces total forward conduction losses.

[0526] Embodiments of the devices described herein use a different type of Schottky metal in the metal 1 layer compared to metal 1 of the prior art. The selection of metal 1 205 in the apparatus described in Figure 28A is made such that the barrier height of its Schottky contacts is lower than that of the prior art. Due to the lower height of the Schottky barrier, the injection of majority carriers onto the Schottky barrier becomes more efficient, which is reflected as a lower knee voltage (VKnee) in the forward IV characteristics, as shown in Figure 28B. Novel devices with lower VKnee (labeled #2 and #3) have lower forward conduction losses than their counterparts (labeled #1). The lower the height of the Schottky barrier, the more it is represented by the inverse IV curve (labeled #2 and #3). Consequently, the reverse leakage current increases. The amount of leakage current can be kept under control in the embodiments described herein by fine-tuning the barrier height, which depends on various design elements including, but not limited to, the annealing temperature of the Schottky contacts, the device pitch, the depth and doping of the P+ region, the doping and depth of the N+ region, and the doping of the Ndrift region.

[0527] Another distinct feature of the embodiments described herein is that the N+ substrate of the new device is thinner (typically 100-200 μm) than its counterpart (typically -350 μm). The thinner N+ substrate directly affects the forward I-V characteristics, which are the linear region of the forward I-V curve. Here, the steeper slope of VF > VKnee is due to the reduced series resistance of the thinner substrate on the total forward conduction loss. As shown in Figure 28B, lower VKnee and thinner substrate (marked #3) A diode having precisely low VKnee and thick substrate (marked #2) must have lower conduction losses than another diode having a thicker substrate (marked #2). In the embodiments herein, the differential on-resistance (RON, Diff), which is the reciprocal of the slope of the linear segment of the forward IV curve, is significantly reduced by thinning the N+ substrate. The lower VKnee and RON, Diff of the diodes in the embodiments herein allow for a significant reduction in forward conduction losses while maintaining sufficiently low reverse leakage to meet appropriate market needs.

[0528] Figures 29A to 29L illustrate the process for manufacturing the structure shown in Figure 28A. Device Manufacturing In the process shown in Figure 29A, the highly conductive N+ substrate 301 and the N-drift region are typically epitaxially grown. The process includes preparing a SiC wafer consisting of an N-drift region 302. The doping concentration and thickness in the N-drift region are determined based on the required blocking performance. It is primarily designed to be selected. When the SiC wafer is prepared, an ion implantation step with n-type species such as nitrogen and / or phosphorus is performed on the active region of the device shown in Figure 29B. Thus, an n+ region is formed within the n-drift region. The end terminals, which are not shown, need to be masked during the n-type ion implantation step. Note that in Figure 29(C), the n+ region 304 is the n-drift region. An n-type ion implantation step 303 is necessary so that the ion implantation is completely embedded within the wafer. The ion implantation step should form an N+ region 304 where the upper part of the N+ region is physically separated from the wafer surface. be.

[0529] The patterned mask 305 is preferably an oxide, nitride, polysilicon layer, or the same This hard mask is made from a combination of these, and as shown in Figure 29D, it forms a shape on the wafer surface. The patterned mask must be thick enough to completely block high-energy impurities during the subsequent ion implantation step. (Aluminum and / or holographic material) A p-type ion implantation step using p-type impurities such as 306 is performed in Figure 29E, and Figure 29F shows 1 A set of multiple p+ wells 307 is formed. The bottom of the set of multiple p+ wells 307 is formed such that they are above the bottom of the N+ region 304. In the embodiments herein, the multiple p+ wells The depth of the set is less than the depth of the N+ region. In Figure 29F, a set of multiple P+ wells is the whole. This then becomes the P+ region. Note that the end-terminal regions, which are not shown, are formed by a p-type ion implantation process. This may be done. The patterned mask 305 is removed by a dry or wet etching process as shown in Figure 29G. This is followed by a process step in which all implanted impurity species are electrically activated by coating the wafer with a suitable coating material such as a carbon cap and annealing it at a high temperature such as 1700°C. The active region is then defined by forming a field oxide layer across the entire wafer surface and removing a portion of the field oxide through which conduction current needs to flow for the device to operate on-state.

[0530] The Schottky contact is formed on the wafer surface by directly depositing a Schottky metal 308 marked as metal 1 onto the wafer surface, as shown in Figure 29H. Then, The deposited Schottky metal layer can be removed by dry etching, wet etching, or lifting. The material is patterned using a to-off process and then annealed at a specific temperature for a specific time using a furnace or RTA (Rapid Thermal Annealing). The thermal balance of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and therefore needs to be carefully designed and controlled. Next, in Figure 291, a first pad metal 309 marked METAL 2 is deposited on the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal is Aluminum / aluminum alloy may also be used. Next, in Figure 29J, the wafer is thinned from its back side until the wafer thickness reaches the target thickness of 100 to 200 μm. Wafer thinning technique If the technique is improved and provides the aforementioned target thickness of less than 100-200 μm, the thickness will be... Further reductions can be achieved by chemical mechanical polishing (CMP), wet etching, and dry cleaning. This can be achieved by etching, or by a combination of the aforementioned grinding techniques and an appropriate protective coating on the front surface of the wafer.

[0531] Next, in Figure 29K, a silicide region 310 is formed on the back side of the wafer. The silicide region is necessary to form good ohmic contacts on the back side of the wafer. As an example, the silicide region is formed by depositing an ohmic metal stack and annealing the wafer using laser annealing technology. In Figure 29L, a second pad metal 311, marked as metal 3, is formed on the back side of the wafer. The second pad metal is aluminum... Alternatively, it may be an aluminum-based alloy. After the second pad metal step is completed. A protective coating process step may follow on the wafer to form a moisture barrier.

[0532] Another method for manufacturing this embodiment is to first use a SiC wafer having multiple n-type epitaxial growth layers. In this case, the SiC wafer consists of three n-type epitaxial growth layers having different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 29C. The three n-type epitaxial growth layers are such that n layer 302 merges with the device side of the wafer, and n+ layer 304 is located directly beneath the n layer. It should be formed in such a way that the n+ layer is also labeled as 302, which functions as a drift region. It is located above the second n layer, and the second n layer is located above the n+ substrate 301.

[0533] When fabricating a SiC wafer with the above epitaxial structure, a patterned mask 305 is preferably formed on the wafer surface as shown in Figure 29D, which is a hard mask such as an oxide, nitride, polysilicon layer, or a combination thereof. The patterned mask is used to protect subsequent ions. The thickness must be sufficient to completely block high-energy impurities during the implantation step. A p-type ion implantation step using p-type impurities 306 such as aluminum and / or boron is performed in Figure 29E to form a set of multiple p+ wells 307 in Figure 29F. Multiple p+ wells 307 The bottom of the set is formed such that they are above the bottom of the N+ region 304. In this embodiment, the depth of a set of multiple P+ wells is less than the depth of the N+ region. In Figure 29F, A set of multiple P+ wells collectively yields a P+ region. Note that end-terminal regions, not shown, may be formed by a p-type ion implantation process. The patterned mask 305 is removed by a dry or wet etching process as shown in Figure 29G. Subsequently, carbon crystals are used. The process steps involve coating the wafer with a suitable coating material such as CAP and annealing it at a high temperature such as 1700°C to electrically activate all implanted impurity species. Subsequently, a field oxide layer is formed across the entire wafer surface, and the active region is defined by removing a portion of the field oxide through which conduction current needs to flow for the device to operate in the on-state.

[0534] The Schottky contact is formed on the wafer surface by directly depositing a Schottky metal 308 marked as metal 1 onto the wafer surface, as shown in Figure 29H. Then, The deposited Schottky metal layer is patterned by using dry etching, wet etching, or lift-off processes, and by using a furnace or RTA. It is annealed at a specific temperature for a specific time. The heat balance of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and therefore needs to be carefully designed and controlled. Next, in Figure 291, the first is marked METAL 2. The pad metal 309 is deposited on the wafer, and then dry etching, wet etching, Alternatively, it is patterned by lift-off. The first pad metal may be an aluminum / aluminum alloy. Next, in Figure 29J, the wafer thickness is set to a target thickness of 100 to 200. The wafer is thinned from its back surface until it reaches a thickness of μm. If wafer thinning technology improves and provides the aforementioned target thickness of less than 100-200 μm, the thickness may be further reduced in the future. Wafer thinning is performed using CMP, wet etching, dry etching, or the aforementioned grinding techniques. This can be achieved by combining it with an appropriate protective coating on the front surface of the wafer.

[0535] Next, in Figure 29K, a silicide region 310 is formed on the back side of the wafer. The silicide region is necessary to form good ohmic contacts on the back side of the wafer. As an example, the silicide region is formed by depositing an ohmic metal stack and annealing the wafer using laser annealing technology. In Figure 29L, a second pad metal 311, marked as metal 3, is formed on the back side of the wafer. The second pad metal is aluminum... Alternatively, it may be an aluminum-based alloy. After the second pad metal step is completed. A protective coating process step may follow on the wafer to form a moisture barrier.

[0536] As seen in the embodiment shown in Figure 28A, the P+ region 204 of the SiC MPS diode of the present invention is The sets of multiple P+ wells are spaced more narrowly apart laterally compared to the conventional method, N It is formed to extend more deeply vertically within the drift region 202. The P+ region of the present invention is Together with the aforementioned N+ region, it is designed to provide robust shielding to the Schottky barrier formed on the wafer surface. In contrast, prior art devices are vulnerable to high stress in the electric field at Schottky contacts, which results in high leakage current and / or irreversible damage to the device. This easily leads to temporary / permanent degradation of Schottky contacts, which can result in failure. It is clear that the device has an Ndrift region as its sole conduction path, and that the majority carriers flowing through the JFET-like region between P+ wells near the wafer surface are affected by carrier transport, increasing the total forward conduction loss.

[0537] Figure 28C compares the main dimensions of the device structure of the present invention, regardless of the device type. The lateral distance between two adjacent P+ wells is defined as W1, and the vertical depth of the P+ well, measured from the surface of the SiC wafer, is defined as DI. Note that the ratio of W1 to DI (or Wl / Dl) of the device of the present invention is less than 3.0 (or Wl / Dl < 3.0).

[0538] The device of the embodiment shown in Figure 30 is a schematic cross-sectional view of a SiC MPS diode. The critical area of ​​the vise is the bottom N+ substrate 401, which provides mechanical support for the wafer and has a thickness of ~350 μm. Typically, this is the epitaxial layer, and above the N+ substrate is the N-drift region 402. Linear stripes... Alternatively, there are multiple P+ wells 404 that are formed as more complex circular or hexagonal patterns. The device is a Schottky metal into the n-type SiC semiconductor region, and into the n-type region beneath it. It has a first metal layer 405, indicated as METAL 1, which forms a Schottky contact. The wafer has a second metal layer 406, indicated as metal 2, on the front surface of the wafer in contact with metal 1. Metal 2 is often called "power metal" and is usually aluminum. A silicide layer 407 is located beneath the bottom of the plate. Below the back surface of the wafer in contact with the silicide layer. There is a third metal layer 408, which is shown as metal 3.

[0539] The device shown in Figure 30 has N+ regions 403 scattered among sets of multiple P+ wells 404. The N+ regions 403 extend in the vicinity of the P+ regions 404 but are shaped not to completely cover the bottom of the P+ regions. Physical separation of the N+ region from the SiC wafer surface is achieved in the implementation described herein. This is a key feature of the invention and distinguishes it from other similar inventions. The portion of the SiC wafer that is in contact with the Schottky metal 405, referred to as METAL 1, and is an n-type semiconductor, has the same doping concentration of Ndrift 402. In the embodiments described herein, the Schottky metal labeled METAL 1 is... The doping concentration of the n-type SiC semiconductor in direct contact with metal 405 is important for reducing the electric field strength at the wafer surface during the high-voltage blocking mode of operation of the SiC MPS diode. The vertical extent of the N+ region 403 is above the bottom of the P+ region 404. The embedded N+ region does not completely cover the bottom of the P+ region.

[0540] Figures 31A to 3 IL illustrate the process for manufacturing the structure shown in Figure 30. Device Manufacturing In the process shown in Figure 31A, the highly conductive N+ substrate 501 and the N-drift region are typically epitaxially grown. The process includes preparing a SiC wafer consisting of an N-drift region 502. The doping concentration and thickness in the N-drift region are determined based on the required blocking performance. It is primarily designed to be selected. Once the SiC wafer is prepared, an ion implantation step with n-type species 503 such as nitrogen and / or phosphorus is performed on the active region of the device in Figure 3 IB to form an n+ region within the n-drift region. The end terminals, not shown, need to be masked during the n-type ion implantation step. Note that in Figure 31C, the n+ region 504 is within the n-drift region. An n-type ion implantation step 503 is necessary to ensure complete embedding. The ion implantation step should form an N+ region 504 where the top of the N+ region is physically separated from the wafer surface. .

[0541] The patterned mask 505 is preferably an oxide, nitride, polysilicon layer, or a combination thereof. This is a hard mask fabricated from a combination of materials, and is formed on the wafer surface shown in Figure 31D. The patterned mask must be thick enough to completely block high-energy impurities during the subsequent ion implantation step. A p-type ion implantation step using p-type impurities 506 such as aluminum and / or boron is performed in Figure 31E, forming a set of multiple p+ wells 507 in Figure 31F. The bottom of the set of multiple p+ wells 507 is formed such that they lie below the bottom of the N+ region 504. In the embodiments herein, the depth of the set of multiple p+ wells is greater than the depth of the N+ region. In Figure 31F, the set of multiple p+ wells is This results in a P+ region as a whole. Note that the end-terminal regions, which are not shown in the diagram, are formed by a p-type ion implantation process. It may be formed in this way. The patterned mask 505 is removed by a dry etching process or a wet etching process as shown in Figure 31G. This is followed by a process step in which all implanted impurity species are electrically activated by coating the wafer with a suitable coating material such as a carbon cap and annealing it at a high temperature such as 1700°C. The active region is then defined by forming a field oxide layer across the entire wafer surface and removing a portion of the field oxide through which conduction current needs to flow for the device to operate on-state.

[0542] The Schottky contact is formed on the wafer surface by directly depositing a Schottky metal 508 marked as metal 1 onto the wafer surface, as shown in Figure 31H. Then, The deposited Schottky metal layer is patterned by using dry etching, wet etching, or lift-off processes, and by using a furnace or RTA. It is annealed at a specific temperature for a specific time. The heat balance of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and therefore needs to be carefully designed and controlled. Next, in Figure 311, the first is marked METAL 2. The pad metal 509 is deposited on the wafer, and then dry etching, wet etching, Alternatively, it is patterned by lift-off. The first pad metal may be an aluminum / aluminum alloy. Next, in Figure 31 J, the wafer is thinned from its back side until the wafer thickness reaches a target thickness of 100-200 μm. If wafer thinning technology improves and provides the aforementioned target thickness of less than 100-200 μm, the thickness may be further reduced in the future. The thinning of the layer can be achieved using CMP, wet etching, dry etching, or the aforementioned grinding techniques. This can be achieved by combining it with an appropriate protective coating on the front surface of the wafer.

[0543] Next, in Figure 31K, a silicide region 510 is formed on the back side of the wafer. The silicide region is necessary to form good ohmic contacts on the back side of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using laser annealing technology. In Figure 31L, a second pad metal 511, marked as metal 3, is formed on the back side of the wafer. The second pad metal is aluminum... Alternatively, it may be an aluminum-based alloy. After the second pad metal step is completed. A protective coating process step may follow on the wafer to form a moisture barrier.

[0544] Another method for manufacturing this embodiment is to first use a SiC wafer having multiple n-type epitaxial growth layers. In this case, the SiC wafer consists of three n-type epitaxial growth layers having different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 31C. The three n-type epitaxial growth layers are such that n layer 502 merges with the device side of the wafer, and n+ layer 504 is located directly beneath the n layer. It should be formed in such a way that the n+ layer is also labeled as 502, which functions as a drift region. It is located above the second n layer, and the second n layer is located above the n+ substrate 501.

[0545] When preparing a SiC wafer having the epitaxial structure described above, a patterned mask 505 is preferably formed on the wafer surface as shown in Figure 31D, which is a hard mask consisting of an oxide, nitride, polysilicon layer, or a combination thereof. The layer must be thick enough to completely block high-energy impurities during the subsequent ion implantation step. A p-type ion implantation step using p-type impurities such as aluminum and / or boron is performed in Figure 31E, and in Figure 31F, a set of multiple p+ welds is implanted. The bottom of the set of multiple P+ wells 507 is below the bottom of the N+ region 504. It is formed in such a way as shown. In the embodiments herein, the depth of a set of multiple P+ wells is greater than the depth of the N+ region. In Figure 31F, the set of multiple P+ wells as a whole forms the P+ region. This results in the end-terminal region, which is not shown in the diagram, being formed by the p-type ion implantation process. Good. The patterned mask 505 is removed by a dry etching process or a wet etching process as shown in Figure 31G. This is followed by a process step in which all implanted impurity species are electrically activated by coating the wafer with a suitable coating material such as a carbon cap and annealing it at a high temperature such as 1700°C. The active region is then defined by forming a field oxide layer across the entire wafer surface and removing a portion of the field oxide through which conduction current needs to flow for the device to operate on-state. ru.

[0546] The Schottky contact is formed on the wafer surface by directly depositing a Schottky metal 508 marked as metal 1 onto the wafer surface, as shown in Figure 31H. Then, The deposited Schottky metal layer is patterned by using dry etching, wet etching, or lift-off processes, and by using a furnace or RTA. It is annealed at a specific temperature for a specific time. The heat balance of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and therefore needs to be carefully designed and controlled. Next, in Figure 311, the first is marked METAL 2. The pad metal 509 is deposited on the wafer, and then dry etching, wet etching, Alternatively, it is patterned by lift-off. The first pad metal may be an aluminum / aluminum alloy. Next, in Figure 31 J, the wafer is thinned from its back side until the wafer thickness reaches a target thickness of 100-200 μm. If wafer thinning technology improves and provides the aforementioned target thickness of less than 100-200 μm, the thickness may be further reduced in the future. The thinning of the layer can be achieved using CMP, wet etching, dry etching, or the aforementioned grinding techniques. This can be achieved by combining it with an appropriate protective coating on the front surface of the wafer.

[0547] Next, in Figure 31K, a silicide region 510 is formed on the back side of the wafer. The silicide region is necessary to form good ohmic contacts on the back side of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using laser annealing technology. In Figure 31L, a second pad metal 511, marked as metal 3, is formed on the back side of the wafer. The second pad metal is aluminum... Alternatively, it may be an aluminum-based alloy. After the second pad metal step is completed. A protective coating process step may follow on the wafer to form a moisture barrier.

[0548] The embodiment shown in Figure 30 further reduces the electric field at the Schottky metal interface, resulting in lower leakage current and better blocking performance than the embodiment shown in Figure 28A. However, compared to the embodiment shown in Figure 28A, it has a higher on-state voltage drop and trade-off It is possible to do this.

[0549] The devices of the embodiments shown in Figures 32A to 32F are schematic cross-sectional views of a SiC MPS diode. A critical area of ​​these devices is the bottom N+ substrate 601, which provides mechanical support for the wafer. The thickness is -350 μm. It is usually an epitaxial layer, an N-drift region 602 on top of an N+ substrate. Vice is a Schottky metal into the n-type SiC semiconductor region, and Schottky metal into the n-type region beneath it. The device has a first metal layer 605, indicated as METAL 1, which forms a key contact. The wafer in contact with metal 1 has a second metal layer 606, indicated as metal 2. Metal 2 is often called "power metal" and is usually aluminum. Below the bottom is the silicide layer 607. Below the back surface of the wafer that is in contact with the silicide layer There is a third metal layer 608, indicated as metal 3. The devices in the embodiments shown in Figures 32A to 32F are This differs from the device shown in the embodiments of Figures 28A and 30, as the N+ region in the previous embodiment is replaced by a set of multiple N sub-regions 603 arranged in layers. The thickness and doping concentration in each of these subregions may differ. Similarly, the P+ region of the device in the embodiments of Figures 28A and 30 is replaced by a set of multiple layered P subregions. The doping concentration in each slice can preferably be designed.

[0550] The device in the embodiment shown in Figures 32A to 32F has N+ regions 603 scattered among a set of multiple P+ wells 604. Some potential examples of the embodiment shown in Figures 32A to 32F The device has a set of multiple n-type sublayers with different thicknesses and doping concentrations, but the device has a set of multiple p-type wells of the same type as in Figures 32A and 32B, and the device has a set of multiple p-type sublayers with different thicknesses and doping concentrations, but wells of the same type as in Figures 32C and 32D A device having a single n-type layer acting as an n+ region, with different thicknesses as shown in Figures 32E and 32F. A device having a set of multiple n-type sublayers having doping concentrations, and A device having a set of multiple p-type sublayers with different thicknesses and doping concentrations. Includes. The devices in Figures 32A, 32C, and 32E have N+ regions 603 around and below the P+ wells 604, while the devices in Figures 32B, 32D, and 32F have N+ regions 603 positioned between the P+ wells. It has but is not located around the P+ well 604. Physical separation of the N+ region from the SiC wafer surface is a key feature of the embodiments described herein and distinguishes it from other similar inventions. Of the SiC wafer, the portion that is in contact with the Schottky metal 605 labeled METAL 1 and is an n-type semiconductor has the same doping concentration of Ndrift 602. In the embodiments described herein, the doping concentration of the n-type SiC semiconductor in direct contact with the Schottky metal 605 labeled METAL 1 is such that during the high-voltage blocking mode of operation of the SiC MPS diode, the electrons on the wafer surface It is important for reducing the intensity of the field.

[0551] Figures 33AA to 33AL illustrate the process for manufacturing the structure shown in Figure 32A. In Figure 33AA, the process shows that the highly conductive N+ substrate 701a and the N-drift region are typically epitaxially grown. This includes preparing a SiC wafer consisting of an N-drift region 702a. The N-drift region 702a is designed such that the doping concentration and thickness of the N-drift region are primarily selected based on the required blocking performance. Once the SiC wafer is prepared, a set of multiple ion implantation steps having n-type species 703a such as nitrogen and / or phosphorus is performed on the active region of the device in Figure 33 AB. The set of multiple ion implantation steps having n-type species is shown in Figure 33 AC. This forms a set of sub-n type regions 704a, and each sub-region shows the top and bottom of the sub-region. In the schematic diagram, all sub-regions are defined by dotted lines and are interconnected. The interconnected sub-regions together comprise N+ regions. Edge terminations not shown are n It needs to be masked during the setup of the n-type ion implantation step. Note that in Figure 33C), the n-type ion implantation step 703a must be performed so that the n+ region 704a is completely embedded within the n-drift region. The ion implantation step should form an N+ region 704a in which the upper part of the N+ region is physically separated from the wafer surface.

[0552] The patterned mask 705a is preferably a hard mask consisting of an oxide, nitride, polysilicon layer, or a combination thereof, and is shaped on the wafer surface in Figure 33 AD. The patterned mask must be thick enough to completely block high-energy impurities during the subsequent ion implantation step. In Figure 33AE, a p-type ion implantation step is performed using p-type impurities 706a such as aluminum and / or boron, and in Figure 33AF... Then a set of multiple p+ wells 707a is formed. The bottom of the set of multiple P+ wells 707a is formed so that they are above the bottom of the N+ region 704a. In the embodiments herein, the depth of the set of multiple P+ wells is less than the depth of the N+ region. The set of multiple P+ wells together give rise to the P+ region in Figure 33AF. End-terminal regions (not shown) are p-type ion injection The patterned mask 705a may be formed by an input process. The patterned mask 705a is removed by a dry etching or wet etching process, as shown in Figure 33AG. This is followed by a process step in which all implanted impurity species are electrically activated by coating the wafer with a suitable coating material such as a carbon cap and annealing it at a high temperature such as 1700°C. The active region is then defined by forming a field oxide layer across the entire wafer surface and removing a portion of the field oxide through which conduction current needs to flow for the device to operate on-state.

[0553] The Schottky contact is marked directly on the wafer surface as Metal 1 in Figure 33AH. The Schottky metal 708a is deposited on the wafer surface. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes, and then processed using a furnace or RTA. This process involves annealing at a specific temperature for a specific period of time. The heat balance of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and therefore needs to be carefully designed and controlled. Next, in Figure 33AI, METAL 2 is shown as The first pad metal 709a is deposited on the wafer, followed by dry etching, wet etching, etc. Patterned by tapping or lift-off. The first pad metal is aluminum It may also be an aluminum / aluminum alloy. Next, in Figure 33 AJ, the wafer is thinned from its back side until the wafer thickness reaches the target thickness of 100 to 200 μm. Wafer thinning technology is improved If improved and the aforementioned target thickness of less than 100-200 μm is achieved, the thickness may be further reduced in the future. It can be reduced. Wafer thinning can be done by CMP, wet etching, dry etching, or This can be achieved by combining the aforementioned grinding technique with an appropriate protective coating on the front surface of the wafer.

[0554] Next, in Figure 33AK, the silicide region 710a is formed on the back side of the wafer. The silicide region is necessary to form good ohmic contacts on the back side of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using laser annealing technology. In Figure 33(A), the back side of the wafer is A second pad metal 711a, labeled Metal 3, is formed. The second pad metal is It may be a luminium or aluminum-based alloy. Second pad metal step After this is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0555] Another method for manufacturing this embodiment is to first use a SiC wafer having multiple n-type epitaxial growth layers. In this case, the SiC wafer consists of multiple n-type epitaxial growth layers having different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 33C. An N-drift layer 702a can be epitaxially grown on the N+ substrate 701a to function as a drift / blocking layer. Several n-type epitaxial layers can be grown on the n-drift layer to form an n+ regio...

Claims

1. A device having a unit cell at least partially formed in a silicon carbide (SiC) substrate, The aforementioned unit cell is A trench defined on the upper surface of the SiC substrate, A silicide layer disposed on at least one surface of the trench, A drift region of a first conductivity type having a first thickness is formed in the SiC substrate, A source region of a first conductivity type having a second thickness smaller than the first thickness, formed within the SiC substrate, A second conductivity type well region formed within the SiC substrate and It has, The device comprises a vertical SiC double-injection metal oxide semiconductor field-effect transistor (DMOSFET) including a drain terminal located on the back surface of the SiC substrate and a source terminal located on the top surface of the SiC substrate and within the trench, wherein the portion of the source terminal located outside the trench is positioned on the non-trenched surface of the source region and is electrically coupled to the non-trenched surface of the source region. The source region is located adjacent to the trench and the well region. device.

2. The device according to claim 1, wherein the source region is adjacent to the first side of the well region that faces the second side of the well region adjacent to the drift region.

3. The device according to claim 1, wherein the source region is located within the well region.

4. The device according to claim 1, wherein the source region includes a first portion located adjacent to the first side of the trench and a second portion located adjacent to the second side of the trench facing the first side.

5. The device according to claim 4, wherein the source region includes a third portion adjacent to the first and second portions of the source region and adjacent to the lower part of the trench.

6. The device according to claim 1, wherein the silicide layer is disposed on the lower surface of the trench.

7. The device according to claim 1, wherein at least one portion of the drift region is located below the lower part of the trench.

8. The device according to claim 1, wherein at least one portion of the drift region is located below the lower part of the well region.

9. A gate insulator is positioned above the upper surface of the SiC substrate and below the source terminal, A gate electrode disposed between the gate insulator and the source terminal and The device according to claim 1, further comprising the above.

10. The device according to claim 1, wherein at least one portion of the source terminal is located within the trench.

11. The device according to claim 1, wherein the source region is electrically coupled to the source terminal.

12. A method for forming a unit cell of a vertical SiC double-injection metal oxide semiconductor field-effect transistor (DMOSFET) at least partially within a silicon carbide (SiC) substrate having a first surface, a second surface, and a drift region of a first conductivity type, The aforementioned method, Forming a second conductivity type well region within the SiC substrate, A source region of the first conductivity type, which is thinner than the drift region, is formed within the well region. A trench is formed on the first surface of the SiC substrate, extending into the source region, wherein the source region is laterally adjacent to the trench and the well region between the trench and the well region. Forming a silicide layer on at least one surface of the trench, A conductive source electrode is formed above the first surface of the SiC substrate and within the trench, wherein a portion of the source electrode is positioned on the surface of the source region outside the trench and is electrically coupled to the surface of the source region, and the conductive source electrode is substantially coplanar with the first surface of the SiC substrate. A conductive drain electrode is formed on the second surface of the SiC substrate. Methods that include...

13. The method according to claim 12, wherein forming the trench includes forming the trench such that a first portion of the source region is located adjacent to the first side of the trench, and a second portion of the source region is located adjacent to the second side of the trench opposite to the first side.

14. The method according to claim 13, wherein forming the trench includes forming the trench adjacent to the first and second portions of the source region, leaving a third portion of the source region below the trench.

15. The method according to claim 12, wherein forming the silicide layer includes forming a silicide layer on the lower part of the trench.

16. The method according to claim 12, wherein forming the well region includes forming the well region within the drift region.

17. Before forming the source electrode on the first surface of the SiC substrate, a gate insulator is formed. Before forming the source electrode, the gate electrode is formed on the gate insulator. The method according to claim 12, further comprising:

18. A silicon carbide (SiC) substrate having a first surface and a second surface, A drift region of a first conductivity type having a first height is formed in the SiC substrate, A second conductivity type well region formed within the drift region and A source region of the first conductivity type having a second height smaller than the first height, formed within the well region, A trench extending from the first surface of the SiC substrate to the intermediate portion of the source region, A silicide disposed on at least one surface of the trench, A source electrode disposed on the first surface of the SiC substrate and within the trench, wherein the portion of the source electrode outside the trench is disposed on the first surface of the source region outside the trench and conductively coupled with the first surface of the source region, A drain electrode disposed on the second surface of the SiC substrate and A vertical SiC double-injection metal oxide semiconductor field-effect transistor (DMOSFET) having the following characteristics.

19. A gate insulator disposed on the first surface of the SiC substrate, On the gate insulator, and a gate electrode located below the source electrode, The transistor according to claim 18, further comprising:

20. The transistor according to claim 19, further comprising an intermediate insulator located on the gate electrode and below the source electrode.

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