Photodetector and electronic equipment

Abstract

Provided is a light detection device capable of suppressing an increase in the parasitic capacitance of an electrode pad. The light detection device comprises: a first semiconductor layer which has a photoelectric conversion unit, one surface of which is a light receiving surface, and the other surface of which is an element formation surface; an insulation layer which is laminated on the light receiving surface side of the first semiconductor layer; an electrode pad which is exposed from a surface of the insulation layer on the opposite side from the surface on the first semiconductor layer side, with the insulation layer interposed between the first semiconductor layer and the electrode pad; and an insulation ring which has insulating properties, which passes through the first semiconductor layer in the thickness direction, and which surrounds the electrode pad in a planar view.

Description

Technical Field

[0001] This technology (the technology according to the present disclosure) relates to a photodetection device and an electronic device, and particularly to a photodetection device and an electronic device having electrode pads.

Background Art

[0002] Regarding the wire bonding pads of a stacked image sensor, a structure in which electrode pads are arranged on the surface of the upper substrate has been proposed (for example, Patent Document 1) from the viewpoint of ease of ball installation. By arranging the electrode pads on the outermost surface, the ball size can be reduced, so that the size of the electrode pads can be reduced, and thus the chip size can be reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a system that operates at high speed, it is necessary to suppress an increase in parasitic capacitance, for example, the parasitic capacitance of electrode pads.

[0005] An object of the present technology is to provide a photodetection device and an electronic device that can suppress an increase in the parasitic capacitance of electrode pads.

Means for Solving the Problems

[0006] A photodetector according to one aspect of this technology includes a photoelectric conversion unit, a first semiconductor layer having one side as a light incident surface and the other side as an element formation surface, an insulating layer laminated on the light incident surface side of the first semiconductor layer, an electrode pad exposed from the side of the insulating layer opposite to the side of the first semiconductor layer with the insulating layer interposed between it and the first semiconductor layer, and an insulating ring which is an insulating ring that penetrates the first semiconductor layer in the thickness direction and surrounds the electrode pad in a plan view.

[0007] An electronic device according to one aspect of this technology comprises the above-mentioned light detection device and an optical system for forming an image of light from an object on the above-mentioned light detection device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a chip layout diagram showing an example configuration of a photodetector according to the first embodiment of this technology. [Figure 2] This is a block diagram showing an example configuration of a light detection device according to the first embodiment of this technology. [Figure 3] This is an equivalent circuit diagram of a pixel in a photodetector according to the first embodiment of this technology. [Figure 4A] This is a plan view showing the arrangement of electrode pads according to the first embodiment of this technology. [Figure 4B] This is a longitudinal cross-sectional view showing the cross-section of the electrode pad when viewed along the BB cutting line in Figure 4A. [Figure 5] This is a longitudinal cross-sectional view showing the relative relationship between the electrode pad and the pixel area of ​​the photodetector according to the first embodiment of this technology, when viewed in cross-section along the AA cutting line in Figure 1. [Figure 6A] This is a plan view showing the positional relationship between the insulating ring, plug, and electrode pad according to the first embodiment of this technology. [Figure 6B] This is a longitudinal cross-sectional view showing the positional relationship between the insulating ring, plug, and electrode pad according to the first embodiment of this technology, when viewed in cross-section along the CC cutting line in Figure 6A. [Figure 6C]In the light detection device according to the first embodiment of the present technology, it is a schematic diagram showing the configuration of a capacitor when there are two insulating rings. [Figure 7A] It is a process cross-sectional view showing a method for manufacturing a light detection device according to the first embodiment of the present technology. [Figure 7B] It is a process cross-sectional view following FIG. 7A. [Figure 7C] It is a process cross-sectional view following FIG. 7B. [Figure 7D] It is a process cross-sectional view following FIG. 7C. [Figure 7E] It is a process cross-sectional view following FIG. 7D. [Figure 7F] It is a plan view showing a resist pattern formed in the process of FIG. 7E. [Figure 7G] It is a process cross-sectional view following FIG. 7E. [Figure 7H] It is a process cross-sectional view following FIG. 7G. [Figure 7I] It is a process cross-sectional view following FIG. 7H. [Figure 7J] It is a process cross-sectional view following FIG. 7I. [Figure 7K] It is a process cross-sectional view following FIG. 7J. [Figure 7L] It is a process cross-sectional view following FIG. 7K. [Figure 7M] It is a process cross-sectional view following FIG. 7L. [Figure 8A] It is a plan view showing the positional relationship among one insulating ring, a plug, and an electrode pad according to the first embodiment of the present technology. [Figure 8B] In the light detection device according to the first embodiment of the present technology, it is a schematic diagram showing the configuration of a capacitor when there is one insulating ring. [Figure 9A] It is a plan view showing the positional relationship among three insulating rings, a plug, and an electrode pad according to the first embodiment of the present technology. [Figure 9B] In the light detection device according to the first embodiment of the present technology, it is a schematic diagram showing the configuration of a capacitor when there are three insulating rings. [Figure 10]It is a schematic diagram showing the configuration of a capacitor when no insulating ring is provided. [Figure 11] It is a graph showing the relationship between the number of insulating rings and the calculation result of the combined capacitance. [Figure 12] It is a diagram showing a conventional optical detection device. [Figure 13] It is a longitudinal sectional view showing the relative relationship between the electrode pad and the pixel region of the optical detection device according to Modification 1 of the first embodiment of the present technology when viewed in cross section along the cutting line A-A in FIG. 1. [Figure 14] It is a longitudinal sectional view showing the relative relationship between the electrode pad and the pixel region of the optical detection device according to Modification 2 of the first embodiment of the present technology when viewed in cross section along the cutting line A-A in FIG. 1. [Figure 15] It is a longitudinal sectional view showing the relative relationship between the electrode pad and the pixel region of the optical detection device according to Modification 3 of the first embodiment of the present technology when viewed in cross section along the cutting line A-A in FIG. 1. [Figure 16] It is a longitudinal sectional view showing the relative relationship between the electrode pad and the pixel region of the optical detection device according to Modification 4 of the first embodiment of the present technology when viewed in cross section along the cutting line A-A in FIG. 1. [Figure 17] It is a longitudinal sectional view showing the relative relationship between the electrode pad and the pixel region of the optical detection device according to Modification 5 of the first embodiment of the present technology when viewed in cross section along the cutting line A-A in FIG. 1. [Figure 18] It is a longitudinal sectional view showing the insulating ring of the optical detection device according to Modification 6 of the first embodiment of the present technology. [Figure 19] It is a longitudinal sectional view showing the insulating ring of the optical detection device according to Modification 7 of the first embodiment of the present technology. [Figure 20] It is a longitudinal sectional view showing the relative relationship between the electrode pad and the pixel region of the optical detection device according to the second embodiment of the present technology when viewed in cross section along the cutting line A-A in FIG. 1. [Figure 21A] It is a plan view showing the positional relationship between the insulating ring, the plugging, and the electrode pad according to the second embodiment of the present technology. [Figure 21B]This is a longitudinal cross-sectional view showing the positional relationship between the insulating ring, plug ring, and electrode pad according to the second embodiment of this technology, when viewed in cross-section along the CC cutting line in Figure 21A. [Figure 22A] This is a longitudinal cross-sectional view showing the positional relationship between one insulating ring, one plug ring, and an electrode pad according to the second embodiment of this technology. [Figure 22B] This is a schematic diagram showing the capacitor configuration in the second embodiment of the present technology, where there is one insulating ring. [Figure 23] This is a plan view showing a resist pattern formed in the manufacturing process of a photodetector according to the second embodiment of this technology. [Figure 24] This is a longitudinal cross-sectional view showing the cross-sectional shape of an insulating ring, a plug ring, and an electrode pad according to another embodiment of the second embodiment of this technology. [Figure 25A] This is a plan view showing the positional relationship between the insulating ring, two plug rings, and electrode pads according to a modified example 1 of the second embodiment of this technology. [Figure 25B] This is a longitudinal cross-sectional view showing the positional relationship between the insulating ring, plug ring, and electrode pad according to Modification 1 of the second embodiment of this technology, when viewed in cross-section along the CC cutting line in Figure 25A. [Figure 26A] This is a longitudinal cross-sectional view showing the positional relationship between one insulating ring, two plug rings, and an electrode pad according to a modified example 1 of the second embodiment of this technology. [Figure 26B] This is a schematic diagram showing the capacitor configuration in a photodetector according to Modification 1 of the second embodiment of this technology, where there is one insulating ring and two plug rings. [Figure 27] This is a longitudinal cross-sectional view showing the cross-sectional shape of the insulating ring, plug ring, and electrode pad according to a modified example 2 of the second embodiment of this technology. [Figure 28A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the second embodiment of this technology. [Figure 28B] This is a cross-sectional view of the process following Figure 28A. [Figure 28C] This is a cross-sectional view of the process, following Figure 28B. [Figure 29A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 3 of the second embodiment of this technology. [Figure 29B] This is a cross-sectional view of the process following Figure 29A. [Figure 29C] This is a cross-sectional view of the process, following Figure 29B. [Figure 30] This figure shows a schematic configuration of an electronic device according to the third embodiment of this technology. [Modes for carrying out the invention]

[0009] The following describes preferred embodiments for implementing this technology with reference to the drawings. The embodiments described below are merely examples of typical embodiments of this technology and should not be interpreted as narrowing the scope of this technology.

[0010] In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it is also important to note that there may be differences in the relationships and ratios of dimensions between drawings.

[0011] Furthermore, the first to third embodiments described below illustrate devices and methods for realizing the technical concept of this technology, and the technical concept of this technology does not specify the materials, shapes, structures, arrangements, etc., of the components as described below. The technical concept of this technology can be modified in various ways within the technical scope defined by the claims described in the patent claims.

[0012] The explanation will be given in the following order. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment

[0013] [First Embodiment] This embodiment 1 describes an example in which this technology is applied to a photodetector that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0014] ≪Overall Configuration of the Light Detection Device≫ First, the overall configuration of the light detection device 1 will be described. As shown in Figure 1, the light detection device 1 according to the first embodiment of this technology is mainly composed of a semiconductor chip 2 whose two-dimensional planar shape when viewed from above is rectangular. That is, the light detection device 1 is mounted on the semiconductor chip 2. As shown in Figure 30, this light detection device 1 takes in image light (incident light 106) from the subject through an optical system (optical lens) 102, converts the amount of light of the incident light 106 that is imaged on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs it as a pixel signal.

[0015] As shown in Figure 1, the semiconductor chip 2 on which the photodetector 1 is mounted comprises a rectangular pixel region 2A located in the center of a two-dimensional plane including the X and Y directions which intersect with each other, and a peripheral region 2B located outside the pixel region 2A so as to surround it.

[0016] The pixel region 2A is a light-receiving surface that receives light focused by the optical system 102, for example, shown in Figure 30. In the pixel region 2A, multiple pixels 3 are arranged in a matrix in a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in the X and Y directions that intersect each other in the two-dimensional plane. In this embodiment, for example, the X and Y directions are orthogonal. The direction that is orthogonal to both the X and Y directions is the Z direction (thickness direction).

[0017] As shown in Figure 1, multiple electrode pads (bonding pads) 14 are arranged in the peripheral region 2B.

[0018] <Logic Circuits> As shown in Figure 2, the semiconductor chip 2 includes a logic circuit 13 that includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is composed of a CMOS (Complenentary MOS) circuit having, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs as field-effect transistors.

[0019] The vertical drive circuit 4 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive line 10, supplies pulses to the selected pixel drive line 10 to drive the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 of the pixel region 2A vertically row by row, and supplies the pixel signal from each pixel 3, based on the signal charge generated by the photoelectric conversion element of each pixel 3 according to the amount of light received, to the column signal processing circuit 5 through the vertical signal line 11.

[0020] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise reduction on the signal output from one row of pixels 3 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion to remove pixel-specific fixed pattern noise. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5, connected to the horizontal signal line 12.

[0021] The horizontal drive circuit 6 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuit 5, thereby sequentially selecting each of the column signal processing circuits 5, and outputting the processed pixel signals from each of the column signal processing circuits 5 to the horizontal signal line 12.

[0022] The output circuit 7 processes the pixel signals supplied sequentially from each of the column signal processing circuits 5 through the horizontal signal lines 12 and outputs them. Signal processing methods include, for example, buffering, black level adjustment, column variation correction, and various digital signal processing techniques.

[0023] The control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0024] <Pixel> Figure 3 is an equivalent circuit diagram showing one example configuration of pixel 3. Pixel 3 comprises a photoelectric conversion element PD, a charge storage region (floating diffusion) FD that stores (holds) the signal charge photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion element PD to the charge storage region FD. Pixel 3 also includes a readout circuit 15 electrically connected to the charge storage region FD.

[0025] A photoelectric converter (PD) generates a signal charge in accordance with the amount of light received. The PD also temporarily stores (holds) the generated signal charge. The cathode side of the PD is electrically connected to the source region of a transfer transistor (TR), and the anode side is electrically connected to a reference potential line (e.g., ground). A photodiode is used as the PD.

[0026] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line among the pixel drive lines 10 (see Figure 2).

[0027] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0028] The readout circuit 15 reads the signal charge stored in the charge storage region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 is not limited to but includes, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. These transistors (AMP, SEL, RST) are composed of MOSFETs having, for example, a gate insulating film made of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. Alternatively, these transistors may be MISFETs (Metal Insulator Semiconductor FETs) in which the gate insulating film is made of a silicon nitride film (Si3N4 film), or a multilayer film such as a silicon nitride film and a silicon oxide film.

[0029] The amplifying transistor AMP has its source region electrically connected to the drain region of the selection transistor SEL, and its drain region is electrically connected to the power line Vdd and the drain region of the reset transistor. The gate electrode of the amplifying transistor AMP is electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0030] The selection transistor SEL has its source region electrically connected to the vertical signal line 11 (VSL), and its drain electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line among the pixel drive lines 10 (see Figure 2).

[0031] The reset transistor RST has its source region electrically connected to the charge storage region FD and the gate electrode of the amplification transistor AMP, and its drain region electrically connected to the power line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line among the pixel drive lines 10 (see Figure 2).

[0032] ≪Specific Configuration of the Light Detection Device≫ Next, the specific configuration of the light detection device 1 will be explained using Figures 4A, 4B, 5, etc.

[0033] <Laminated structure of a photodetector> As shown in Figure 5, the photodetector 1 (semiconductor chip 2) comprises a first semiconductor layer 20 having a first surface S1 and a second surface S2 located on opposite sides of each other, a first wiring layer 30 superimposed on the first surface S1 of the first semiconductor layer 20, a second wiring layer 40 superimposed on a third surface S3 of the first wiring layer 30, which is the surface opposite to the surface on the first semiconductor layer 20 side, and a second semiconductor layer 50 superimposed on a fifth surface S5 of the second wiring layer 40, which is the surface opposite to the surface on the first wiring layer side (fourth surface S4). Such a laminated structure can be realized, for example, by laminating the first wiring layer 30 onto the first surface S1 of the first semiconductor layer 20, laminating the second wiring layer 40 onto the second semiconductor layer 50, and then superimposing and joining the third surface S3 of the first wiring layer 30 and the fourth surface S4 of the second wiring layer 40. Furthermore, the second surface S2 side, which is one of the surfaces of the first semiconductor layer 20, is sometimes called the light incident surface or back surface, and the first surface S1 side, which is the other surface of the first semiconductor layer 20, is sometimes called the device formation surface or main surface.

[0034] Furthermore, the light detection device 1 (semiconductor chip 2) includes an insulating layer 60, a color filter 81, and an on-chip lens 82. The insulating layer 60, the color filter 81, and the on-chip lens 82 are stacked in that order on the second surface S2 of the first semiconductor layer 20. The insulating layer 60 is provided in both the pixel area 2A and the peripheral area 2B, while the color filter 81 and the on-chip lens 82 are provided in the pixel area 2A of the two peripheral areas 2B.

[0035] Furthermore, the photodetector 1 (semiconductor chip 2) includes an electrode pad 14 and an insulating ring 70 that surrounds the electrode pad 14 in a plan view.

[0036] <First Semiconductor Layer> The first semiconductor layer 20 is made of a single-crystal silicon substrate of a first conductivity type, for example, p-type. As shown in Figure 5, the first semiconductor layer 20 has a well region 21 of a first conductivity type, for example, p-type, and a semiconductor region (photoelectric conversion section) 22 of a second conductivity type, for example, n-type, embedded inside the well region 21. The photoelectric conversion element PD shown in Figure 3 is made up of a region including the well region 21 and the photoelectric conversion section 22.

[0037] Furthermore, as shown in Figure 5, the first semiconductor layer 20 has a pixel region 20a that overlaps with the pixel region 2A in a plan view, and a peripheral region 20b that overlaps with the peripheral region 2B in a plan view. The peripheral region 20b is provided outside the pixel region 20a in a plan view, surrounding the pixel region 20a. The photoelectric conversion unit 22 described above is provided in the pixel region 20a. In other words, the first semiconductor layer 20 has a photoelectric conversion unit 22. The photoelectric conversion unit 22 converts incident light into photoelectrics and generates signal charges. In addition, although not shown in Figure 5, the pixel region 20a is provided with a charge storage region FD and a transfer transistor TR as shown in Figure 3. Note that when it is not necessary to distinguish between the pixel region 20a and the peripheral region 20b, they are not distinguished and are simply referred to as the first semiconductor layer 20.

[0038] In contrast, the peripheral region 20b is provided with an insulating ring 70 and a plug 75, which will be described later, as shown in Figure 5. In order to provide the insulating ring 70 and the plug 75 in the peripheral region 20b, the peripheral region 20b is provided with an annular groove 24 and a hole 25 in a plan view, as shown in Figures 6A and 6B. The peripheral region 20b is also provided with a recess 23 into which a part of the electrode pad 14 is embedded.

[0039] The groove 24 penetrates the first semiconductor layer 20 in the thickness direction and surrounds the electrode pad 14 in a plan view. Figures 6A and 6B show an example in which two grooves 24 are provided for each electrode pad 14. One or more grooves 24 can be provided for each electrode pad 14, but here we will explain assuming that two grooves 24 are provided for each electrode pad 14. To distinguish these two grooves 24, the inner groove is called the first groove 24a, and the outer groove, i.e., the groove surrounding the first groove 24a in a plan view, is called the second groove 24b. When there is no need to distinguish between the first groove 24a and the second groove 24b, they are not distinguished and are simply called groove 24. Furthermore, sometimes the first groove 24a and the second groove 24b together are referred to as groove 24.

[0040] The holes 25 penetrate the first semiconductor layer 20 in the thickness direction of the first semiconductor layer 20. More specifically, they penetrate between the bottom surface 23a of the recess 23 and the first surface S1. Multiple holes 25 are provided. More specifically, two holes 25 are provided.

[0041] <Insulating layer> The insulating layer 60 is an insulating film laminated on the second surface S2 side of the first semiconductor layer 20, for example, by a CVD method. For the insulating layer 60, materials such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and silicon carbide (SiC) can be used.

[0042] Furthermore, the insulating layer 60 fills the inside of the groove 24. The portion of the insulating layer 60 embedded in the groove 24 is called insulating layer 61 to distinguish it from the rest of the insulating layer 60. In addition, the insulating layer 60 is deposited on the bottom surface 23a and side surface 23b of the recess 23 and on the inner surface 25a of the hole 25. The portion of the insulating layer 60 deposited on the bottom surface 23a and side surface 23b of the recess 23 is called insulating layer 62 (first insulating layer) to distinguish it from the rest of the insulating layer 60. Also, to distinguish between the portion of insulating layer 62 deposited on the bottom surface 23a and the portion deposited on the side surface 23b, the portion deposited on the bottom surface 23a is called insulating layer 62a (eleventh insulating layer), and the portion deposited on the side surface 23b is called insulating layer 62b (twelfth insulating layer). When there is no need to distinguish between insulating layer 62a and insulating layer 62b, they are not distinguished and are simply called insulating layer 62. Furthermore, the portion of the insulating layer 60 deposited on the inner surface 25a of the pore 25 is called the insulating layer 63 (second insulating layer) to distinguish it from the rest of the insulating layer 60.

[0043] <plug> Multiple plugs 75 are provided. More specifically, two plugs 75 are provided. The plugs 75 are embedded in the holes 25 via an insulating layer 63, and electrically connect the electrode pad 14 to the metal layer 32 described later. More specifically, the plugs 75 are embedded in the holes 25 with the insulating layer 63 interposed between them and the first semiconductor layer 20. One end of the plug 75 is connected to the electrode pad 14. More specifically, one end of the plug 75 penetrates the insulating layer 62a and is connected to the lower surface 14b of the electrode pad 14, described later. The other end of the plug 75 is connected to the metal layer 32. More specifically, the other end of the plug 75 extends in the thickness direction of the first semiconductor layer 20, through the first semiconductor layer 20, into the first wiring layer 30. It is then connected to the metal layer 32 within the first wiring layer 30. Here, the metal layer 32 to which the other end of the plug 75 is connected is called metal layer 32a to distinguish it from other metal layers 32. Also, tungsten, for example, may be used as the material that makes up the plug 75.

[0044] <Electrode Pads> As shown in Figures 1, 4A, and 4B, multiple electrode pads (bonding pads) 14 are arranged in the peripheral region 2B of the photodetector 1 (semiconductor chip 2). The electrode pads 14 are arranged, for example, along each of the four sides in the two-dimensional plane of the semiconductor chip 2. More specifically, the electrode pads 14 are arranged in a row along each of the four sides in the X and Y directions, as shown in Figures 4A and 4B. Note that the number of electrode pads 14 is not limited to the number shown.

[0045] As shown in Figure 6B, the electrode pad 14 has an upper surface 14a, a lower surface 14b which is the surface opposite to the upper surface 14a, and a side surface 14c which is the side surface extending between the upper surface 14a and the lower surface 14b. The upper surface 14a is an exposed surface that is exposed to the outside. The electrode pad 14 is an input / output terminal used when electrically connecting the photodetector 1 to an external device. Therefore, the electrode pad 14 is exposed to the outside. More specifically, the upper surface 14a of the electrode pad 14 is exposed to the outside. Also, the upper surface 14a of the electrode pad 14 is on the same plane as surface S6 which is the surface of the insulating layer 60 opposite to the surface on the first semiconductor layer 20 side. The lower surface 14b of the electrode pad 14 is connected to the plug 75.

[0046] The electrode pad 14 is provided on the first semiconductor layer 20 side of the second semiconductor layer 50, between the first semiconductor layer 20 and the second semiconductor layer 50. The electrode pad 14 is exposed from surface S6 with an insulating layer 60 (insulating layer 62) interposed between it and the first semiconductor layer 20. Furthermore, a portion of the electrode pad 14 is embedded in the first semiconductor layer 20. More specifically, a portion of the electrode pad 14 is embedded in the recess 23 via the insulating layer 62.

[0047] Furthermore, since an insulating layer 62 is interposed between the electrode pad 14 and the first semiconductor layer 20, the electrode pad 14, the insulating layer 62, and the first semiconductor layer 20 constitute a parasitic capacitance. More specifically, the electrode pad 14, the insulating layer 62, and the region 26a described later constitute the parasitic capacitance C1 shown in Figure 6C.

[0048] <Insulating ring> As shown in Figures 5, 6A, and 6B, the insulating ring 70 is an insulating ring that penetrates the first semiconductor layer 20 in the thickness direction and surrounds the electrode pad 14 in a plan view. The insulating ring 70 is made of an insulating material. More specifically, the insulating ring 70 is an insulating layer 61.

[0049] Figures 5, 6A, and 6B show an example in which two insulating rings 70 are provided for each electrode pad 14. Although one or more insulating rings 70 can be provided for each electrode pad 14, here we will explain assuming that two are provided for each electrode pad 14. To distinguish between the two insulating rings 70, the inner insulating ring is called the first insulating ring 70a, and the outer insulating ring, that is, the insulating ring surrounding the first insulating ring 70a in a plan view, is called the second insulating ring 70b. The first insulating ring 70a is an insulating layer 61 embedded in the first groove 24a, and the second insulating ring 70b is an insulating layer 61 embedded in the second groove 24b. When there is no need to distinguish between the first insulating ring 70a and the second insulating ring 70b, they are not distinguished and are simply called insulating rings 70. Furthermore, the first insulating ring 70a and the second insulating ring 70b are sometimes collectively referred to as the insulating ring 70.

[0050] Furthermore, as shown in Figure 6A, the width d1 between the outer contour 71 and the inner contour 72 of the insulating ring 70 in a plan view is between 10 nm and 300 nm.

[0051] Since the insulating ring 70 penetrates the first semiconductor layer 20 in the thickness direction, the first semiconductor layer 20 is divided into multiple regions 26 by the insulating ring 70. Here, there are two insulating rings 70, so the first semiconductor layer 20 is divided into three regions 26 as shown in Figures 6A and 6B. Here, in order to distinguish these three regions 26 from each other, the region located inside the first insulating ring 70a is called region 26a, the region located between the first insulating ring 70a and the second insulating ring 70b is called region 26b, and the region located outside the second insulating ring 70b is called region 26c. Note that when there is no need to distinguish between regions 26a, 26b, and 26c, they are not distinguished and are simply called region 26. Furthermore, the regions 26 located inside the insulating ring 70, more specifically regions 26a and 26b, are electrically floating.

[0052] Furthermore, the insulating ring 70 and the two regions 26 adjacent to the insulating ring 70 constitute a capacitor. More specifically, region 26a, the first insulating ring 70a, and region 26b constitute capacitor C2 as shown in Figure 6C, and region 26b, the second insulating ring 70b, and region 26c constitute capacitor C3 as shown in Figure 6C. Together with the parasitic capacitance C1 mentioned above, the three capacitors C1, C2, and C3 shown in Figure 6C are connected in series.

[0053] <1st wiring layer> As shown in Figure 5, the first wiring layer 30 includes an interlayer insulating film 31, a metal layer 32, a first connection pad 33, and vias 34. The metal layer 32 and the first connection pad 33 are laminated via the interlayer insulating film 31 as shown. The vias 34 connect the metal layers 32 to each other and to the metal layer 32 and the first connection pad 33. The first connection pad 33 faces the third surface S3 of the first wiring layer 30. The first connection pad 33 is electrically connected to the metal layer 32a. For example, the first connection pad 33 is electrically connected to the metal layer 32a via multiple layers of metal layers 32 and vias 34. Furthermore, the first connection pad 33 is electrically connected to the electrode pad 14 via the metal layer 32a and plug 75.

[0054] <Second wiring layer> As shown in Figure 5, the second wiring layer 40 includes an interlayer insulating film 41, a metal layer 42, a second connection pad 43, and vias 44. The metal layer 42 and the second connection pad 43 are laminated via the interlayer insulating film 41 as shown. The vias 44 connect the metal layers 42 to each other and to the metal layer 42 and the second connection pad 43. The second connection pad 43 faces the fourth surface S4 of the second wiring layer 40 and is joined to the first connection pad 33. As a result, the electrode pad 14 of the first wiring layer 30 is electrically connected to the metal layer 42 of the second wiring layer 40. As shown in Figure 5, the electrode pad 14, the first connection pad 33, and the second connection pad 43 overlap in the thickness direction.

[0055] <Second Semiconductor Layer> As shown in Figure 5, the second semiconductor layer 50 is made of a single-crystal silicon substrate of the first conductivity type, for example, p-type. The second semiconductor layer 50 is provided with transistors that constitute, for example, the logic circuit 13 and the readout circuit 15.

[0056] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will now be described with reference to Figures 7A to 7M. ​​First, as shown in Figure 7A, a substrate 87 is prepared in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 40, and a second semiconductor layer 50 are sequentially stacked in that order. Although not shown, the first semiconductor layer 20 already has diffusion regions such as n-type semiconductor regions 22 and various transistors formed thereon. Although not shown, various transistors are formed on the second semiconductor layer 50. The second connection pad 43 and the first connection pad 33 are joined together.

[0057] Next, as shown in Figure 7B, an insulating layer 60A is laminated onto the second surface S2 of the first semiconductor layer 20. Then, as shown in Figure 7C, a resist pattern 90 is laminated onto the surface of the insulating layer 60A opposite to the surface facing the first semiconductor layer 20. Then, using the resist pattern 90 as a mask, the insulating layer 60A and the first semiconductor layer 20 are etched to form the recess 23 shown in Figure 7D.

[0058] Then, as shown in Figures 7E and 7F, a resist pattern 92 is laminated on the insulating layer 60A and the recess 23. Figure 7F is a plan view showing the resist pattern 92 formed in the process of Figure 7E. Then, as shown in Figure 7G, etching is performed using the resist pattern 92 as a mask. More specifically, the first semiconductor layer 20 exposed from the opening 92a of the resist pattern 92 is etched to form holes 25 that penetrate the first semiconductor layer 20. Furthermore, the insulating layer 60A and the first semiconductor layer 20 exposed from the opening 92b of the resist pattern 92 are etched to form grooves 24 that penetrate the first semiconductor layer 20.

[0059] Next, as shown in Figure 7H, an insulating layer 60B is laminated onto the insulating layer 60A and the first semiconductor layer 20. Note that the insulating layer 60 described above includes insulating layer 60A and insulating layer 60B. The laminated insulating layer 60B is embedded inside the groove 24. The insulating layer 60B embedded inside the groove 24 corresponds to the insulating layer 61 shown in Figure 6B. This forms the insulating ring 70 shown in Figure 6B.

[0060] Furthermore, as shown in Figure 7H, the insulating layer 60B is laminated so as to cover the inner surface 25a of the hole 25. Since the diameter of the hole 25 is larger than the width of the groove 24 (width d1 of the insulating ring 70), the hole 25 is not completely filled with the insulating layer 60B, and the inner surface 25a is covered with the insulating layer 60B. The diameter of the hole 25 is, for example, about two or three times the width of the groove 24. The cavity of the hole 25 after it has been covered with the insulating layer 60B is called hole 25A.

[0061] Then, after removing the insulating layer 60B which is laminated on the metal layer 32a through the holes 25, a tungsten film 75A is laminated so as to cover the insulating layer 60B and fill the inside of the holes 25A, as shown in Figure 7I. After that, as shown in Figure 7J, the entire surface is etched to remove the unnecessary parts of the tungsten film 75A. This forms the plug 75.

[0062] Subsequently, as shown in Figure 7K, an aluminum film 14A is deposited. Then, as shown in Figure 7L, a resist pattern 93 is deposited on the aluminum film 14A, and as shown in Figure 7M, the entire surface is etched to remove the unnecessary parts of the aluminum film 14A. This forms the electrode pad 14.

[0063] After forming the electrode pad 14, although not shown in the diagram, a color filter 81 and an on-chip lens 82 are stacked in that order on the side of the insulating layer 60 opposite to the side facing the first semiconductor layer 20, and the photodetector 1 shown in Figure 5 is almost complete. The photodetector 1 is formed in each of the multiple chip formation regions demarcated by scribe lines (dicing lines) on the semiconductor substrate. Then, by dividing these multiple chip formation regions individually along the scribe lines, a semiconductor chip 2 on which the photodetector 1 is mounted is formed.

[0064] <<Main effects of the first embodiment>> The main effects of the first embodiment will be described below. Here, in addition to the case with two insulating rings 70 shown in Figures 6A and 6C described above, the main effects will be explained using the case with one insulating ring 70 shown in Figures 8A and 8B, and the case with three insulating rings 70 shown in Figures 9A and 9B as examples.

[0065] When there is one insulating ring 70, the two capacitors C1 and C2 shown in Figure 8B are connected in series. When there are two insulating rings 70, as already explained, the three capacitors C1, C2, and C3 shown in Figure 6C are connected in series. And when there are three insulating rings 70, the four capacitors C1, C2, C3, and C4 shown in Figure 9B are connected in series. The parasitic capacitance accumulated in the electrode pad 14 is the combined capacitance C of these multiple capacitors. Here, capacitor C4 is composed of region 26c, the second insulating ring 70c, and region 26dd.

[0066] Conventional photodetectors do not have insulating rings 70, meaning there are zero insulating rings. As shown in Figure 10, when insulating rings 70 are not provided, the combined capacitance of the capacitors is C = C1. In contrast, when there is one insulating ring 70, the combined capacitance of the capacitors is C = C1 × C2 / (C1 + C2), when there are two insulating rings, it is C = C1 × C2 × C3 / (C1 + C2 + C3), and when there are three insulating rings, it is C = C1 × C2 × C3 × C4 / (C1 + C2 + C3 + C4). When capacitors are connected in series, the combined capacitance decreases as the number of series connections increases. Figure 11 shows the calculation results of the combined capacitance. As shown in Figure 11, when there is one insulating ring 70, the combined capacitance is about one-seventh of that when there are zero rings. Furthermore, when there are three insulating rings 70, the combined capacitance is further halved compared to the case of one ring. Furthermore, although Figure 11 does not show the combined capacitance when there are two insulating rings 70, it is thought that the value will be somewhere between the combined capacitance when there is one ring and the combined capacitance when there are three rings.

[0067] The insulating ring 70 penetrates the first semiconductor layer 20 in the thickness direction. Therefore, the region 26 located inside the insulating ring 70 becomes electrically floating, which suppresses the accumulation of electric charge.

[0068] In this way, by utilizing the space around the electrode pad 14 to provide the insulating ring 70, the increase in parasitic capacitance accumulated in the electrode pad 14 can be suppressed. Furthermore, by increasing the number of insulating rings 70, the increase in parasitic capacitance accumulated in the electrode pad 14 can be suppressed even further. This suppresses wiring delay and RC delay, and prevents the signal speed from slowing down.

[0069] Furthermore, in the photodetector 1 according to the first embodiment of this technology, the increase in parasitic capacitance accumulated in the electrode pad 14 can be suppressed, so there is little disadvantage in relocating the electrode pad 14 to the first semiconductor layer 20 side in the thickness direction. Therefore, for example, it is possible to decide to relocate the electrode pad 14, which was conventionally provided on the second wiring layer 40, to the first semiconductor layer 20 side without hesitation. In addition, the degree of freedom in the layout of the electrode pad 14 is increased.

[0070] In the example of a conventional photodetector 1', as shown in Figure 12, the electrode pad 14 was provided in the second wiring layer 40. Therefore, the recess 23' was made deep in the thickness direction, and the electrode pad 14 was provided at the bottom of the recess 23'. Consequently, in order to place the ball B at a deep position and provide the wire W at the end of the ball B, it was necessary to increase the volume of the ball B and the electrode pad 14.

[0071] In contrast, in the photodetector 1 according to the first embodiment of this technology, the insulating ring 70 can suppress the increase in the combined capacitance C between the first semiconductor layer 20 and the electrode pad 14, so that the electrode pad 14 can be moved to the first semiconductor layer 20 side. Since the electrode pad 14 is moved to the first semiconductor layer 20 side, wire bonding can be performed more easily. Furthermore, the size of the wire bonding balls can be reduced, and the dimensions of the semiconductor chip 2 on which the electrode pad 14 and the photodetector 1 are mounted can be made smaller. In addition, the reliability of wire bonding is improved and the semiconductor chip 2 becomes smaller, so the amount of chips that can be obtained from the wafer increases, which can also contribute to cost reduction.

[0072] Furthermore, the electrode pad 14, the first connecting pad 33, and the second connecting pad 43 overlap in the thickness direction. This allows the conductive path from the electrode pad 14 to the metal layer 42 of the second wiring layer 40 to be shorter than when the conductive path is formed by the trench portion 83 described in Figures 14 and 15. Therefore, even with this configuration, it is possible to suppress the increase in parasitic capacitance accumulated in the electrode pad 14.

[0073] In this first embodiment, the number of second insulating rings surrounding the first insulating ring 70a in a plan view was one or two, but it is not limited to these, and may be three or more. That is, the insulating ring 70 may include the first insulating ring 70a and at least one second insulating ring surrounding the first insulating ring 70a in a plan view. Furthermore, although two plugs 75 were provided for each electrode pad 14, this is not limited to this, and one plug may be provided. Moreover, three or more plugs may be provided for each electrode pad 14. Similarly, although two holes 25 were provided for each electrode pad 14, this is not limited to this, and one or three or more holes may be provided depending on the number of plugs 75.

[0074] [Modification 1 of the First Embodiment] A modification 1 of the first embodiment of this technology, shown in Figure 13, will be described below. The difference between the photodetector 1 according to this modification 1 of the first embodiment and the photodetector 1 according to the first embodiment described above is the shape of the electrode pad 14; the other configurations of the photodetector 1 are basically the same as those of the photodetector 1 according to the first embodiment described above. Components that have already been described will be given the same reference numerals and their descriptions will be omitted.

[0075] The electrode pad 14 has a head portion 141 and a body portion 142 formed integrally with the head portion 141. The upper surface 141a of the head portion 141 is an exposed surface that is exposed to the outside. The body portion 142 is connected to the metal layer 32a.

[0076] <<Main effects of Modification 1 of the First Embodiment>> Even with the light detection device 1 according to this modified example 1 of the first embodiment, the same effects as the light detection device 1 according to the first embodiment described above can be obtained.

[0077] [Modification 2 of the First Embodiment] A modified example 2 of the first embodiment of this technology, shown in Figure 14, will be described below. The difference between the photodetector 1 according to this modified example 2 of the first embodiment and the photodetector 1 according to the first embodiment described above is that the first substrate (first semiconductor layer 20 and first wiring layer 30) 84 and the second substrate (second semiconductor layer 50 and second wiring layer 40) 85 are electrically connected via a trench portion 83. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 according to the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0078] The photodetector 1 has a trench portion 83 instead of a plug 75. The trench portion 83 extends from the insulating layer 60 laminated on the first semiconductor layer 20 to the metal layer 42 of the second wiring layer 40, and one end located at a deep position in the direction of extension is connected to the metal layer 42. The electrode pad 14 has a head portion 141 and a connecting portion 143. The upper surface 141a of the head portion 141 is an exposed surface that is exposed to the outside. The connecting portion 143 electrically connects the head portion 141 and the trench portion 83.

[0079] <<Main effects of modified example 2 of the first embodiment>> Even with the light detection device 1 according to this modified example 2 of the first embodiment, the same effects as the light detection device 1 according to the first embodiment described above can be obtained.

[0080] Note that the electrode pad 14 does not necessarily have a connection portion 143. In that case, the head portion 141 and the trench portion 83 are directly connected.

[0081] [Modification 3 of the First Embodiment] A third modification of the first embodiment of this technology, shown in Figure 15, will be described below. The difference between the photodetector 1 according to this third modification of the first embodiment and the photodetector 1 according to the first embodiment and the second modification of the first embodiment described above is that it has only the first substrate 84 of the first substrate 84 and the second substrate 85 described above, and that the first semiconductor layer 20 and the metal layer 32 are electrically connected via the trench portion 83. The configuration of the photodetector 1 otherwise is basically the same as that of the photodetector 1 according to the first embodiment and the second modification of the first embodiment described above. Note that components that have already been described are denoted by the same reference numerals and their descriptions are omitted.

[0082] The light detection device 1 has a trench portion 83 instead of a plug 75. The light detection device 1 also has a first substrate 84 and a support substrate 86. The trench portion 83 extends from the insulating layer 60 laminated on the first semiconductor layer 20 to the metal layer 32 of the first wiring layer 30, and one end located at a deep position in the direction of extension is connected to the metal layer 32. The connection portion 143 electrically connects the head portion 141 and the trench portion 83.

[0083] <<Main effects of Modification 3 of the First Embodiment>> Even with the photodetector 1 according to this modification 3 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment and modification 2 of the first embodiment described above can be obtained.

[0084] Note that the electrode pad 14 does not necessarily have a connection portion 143. In that case, the head portion 141 and the trench portion 83 are directly connected.

[0085] [Modification 4 of the First Embodiment] A modification 4 of the first embodiment of this technology, shown in Figure 16, will be described below. The difference between the photodetector 1 according to this modification 4 of the first embodiment and the first embodiment described above is that the electrode pad 14 protrudes from the surface S6, and the other configurations of the photodetector 1 are basically the same as those of the first embodiment described above. Components that have already been described will be given the same reference numerals and their descriptions will be omitted.

[0086] The electrode pad 14 is laminated on the second surface S2 of the first semiconductor layer 20. The electrode pad 14 protrudes from surface S6. Since the color filter 81 and the on-chip lens 82 are provided by coating surface S6 with, for example, resin, it is preferable that the coated surface be flat. Therefore, in the first embodiment, the electrode pad 14 was provided such that its upper surface 14a was located on the same plane as surface S6.

[0087] In contrast, in the case of a light detection device that does not require a color filter 81 and an on-chip lens 82, such as a monochrome sensor, the electrode pad 14 protruding from the surface S6 does not affect the coating properties of the resin.

[0088] <<Main effects of Modification 4 of the First Embodiment>> Even with the photodetector 1 according to this modified example 4 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment described above can be obtained.

[0089] [Modification 5 of the First Embodiment] A modification 5 of the first embodiment of this technology, shown in Figure 17, will be described below. The difference between the photodetector 1 according to this modification 5 of the first embodiment and the first embodiment described above is that the electrode pad 14 is provided in a recessed position from the surface S6. The other configurations of the photodetector 1 are basically the same as those of the first embodiment described above. Components that have already been described will be given the same reference numerals and their descriptions will be omitted.

[0090] The electrode pad 14 is embedded within the first semiconductor layer 20. The upper surface 14a of the electrode pad 14 is coplanar with the second surface S2. Therefore, the portion of the insulating layer 60 that overlaps with the electrode pad 14 in a plan view is removed.

[0091] For example, in the case of a light detection device that does not require a color filter 81 and an on-chip lens 82, such as a monochrome sensor, the application of the resin will not be affected even if the electrode pad 14 is located in a recessed position from the surface S6.

[0092] <<Main effects of Modification 5 of the First Embodiment>> Even with the photodetector 1 according to this modified example 5 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment described above can be obtained.

[0093] [Modification 6 of the First Embodiment] A modification 6 of the first embodiment of this technology, shown in Figure 18, will be described below. The difference between the photodetector 1 according to modification 6 of the first embodiment and the first embodiment described above is that the insulating ring 70 includes an insulating layer 61F and a gap 28, while the other configurations of the photodetector 1 are basically the same as those of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0094] As shown in the figure, the groove 24 is not completely filled with the insulating layer 60 and contains a void 28. In other words, the insulating ring 70 contains both the insulating layer 61F and the void 28. The void 28 functions as an insulating layer and can therefore function as part of the insulating ring 70.

[0095] <<Main effects of modified example 6 of the first embodiment>> Even with the photodetector 1 according to this modified example 6 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment described above can be obtained.

[0096] [Modification 7 of the first embodiment] A modification 7 of the first embodiment of this technology, shown in Figure 19, will be described below. The difference between the photodetector 1 according to modification 7 of the first embodiment and the first embodiment described above is that the insulating ring 70 includes a gap 28, and the other configurations of the photodetector 1 are basically the same as those of the first embodiment described above. Components that have already been described will be given the same reference numerals and their descriptions will be omitted.

[0097] As shown in the diagram, the inside of the groove 24 is not filled with the insulating layer 60, but is an air gap 28. In other words, the insulating ring 70 is composed of air gaps 28. Since the air gaps 28 function as an insulating layer, the insulating ring 70 can function.

[0098] <<Main effects of Modification 7 of the First Embodiment>> Even with the photodetector 1 according to this modified example 7 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment described above can be obtained.

[0099] [Second Embodiment] A second embodiment of the present technology, shown in Figures 20, 21A, and 21B, will be described below. The difference between the photodetector 1 of this second embodiment and the photodetector 1 of the first embodiment described above is that it has a ring-shaped plug ring 76 instead of a columnar plug 75, and a ring-shaped groove 27 is provided in the first semiconductor layer 20 instead of a hole 25. The rest of the configuration of the photodetector 1 is basically the same as that of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0100] <Plug ring> Figures 20, 21A, and 21B show an example in which a single ring-shaped plug ring 76 is provided. As shown in Figure 21B, one end of the plug ring 76 is connected to the electrode pad 14 and the other end is connected to the metal layer 32a, electrically connecting the electrode pad 14 and the metal layer 32a. The plug ring 76 is embedded in the groove 27 via an insulating layer 63. The plug ring 76 and the groove 27 penetrate the first semiconductor layer 20 in the thickness direction of the first semiconductor layer 20. As shown in Figure 21A, in plan view, the plug ring 76 is annular and positioned inside the contour 14d of the electrode pad 14. The groove 27 is annular in plan view. The insulating layer 63 is interposed between the first semiconductor layer 20 and the plug ring 76. Here, it is desirable that the insulating layer 63 leaves a gap of several tens of nanometers or more between the first semiconductor layer 20 and the plug ring 76.

[0101] The plug ring 76 penetrates the first semiconductor layer 20 in the thickness direction, thereby dividing the first semiconductor layer 20 into multiple regions. More specifically, the plug ring 76 divides region 26a of the first semiconductor layer 20 in the first embodiment into region 26d and region 26e. The divided regions 26d and 26e are electrically floating. Furthermore, it is preferable to place the plug ring 76 as far as possible on the outer circumference of the electrode pad 14. This makes the plug ring 76 less susceptible to damage during wire bonding.

[0102] In Figures 20, 21A, and 21B, two insulating rings 70 are provided. However, for simplicity, we will consider the capacitor configuration when there is only one insulating ring 70, as shown in Figure 22A.

[0103] More specifically, the electrode pad 14, the insulating layer 62 (mainly the insulating layer 62b), and region 26d constitute the parasitic capacitance C5 shown in Figure 22B, and region 26d, the first insulating ring 70a, and region 26b constitute the capacitor C6. The series-connected capacitors C5 and C6 are mainly the capacitance of the side component accumulated on the side surface 14c of the electrode pad 14.

[0104] The electrode pad 14, the insulating layer 62 (mainly the insulating layer 62a), and region 26e form a parasitic capacitance C7 as shown in Figure 22B. Furthermore, region 26e and region 26b form a capacitor C8 via the interlayer insulating film 31 of the first wiring layer 30. The series-connected capacitors C7 and C8 represent the capacitance of the bottom surface component, which is mainly accumulated on the bottom surface 14b of the electrode pad 14. In this way, the plug ring 76 separates the parasitic capacitance of the electrode pad 14 into a side surface component and a bottom surface component.

[0105] Here, the dimensions 14x and 14y of the electrode pad 14 in a plan view as shown in Figure 21A are, for example, on the order of 100 μm, whereas the dimension 14z of the electrode pad 14 in a longitudinal cross-sectional view as shown in Figure 21B is, for example, only a few μm. In other words, the area of ​​the lower surface 14b of the electrode pad 14 is overwhelmingly larger than the area of ​​the side surface 14c.

[0106] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below. Here, the differences from the manufacturing method of the photodetector 1 according to the first embodiment described above will be explained. First, the steps shown in Figures 7A to 7D are performed. Then, in the step shown in Figure 7E, the resist pattern 92A shown in Figure 23 is laminated in place of the resist pattern 92 shown in Figure 7F. Then, using the resist pattern 92A, the etching step shown in Figure 7G is performed. More specifically, the first semiconductor layer 20 exposed from the opening 92c of the resist pattern 92A is etched to form a groove 27 that penetrates the first semiconductor layer 20. This forms a ring-shaped groove 27 in the first semiconductor layer 20. Furthermore, the insulating layer 60A and the first semiconductor layer 20 exposed from the opening 92b of the resist pattern 92 are etched to form a groove 24 that penetrates the first semiconductor layer 20. After that, the steps shown in Figures 7H to 7M are performed. Since the ring-shaped groove 27 is formed by the etching step shown in Figure 7G, a ring-shaped plug ring 76 can be formed.

[0107] <<Main effects of the second embodiment>> Even with the light detection device 1 according to this second embodiment, the same effects as the light detection device 1 according to the first embodiment described above can be obtained.

[0108] Here, the number of insulating rings 70 that can be provided for a single electrode pad 14 may be limited by the spacing between the electrode pads 14. Conversely, it may be necessary to widen the spacing between the electrode pads 14 in order to increase the number of insulating rings 70. Thus, there may be a trade-off between the number of insulating rings 70 and the spacing between the electrode pads 14, and chip shrinking may be limited.

[0109] Even in such cases, in the photodetector 1 according to the second embodiment of this technology, the plug ring 76 is connected to the lower surface 14b of the electrode pad 14, so the area on the lower surface 14b side of the electrode pad 14 can be effectively utilized, and the number of capacitors to suppress the increase in parasitic capacitance can be increased regardless of the spacing between the electrode pads 14.

[0110] Furthermore, in the case where a plug ring 76 is not provided as in the first embodiment, the parasitic capacitance C1 closer to the electrode pad 14 is dominant as the parasitic capacitance contributing to the electrode pad 14. Moreover, the area of ​​the bottom surface 14b of the electrode pad 14 is overwhelmingly larger than the area of ​​the side surface 14c. Therefore, among the dominant parasitic capacitances C1, the parasitic capacitance contributing to the bottom surface 14b is more dominant than the parasitic capacitance contributing to the side surface 14c.

[0111] In the photodetector 1 according to the second embodiment of this technology, the parasitic capacitance to the electrode pad 14 can be separated into a lateral component and a lower component, and a capacitor can be provided on the lower surface 14b, where the parasitic capacitance contributing to the electrode pad 14 is larger, thereby further suppressing the increase in parasitic capacitance.

[0112] In this embodiment 2, the width d1 of the insulating ring 70 and the width d2 of the plug ring 76 shown in Figure 21A were constant along the thickness direction of the first semiconductor layer 20, but are not limited to this, and may have a tapered shape in a longitudinal cross-sectional view. For example, as shown in Figure 24, the width d1 of the insulating ring 70 and the width d2 of the plug ring 76 may be thicker on the electrode pad 14 side than on the metal layer 32a side in the thickness direction of the first semiconductor layer 20. Here, the width d2 of the plug ring 76 is the width between the outer contour 77 and the inner contour 78 of the plug ring 76 in a plan view, as shown in Figure 21A.

[0113] [Modification 1 of the second embodiment] A modification 1 of the second embodiment of the present technology, shown in Figures 25A and 25B, will be described below. The difference between the photodetector 1 according to this modification 1 of the second embodiment and the photodetector 1 according to the second embodiment described above is that it has multiple plug rings 76, and the rest of the configuration of the photodetector 1 is basically the same as that of the photodetector 1 according to the second embodiment described above. Note that components that have already been described are denoted by the same reference numerals and their descriptions are omitted.

[0114] <Plug ring> Figures 25A and 25B show an example in which two ring-shaped plug rings 76 are provided. In other words, the plug ring 76 includes a first plug ring 76a and a second plug ring 76b that surrounds the first plug ring 76a in a plan view. That is, the plug ring 76 is redundant. Note that when there is no need to distinguish between the first plug ring 76a and the second plug ring 76b, they are not distinguished and are simply referred to as plug ring 76.

[0115] The first plug ring 76a and the second plug ring 76b are provided in grooves 27a(27) and grooves 27b(27) provided in the first semiconductor layer 20, via an insulating layer 63.

[0116] The first plug ring 76a and the second plug ring 76b penetrate the first semiconductor layer 20 in the thickness direction of the first semiconductor layer 20, dividing the first semiconductor layer 20 into multiple regions. More specifically, the first plug ring 76a divides the first semiconductor layer 20 inside the second plug ring 76b (i.e., region 26e in the second embodiment) into region 26f and region 26g. The divided regions 26f and 26g are electrically floating. Also, as in the second embodiment, it is preferable to place the plug ring 76 as far to the outer circumference of the electrode pad 14 as possible. This makes the plug ring 76 less susceptible to damage during wire bonding. However, due to space constraints, the plug ring 76 may overlap with the ball B in the thickness direction of the first semiconductor layer 20. However, even in such cases, the plug ring 76 can be made less susceptible to damage during wire bonding by, for example, changing the thickness of the electrode pad 14 or the type of barrier metal.

[0117] Here, although two insulating rings 70 are provided in Figures 25A and 25B, for simplification, we will consider the capacitor configuration when there is only one insulating ring 70, as shown in Figure 26A. Here, only the lower surface component of the capacitor will be explained. The electrode pad 14, the insulating layer 62 (mainly insulating layer 62a), and region 26f constitute the parasitic capacitance C9 shown in Figure 26B, and regions 26f and 26b constitute the capacitor C10 via the interlayer insulating film 31 of the first wiring layer 30. Furthermore, the electrode pad 14, the insulating layer 62 (mainly insulating layer 62a), and region 26g constitute the parasitic capacitance C11 shown in Figure 26B, and regions 26g and 26b constitute the capacitor C12 via the interlayer insulating film 31 of the first wiring layer 30. Capacitors C9 and C10 are connected in series, and capacitors C11 and C12 are connected in series. Capacitors C9, C10, C11, and C12 are primarily the capacitance components of the lower surface 14b of the electrode pad 14. In this way, the parasitic capacitance components of the lower surface of the electrode pad 14 are separated into multiple components.

[0118] <<Main effects of Modification 1 of the second embodiment>> Even with the light detection device 1 according to this modified example 1 of the second embodiment, the same effects as the light detection device 1 according to the second embodiment described above can be obtained.

[0119] Furthermore, by multiplexing the plug rings 76, the portion of the first semiconductor layer 20 that overlaps with the electrode pad 14 in a plan view is divided into multiple floating regions. Since an additional capacitor can be provided on the lower surface 14b, which has a larger parasitic capacitance contributing to the electrode pad 14, the increase in parasitic capacitance can be further suppressed.

[0120] Furthermore, since the contact area between the plug ring 76 and the electrode pad 14 can be increased, contact resistance can also be reduced.

[0121] In the plug ring 76, the plug ring 76 included a first plug ring 76a and a second plug ring 76b that surrounds the first plug ring 76a in a plan view. However, the number of second plug rings 76b is not limited to one, and there may be two or more. That is, the plug ring 76 may include a first plug ring 76a and at least one second plug ring 76b that surrounds the first plug ring 76a in a plan view.

[0122] [Modification 2 of the second embodiment] A modified example 2 of the second embodiment of this technology, shown in Figure 27, will be described below. The difference between the photodetector 1 according to this modified example 2 of the second embodiment and the photodetector 1 according to the second embodiment described above is that the shape of the insulating ring 70 and the plug ring 76 in the longitudinal cross-section is an inverse taper shape. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 according to the second embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0123] As shown in the figure, the cross-sectional shapes of the insulating ring 70 and the plug ring 76 are inversely tapered. As shown in Figure 27, the width d1 of the insulating ring 70 and the width d2 of the plug ring 76 are narrower towards the electrode pad 14 side than towards the metal layer 32a side in the thickness direction of the first semiconductor layer 20.

[0124] ≪Manufacturing Method for Light Detection Devices≫ The following describes the manufacturing method of the modified photodetector 1 (Modified Example 2). Here, the focus will be on the differences from the manufacturing method of the photodetector 1 according to the second embodiment described above. Note that, for the sake of simplification, the shapes of the parts are not reverse-tapered in this example.

[0125] In the second embodiment, the grooves 24 and 27 for providing the insulating ring 70 and plug ring 76 are formed in the first semiconductor layer 20 after the first wiring layer 30 and the second wiring layer 40 are joined, whereas in the modified example 2 of this second embodiment, grooves 24 and 27 are formed in the first semiconductor layer 20 before joining.

[0126] First, the first substrate (first semiconductor layer 20 and first wiring layer 30) 84 and the second substrate (second semiconductor layer 50 and second wiring layer 40) 85 are prepared. For the first substrate 84, as shown in Figure 28A, after forming transistors etc. on the first semiconductor layer 20, and before forming the metal layer 32a, grooves 24 and 27 are formed on the first semiconductor layer 20, and an insulating film is laminated thereon. The insulating layer embedded in groove 24 is the insulating layer 61, and the insulating layer embedded in groove 27 is the insulating layer 63. After that, the first wiring layer 30 is formed. A detailed explanation of the manufacturing method for the second substrate 85 is omitted here. Then, as shown in Figure 28B, the first substrate 84 and the second substrate 85 are joined together.

[0127] Subsequently, although not shown in the diagram, holes for embedding the plug ring 76 and recesses 23 are formed in the insulating layer 63 embedded in the groove 27. After that, the same process as shown in Figures 7I to 7M is carried out to obtain the plug ring 76 and insulating ring 70 shown in Figure 28C.

[0128] <<Main effects of modified example 2 of the second embodiment>> Even with the light detection device 1 according to this modified example 2 of the second embodiment, the same effects as the light detection device 1 according to the second embodiment described above can be obtained.

[0129] In addition, other steps may be used in the process of forming a hole for embedding the plug ring 76 in the insulating layer 63 embedded in the groove 27, as described above. For example, the insulating layer 63 in the groove 27 may be completely removed, and then an insulating film may be deposited again along the inner surface of the groove 27. The newly deposited insulating film does not fill the inside of the groove 27, but is deposited leaving a gap in which the plug ring 76 can be formed. That is, the insulating film is deposited along the inner surface of the groove 27 to a certain thickness, and the plug ring 76 is then embedded in the gap in the groove 27.

[0130] [Modification 3 of the second embodiment] A third modification of the second embodiment of this technology is described below. The difference between the photodetector 1 according to this third modification of the second embodiment and the photodetector 1 according to the second embodiment described above is that, similar to the second modification of the second embodiment described above, the shape of the insulating ring 70 and the plug ring 76 in the longitudinal cross-section is an inverse taper shape. Furthermore, this third modification of the second embodiment employs a different manufacturing method than the second modification of the second embodiment. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 according to the second embodiment described above. Note that components that have already been described are denoted by the same reference numerals and their descriptions are omitted.

[0131] ≪Manufacturing Method for Light Detection Devices≫ The following describes the manufacturing method of the photodetector 1 according to the modified example 3. Here, we will mainly explain the differences from the manufacturing method of the photodetector 1 according to the second embodiment and the modified example 2 of the second embodiment described above. Note that, for the sake of simplification, the shape of each part is not reverse-tapered in this example.

[0132] In Modification 2 of the Second Embodiment, the material constituting the plug ring 76 is embedded in the groove 27 after the first wiring layer 30 and the second wiring layer 40 are joined, whereas in Modification 3 of the Second Embodiment, the material constituting the plug ring 76 is embedded in the groove 27 before joining.

[0133] First, a first substrate (first semiconductor layer 20 and first wiring layer 30) 84 and a second substrate (second semiconductor layer 50 and second wiring layer 40) 85 are prepared. For the first substrate 84, as shown in Figure 29A, after forming transistors and the like, and before forming the metal layer 32a, grooves 24 and 27 are formed in the first semiconductor layer 20, and an insulating film is laminated thereon. The insulating layer embedded in groove 24 is the insulating layer 61, and the insulating layer embedded in groove 27 is the insulating layer 63. Next, as shown in the same figure, a hole is formed in the insulating layer 63 embedded in groove 27 for embedding a plug ring 76, and the material constituting the plug ring 76 is embedded in the hole to form the plug ring 76. Then, the first wiring layer 30 is formed. After that, as shown in Figure 29B, the first substrate 84 and the second substrate 85 are joined together.

[0134] Next, the same process as shown in Figures 7D and 7K to 7M is carried out to obtain the plug ring 76 and insulating ring 70 shown in Figure 29C.

[0135] <<Main effects of Modification 3 of the second embodiment>> Even with the photodetector 1 according to this modified example 3 of the second embodiment, the same effects as the photodetector 1 according to the second embodiment described above can be obtained.

[0136] Furthermore, in Modification 3 of the second embodiment, the embedding of the material constituting the plug ring 76 (e.g., tungsten) is completed before joining the first substrate 84 and the second substrate 85. Therefore, the tungsten metal 79 (Figure 28C) that remained in contact with the side wall of the electrode pad 14 in Modification 2 of the second embodiment does not remain in Modification 3 of the second embodiment. As a result, the pad resistance of the electrode pad 14 can be suppressed.

[0137] In the process of forming the plug ring 76 described above, a hole for embedding the plug ring 76 was formed in the insulating layer 63 embedded in the groove 27, and tungsten was embedded in that hole, but this is not the only method. For example, an insulating film may be formed without completely filling the groove 27 with the insulating layer 63, as shown in Figure 7H, and then the tungsten may be embedded.

[0138] [Third Embodiment] <Examples of applications in electronic devices> Next, an electronic device according to the third embodiment of this technology, shown in Figure 30, will be described. The electronic device 100 according to the third embodiment includes a light detection device (solid-state imaging device) 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 of the third embodiment shows an embodiment in which the above-described light detection device 1 is used as the light detection device 101 in an electronic device (for example, a camera).

[0139] The optical lens (optical system) 102 forms an image of the incident light (incident light 106) from the subject onto the imaging surface of the light detection device 101. As a result, signal charge accumulates in the light detection device 101 over a certain period of time. The shutter device 103 controls the light irradiation period and the light shielding period for the light detection device 101. The drive circuit 104 supplies drive signals to control the transfer operation of the light detection device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause the light detection device 101 to transfer signals. The signal processing circuit 105 performs various signal processing on the signal (pixel signal) output from the light detection device 101. The processed video signal is stored in a storage medium such as memory, or output to a monitor.

[0140] With this configuration, the electronic device 100 of the third embodiment can suppress the parasitic capacitance accumulated in the electrode pad 14 in the photodetector 101, thereby improving the image quality of the video signal.

[0141] Furthermore, the electronic device 100 to which the light detection device 1 according to the first and second embodiments can be applied is not limited to cameras, but can also be applied to other electronic devices. For example, it may be applied to imaging devices such as camera modules for mobile devices such as mobile phones.

[0142] Furthermore, in the third embodiment, the photodetector 101 can be a photodetector 1 according to either the first embodiment and its modifications, or the second embodiment and its modifications, or a photodetector 1 according to at least two embodiments or modifications of the first embodiment and its modifications and the second embodiment and its modifications, or a combination of modifications.

[0143] [Other embodiments] As described above, this technology has been presented in three embodiments; however, the discussions and drawings that constitute part of this disclosure should not be understood as limiting this technology. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0144] For example, it is possible to combine the technical concepts described in the first to third embodiments. For instance, the insulating ring 70 in the modified versions 6 and 7 of the first embodiment described above had a gap 28, but various combinations are possible in accordance with each technical concept, such as applying such a technical concept to the photodetector 1 described in the second embodiment.

[0145] Furthermore, the insulating ring 70 may be made of a different material from the insulating layer laminated on the first surface S1 and the second surface S2 of the first semiconductor layer 20. In addition, the insulating ring 70 may be formed by a different process than the insulating layer laminated on the first surface S1 and the second surface S2 of the first semiconductor layer 20. For example, the insulating ring 70 may be formed by performing an STI (Shallow Trench Isolation) process from the first surface S1 side and a DTI (Deep Trench Isolation) process from the second surface S2 side, and laminating various types, multiple layers, or multiple parts of insulating material in the groove 24. Furthermore, this technology is applicable to all types of optical detection devices, including not only solid-state imaging devices as image sensors as described above, but also distance measuring sensors, also known as ToF (Time of Flight) sensors. This is possible. The distance measuring sensor emits light toward an object, detects the reflected light that is reflected back from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until the reflected light is received. The structure of this distance measuring sensor can be the insulating ring 70, plug ring 76, and electrode pad 14 described above.

[0146] Thus, this technology naturally includes various embodiments and other features not described herein. Therefore, the technical scope of this technology is determined solely by the inventive features described in the claims as appropriate from the above description.

[0147] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0148] Furthermore, this technology may also be configured as follows. (1) A first semiconductor layer having a photoelectric conversion section, with one side being a light incident surface and the other side being an element formation surface, An insulating layer laminated on the light incident surface side of the first semiconductor layer, With the insulating layer interposed between the first semiconductor layer and the electrode pad exposed from the side of the insulating layer opposite to the side facing the first semiconductor layer, An insulating ring, which is an insulating ring that penetrates the first semiconductor layer in the thickness direction and surrounds the electrode pad in a plan view, A light detection device equipped with this device. (2) The photodetector according to (1), wherein the insulating ring includes a first insulating ring and at least one second insulating ring that surrounds the first insulating ring in a plan view. (3) The photodetector according to (1) or (2), wherein the width between the outer contour and the inner contour of the insulating ring in a plan view is 10 nm or more and 300 nm or less. (4) The photodetector according to any one of (1) to (3), wherein the insulating ring includes at least one of an insulating material and a void. (5) A first wiring layer superimposed on the element formation surface of the first semiconductor layer, A second wiring layer superimposed on the side of the first wiring layer opposite to the side facing the first semiconductor layer, The second semiconductor layer is superimposed on the side of the second wiring layer opposite to the side of the first wiring layer, The first wiring layer has a first connection pad that is electrically connected to the electrode pad on the side of the first wiring layer opposite to the side of the first semiconductor layer, The second wiring layer has a second connection pad that is bonded to the first connection pad on the side of the second wiring layer opposite to the side of the second semiconductor layer. The photodetector according to any one of (1) to (4), wherein the electrode pad, the first connecting pad, and the second connecting pad overlap in the thickness direction. (6) A first wiring layer, which includes a metal layer, is superimposed on the element formation surface of the first semiconductor layer. A plug ring that penetrates the first semiconductor layer in the thickness direction of the first semiconductor layer, is annular in plan view and is positioned inside the contour of the electrode pad, The device comprises an insulating layer interposed between the first semiconductor layer and the plug ring, The photodetector according to (1), wherein one end of the plug ring is connected to the electrode pad and the other end is connected to the metal layer, thereby electrically connecting the electrode pad and the metal layer. (7) The light detection device according to (6), wherein the plug ring includes a first plug ring and at least one second plug ring that surrounds the first plug ring in a plan view. (8) The photodetector according to (6) or (7), wherein the width between the outer and inner contours of the plug ring in a plan view is wider in the thickness direction towards the electrode pad than towards the metal layer. (9) The photodetector according to (6) or (7), wherein the width between the outer and inner contours of the plug ring in a plan view is narrower in the thickness direction towards the electrode pad than towards the metal layer. (10) The photodetector according to any one of (1) to (9), wherein the exposed surface of the electrode pad is on the same plane as the surface of the insulating layer laminated on the light incident surface side that is opposite to the surface on the first semiconductor layer side. (11) The system comprises a light detection device and an optical system for forming an image of light from an object onto the light detection device, The aforementioned light detection device is A first semiconductor layer having a photoelectric conversion section, with one side being a light incident surface and the other side being an element formation surface, An insulating layer laminated on the light incident surface side of the first semiconductor layer, With the insulating layer interposed between the first semiconductor layer and the electrode pad exposed from the side of the insulating layer opposite to the side facing the first semiconductor layer, The first semiconductor layer has an insulating ring which penetrates the first semiconductor layer in the thickness direction and surrounds the electrode pad in a plan view, electronic equipment. [Explanation of symbols]

[0149] 1. Light detection device 2 Semiconductor chips 2A Pixel area 2B Peripheral area 3 pixels 4. Vertical drive circuit 5-column signal processing circuit 6. Horizontal drive circuit 7 Output Circuit 8 Control circuits 10 pixel drive lines 11 Vertical signal lines 12 Horizontal signal lines 13 Logic Circuits 15. Readout Circuit 20 First Semiconductor Layer 23 Recess 24 groove 25 holes 26,26a,26b,26c,26d,26e,26f,26g area 27 Groove 28 void 30 1st wiring layer 33. First connection pad 40 2nd wiring layer 43. Second connection pad 50 Second Semiconductor Layer 60 Insulating layer 70 Insulating Rings 75 plugs 76 Plug Rings 100 Electronic equipment

Claims

1. A first semiconductor layer having a photoelectric conversion section, with one side being a light incident surface and the other side being an element formation surface, A first insulating layer laminated on the light incident surface side of the first semiconductor layer, With the first insulating layer interposed between the first semiconductor layer and the electrode pad exposed from the side of the first insulating layer opposite to the side facing the first semiconductor layer, A plug is provided that penetrates the first semiconductor layer in the thickness direction and has one end connected to the lower surface of the electrode pad, A second insulating layer interposed between the plug and the first semiconductor layer, An insulating ring, which is an insulating ring that penetrates the first semiconductor layer in the thickness direction and surrounds the electrode pad and the plug in a plan view, Equipped with, The insulating ring includes a first insulating ring and at least one second insulating ring that surrounds the first insulating ring in a plan view. Light detection device.

2. The photodetector according to claim 1, wherein the width between the outer contour and the inner contour of each of the first insulating ring and the second insulating ring in a plan view is 10 nm or more and 300 nm or less.

3. The photodetector according to claim 1, wherein the insulating ring includes at least one of an insulating material and a void.

4. A first wiring layer superimposed on the element formation surface of the first semiconductor layer, A second wiring layer superimposed on the side of the first wiring layer opposite to the side facing the first semiconductor layer, The second semiconductor layer is superimposed on the side of the second wiring layer opposite to the side of the first wiring layer, The first wiring layer has a first connection pad that is electrically connected to the electrode pad on the side of the first wiring layer opposite to the side of the first semiconductor layer, The second wiring layer has a second connection pad that is joined to the first connection pad on the side of the second wiring layer opposite to the side of the second semiconductor layer, The photodetector according to claim 1, wherein the electrode pad, the first connecting pad, and the second connecting pad overlap in the thickness direction.

5. The first semiconductor layer is superimposed on the element formation surface and comprises a first wiring layer including a metal layer, The plug is a plug ring that penetrates the first semiconductor layer in the thickness direction of the first semiconductor layer, is annular in plan view, and is positioned inside the contour of the electrode pad. The second insulating layer is interposed between the first semiconductor layer and the plug ring. The photodetector according to claim 1, wherein one end of the plug ring is connected to the electrode pad and the other end is connected to the metal layer, thereby electrically connecting the electrode pad and the metal layer.

6. The light detection device according to claim 5, wherein the plug ring includes a first plug ring and at least one second plug ring that surrounds the first plug ring in a plan view.

7. The photodetector according to claim 5, wherein the width between the outer and inner contours of the plug ring in a plan view is wider in the thickness direction towards the electrode pad than towards the metal layer.

8. The photodetector according to claim 5, wherein the width between the outer contour and the inner contour of the plug ring in a plan view is narrower in the thickness direction towards the electrode pad than towards the metal layer.

9. The photodetector according to claim 1, wherein the exposed surface of the electrode pad lies on the same plane as the surface of the first insulating layer laminated on the light incident surface side that is opposite to the surface on the first semiconductor layer side.

10. The system comprises a light detection device and an optical system for forming an image of light from an object onto the light detection device, The aforementioned light detection device is A first semiconductor layer having a photoelectric conversion section, with one side being a light incident surface and the other side being an element formation surface, A first insulating layer laminated on the light incident surface side of the first semiconductor layer, With the first insulating layer interposed between the first semiconductor layer and the electrode pad exposed from the side of the first insulating layer opposite to the side facing the first semiconductor layer, A plug is provided that penetrates the first semiconductor layer in the thickness direction and has one end connected to the lower surface of the electrode pad, A second insulating layer interposed between the plug and the first semiconductor layer, The first semiconductor layer has an insulating ring which penetrates the first semiconductor layer in the thickness direction and surrounds the electrode pad and the plug in a plan view, The insulating ring includes a first insulating ring and at least one second insulating ring that surrounds the first insulating ring in a plan view. electronic equipment.

Images