Semiconductor equipment

Abstract

A semiconductor device according to the present invention comprises: a first semiconductor element; a second semiconductor element; an insulation element which includes a first coil; a second coil which is magnetically coupled to the first coil; and a supporting substrate on which the first semiconductor element and the second semiconductor element are mounted. The supporting substrate includes an insulating base material and substrate wiring which is formed on the base material. The substrate wiring includes a first wiring part which is electrically interposed between the first semiconductor element and the first coil, and a second wiring part which is electrically interposed between the second semiconductor element and the second coil. The second coil is disposed between the first coil and the base material. The insulation element is supported by the supporting substrate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] There is a semiconductor device for driving a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Patent Document 1 discloses an example of such a semiconductor device (switch control device). The switch control device described in Patent Document 1 includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a first island, and a second island. The first semiconductor chip is a controller chip, and a controller that generates a switch control signal based on an input signal is integrated therein. The second semiconductor chip is a driver chip, and a driver that performs drive control of a switch based on a switch control signal input from the first semiconductor chip via the third semiconductor chip is integrated therein. A higher power supply voltage is applied to the second semiconductor chip than to the first semiconductor chip. The third semiconductor chip is, for example, a transformer chip, and a transformer that transfers a switch control signal and the like while insulating the first semiconductor chip and the second semiconductor chip from each other in a direct current manner is integrated therein. The first semiconductor chip and the third semiconductor chip are mounted on the first island, and the second semiconductor chip is mounted on the second island. The switch control device described in Patent Document 1 separates the power supply systems from each other by separating the first island and the second island from each other, such that the first island is a low-voltage side island and the second island is a high-voltage side island.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] In recent years, there has been a growing demand for miniaturization of semiconductor devices, particularly in applications such as electric vehicles. However, in the switch control device described in Patent Document 1, miniaturization may result in a reduced distance between the first and second islands. In this case, it becomes difficult to ensure sufficient distance between the first and second islands. Therefore, miniaturization of the switch control device described in Patent Document 1 raises concerns about a decrease in the dielectric strength of the device.

[0005] This disclosure was conceived in view of the above circumstances, and one of its objectives is to provide a semiconductor device that can suppress a decrease in dielectric strength even when miniaturized. [Means for solving the problem]

[0006] The semiconductor device of this disclosure comprises a first semiconductor element, a second semiconductor element, an insulating element including a first coil, a second coil magnetically coupled to the first coil, and a support substrate on which the first semiconductor element and the second semiconductor element are mounted, wherein the support substrate includes an insulating substrate and substrate wiring formed on the substrate, the substrate wiring includes a first wiring portion electrically interposed between the first semiconductor element and the first coil, and a second wiring portion electrically interposed between the second semiconductor element and the second coil, the second coil is disposed between the first coil and the substrate, and the insulating element is supported on the support substrate. [Effects of the Invention]

[0007] According to the semiconductor device of this disclosure, a decrease in dielectric strength can be suppressed even when miniaturization is achieved. [Brief explanation of the drawing]

[0008] [Figure 1]Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of Figure 1 with the sealing resin omitted. [Figure 3] Figure 3 is a plan view of Figure 2, in which the first semiconductor element, the second semiconductor element, and the insulating element are indicated by dashed lines. [Figure 4] Figure 4 is a front view showing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a left side view showing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a right side view showing a semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view along the line VII-VII in Figure 2. [Figure 8] Figure 8 is a partially enlarged cross-sectional view of a portion of Figure 7 (near the first semiconductor device). [Figure 9] Figure 9 is a partially enlarged cross-sectional view of a portion of Figure 7 (near the second semiconductor element). [Figure 10] Figure 10 is a partially enlarged cross-sectional view of a portion of Figure 7 (near the insulating element). [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI in Figure 2. [Figure 12] Figure 12 is an exploded perspective view showing an example of the configuration of an insulating element. [Figure 13] Figure 13 is a plan view showing a semiconductor device according to the second embodiment, in which the sealing resin is omitted. [Figure 14] Figure 14 is a cross-sectional view along the line XIV-XIV in Figure 13. [Figure 15] Figure 15 is a plan view showing a semiconductor device according to the third embodiment, in which the sealing resin is omitted. [Figure 16] Figure 16 is a cross-sectional view along the line XVI-XVI in Figure 15. [Figure 17] Figure 17 is a plan view showing a semiconductor device according to a modified example of the third embodiment, in which the sealing resin is omitted. [Figure 18] Figure 18 is a cross-sectional view taken along line XVIII-XVIII of Figure 17. [Figure 19] Figure 19 is a cross-sectional view showing a semiconductor device according to the fourth embodiment, corresponding to the cross-section of Figure 7. [Figure 20] Figure 20 is a partially enlarged cross-sectional view enlarging a part (near the insulating element) of Figure 19. [Figure 21] Figure 21 is a cross-sectional view showing a semiconductor device according to the fourth embodiment, corresponding to the cross-section of Figure 11. [Figure 22] Figure 22 is a partially enlarged cross-sectional view of a main part showing a semiconductor device according to a modification of the fourth embodiment. [Figure 23] Figure 23 is a cross-sectional view showing a semiconductor device according to a modification, corresponding to the cross-section of Figure 7. [Figure 24] Figure 24 is a cross-sectional view showing a semiconductor device according to a modification, corresponding to the cross-section of Figure 7. [Figure 25] Figure 25 is a cross-sectional view of a main part showing an insulating element according to a modification, corresponding to the cross-section of Figure 10. [Figure 26] Figure 26 is a cross-sectional view showing a semiconductor device according to a modification, corresponding to the cross-section of Figure 7. [Figure 27] Figure 27 is a cross-sectional view showing a semiconductor device according to a modification, corresponding to the cross-section of Figure 7. [Figure 28] Figure 28 is a plan view showing a configuration example of an insulating element (first coil and second coil) according to a modification. [Figure 29] Figure 29 is a plan view showing a configuration example of an insulating element (first coil and second coil) according to a modification. [Figure 30] Figure 30 is a plan view showing a configuration example of an insulating element (first coil and second coil) according to a modification.

Embodiments for Carrying Out the Invention

[0009] Preferred embodiments of the semiconductor devices of this disclosure will be described below with reference to the drawings. Hereafter, identical or similar components will be denoted by the same reference numerals, and redundant descriptions will be omitted. The terms "first," "second," "third," etc., used in this disclosure are used merely as labels and are not necessarily intended to assign a sequence to the objects.

[0010] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, unless otherwise specified, "object A overlaps with object B when viewed from a certain direction" includes both "object A overlapping with all of object B" and "object A overlapping with a part of object B."

[0011] Figures 1 to 12 show a semiconductor device A1 according to a first embodiment. The semiconductor device A1 is surface-mounted on a circuit board of an inverter device such as an electric vehicle or a hybrid vehicle. The semiconductor device A1 comprises a first semiconductor element 1, a second semiconductor element 2, an insulating element 3, a support substrate 4, a plurality of first external terminals 51, a plurality of second external terminals 52, and a sealing resin 6. In the semiconductor device A1, the insulating element 3 includes a first coil L1 and a second coil L2 that are magnetically coupled to each other.

[0012] For the sake of explanation, the thickness direction of semiconductor device A1 is referred to as the "thickness direction z". In this disclosure, "plan view" refers to the view in the thickness direction z. For example, one direction perpendicular to the thickness direction z is referred to as the "first direction x". Also, a direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y".

[0013] The first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are the core components of the semiconductor device A1. As shown in Figures 1 to 4 and Figures 7 to 11, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are all composed of individual elements. As shown in Figures 1 to 3, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are each rectangular in shape with the second direction y as the longer side in a plan view, but their plan view shapes are not limited to the examples shown.

[0014] The first semiconductor element 1 is a driving element (e.g., a gate driver) for driving a switching element such as an IGBT or MOSFET. The first semiconductor element 1 has a first functional circuit. The first functional circuit includes, for example, a receiving circuit for receiving a PWM control signal, a circuit for controlling the driving of the switching element based on the PWM signal, and a transmitting circuit for transmitting an electrical signal to the second semiconductor element 2 via an insulating element 3. The electrical signal may be, for example, an output signal from a temperature sensor located near the motor. As shown in Figures 1 to 4, 7, 8 and 11, the first semiconductor element 1 is mounted on a support substrate 4.

[0015] The first semiconductor element 1 has a first element main surface 10a and a first element back surface 10b. The first element main surface 10a and the first element back surface 10b are spaced apart in the thickness direction z. As shown in Figure 8, the first element main surface 10a faces downward in the thickness direction z and faces the support substrate 4. The first element back surface 10b faces upward in the thickness direction z. The first element main surface 10a and the first element back surface 10b are both flat.

[0016] As shown in Figures 7, 8, and 11, the first semiconductor element 1 includes a first substrate 11, a first wiring layer 12, a first insulating layer 13, and a plurality of first pads 14.

[0017] As shown in Figure 8, the first substrate 11 has a first functional surface 11a on which the first functional circuit is formed. The first functional surface 11a faces downward in the thickness direction z. The constituent material of the first substrate 11 includes, for example, a semiconductor material, which is one of the following: Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), GaN (gallium nitride), or InP (indium phosphide).

[0018] The first wiring layer 12 is laminated on the first functional surface 11a, as shown in Figure 8. The first wiring layer 12 is conductive to the first functional circuit. In the examples shown in Figures 7, 8, and 11, the first wiring layer 12 has a two-layer structure, but it may have three or more layers, or even just one layer. The constituent material of the first wiring layer 12 is, for example, Cu (copper) or a Cu alloy.

[0019] The first insulating layer 13 is laminated on the first functional surface 11a, as shown in Figure 8. The first insulating layer 13 covers the first wiring layer 12, as shown in Figures 7, 8, and 11. The constituent material of the first insulating layer 13 includes, for example, glass, and the glass includes, for example, SiO2 (silicon dioxide).

[0020] Multiple first pads 14 are provided on the main surface 10a of the first element, as shown in Figure 8. Each of the multiple first pads 14 is conductive to the first functional circuit via the first wiring layer 12. The constituent material of each of the multiple first pads 14 is, for example, Cu or a Cu alloy. The constituent material may not be either Cu or a Cu alloy, but Al (aluminum) or an Al alloy. The multiple first pads 14 include multiple electrodes 141 and multiple electrodes 142, as shown in Figures 2, 7, 8, and 11. As will be understood from the configuration to be described in detail later, the multiple electrodes 141 are conductive to the first coil L1 of the insulating element 3, and the multiple electrodes 142 are conductive to the multiple first external terminals 51. The multiple electrodes 141 are located closer to the insulating element 3 in the first direction x than the multiple electrodes 142, as shown in Figures 2, 7, and 11.

[0021] As shown in Figure 8, the first semiconductor element 1 has a first insulating layer 13 and a plurality of first pads 14 (a plurality of electrodes 141, 142) that are exposed on the main surface 10a of the first element. In semiconductor device A1, since the main surface 10a of the first element faces downward in the thickness direction z, the first insulating layer 13 and the plurality of first pads 14 are exposed on the bottom surface (the surface facing downward in the thickness direction z) of the first semiconductor element 1. The surface of the first insulating layer 13 that faces downward in the thickness direction z and the surface of each of the plurality of first pads 14 that faces downward in the thickness direction z are flush. For example, these surfaces become flush by applying a mirror finish to the main surface 10a of the first element. The main surface 10a of the first element is composed of the surface of the first insulating layer 13 that faces downward in the thickness direction z and the surface of each of the plurality of first pads 14 that faces downward in the thickness direction z. The back surface 10b of the first element is composed of the surface of the first substrate 11 that faces upward in the thickness direction z.

[0022] The second semiconductor element 2 is a control element (for example, a gate driver controller) for controlling the driving of the switching element. The second semiconductor element 2 has a second functional circuit. The second functional circuit includes, for example, a circuit that converts a control signal input from an ECU or the like into a PWM signal, a transmitting circuit for transmitting the PWM signal to the insulating element 3, and a receiving circuit that receives an electrical signal from the first semiconductor element 1 via the insulating element 3. As shown in Figures 1 to 4, Figure 7, Figure 9, and Figure 11, the second semiconductor element 2 is mounted on a support substrate 4.

[0023] The second semiconductor element 2 has a second element main surface 20a and a second element back surface 20b. The second element main surface 20a and the second element back surface 20b are spaced apart in the thickness direction z. As shown in Figure 9, the second element main surface 20a faces downward in the thickness direction z and faces the support substrate 4. The second element back surface 20b faces upward in the thickness direction z. The second element main surface 20a and the second element back surface 20b are both flat.

[0024] As shown in Figures 7, 9, and 11, the second semiconductor element 2 includes a second substrate 21, a second wiring layer 22, a second insulating layer 23, and a plurality of second pads 24.

[0025] As shown in Figure 9, the second substrate 21 has a second functional surface 21a on which the second functional circuit is formed. The second functional surface 21a faces downward in the thickness direction z. The constituent material of the second substrate 21 includes, for example, a semiconductor material, which is one of the following: Si, SiC, GaAs, GaN, or InP.

[0026] The second wiring layer 22 is laminated on the second functional surface 21a, as shown in Figure 9. The second wiring layer 22 is conductive to the second functional circuit. In the examples shown in Figures 7, 9, and 11, the second wiring layer 22 has a two-layer structure, but it may have three or more layers, or even be a single layer. The constituent material of the second wiring layer 22 is, for example, Cu or a Cu alloy.

[0027] The second insulating layer 23 is laminated on the second functional surface 21a, as shown in Figure 9. The second insulating layer 23 covers the second wiring layer 22, as shown in Figures 7, 9, and 11. The constituent material of the second insulating layer 23 includes, for example, glass, which includes, for example, SiO2.

[0028] Multiple second pads 24 are provided on the main surface 20a of the second element, as shown in Figure 9. Each of the multiple second pads 24 is conductive to the second functional circuit via the second wiring layer 22. The constituent material of each of the multiple second pads 24 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy, rather than either Cu or a Cu alloy. The multiple second pads 24 include multiple electrodes 241 and multiple electrodes 242, as shown in Figures 2, 7, 9, and 11. As will be understood from the configuration to be described in detail later, the multiple electrodes 241 are conductive to the second coil L2 of the insulating element 3, and the multiple electrodes 242 are conductive to the multiple second external terminals 52. The multiple electrodes 241 are located closer to the insulating element 3 in the first direction x than the multiple electrodes 242, as shown in Figures 2, 7, and 11.

[0029] As shown in Figure 9, the second semiconductor element 2 has a second insulating layer 23 and a plurality of second pads 24 (a plurality of electrodes 241, 242) which are exposed on the main surface 20a of the second element. In semiconductor device A1, since the main surface 20a of the second element faces downward in the thickness direction z, the second insulating layer 23 and the plurality of second pads 24 are exposed on the bottom surface (the surface facing downward in the thickness direction z) of the second semiconductor element 2. The surface of the second insulating layer 23 that faces downward in the thickness direction z and the surface of each of the plurality of second pads 24 that faces downward in the thickness direction z are flush. For example, these surfaces become flush by applying a mirror finish to the main surface 20a of the second element. The main surface 20a of the second element is composed of the surface of the second insulating layer 23 that faces downward in the thickness direction z and the surface of each of the plurality of second pads 24 that faces downward in the thickness direction z. The back surface 20b of the second element is composed of the surface of the second substrate 21 that faces upward in the thickness direction z.

[0030] The insulating element 3 is an element for transmitting PWM control signals and other electrical signals in an isolated state. The insulating element 3 is, for example, an inductor-coupled type. An example of an inductor-coupled insulating element is an isolated transformer. In semiconductor device A1, the insulating element 3 transmits electrical signals in an isolated state by inductively coupling two inductors (first coil L1 and second coil L2). As shown in Figures 1 to 4, 7, 10 and 11, the insulating element 3 is mounted on a support substrate 4. Thus, the insulating element 3 is supported by the support substrate 4. As shown in Figures 1 to 4, 7 and 11, the insulating element 3 is located between the first semiconductor element 1 and the second semiconductor element 2 in the first direction x.

[0031] In semiconductor device A1, the second semiconductor element 2 requires a higher voltage than the first semiconductor element 1. For example, in an inverter device for an electric or hybrid vehicle, the power supply voltage required for the second semiconductor element 2 is approximately 0-5V, while the power supply voltage required for the first semiconductor element 1 is 600V or higher. In this example, a significant potential difference arises between the first semiconductor element 1 and the second semiconductor element 2, so the first circuit including the first semiconductor element 1 and the second circuit including the second semiconductor element 2 are insulated by the insulating element 3. In other words, the insulating element 3 insulates the first circuit including the relatively high-voltage first semiconductor element 1 from the second circuit including the relatively low-voltage second semiconductor element 2.

[0032] As shown in Figures 7, 10, and 11, the insulating element 3 has a third element main surface 30a and a third element back surface 30b. The third element main surface 30a and the third element back surface 30b are spaced apart in the thickness direction z. As shown in Figures 7, 10, and 11, the third element main surface 30a faces upward in the thickness direction z. The third element back surface 30b faces downward in the thickness direction z and faces the support substrate 4. The third element main surface 30a and the third element back surface 30b are both flat.

[0033] As shown in Figures 7 and 10 to 12, the insulating element 3 includes a third insulating layer 31, an upper wiring layer 32, a lower wiring layer 33, a plurality of third pads 34, a plurality of fourth pads 35, and a plurality of connecting wires 36.

[0034] The third insulating layer 31 includes, for example, glass as a constituent material, and the glass includes, for example, SiO2. The third insulating layer 31 includes an intermediate portion 311, an upper covering portion 312, and a lower covering portion 313, as shown in Figures 10 and 12. As shown in Figure 10, the intermediate portion 311 is interposed between the upper wiring layer 32 and the lower wiring layer 33 in the thickness direction z. The upper covering portion 312 is located above the intermediate portion 311 in the thickness direction z and covers the upper wiring layer 32. The lower covering portion 313 is located below the intermediate portion 311 in the thickness direction z and covers the lower wiring layer 33.

[0035] As shown in Figure 10, the upper wiring layer 32 is formed above the intermediate portion 311 in the thickness direction z. The upper wiring layer 32 includes the first coil L1 and a plurality of lead wires 321.

[0036] The first coil L1 is provided on the main surface 30a of the third element, as shown in Figures 10 and 12. The first coil L1 includes a plurality of winding sections L11, as shown in Figures 10 and 12. In the illustrated example, the first coil L1 includes four winding sections L11. The number of winding sections L11 is not limited to four and can be appropriately changed according to the specifications of the semiconductor device A1. Each of the plurality of winding sections L11 is wound along a plane (xy plane) perpendicular to the thickness direction z. Each of the plurality of winding sections L11 is wound in a spiral shape. In the example shown in Figure 2, each of the plurality of winding sections L11 is wound in an elliptical shape in plan view, but unlike this example, they may be wound in a circular or rectangular shape. The plurality of winding sections L11 are arranged along the second direction y.

[0037] Each of the multiple winding sections L11 has an inner end L12 and an outer end L13, as shown in Figures 7 and 10-12. The inner end L12 is the inner end of each winding section L11, and the outer end L13 is the outer end of each winding section L11. In a plan view, the inner end L12 is located at the center of each winding section L11. In the illustrated example, in a plan view, the inner end L12 coincides with the winding axis of each winding section L11. In each winding section L11, moving from the inner end L12 along the winding section L11 leads to the outer end L13. One of the inner end L12 and the other of the outer end L13 is the current input terminal in each winding section L11, and the other is the current output terminal in each winding section L11.

[0038] Multiple lead wires 321 electrically connect multiple winding sections L11 to each other, or electrically connect multiple winding sections L11 to multiple connecting wires 36 in the upper wiring layer 32. As shown in Figures 7 and 10 to 12, some of the multiple lead wires 321 are connected to the outer ends L13 of two winding sections L11 located on one side of the second direction y and also connected to any of the multiple connecting wires 36; some are connected to the outer ends L13 of two winding sections L11 located on the other side of the second direction y and also connected to any of the multiple connecting wires 36; and some are connected to the inner ends L12 of multiple winding sections L11 and each connecting wire 36. Some of the lead wires 321 are located below the first coil L1 (each winding portion L11) in the thickness direction z, as shown in Figure 12, and between the first coil L1 (each winding portion L11) and the intermediate portion 311. However, in a different configuration, they may be arranged above each winding portion L11 in the thickness direction z. In this case, the first coil L1 is not exposed on the main surface 30a of the third element and is covered by the upper covering portion 312.

[0039] As shown in Figure 10, the lower wiring layer 33 is formed below the intermediate portion 311 in the thickness direction z. The lower wiring layer 33 includes the second coil L2 and a plurality of lead wires 331.

[0040] The second coil L2 is provided on the back surface 30b of the third element, as shown in Figures 10 and 12. The second coil L2 is positioned between the first coil L1 and the support substrate 4 (substrate 41, described later) in the thickness direction z. The second coil L2 includes a plurality of winding sections L21, as shown in Figures 10 and 12. In the illustrated example, the number of winding sections L21 is the same as the number of winding sections L11, i.e., four. The number of winding sections L21 is not limited to four and can be appropriately changed according to the specifications of the semiconductor device A1. Each of the plurality of winding sections L21 is wound along a plane (xy plane) perpendicular to the thickness direction z. Each of the plurality of winding sections L21 is wound in a spiral shape. Each of the plurality of winding sections L21 is wound in an elliptical shape in plan view, but unlike this example, they may be wound in a circular or rectangular shape. As shown in Figures 2, 7, and 10, the multiple winding sections L21 overlap the multiple winding sections L11 in a plan view. Each of the multiple winding sections L21 is magnetically coupled to each of the multiple winding sections L11. This magnetically couples the first coil L1 and the second coil L2.

[0041] Each of the multiple winding sections L21 has an inner end L22 and an outer end L23, as shown in Figures 7 and 10-12. The inner end L22 is the inner end of each winding section L21, and the outer end L23 is the outer end of each winding section L21. In a plan view, the inner end L22 is located at the center of each winding section L21. In the illustrated example, in a plan view, the inner end L22 coincides with the winding axis of each winding section L21. In each winding section L21, proceeding from the inner end L22 along the winding section L21 leads to the outer end L23. Either the inner end L22 or the outer end L23 is the current input terminal in each winding section L21, and the other is the current output terminal in each winding section L21.

[0042] Multiple lead wires 331 electrically connect multiple winding sections L21 to each other, or electrically connect multiple winding sections L21 to multiple fourth pads 35 in the lower wiring layer 33. As shown in Figures 7 and 10 to 12, some of the multiple lead wires 331 are connected to the outer ends L23 of two winding sections L21 located on one side of the second direction y and also connected to one of the multiple fourth pads 35; some are connected to the outer ends L23 of two winding sections L21 located on the other side of the second direction y and also connected to one of the multiple fourth pads 35; and some are connected to the inner ends L22 of multiple winding sections L21 and each fourth pad 35. Some of the lead wires 331 are located above the second coil L2 (each winding portion L21) in the thickness direction z, as shown in Figure 12, and between the second coil L2 (each winding portion L21) and the intermediate portion 311. However, they may also be arranged below each winding portion L21 in the thickness direction z. In this case, the second coil L2 is not exposed on the back surface 30b of the third element, but is covered by the lower covering portion 313.

[0043] Each of the multiple third pads 34 is provided on the back surface 30b of the third element, as shown in Figures 7 and 10 to 12. The constituent material of each of the multiple third pads 34 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy, rather than Cu or a Cu alloy. Each of the multiple third pads 34 is electrically connected to the upper wiring layer 32 via each connecting wire 36. As shown in Figure 2, in the first direction x, the multiple third pads 34 are located on the side where the first semiconductor element 1 is placed, relative to the first coil L1 and the second coil L2.

[0044] Each of the multiple fourth pads 35 is provided on the back surface 30b of the third element, as shown in Figures 7 and 10 to 12. The constituent material of each of the multiple fourth pads 35 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy, rather than Cu or a Cu alloy. Each of the multiple fourth pads 35 is electrically connected to the lower wiring layer 33. As shown in Figure 2, in the first direction x, the multiple fourth pads 35 are located on the side where the second semiconductor element 2 is placed, relative to the first coil L1 and the second coil L2.

[0045] Each of the multiple connection wires 36 connects each of the multiple lead wires 321 of the upper wiring layer 32 to each of the multiple third pads 34. Each of the multiple connection wires 36 is covered by the third insulating layer 31. Each of the multiple connection wires 36 extends in the thickness direction z and penetrates the intermediate portion 311 and the lower covering portion 313.

[0046] As shown in Figure 10, the insulating element 3 has a third insulating layer 31 (lower covering portion 313), a plurality of third pads 34, and a plurality of fourth pads 35, all of which are exposed on the back surface 30b of the third element. In semiconductor device A1, since the back surface 30b of the third element faces downward in the thickness direction z, the third insulating layer 31, the third pads 34, and the fourth pads 35 are exposed on the lower surface (the surface facing downward in the thickness direction z) of the insulating element 3. The surface of the third insulating layer 31 facing downward in the thickness direction z, the surfaces of the plurality of third pads 34 facing downward in the thickness direction z, and the surfaces of the plurality of fourth pads 35 facing downward in the thickness direction z are flush. For example, these surfaces can be made flush by applying a mirror finish to the back surface 30b of the third element. Furthermore, in the example shown in Figure 10, a portion of the upper wiring layer 32 (for example, the first coil L1) is exposed on the main surface 30a of the third element, and a portion of the lower wiring layer 33 (for example, the second coil L2) is exposed on the back surface 30b of the third element. The surface of the portion of the lower wiring layer 33 (for example, the second coil L2) in the thickness direction z downward is flush with the surface of the third insulating layer 31 in the thickness direction z downward.

[0047] The support substrate 4 mounts and supports the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3. Conductive paths are formed between the first semiconductor element 1, the second semiconductor element 2, the insulating element 3, the plurality of first external terminals 51, and the plurality of second external terminals 52 by a portion of the support substrate 4 (substrate wiring 42, which will be described later).

[0048] As shown in Figures 4 to 11, the support substrate 4 has a mounting surface 40a and a terminal surface 40b. The mounting surface 40a and the terminal surface 40b are spaced apart in the thickness direction z. The mounting surface 40a faces upward in the thickness direction z, and the terminal surface 40b faces downward in the thickness direction z. The mounting surface 40a and the terminal surface 40b are flat. The mounting surface 40a is, for example, mirror-finished. As shown in Figures 4 to 11, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are mounted on the mounting surface 40a. The mounting surface 40a is in close contact with and directly joined to the first semiconductor element 1 (first element main surface 10a), the second semiconductor element 2 (second element main surface 20a), and the insulating element 3 (third element main surface 30a). In this disclosure, "A and B are in close contact" means that A and B are in close contact with each other. Under ideal conditions, there are no inclusions (foreign matter such as dust or dirt) or voids at the boundary between A and B, but some inclusions or voids may be present at this boundary. Also, "A and B are directly joined" means that A and B are joined without the use of adhesives or the like. Under ideal conditions, when A and B are directly joined, A and B will be in close contact. As shown in Figures 4 to 7 and Figure 11, a plurality of first external terminals 51 and a plurality of second external terminals 52 are arranged on the terminal surface 40b.

[0049] As shown in Figures 1 to 11, the support substrate 4 includes a base material 41, substrate wiring 42, and a plurality of through-wirings 43.

[0050] The substrate 41 is made of an insulating material. This insulating material is, for example, an amorphous glass such as SiO2. This insulating material may be a ceramic such as AlN instead of SiO2. As shown in Figures 1 to 3, the substrate 41 is rectangular in shape, for example, in a plan view. The substrate 41 has trench regions formed by trenching. The trench regions are formed on a part of the upper surface (the surface facing upward in the thickness direction z) of the substrate 41 and are recessed portions from the upper surface (thickness direction z) of the substrate 41. Substrate wiring 42 is formed in these trench regions.

[0051] The substrate wiring 42 is formed on the upper surface (the surface facing upward in the thickness direction z) of the base material 41. The constituent material of the substrate wiring 42 is, for example, Cu or a Cu alloy.

[0052] As shown in Figures 2, 3, 7 to 11, the board wiring 42 includes a plurality of first wiring sections 421 and a plurality of second wiring sections 422.

[0053] Each of the multiple first wiring sections 421 is electrically interposed between the first semiconductor element 1 and the first coil L1 of the insulating element 3. Each electrode 141 of the first semiconductor element 1 and each third pad 34 of the insulating element 3 are directly joined to each first wiring section 421. Each of the multiple first wiring sections 421 extends from a region overlapping the first semiconductor element 1 to a region overlapping the insulating element 3 in a plan view. In the examples shown in Figures 2 and 3, each of the multiple first wiring sections 421 is a strip extending in a first direction x in a plan view, and is arranged parallel (or approximately parallel) to a second direction y in a plan view. The shape and arrangement of each first wiring section 421 are not limited to the examples shown in Figures 2 and 3, and can be appropriately changed depending on the position of each electrode 141 of the first semiconductor element 1 and the position of each third pad 34 of the insulating element 3. Each first wiring section 421 is part of the first circuit described above.

[0054] Each of the multiple second wiring sections 422 is electrically interposed between the second semiconductor element 2 and the second coil L2 of the insulating element 3. Each electrode 241 of the second semiconductor element 2 and each fourth pad 35 of the insulating element 3 are directly joined to each second wiring section 422. Each of the multiple second wiring sections 422 extends from a region overlapping the second semiconductor element 2 to a region overlapping the insulating element 3 in a plan view. In the examples shown in Figures 2 and 3, each of the multiple second wiring sections 422 is a strip extending in a first direction x in a plan view, and is arranged parallel (or approximately parallel) to the second direction y in a plan view. The shape and arrangement of each second wiring section 422 are not limited to the examples shown in Figures 2 and 3, and can be appropriately changed depending on the position of each electrode 241 of the second semiconductor element 2 and the position of each fourth pad 35 of the insulating element 3. Each second wiring section 422 is part of the second circuit described above.

[0055] The support substrate 4 has a base material 41 and a portion of the substrate wiring 42 (a plurality of first wiring sections 421 and a plurality of second wiring sections 422) exposed on the mounting surface 40a. The surface of the base material 41 in the thickness direction z-upper and the surface of the substrate wiring 42 in the thickness direction z-upper are flush. For example, these surfaces become flush by mirror polishing applied to the mounting surface 40a. The mounting surface 40a is composed of the surface of the base material 41 in the thickness direction z-upper and the surface of the substrate wiring 42 in the thickness direction z-upper.

[0056] In semiconductor device A1, the first semiconductor element 1 and the support substrate 4 are directly joined to each of the multiple first pads 14 (each of the multiple electrodes 141) and each of the multiple first wiring portions 421, and the first insulating layer 13 and the base material 41 are directly joined. As a result, the first semiconductor element 1 is in close contact with the support substrate 4. The second semiconductor element 2 and the support substrate 4 are directly joined to each of the multiple second pads 24 (each of the multiple electrodes 241) and each of the multiple second wiring portions 422, and the second insulating layer 23 and the base material 41 are directly joined. As a result, the second semiconductor element 2 is in close contact with the support substrate 4. The insulating element 3 and the support substrate 4 are directly joined to each of the multiple third pads 34 and each of the multiple first wiring portions 421, each of the multiple fourth pads 35 and each of the multiple second wiring portions 422, and the third insulating layer 31 and the base material 41 are directly joined. As a result, the insulating element 3 is in close contact with the support substrate 4.

[0057] Each of the multiple through-wirings 43 penetrates the base material 41 in the thickness direction z. The constituent material of each of the multiple through-wirings 43 is, for example, Cu or a Cu alloy. The multiple through-wirings 43 include a plurality of first through-parts 431 and a plurality of second through-parts 432.

[0058] Each of the multiple first through-holes 431 is in contact with each electrode 142 and each first external terminal 51 of the first semiconductor element 1, thereby creating electrical conductivity between them. Each electrode 142 is directly bonded to the upper surface (the surface facing upward in the thickness direction z) of each first through-hole 431. As shown in Figure 3, in semiconductor device A1, the multiple first through-holes 431 overlap the first semiconductor element 1 in a plan view. Each first through-hole 431 is part of the first circuit described above.

[0059] Each of the multiple second through-holes 432 is in contact with each electrode 242 and each second external terminal 52 of the second semiconductor element 2, thereby creating electrical conductivity between them. Each electrode 242 is directly bonded to the upper surface (the surface facing upward in the thickness direction z) of each second through-hole 432. As shown in Figure 3, in semiconductor device A1, the multiple second through-holes 432 overlap the second semiconductor element 2 in a plan view. Each second through-hole 432 is part of the second circuit described above.

[0060] In semiconductor device A1, multiple through-wirings 43 are formed, for example, by the following method: Laser light is irradiated onto the substrate 41 to form through-holes (or grooves) in the thickness direction z of the substrate 41. Then, Cu or a Cu alloy is formed in the through-holes (or grooves) formed in the substrate 41 to form multiple through-wirings 43. If grooves are formed in the substrate 41, after forming Cu or a Cu alloy in the grooves of the substrate 41, the surface of the substrate 41 opposite to the surface where the grooves were formed is ground to form multiple through-wirings 43.

[0061] Each of the multiple first external terminals 51 is electrically connected to the first semiconductor element 1. The multiple first external terminals 51 serve as terminals when mounting the semiconductor device A1 onto a circuit board. As shown in Figures 4, 6, 7, and 11, the multiple first external terminals 51 are formed on the terminal surface 40b of the support substrate 4. As shown in Figure 3, each of the multiple first external terminals 51 overlaps each of the multiple first through-holes 431 in a plan view, and also overlaps the first semiconductor element 1 in a plan view. As shown in Figures 7 and 11, each of the multiple first external terminals 51 is in contact with the lower surface (the surface facing downward in the thickness direction z) of each of the multiple first through-holes 431. Each of the multiple first external terminals 51 is electrically connected to each of the multiple electrodes 142 via each of the multiple first through-holes 431. In the example shown in Figures 2 and 3, the multiple first external terminals 51 are arranged along the second direction y, corresponding to the arrangement of the multiple electrodes 142. The arrangement of the multiple first external terminals 51 is not limited to the illustrated example and can be appropriately changed depending on the positions of the multiple electrodes 142. Each first external terminal 51 is formed, for example, by electroless plating. Each first external terminal 51 is composed of, for example, a Ni (nickel) layer in contact with each first through portion 431, a Pd (palladium) layer covering the Ni layer, and an Au (gold) layer covering the Pd layer. The configuration of each first external terminal 51 is not limited to the example described above and may consist of stacked Ni and Au layers, or it may consist only of an Au layer. Alternatively, it may be a ball-shaped solder.

[0062] Each of the multiple second external terminals 52 is electrically connected to the second semiconductor element 2. The multiple second external terminals 52 serve as terminals when mounting the semiconductor device A1 to a circuit board. As shown in Figures 4, 5, 7, and 11, the multiple second external terminals 52 are formed on the terminal surface 40b of the support substrate 4. As shown in Figure 3, each of the multiple second external terminals 52 overlaps each of the multiple second through-holes 432 in a plan view. As shown in Figures 7 and 11, each of the multiple second external terminals 52 is in contact with the lower surface (the surface facing downward in the thickness direction z) of each of the multiple second through-holes 432. Each of the multiple second external terminals 52 is electrically connected to each of the multiple electrodes 242 via each of the multiple second through-holes 432. In the example shown in Figures 2 and 3, the multiple second external terminals 52 are arranged along the second direction y, corresponding to the arrangement of the multiple electrodes 242. The arrangement of the multiple second external terminals 52 is not limited to the illustrated example and can be appropriately changed depending on the positions of the multiple electrodes 242. Each second external terminal 52 is formed, for example, by electroless plating. Each second external terminal 52 is composed of, for example, a Ni layer in contact with each second through-hole 432, a Pd layer covering the Ni layer, and an Au layer covering the Pd layer. The configuration of each second external terminal 52 is not limited to the example described above and may consist of a stacked Ni layer and an Au layer, or it may consist only of an Au layer. Alternatively, it may be a ball-shaped solder.

[0063] The sealing resin 6 is formed above the support substrate 4 (on the mounting surface 40a) and covers the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3. The sealing resin 6 is in contact with the mounting surface 40a of the support substrate 4. As shown in Figure 1, the sealing resin 6 is, for example, rectangular in plan view.

[0064] The sealing resin 6 has a top surface 61, a pair of first side surfaces 63, and a pair of second side surfaces 64. The top surface 61 faces upward in the thickness direction z, as shown in Figures 4 to 11. The top surface 61 is flat (or nearly flat). The pair of first side surfaces 63 each connect to the top surface 61. The pair of first side surfaces 63 each are flat (or nearly flat). As shown in Figure 1, the pair of first side surfaces 63 are spaced apart in a first direction x and face opposite each other in the first direction x. In the examples in Figures 4, 7, and 11, the pair of first side surfaces 63 each are perpendicular to the top surface 61. The pair of second side surfaces 64 each connect to the top surface 61. The pair of second side surfaces 64 each are flat (or nearly flat). As shown in Figure 1, the pair of second side surfaces 64 are spaced apart in a second direction y and face opposite each other in the second direction y. In the examples shown in Figures 5 and 6, the pair of second sides 64 are each perpendicular to the top surface 61.

[0065] The operation and effects of semiconductor device A1 are as follows:

[0066] The semiconductor device A1 includes a support substrate 4 on which a first semiconductor element 1 and a second semiconductor element 2 are mounted. The support substrate 4 includes an insulating base material 41 and substrate wiring 42 formed on the base material 41. The substrate wiring 42 includes a first wiring section 421 and a second wiring section 422. The first wiring section 421 is electrically interposed between the first semiconductor element 1 and the first coil L1. The second wiring section 422 is electrically interposed between the second semiconductor element 2 and the second coil L2. With this configuration, the first circuit (e.g., the first wiring section 421) including the first semiconductor element 1 and the second circuit (e.g., the second wiring section 422) including the second semiconductor element 2 are insulated by the base material 41. Therefore, the dielectric breakdown voltage of the base material 41 affects the dielectric breakdown voltage between the first circuit and the second circuit, that is, the dielectric breakdown voltage of the semiconductor device A1, and does not depend on the distance between the first island and the second island, as in conventional semiconductor devices (Patent Document 1). This makes it possible to suppress a decrease in dielectric strength even when the semiconductor device A1 is miniaturized.

[0067] In semiconductor device A1, the first pad 14 is exposed on the first element main surface 10a, and the first element main surface 10a faces the mounting surface 40a. Each electrode 141 of the first pad 14 is bonded to each first wiring portion 421. With this configuration, since the first semiconductor element 1 is flip-chip bonded to the support substrate 4, there is no need for bonding wire mounting. Therefore, semiconductor device A1 is preferable for miniaturizing the device (especially the dimension in the thickness direction z).

[0068] In semiconductor device A1, the first semiconductor element 1 and the support substrate 4 are directly joined by the electrodes 141 of the first pad 14 and the first wiring portions 421 of the substrate wiring 42, while the first insulating layer 13 and the base material 41 are also directly joined. In semiconductor device A1, for example, the main surface 10a of the first element and the mounting surface 40a are mirror-finished, so that the first semiconductor element 1 and the support substrate 4 are in close contact with each other. With this configuration, semiconductor device A1 can join the first semiconductor element 1 to the support substrate 4 without using adhesive. Also, in semiconductor device A1, because the first semiconductor element 1 and the support substrate 4 are in close contact, the gap between the first semiconductor element 1 and the support substrate 4 is suppressed. Unlike semiconductor device A1, if the first semiconductor element 1 is joined to the support substrate 4 using, for example, a conductive bonding material, a gap equal to the thickness of the conductive bonding material may be formed between the first semiconductor element 1 and the support substrate 4. Foreign matter such as dust and dirt, as well as the sealing resin 6, can enter this gap. The occurrence of gaps, the inclusion of foreign matter, and the intervention of the sealing resin 6 are factors that reduce the dielectric strength and the bonding strength between the first semiconductor element 1 and the support substrate 4. On the other hand, in semiconductor device A1, the first semiconductor element 1 and the support substrate 4 are in close contact, which suppresses the occurrence of gaps, the inclusion of foreign matter, and the intervention of the sealing resin 6 between the first semiconductor element 1 and the support substrate 4. In other words, semiconductor device A1 can suppress the reduction in dielectric strength and the reduction in bonding strength between the first semiconductor element 1 and the support substrate 4.

[0069] In semiconductor device A1, the first insulating layer 13 and the substrate 41 are each made of glass (for example, SiO2). In other words, the first insulating layer 13 and the substrate 41 are made of the same material. With this configuration, the adhesion between the first insulating layer 13 and the substrate 41 can be increased compared to the case where the first insulating layer 13 and the substrate 41 are made of different materials. Therefore, semiconductor device A1 can suppress the peeling of the first semiconductor element 1 from the support substrate 4. The same applies to the relationship between some of the first pads 14 (each electrode 141) and each first wiring portion 421.

[0070] In semiconductor device A1, the second pad 24 is exposed on the main surface 20a of the second element, and the main surface 20a of the second element faces the mounting surface 40a. Each electrode 241 of the second pad 24 is bonded to each second wiring portion 422. With this configuration, since the second semiconductor element 2 is flip-chip bonded to the support substrate 4, there is no need for bonding wire mounting. Therefore, semiconductor device A1 is preferable for miniaturizing the device (especially the dimension in the thickness direction z).

[0071] In semiconductor device A1, the second semiconductor element 2 and the support substrate 4 are directly joined by each electrode 241 of the second pad 24 and each second wiring portion 422 of the substrate wiring 42, and the second insulating layer 23 and the base material 41 are also directly joined. In semiconductor device A1, for example, the main surface 20a of the second element and the mounting surface 40a are mirror-finished, so that the second semiconductor element 2 and the support substrate 4 are in close contact with each other. With this configuration, semiconductor device A1 can join the second semiconductor element 2 to the support substrate 4 without using adhesive. In addition, since the second semiconductor element 2 and the support substrate 4 are in close contact in semiconductor device A1, the gap between the second semiconductor element 2 and the support substrate 4 is suppressed. Therefore, semiconductor device A1 can suppress the occurrence of gaps, the inclusion of foreign matter, and the intervention of the sealing resin 6 between the second semiconductor element 2 and the support substrate 4, thereby suppressing a decrease in dielectric strength and a decrease in the bonding strength between the second semiconductor element 2 and the support substrate 4.

[0072] In semiconductor device A1, the second insulating layer 23 and the substrate 41 are each made of glass (for example, SiO2). In other words, the second insulating layer 23 and the substrate 41 are made of the same material. With this configuration, the adhesion between the second insulating layer 23 and the substrate 41 can be increased compared to the case where the second insulating layer 23 and the substrate 41 are made of different materials. Therefore, semiconductor device A1 can suppress the peeling of the second semiconductor element 2 from the support substrate 4. The same applies to the relationship between some of the second pads 24 (each electrode 241) and each second wiring portion 422.

[0073] In semiconductor device A1, the third pad 34 and the fourth pad 35 are exposed on the back surface 30b of the third element, and the back surface 30b of the third element faces the terminal surface 40b. The third pad 34 is bonded to the first wiring section 421, and the fourth pad 35 is bonded to the second wiring section 422. With this configuration, there is no need to use bonding wires for conductivity between the third pad 34 and the first wiring section 421, and between the fourth pad 35 and the second wiring section 422. Therefore, semiconductor device A1 is preferable for miniaturizing the device (especially the dimension in the thickness direction z).

[0074] In semiconductor device A1, the insulating element 3 and the support substrate 4 are directly joined at the third pad 34 and the first wiring portion 421, at the fourth pad 35 and the second wiring portion 422, and at the third insulating layer 31 and the base material 41. In semiconductor device A1, for example, the back surface 30b of the third element and the mounting surface 40a are mirror-finished, so that the insulating element 3 and the support substrate 4 are in close contact with each other. With this configuration, the insulating element 3 and the support substrate 4 can be joined without using adhesive. In addition, since the insulating element 3 and the support substrate 4 are in close contact in semiconductor device A1, the gap between the insulating element 3 and the support substrate 4 is suppressed. Therefore, semiconductor device A1 can suppress the occurrence of gaps between the insulating element 3 and the support substrate 4, the inclusion of foreign matter, and the intervention of the sealing resin 6, thereby suppressing a decrease in dielectric strength and a decrease in the bonding strength between the insulating element 3 and the support substrate 4.

[0075] In semiconductor device A1, the third insulating layer 31 and the substrate 41 are each made of glass (for example, SiO2). In other words, the third insulating layer 31 and the substrate 41 are made of the same material. With this configuration, the adhesion between the third insulating layer 31 and the substrate 41 can be increased compared to the case where the third insulating layer 31 and the substrate 41 are made of different materials. Therefore, semiconductor device A1 can suppress the delamination of the insulating element 3 from the support substrate 4. The same applies to the relationship between each third pad 34 and each first wiring portion 421, and the relationship between each fourth pad 35 and each second wiring portion 422.

[0076] In semiconductor device A1, the first coil L1 and the second coil L2 are located between the first semiconductor element 1 and the second semiconductor element 2 in a plan view. In other words, the first semiconductor element 1 and the second semiconductor element 2 are located on opposite sides of each other with the insulating element 3 in between in a plan view. With this configuration, an appropriate distance is ensured between the first wiring section 421 and the second wiring section 422. In other words, a distance is ensured between the first circuit including the first semiconductor element 1 and the second circuit including the second semiconductor element 2. Therefore, semiconductor device A1 is preferable for improving dielectric strength.

[0077] Figures 13 and 14 show a semiconductor device A2 according to a second embodiment. As shown in these figures, semiconductor device A2 differs from semiconductor device A1 mainly in the following ways. First, in semiconductor device A2, the substrate wiring 42 further includes a plurality of third wiring sections 423 and a plurality of fourth wiring sections 424. Second, in semiconductor device A2, a plurality of first external terminals 51 are each located outside the first semiconductor element 1 in a plan view. Third, in semiconductor device A2, a plurality of second external terminals 52 are each located outside the second semiconductor element 2 in a plan view.

[0078] Each of the multiple third wiring sections 423 is electrically interposed between the first semiconductor element 1 and each of the multiple first external terminals 51. Each electrode 142 of the first semiconductor element 1 is directly joined to each third wiring section 423. Each of the multiple third wiring sections 423 extends from a region overlapping the first semiconductor element 1 to a region overlapping each first external terminal 51 in a plan view. As described above, each first external terminal 51 is located outside the first semiconductor element 1 in a plan view. The shape and arrangement of each third wiring section 423 are not limited to the example shown in Figure 13 and can be appropriately changed depending on the position of each electrode 142 of the first semiconductor element 1 and the position of each first external terminal 51.

[0079] Each of the multiple fourth wiring sections 424 is electrically interposed between the second semiconductor element 2 and each of the multiple second external terminals 52. Each electrode 242 of the second semiconductor element 2 is directly joined to each fourth wiring section 424. Each of the multiple fourth wiring sections 424 extends from a region overlapping the second semiconductor element 2 to a region overlapping each second external terminal 52 in a plan view. As described above, each second external terminal 52 is located outside the second semiconductor element 2 in a plan view. The shape and arrangement of each fourth wiring section 424 are not limited to the example shown in Figure 13 and can be appropriately changed depending on the position of each electrode 242 and each second external terminal 52 of the second semiconductor element 2.

[0080] In semiconductor device A2, as in semiconductor device A1, the first circuit including the first semiconductor element 1 and the second circuit including the second semiconductor element 2 are insulated by the substrate 41. In other words, like semiconductor device A1, semiconductor device A2 can suppress a decrease in dielectric breakdown voltage even when miniaturized. Furthermore, semiconductor device A2 can achieve the effects obtained by having a configuration common to semiconductor device A1.

[0081] In semiconductor device A2, the substrate wiring 42 includes a plurality of third wiring sections 423, each of which is interposed between the first semiconductor element 1 and a plurality of first external terminals 51. With this configuration, by extending each third wiring section 423 to the outside of the first semiconductor element 1 in a plan view, each first external terminal 51 can be positioned outside the first semiconductor element 1 in a plan view. In other words, semiconductor device A2 offers increased flexibility in the arrangement of the plurality of first external terminals 51. Similarly, in semiconductor device A2, the substrate wiring 42 includes a plurality of fourth wiring sections 424. Each of which is interposed between the second semiconductor element 2 and a plurality of second external terminals 52. With this configuration, by extending each fourth wiring section 424 to the outside of the first semiconductor element 1 in a plan view, each second external terminal 52 can be positioned outside the first semiconductor element 1 in a plan view. In other words, the semiconductor device A2 offers increased flexibility in the arrangement of the multiple second external terminals 52.

[0082] Figures 15 and 16 show a semiconductor device A3 according to a third embodiment. As shown in these figures, semiconductor device A3 differs from semiconductor device A1 mainly in the following ways: Firstly, in semiconductor device A3, the orientation of the thickness direction z of the first semiconductor element 1 is reversed. Secondly, in semiconductor device A3, the orientation of the thickness direction z of the second semiconductor element 2 is reversed. Thirdly, semiconductor device A3 further comprises a plurality of connecting members 7.

[0083] In semiconductor device A3, the first semiconductor element 1 is positioned so that its back surface 10b faces the support substrate 4. As a result, multiple first pads 14 (multiple electrodes 141, 142) are exposed on the upper surface (the surface facing upward in the thickness direction z) of the first semiconductor element 1.

[0084] Similarly, in semiconductor device A3, the second semiconductor element 2 is positioned so that its back surface 20b faces the support substrate 4. As a result, multiple second pads 24 (multiple electrodes 241, 242) are exposed on the upper surface of the second semiconductor element 2.

[0085] In semiconductor device A3, the insulating element 3 has multiple third pads 34 exposed on the main surface 30a of the third element. Therefore, the insulating element 3 does not include multiple connection wires 36.

[0086] In semiconductor device A3, the multiple first external terminals 51 and the multiple first through-holes 431 (some through-wiring 43) are arranged outside the first semiconductor element 1 in a plan view, similar to semiconductor device A2. Furthermore, the multiple second external terminals 52 and the multiple second through-holes 432 (some through-wiring 43) are arranged outside the second semiconductor element 2 in a plan view, similar to semiconductor device A2.

[0087] Multiple connecting members 7 electrically connect two separated parts. The multiple connecting members 7 are, for example, bonding wires. Each component material of the multiple connecting members 7 includes Au, Cu, or Al. The multiple connecting members 7 include multiple first wires 71, multiple second wires 72, multiple third wires 73, and multiple fourth wires 74.

[0088] Each of the multiple first wires 71 is joined to each electrode 141 (some of the first pads 14) of the first semiconductor element 1 and each third pad 34 of the insulating element 3, thereby creating electrical conductivity between them. In semiconductor device A3, since each first wire 71 connects each electrode 141 and each third pad 34, the substrate wiring 42 does not include each first wiring section 421, as shown in Figures 15 and 16.

[0089] Each of the multiple second wires 72 is joined to each electrode 241 (some of the second pads 24) of the second semiconductor element 2 and to each second wiring portion 422 of the substrate wiring 42, thereby creating electrical conductivity between them. In semiconductor device A3, each second wiring portion 422 is joined to each fourth pad 35, similar to semiconductor device A1, but in a plan view, it does not extend to the second semiconductor element 2 and therefore the electrodes 241 are not joined. In semiconductor device A3, each second wire 72 creates electrical conductivity between each electrode 241 and each second wiring portion 422, so as shown in Figures 15 and 16, each second wiring portion 422 does not overlap with the second semiconductor element 2 in a plan view.

[0090] Each of the multiple third wires 73 is joined to each electrode 142 (some of the first pads 14) of the first semiconductor element 1 and to each first through-hole 431 of the multiple through-wirings 43, thereby creating electrical conductivity between them. In semiconductor device A3, since each third wire 73 connects each electrode 142 to each first through-hole 431, the substrate wiring 42 does not include each third wiring portion 423, as shown in Figures 15 and 16.

[0091] Each of the multiple fourth wires 74 is joined to each electrode 242 (some of the second pads 24) of the second semiconductor element 2 and to each second through-hole 432 of the multiple through-wirings 43, thereby creating electrical conductivity between them. In semiconductor device A3, since each fourth wire 74 connects each electrode 242 and each second through-hole 432, the substrate wiring 42 does not include each fourth wiring portion 424, as shown in Figures 15 and 16.

[0092] In semiconductor device A3, as with semiconductor devices A1 and A2, the first circuit including the first semiconductor element 1 and the second circuit including the second semiconductor element 2 are insulated by the substrate 41. In other words, semiconductor device A3, like semiconductor devices A1 and A2, can suppress a decrease in dielectric breakdown voltage even when miniaturized. Furthermore, semiconductor device A3 can achieve the effects obtained by the configuration common to semiconductor devices A1 and A2.

[0093] In semiconductor device A3, since each fourth pad 35 is located on the back surface 30b of the third element, the substrate wiring 42 includes each second wiring portion 422 in order to provide electrical conductivity between each second wire 72 and each fourth pad 35. In a configuration different from this, if each fourth pad 35 is exposed on the main surface 30a of the third element, each second wire 72 may be joined to each fourth pad 35 instead of each second wiring portion 422, as shown in Figures 17 and 18. In the example shown in Figures 17 and 18, each second wiring portion 422 is unnecessary, so the substrate wiring 42 does not include each second wiring portion 422. Also, each fourth pad 35 is electrically connected to the lower wiring layer 33 via each connecting wiring 36.

[0094] Figures 19 to 21 show a semiconductor device A4 according to the fourth embodiment. As shown in these figures, semiconductor device A4 differs from semiconductor device A1 mainly in the following respects. In semiconductor device A4, the second coil L2 is formed on the support substrate 4.

[0095] In semiconductor device A4, the substrate wiring 42 further comprises a fifth wiring section 425, as shown in Figures 19 to 21. The fifth wiring section 425 includes a second coil L2 and a lead wiring 426. The second coil L2 has a plurality of winding sections L21, similar to each semiconductor device A1 to A3. The lead wiring 426 connects, for example, each outer end L23 to one of the plurality of second wiring sections 422, as shown in Figure 21. In this case, the second wiring section 422 and the lead wiring 426 may be formed integrally.

[0096] In semiconductor device A4, the insulating element 3 further includes a sixth pad 37, as shown in Figure 20. The sixth pad 37 is joined to each of the multiple inner ends L22 of the second coil L2. Each sixth pad 37 is electrically connected to each fourth pad 35 by lead wiring 331 of the lower wiring layer 33.

[0097] In semiconductor device A4, as with semiconductor devices A1 to A3, the first circuit including the first semiconductor element 1 and the second circuit including the second semiconductor element 2 are insulated by the substrate 41. In other words, semiconductor device A4, like semiconductor devices A1 to A3, can suppress a decrease in dielectric breakdown voltage even when miniaturized. Furthermore, semiconductor device A4 can achieve the effects obtained by the configuration common to semiconductor devices A1 to A3.

[0098] In the semiconductor device A4 shown in Figures 19 to 21, each inner end L22 of the second coil L2 is electrically connected to one of the multiple second wiring sections 422 by the lower wiring layer 33 (each lead wire 331) of the insulating element 3. However, as shown in Figure 22, instead of this configuration, each inner end L22 may be connected to one of the multiple second wiring sections 422 by a fifth wiring section 425 (lead wire 426).

[0099] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, the support substrate 4 may further include a heat dissipation section 44. Figure 23 shows an example in which a heat dissipation section 44 is added to the semiconductor device A1.

[0100] As shown in Figure 23, the heat dissipation portion 44 penetrates the substrate 41 in the thickness direction z. The heat dissipation portion 44 is formed, for example, below the first semiconductor element 1 in the thickness direction z. That is, the heat dissipation portion 44 is formed in a region that overlaps with the first semiconductor element 1 in a plan view, for example. The region in which the heat dissipation portion 44 is formed is not particularly limited. However, the heat dissipation portion 44 is formed so as to avoid at least each first wiring portion 421 (and each third wiring portion 423 if there are any). The heat dissipation portion 44 is made of Cu or a Cu alloy, for example, similar to the through-wiring 43.

[0101] The semiconductor device shown in Figure 23 can release heat from the first semiconductor element 1 through the heat dissipation section 44, thereby improving the heat dissipation efficiency from the first semiconductor element 1.

[0102] In the example shown in Figure 23, the heat dissipation section 44 is positioned in a region that overlaps with the first semiconductor element 1 in a plan view. However, unlike this configuration, the heat dissipation section 44 may be formed below the second semiconductor element 2 in the thickness direction z. In other words, the heat dissipation section 44 may be formed in a region that overlaps with the second semiconductor element 2 in a plan view. In this case, the heat dissipation section 44 can release heat from the second semiconductor element 2, thereby improving the heat dissipation performance from the second semiconductor element 2. However, in the example where the power supply voltage applied to the first semiconductor element 1 is higher than the power supply voltage applied to the second semiconductor element 2, the amount of heat generated by the first semiconductor element 1 will be higher than the amount of heat generated by the second semiconductor element 2, so it is preferable to position the heat dissipation section 44 below the first semiconductor element 1. Alternatively, a plurality of heat dissipation sections 44 may be provided on the support substrate 4, and the plurality of heat dissipation sections 44 may be formed below the first semiconductor element 1 in the thickness direction z and below the second semiconductor element 2 in the thickness direction z, respectively.

[0103] Each of the semiconductor devices A1 to A4 according to the first to fourth embodiments may further include a resin material 67. Figure 24 shows a modified example in which the resin material 67 is added to the semiconductor device A1.

[0104] As shown in Figure 24, the resin material 67 is formed on the terminal surface 40b of the support substrate 4. The resin material 67 is positioned, for example, between a plurality of first external terminals 51 and a plurality of second external terminals 52 in a first direction x. The resin material 67 is made of an insulating resin material, such as epoxy resin, polyimide resin, and phenolic resin.

[0105] In the semiconductor device shown in Figure 24, the resin material 67 protects the terminal surface 40b of the substrate 41. This prevents damage to the substrate 41. Furthermore, the resin material 67 acts as a reinforcing material for the substrate 41, preventing cracking of the substrate 41.

[0106] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, a passivation film 38 covering a portion of the insulating element 3 may be further provided. Figure 25 shows an example in which a passivation film 38 is added to the insulating element 3 in semiconductor device A1.

[0107] As shown in Figure 25, the passivation film 38 covers, for example, the upper surface (third element main surface 30a) of the insulating element 3. If multiple third pads 34 or multiple fourth pads 35 are provided on the third element main surface 30a (for example, the configuration shown in Figure 16 or Figure 18), the passivation film 38 is formed to expose each third pad 34 and each fourth pad 35. Unlike the configuration shown in Figure 25, the passivation film 38 may also cover the sides of the insulating element 3 (the surface facing the first direction x and the surface facing the second direction y) along with the third element main surface 30a. The passivation film 38 is made of, for example, polyimide.

[0108] The semiconductor device shown in Figure 25 can protect the first coil L1, which is exposed on the main surface 30a of the third element, by the passivation film 38.

[0109] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, the plurality of first external terminals 51 and the plurality of second external terminals 52 may be formed not only on the back surface of the semiconductor device A1 but also on the side surfaces. Figure 26 shows an example in which each of the plurality of first external terminals 51 and the plurality of second external terminals 52 in the semiconductor device A1 is also formed on the side surfaces (each side surface facing the first direction x) of the substrate 41.

[0110] In the semiconductor device shown in Figure 26, each through-wiring 43 is formed up to the side surface of the substrate 41 and is exposed on that side surface. As a result, each through-wiring 43 has either a first external terminal 51 or a second external terminal 52 formed on the surface exposed from the side surface of the substrate 41. Furthermore, in this modified example, as shown in Figure 27, each through-wiring 43 may have a recessed corner on the outward side in the first direction x and downward side in the thickness direction z. Such a semiconductor device as shown in Figure 27 makes it easy to inspect the mounting state when the semiconductor device is mounted on a circuit board.

[0111] In the first to fourth embodiments, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are shown to be directly bonded to the support substrate 4, but the invention is not limited to this, and they may be bonded using conductive bonding materials such as solder, metal paste, or sintered metal.

[0112] In the first to fourth embodiments, an example was shown in which the first semiconductor element 1 is a driving element and the second semiconductor element 2 is a control element. However, conversely, the first semiconductor element 1 may be a control element and the second semiconductor element 2 may be a driving element.

[0113] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, the first coil L1 and the second coil L2 may have configurations as shown in Figures 28 to 30, for example. Figures 28 to 30 show modified configurations of the first coil L1 and the second coil L2. Figures 28 to 30 mainly show the configuration of the modified first coil L1, but the same applies to the second coil L2.

[0114] In each semiconductor device A1 to A4, the first coil L1 had its two winding sections L11's outer ends L13 electrically connected by lead wires 321. In contrast, in the examples shown in Figures 28 and 29, the first coil L1 has its two winding sections L11's inner ends L12 electrically connected by lead wires 321. Note that although the wiring shape of each lead wire 321 differs between the example in Figure 28 and the example in Figure 29, the electrical connection relationship is the same. Furthermore, in the example shown in Figure 30, the first coil L1 has four winding sections L11 that are each electrically independent, and neither the inner ends L12 nor the outer ends L13 of any two winding sections L11 are electrically connected by lead wires 321. Similarly, in each semiconductor device A1 to A4, the second coil L2 was electrically connected at the outer ends L23 of the two winding sections L21 by lead wires 331. However, in the examples shown in Figures 28 and 29, the second coil L2 is electrically connected at the inner ends L22 of the two winding sections L21 by lead wires 331. Note that although the wiring shape of each lead wire 331 differs between the example shown in Figure 28 and the example shown in Figure 29, the electrical connection relationship is the same. Furthermore, in the example shown in Figure 30, the second coil L2 has four winding sections L21 that are each electrically independent, and neither the inner ends L22 nor the outer ends L23 of any two winding sections L21 are electrically connected by lead wires 331.

[0115] The semiconductor devices relating to this disclosure are not limited to the embodiments described above. The specific configurations of the parts of the semiconductor devices relating to this disclosure can be modified in various ways. For example, this disclosure includes the embodiments described in the following appendix. Note 1. First semiconductor device, The second semiconductor element, An insulating element including the first coil, A second coil is magnetically coupled to the first coil, A support substrate on which the first semiconductor element and the second semiconductor element are mounted, It is equipped with, The support substrate includes an insulating base material and substrate wiring formed on the base material. The substrate wiring includes a first wiring section electrically interposed between the first semiconductor element and the first coil, and a second wiring section electrically interposed between the second semiconductor element and the second coil. The second coil is positioned between the first coil and the substrate. The insulating element is supported on the support substrate, and the semiconductor device is a semiconductor device. Note 2. The first semiconductor element is a driver element for driving a switching element, The second semiconductor element is a control element for controlling the driving of the switching element, The semiconductor device described in Appendix 1, wherein the driving element requires a higher voltage than the control element. Note 3. The support substrate has a mounting surface on which the first semiconductor element, the second semiconductor element, and the insulating element are mounted. The mounting surface faces one direction in the thickness direction of the support substrate. The semiconductor device according to Appendix 1 or Appendix 2, wherein a portion of the substrate and the substrate wiring are exposed on the mounting surface. Note 4. The semiconductor device described in Appendix 3, wherein the substrate is made of glass. Note 5. The first semiconductor element has a first element main surface and a first element back surface facing opposite directions in the thickness direction, and includes a first substrate, a first wiring layer, a first insulating layer, and a first pad. The first substrate has a first functional surface on which a first functional circuit is formed, The first wiring layer is conductive to the first functional circuit and is formed on the first functional surface. The first insulating layer covers the first wiring layer and is formed on the first functional surface. The first pad is electrically connected to the first wiring layer, The semiconductor device according to Appendix 3 or Appendix 4, wherein the first insulating layer and the first pad are exposed on the main surface of the first element. Note 6. The main surface of the first element faces the mounting surface in the thickness direction, The semiconductor device according to Appendix 5, wherein the first semiconductor element and the support substrate are directly joined to the first pad and the first wiring portion, and the first insulating layer and the substrate. Note 7. The semiconductor device according to Appendix 5 or Appendix 6, wherein the first insulating layer is made of glass. Note 8. The second semiconductor element has a second element main surface and a second element back surface facing opposite directions in the thickness direction, and includes a second substrate, a second wiring layer, a second insulating layer, and a second pad. The second substrate has a second functional surface on which a second functional circuit is formed, The second wiring layer is conductive to the second functional circuit and is formed on the second functional surface. The second insulating layer covers the second wiring layer and is formed on the second functional surface. The second pad is electrically connected to the second wiring layer, The semiconductor device according to any one of the appendices 3 to 7, wherein the second insulating layer and the second pad are exposed on the main surface of the second element. Note 9. The main surface of the second element faces the mounting surface in the thickness direction, The semiconductor device according to Appendix 8, wherein the second semiconductor element and the support substrate are directly joined to the second pad and the second wiring portion, and the second insulating layer and the substrate. Note 10. The semiconductor device according to Appendix 8 or Appendix 9, wherein the second insulating layer is made of glass. Note 11. The insulating element includes the second coil and the third insulating layer. The semiconductor device according to any one of appendices 3 to 10, wherein at least a portion of the third insulating layer is interposed between the first coil and the second coil in the thickness direction. Note 12. The insulating element has a third element main surface and a third element back surface facing opposite directions in the thickness direction, The back surface of the third element faces the mounting surface in the thickness direction, The first coil is arranged on the main surface of the third element, The second coil is located on the back surface of the third element, and is the semiconductor device described in Appendix 11. Note 13. The insulating element includes a third pad connected to the first coil and a fourth pad connected to the second coil. The third pad, the fourth pad, and the third insulating layer are exposed on the back surface of the third element. The semiconductor device according to Appendix 12, wherein the insulating element and the support substrate are directly joined, the third pad and the first wiring portion are directly joined, the fourth pad and the second wiring portion are directly joined, and the third insulating layer and the substrate are directly joined. Note 14. The semiconductor device according to any one of appendices 11 to 13, wherein the third insulating layer is made of glass. Note 15. The semiconductor device according to any one of Appendix 3 to Appendix 14, wherein the support substrate is arranged in a region that overlaps with the first semiconductor element when viewed in the thickness direction, and includes a heat dissipation portion that penetrates the substrate in the thickness direction. Note 16. The device further comprises a first external terminal that conducts to the first semiconductor element and a second external terminal that conducts to the second semiconductor element. The semiconductor device according to any one of Appendix 3 to Appendix 15, wherein the support substrate faces away from the mounting surface in the thickness direction and has a terminal surface on which the first external terminal and the second external terminal are arranged. Note 17. The substrate wiring includes a third wiring section electrically interposed between the first semiconductor element and the first external terminal, and a fourth wiring section electrically interposed between the second semiconductor element and the second external terminal. The first external terminal is located outside the first semiconductor element when viewed in the thickness direction. The semiconductor device described in Appendix 16, wherein the second external terminal is located outside the second semiconductor element when viewed in the thickness direction. Note 18. The semiconductor device according to Appendix 17, further comprising an insulating resin material formed on the terminal surface and located between the first external terminal and the second external terminal when viewed in the thickness direction. Note 19. The semiconductor device according to any one of the appendices 3 to 18, wherein the first coil and the second coil are located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction. Note 20. Each of the first coil and the second coil has two winding portions wound on a plane perpendicular to the thickness direction, The semiconductor device according to any one of the appendices 3 to 19, wherein in each of the first coil and the second coil, the two winding portions each have a current input terminal and a current output terminal, and the current input terminals are connected to each other or the current output terminals are connected to each other. [Explanation of symbols]

[0116] A1~A4: Semiconductor device L1: First coil L11: Winding section L12: Inner end L13: Outer end L2: Second coil L21: Winding part L22: Inner end L23: Outer end 1: First semiconductor element 10a: Main surface of the first element 10b: Back side of the first component 11: First circuit board 11a: 1st functional surface 12: 1st wiring layer 13: First insulating layer 14: First pad 141,142: Electrodes 2: Second semiconductor element 20a: Main surface of the second element 20b: Second related back side 21: Second substrate 21a: 2nd functional surface 22: 2nd wiring layer 23: Second insulating layer 24: Second pad 241, 242: Electrodes 3: Insulating element 30a: Main surface of third element 30b: Back surface of third element 31: Third insulating layer 311: Intermediate section 312: Upper covering section 313: Lower covering layer 32: Upper wiring layer 321: Outlet wiring 33: Lower wiring layer 331: Outlet wiring 34: Third pad 35: Pad 4 36: Connection wiring 37: Pad 6 38: Passivation film 4: Support substrate 40a: Mounting surface 40b: Terminal surface 41: Base material 42: Board wiring 421: First wiring section 422: Second wiring section 423: Third wiring section 424: 4th wiring section 425: 5th wiring section 426: Output wiring 43: Through wiring 431: First through section 432: Second through section 44: Heat dissipation section 51: First external terminal 52: Second external terminal 6: Sealing resin 61: Top surface 63: First side surface 64: Second side 67: Resin material 7: Connecting member 71: First wire 72: Second wire 73: Third wire 74: Fourth wire

Claims

1. First semiconductor device, The second semiconductor element, An insulating element including the first coil, A second coil is magnetically coupled to the first coil, A support substrate on which the first semiconductor element and the second semiconductor element are mounted, It is equipped with, The support substrate includes an insulating base material and substrate wiring formed on the base material. The substrate wiring includes a first wiring portion electrically interposed between the first semiconductor element and the first coil, and a second wiring portion electrically interposed between the second semiconductor element and the second coil. The second coil is positioned between the first coil and the substrate. The insulating element is supported on the support substrate, and the semiconductor device is a semiconductor device.

2. The first semiconductor element is a driving element for driving a switching element, The second semiconductor element is a control element for controlling the driving of the switching element, The semiconductor device according to claim 1, wherein the driving element requires a higher voltage than the control element.

3. The support substrate has a mounting surface on which the first semiconductor element, the second semiconductor element, and the insulating element are mounted. The mounting surface faces one direction in the thickness direction of the support substrate. The semiconductor device according to claim 1, wherein a portion of the substrate and the substrate wiring are exposed on the mounting surface.

4. The semiconductor device according to claim 3, wherein the substrate is made of glass.

5. The first semiconductor element has a first element main surface and a first element back surface facing opposite directions in the thickness direction, and includes a first substrate, a first wiring layer, a first insulating layer, and a first pad. The first substrate has a first functional surface on which a first functional circuit is formed, The first wiring layer is conductive to the first functional circuit and is formed on the first functional surface. The first insulating layer covers the first wiring layer and is formed on the first functional surface. The first pad is electrically connected to the first wiring layer, The semiconductor device according to claim 3, wherein the first insulating layer and the first pad are exposed on the main surface of the first element.

6. The main surface of the first element faces the mounting surface in the thickness direction, The semiconductor device according to claim 5, wherein the first semiconductor element and the support substrate are directly joined to the first pad and the first wiring portion, and the first insulating layer and the substrate are directly joined.

7. The semiconductor device according to claim 5, wherein the first insulating layer is made of glass.

8. The second semiconductor element has a second element main surface and a second element back surface facing opposite directions in the thickness direction, and includes a second substrate, a second wiring layer, a second insulating layer, and a second pad. The second substrate has a second functional surface on which a second functional circuit is formed, The second wiring layer is conductive to the second functional circuit and is formed on the second functional surface. The second insulating layer covers the second wiring layer and is formed on the second functional surface. The second pad is electrically connected to the second wiring layer, The semiconductor device according to any one of claims 3 to 7, wherein the second insulating layer and the second pad are exposed on the main surface of the second element.

9. The main surface of the second element faces the mounting surface in the thickness direction, The semiconductor device according to claim 8, wherein the second semiconductor element and the support substrate are directly joined to the second pad and the second wiring portion, and the second insulating layer and the substrate.

10. The semiconductor device according to claim 8, wherein the second insulating layer is made of glass.

11. The insulating element includes the second coil and the third insulating layer. The semiconductor device according to any one of claims 3 to 7, wherein at least a portion of the third insulating layer is interposed between the first coil and the second coil in the thickness direction.

12. The insulating element has a third element main surface and a third element back surface facing opposite directions in the thickness direction, The back surface of the third element faces the mounting surface in the thickness direction, The first coil is arranged on the main surface of the third element, The semiconductor device according to claim 11, wherein the second coil is arranged on the back surface of the third element.

13. The insulating element includes a third pad connected to the first coil and a fourth pad connected to the second coil. The third pad, the fourth pad, and the third insulating layer are exposed on the back surface of the third element. The semiconductor device according to claim 12, wherein the insulating element and the support substrate are directly joined, the third pad and the first wiring portion are directly joined, the fourth pad and the second wiring portion are directly joined, and the third insulating layer and the substrate are directly joined.

14. The semiconductor device according to claim 11, wherein the third insulating layer is made of glass.

15. The semiconductor device according to any one of claims 3 to 7, wherein the support substrate is arranged in a region that overlaps with the first semiconductor element when viewed in the thickness direction, and includes a heat dissipation portion that penetrates the substrate in the thickness direction.

16. The device further comprises a first external terminal that conducts to the first semiconductor element and a second external terminal that conducts to the second semiconductor element. The semiconductor device according to any one of claims 3 to 7, wherein the support substrate faces away from the mounting surface in the thickness direction and has a terminal surface on which the first external terminal and the second external terminal are arranged.

17. The substrate wiring includes a third wiring section electrically interposed between the first semiconductor element and the first external terminal, and a fourth wiring section electrically interposed between the second semiconductor element and the second external terminal. The first external terminal is located outside the first semiconductor element when viewed in the thickness direction. The semiconductor device according to claim 16, wherein the second external terminal is arranged outside the second semiconductor element when viewed in the thickness direction.

18. The semiconductor device according to claim 17, further comprising an insulating resin material formed on the terminal surface and located between the first external terminal and the second external terminal when viewed in the thickness direction.

19. The semiconductor device according to any one of claims 3 to 7, wherein the first coil and the second coil are located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction.

20. Each of the first coil and the second coil has two winding portions wound on a plane perpendicular to the thickness direction, The semiconductor device according to any one of claims 3 to 7, wherein in each of the first coil and the second coil, the two winding portions each have a current input terminal and a current output terminal, and the current input terminals are connected to each other or the current output terminals are connected to each other.

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