Memory device

Abstract

In the present invention, an upper bit-line (BL_A) extends in a Y-direction in an upper memory array (1A) and a Y-decoder (3), and a lower bit-line (BL_B) extends in the Y-direction in a lower memory array (1B) and the Y-decoder. The Y-decoder has: an upper Y-line selection switch (YS_A) connected to the upper bit-line; and a lower Y-line selection switch (YS_B) connected to the lower bit-line and disposed on the other side in the Y-direction with respect to the upper Y-line selection switch. A switch circuit (SWC) is configured to be able to switch between conduction between a sense amplifier (SA) and the upper Y-line selection switch and conduction between the sense amplifier and the lower Y-line selection switch.

Description

Technical Field

[0001] The present disclosure relates to a memory device.

Background Art

[0002] Conventionally, a memory device having memory cells is known. The memory cells include memory transistors. The memory transistor has, for example, a control gate and a floating gate, and by applying a high voltage to the control gate, electrons are injected into and extracted from the floating gate to perform erasure (erase) and writing (program) (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Recently, memory devices have been miniaturized and increased in capacity. A bit line is connected to the memory cell as described above. With the increase in the capacity of the memory device, the number of memory cells connected to the bit line increases, and the leakage current flowing through the memory cell at high temperature increases. In addition, with the increase in the above capacity, the wiring length of the bit line becomes longer, and the parasitic capacitance of the bit line increases. Such an increase in leakage current and parasitic capacitance affects the data read characteristics when reading data from the memory cell. In addition, due to the miniaturization of the memory device, the wiring space becomes a problem.

[0005] In view of the above situation, an object of the present disclosure is to provide a memory device capable of improving data read characteristics while realizing miniaturization and increased capacity.

Means for Solving the Problems

[0006] For example, the memory device relating to this disclosure is An upper memory array configured such that memory cells are arranged in a matrix in orthogonal X and Y directions, A lower memory array is configured such that memory cells are arranged in a matrix in the X and Y directions, and is positioned on the other side in the Y direction from the upper memory array. A Y decoder is configured to be sandwiched between the upper memory array and the lower memory array in the Y direction in a plan view, SenseAmp and Switch circuit and Equipped with, The upper bit line connected to the memory cell of the upper memory array extends in the Y direction between the upper memory array and the Y decoder. The lower bit line connected to the memory cell of the lower memory array extends in the Y direction between the lower memory array and the Y decoder. The aforementioned Y decoder is An upper Y-line selection switch connected to the upper bit line, A lower Y-line selection switch is connected to the lower bit line and is located on the other side in the Y direction from the upper Y-line selection switch, It has, The switch circuit is configured to allow switching between conduction between the sense amplifier and the upper Y-line selection switch, and conduction between the sense amplifier and the lower Y-line selection switch. [Effects of the Invention]

[0007] The memory device described herein makes it possible to improve data read characteristics while achieving miniaturization and increased capacity. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic layout diagram of the memory device before improvement and the memory device according to the present disclosure after improvement. [Figure 2A] FIG. 2A is a circuit diagram showing a partial configuration of a memory device according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a diagram showing the circuit configuration of a column latch unit. [Figure 3] FIG. 3 is a diagram showing the configuration related to signals input to the gates of NMOS transistors NM11 and NM12. [Figure 4] FIG. 4 is a timing chart schematically showing the waveforms of respective signals during data writing. [Figure 5] FIG. 5 is a diagram showing a modification example of the configuration of FIG. 3. [Figure 6] FIG. 6 is a partially enlarged view of a memory device before improvement. [Figure 7] FIG. 7 is a partially enlarged view of a memory device after improvement (embodiment of the present disclosure). [Figure 8] FIG. 8 is a schematic layout diagram showing the configuration of a conventional memory device. [Figure 9] FIG. 9 is a diagram showing a partial configuration in a memory array. [Figure 10] FIG. 10 is a diagram showing the configuration related to data read in a memory device according to a first comparative example. [Figure 11] FIG. 11 is a diagram showing the configuration related to data read in a memory device according to a second comparative example. [Figure 12] FIG. 12 is a diagram showing the configuration related to data read in a memory device according to a third comparative example. [Figure 13] FIG. 13 is a diagram showing a configuration example of a sense amplifier. [Figure 14] FIG. 14 is a timing chart showing an operation example of a sense amplifier.

MODE FOR CARRYING OUT THE INVENTION

[0009] Exemplary embodiments of the present disclosure will be described below with reference to the drawings.

[0010] <1. Problems of Memory Device> Here, before describing the embodiments of the present disclosure, problems in the memory device will be described.

[0011] FIG. 8 is a schematic layout diagram showing the configuration of a conventional memory device. Note that FIG. 8 shows orthogonal X and Y directions. FIG. 8 is a plan view seen in a direction perpendicular to the X and Y directions. The memory device shown in FIG. 8 includes a memory array 100, an X decoder 200, a Y decoder 300, and a sense amplifier region 400.

[0012] The memory array 100 is composed of memory cells (not shown) arranged in a matrix in the X and Y directions. The memory cells can store 1-bit data. The memory array 100 is a non-volatile memory and is configured as an EEPROM as an example. The X decoder 200 and the Y decoder 300 are arranged around the memory array 100.

[0013] Word lines (not shown), which are address selection lines drawn from the X decoder 200 and extending in the X direction, cross the memory array 100 in the X direction. Bit lines (not shown), which are address selection lines drawn from the Y decoder 300 and extending in the Y direction, cross the memory array 100 in the Y direction.

[0014] A plurality of sense amplifiers (not shown) are arranged in the sense amplifier region 400. In the memory array 100, cell units are formed from memory cells of a predetermined number of bits as units for reading (data read) and writing (data write). Note that the predetermined number of bits is, for example, 38 bits. In the sense amplifier region 400, the number of sense amplifiers corresponding to the predetermined number of bits (for example, 38) is arranged.

[0015] The X decoder 200 decodes the address signal in the X direction and selects the word line. The Y decoder 300 decodes the address signal in the Y direction and selects the bit line. During data reading, data is read from the memory cells corresponding to the selected word line and bit line using a sense amplifier. During data writing, writing (write operation) is performed by applying a high voltage to the memory cells corresponding to the selected word line and bit line. The application of the high voltage is performed by a charge pump (not shown).

[0016] Figure 9 shows a partial configuration of the memory array 100. As shown in Figure 9, a memory cell MC has a selection transistor ST and a memory transistor MT. The memory transistor MT has a control gate and a floating gate. The first end of the selection transistor ST is connected to a bit line BL. The second end of the selection transistor ST is connected to the first end of the memory transistor MT. A predetermined number (e.g., 512) memory cells MC are connected to one bit line BL. One word line WL is connected to each control end (read gate) of the selection transistors ST arranged in the X direction.

[0017] In the memory array 100, selection lines SL extend in the Y direction and traverse the array. Each selection line SL is connected to the first terminal of each selection switch SW, which are arranged in the Y direction. The second terminal of each selection switch SW is connected to the control gates of each memory transistor MT, which are arranged in the X direction in a number corresponding to the predetermined number of bits. The control terminals of the selection switches SW are connected to the word line WL.

[0018] The memory cell MC can perform erase and write operations. During the erase operation, a high voltage (e.g., 17V) is applied to the selected word line WL, which turns on the corresponding selection transistor ST. The selection switch SW corresponding to the selected word line WL is also turned on, and a high voltage (e.g., 17V) is applied to the control gate of the corresponding memory transistor MT via the selection line SL. Additionally, 0V is applied to the first end of the corresponding memory transistor MT via the selected bit line BL. As a result, electrons are injected into the floating gate of the memory transistor MT, and the data "1" is written.

[0019] On the other hand, during the write process, a high voltage (e.g., 17V) is applied to the selected word line WL, which turns on the corresponding selection transistor ST. The selection switch SW corresponding to the selected word line WL is also turned on, and 0V is applied to the control gate of the corresponding memory transistor MT via the selection line SL. Furthermore, a high voltage (e.g., 14V) is applied to the first end of the corresponding memory transistor MT via the selected bit line BL. This extracts electrons from the floating gate of the memory transistor MT, resulting in the data "0" being written. A charge pump CP, shown in Figure 9, is used to apply the high voltage to the memory transistor MT via the bit line BL.

[0020] Furthermore, during data reading, the power supply voltage (Vcc) is applied to the selected word line WL, which turns on the corresponding selection transistor ST. The selection switch SW corresponding to the selected word line WL is also turned on, and a read voltage (e.g., 1.4V) is applied to the control gate of the corresponding memory transistor MT via the selection line SL. Then, the sense amplifier SA reads the data from the memory cell MC via the selected bit line BL. The sense amplifier SA detects that "1" has been written to the memory transistor MT when no current flows through the memory cell MC, and detects that "0" has been written to the memory transistor MT when current flows through the memory cell MC.

[0021] However, as these conventional memory devices become smaller and larger in capacity, the following problems arise.

[0022] Three challenges arise during data reading. First, there is the influence of parasitic capacitance Cbb formed between adjacent bit lines BL. When reading data with the sense amplifier SA, pre-charging is performed to charge the parasitic capacitance (Csub, described later) of the bit line BL. When reading data from a memory cell MC to which data "0" has been written, current flows to the memory cell MC, so charge is drawn from the parasitic capacitance of the bit line BL, and the voltage of the bit line BL drops from the voltage due to pre-charging. The sense amplifier SA detects this voltage drop. However, if a memory cell MC connected to an adjacent bit line BL has "1" written to it, current should not flow to the memory cell MC, so the voltage of the bit line BL should not drop from the voltage due to pre-charging, but there is a risk that the voltage will drop due to the influence of parasitic capacitance Cbb. Therefore, there is a risk that the sense amplifier SA will mistakenly detect that data "0" has been written when it should correctly detect that data "1" has been written (data corruption from "1" to "0").

[0023] The second challenge is the effect of leakage current flowing through memory cells MC at high temperatures. During data reading, 0V is applied to the unselected word line WL, and the corresponding selection transistor ST is turned off. At this time, the corresponding selection switch SW is also turned off, and the control gate of the corresponding memory transistor MT is open. At high temperatures, a leakage current IL may flow through the memory cell MC corresponding to such an unselected word line WL. As the capacity increases, the number of memory cells MC connected to the bit line BL increases, which may lead to an increase in leakage current. If the above-mentioned increased leakage current flows when the data "1" is written to the memory cell MC corresponding to the selected word line WL, there is a risk that it may be mistakenly detected as having written data "0".

[0024] The third issue is the effect of parasitic capacitance Csub associated with the bit line BL and the substrate. As the capacity increases, the wiring length of the bit line BL also increases, which increases the capacitance value of the parasitic capacitance Csub. In this case, when reading from the memory cell MC on which data "0" has been written using the sense amplifier SA, the rate at which the voltage of the bit line BL decreases decreases due to the effect of the parasitic capacitance Csub. Consequently, there is a risk that the sense speed of the sense amplifier SA will decrease.

[0025] Furthermore, the following issues arise during data writing: As the capacity increases, parasitic capacitance Csub and leakage current also increase, which may prevent the charge pump CP from performing the desired boost operation at low power supply voltages.

[0026] <2. First Comparative Example> Embodiments relating to comparative examples that solve the above-mentioned problems are described below. Figure 10 is a diagram showing the configuration of data reading in a memory device relating to the first comparative example. The first comparative example is implemented to solve the first problem (interference between adjacent bit lines) mentioned above.

[0027] To describe the configuration shown in Figure 10, the sense amplifier SA1 is connected to the first end of the Y-line selection switch YS1_U via the read data line DL_RD1. The second end of the Y-line selection switch YS1_U is connected to one end of the bit line BL1_U. The other end of the bit line BL1_U is connected to the memory cell MC1_U.

[0028] Furthermore, the sense amplifier SA2 is connected to the first end of the Y-line selection switch YS2_U via the read data line DL_RD2. The second end of the Y-line selection switch YS2_U is connected to one end of the bit line BL2_U. The other end of the bit line BL2_U is connected to the memory cell MC2_U.

[0029] Memory cells MC1_U and MC2_U are upper memory cells. The Y-line selection switches YS1_U and YS2_U are switched on / off by the upper Y-line selection signal YDEC_U. When the Y-line selection switches YS1_U and YS2_U are turned on, the upper bit lines BL1_U and BL2_U are selected.

[0030] The first terminals of the discharge switches DS1_U and DS2_U are connected to the bit lines BL1_U and BL2_U. The second terminals of the discharge switches DS1_U and DS2_U are connected to the terminals to which the ground potential is applied. The upper discharge signal BLDIS_U switches the discharge switches DS1_U and DS2_U on and off. When the discharge switches DS1_U and DS2_U are turned on, the bit lines BL1_U and BL2_U are discharged.

[0031] Furthermore, the sense amplifier SA1 is connected to the first end of the Y-line selection switch YS1_L via the read data line DL_RD1. The second end of the Y-line selection switch YS1_L is connected to one end of the bit line BL1_L. The other end of the bit line BL1_L is connected to the memory cell MC1_L.

[0032] The sense amplifier SA2 is connected to the first end of the Y-line selection switch YS2_L via the read data line DL_RD2. The second end of the Y-line selection switch YS2_L is connected to one end of the bit line BL2_L. The other end of the bit line BL2_L is connected to the memory cell MC2_L.

[0033] Memory cells MC1_L and MC2_L are the lower memory cells. The Y-selection switches YS1_L and YS2_L are switched on / off by the lower Y-line selection signal YDEC_L. When the Y-line selection switches YS1_L and YS2_L are turned on, the lower bit lines BL1_L and BL2_L are selected.

[0034] Furthermore, the first terminals of the discharge switches DS1_L and DS2_L are connected to the bit lines BL1_L and BL2_L. The second terminals of the discharge switches DS1_L and DS2_L are connected to the terminals to which the ground potential is applied. The lower discharge signal BLDIS_L switches the discharge switches DS1_L and DS2_L on and off. When the discharge switches DS1_L and DS2_L are turned on, the bit lines BL1_L and BL2_L are discharged.

[0035] The Y-line selection signals YDEC_U and YDEC_L are controlled complementaryly. That is, when the upper Y-selection switches YS1_U and YS2_U are ON, the lower Y-selection switches YS1_L and YS2_L are OFF, and when the upper Y-selection switches YS1_U and YS2_U are OFF, the lower Y-selection switches YS1_L and YS2_L are ON.

[0036] For example, when the upper Y-selection switches YS1_U and YS2_U are ON, the upper bit lines BL1_U and BL2_U are selected, and the lower bit lines BL1_L and BL2_L are deselected. In this case, the upper bit lines BL1_U and BL2_U are pre-charged by the sense amplifiers SA1 and SA2, and data is read out depending on whether or not current flows to the upper memory cells MC1_U and MC2_U. At this time, the deselected bit lines BL1_L and BL2_L are brought to ground potential by the discharge switches DS1_L and DS2_L, which are turned ON.

[0037] Here, as shown in Figure 10, for example, when the data "0" is written to memory cell MC1_U, current flows through memory cell MC1_U, causing the voltage of bit line BL1_U to drop from the voltage after precharging. As shown in Figure 10, memory cells and bit lines are arranged alternately on the upper and lower sides. Therefore, the lower bit line BL1_L is located adjacent to the upper bit lines BL1_U and BL2_U, and its voltage is at ground potential. Consequently, even if a parasitic capacitance Cbb is formed between adjacent bit lines, the decrease in the voltage of bit line BL1_U does not affect the voltage of BL2_U. This suppresses the drop in the voltage of bit line BL2_U from the voltage after precharging when the data "1" is written to memory cell MC2_U, thereby suppressing the erroneous reading of data "0". Therefore, it is possible to suppress data corruption due to interference between adjacent bit lines. The same effect can be enjoyed when reading from the lower memory cell, as the upper bit line is at ground potential.

[0038] Thus, according to the first comparative example, interference between bit lines is suppressed by shielding the selected bit lines with non-selected bit lines. However, the first comparative example has the following problems. For example, suppose the configuration reads one group of 38 bits of data when reading data at a specified address (8 bits). The above 38 bits of data consists of 32 bits (for 4 addresses) + 6 bits of ECC (error correction code). In this case, the configuration of the first comparative example requires reading the data in two separate steps: the upper 19 bits and the lower 19 bits. However, when serially outputting data at a specified address, a separate section is required for detecting and correcting a 1-bit error using ECC, and for selecting and outputting data at the specified address from the data for 4 addresses. Therefore, it is not possible to secure the section for reading the data in two separate steps during the transmission of 8 bits of data.

[0039] <3. Second Comparative Example> Figure 11 shows the configuration for data reading in the memory device according to the second comparative example. The second comparative example is implemented to solve the second problem mentioned above (the effect of increased leakage current).

[0040] In the configuration shown in Figure 11, the sense amplifier SA is connected to the first terminal of the upper switch US and the first terminal of the lower switch LS via the lead data line DL_RD.

[0041] In the configuration shown in Figure 11, the memory array is divided in the Y direction into an upper cell array CAR_U and a lower cell array CAR_L. The second end of the upper switch US is connected to one end of the upper bit line BL_U. The upper bit line BL_U traverses the upper cell array CAR_U in the Y direction, and a predetermined number of memory cells MC (e.g., 256) are connected to it. The second end of the lower switch LS is connected to one end of the lower bit line BL_L. The lower bit line BL_L traverses both the upper cell array CAR_U and the lower cell array CAR_L in the Y direction, and a predetermined number of memory cells MC (e.g., 256) are connected to it.

[0042] The up / down selection signal A is applied to the control terminal of the upper switch US and, after being inverted by inverter IV, is applied to the control terminal of the lower switch LS. As a result, the upper switch US and the lower switch LS are controlled complementaryly. That is, when the upper switch US is ON, the lower switch LS is OFF, and when the upper switch US is OFF, the lower switch LS is ON.

[0043] For example, as shown in Figure 11, when the upper switch US is ON and the lower switch LS is OFF, the upper bit line BL_U (i.e., the upper cell array CAR_U) is selected, and the lower bit line BL_L (i.e., the lower cell array CAR_L) is not selected. In this state, the upper bit line BL_U is precharged by the sense amplifier SA, and data is read out depending on whether or not current flows to the memory cell MC to be read, which corresponds to the selected word line WL.

[0044] In the example shown in Figure 11, the data "1" is written to the memory cell MC being read (with the selection transistor in the ON state), and no current flows through the memory cell MC being read. On the other hand, a leakage current IL may flow through memory cell MCs other than the one being read (with the selection transistor in the OFF state) connected to the upper bit line BL_U at high temperatures. However, because the memory cell is divided into upper and lower sections, the number of memory cell MCs connected to each upper and lower bit line can be reduced, thereby reducing the amount of leakage current. Therefore, it is possible to suppress the erroneous reading of "0" from the memory cell MC being read due to leakage current.

[0045] However, in this second comparative example, it is necessary to pass two bit lines through the upper cell array CAR_U, and if the memory device is miniaturized, there is a problem in that there is no space to pass the bit lines.

[0046] <4. Third Comparative Example> Figure 12 shows the configuration for data reading in the memory device according to the third comparative example. The third comparative example is implemented to solve the second problem mentioned above (the effect of increased leakage current).

[0047] In the configuration shown in Figure 12, a depletion-type NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) M and a variable resistor R are provided. The gate and source of the NMOS transistor M are short-circuited. One end of the variable resistor R is connected to the source of the NMOS transistor M. The other end of the variable resistor R is connected to the terminal to which the ground potential is applied.

[0048] Furthermore, in the configuration shown in Figure 12, a dummy cell DMC is provided. The gate of the selection transistor ST included in the dummy cell DMC and the control gate of the memory transistor MT included in the dummy cell DMC are connected to the terminals to which the ground potential is applied.

[0049] The drains of the dummy cell DMC and NMOS transistor M are connected to the drain of the input-side PMOS transistor (P-channel MOSFET) PM1 that constitutes the current mirror CM.

[0050] The reference current Iref flowing through the NMOS transistor M and the leakage current Icell flowing through the dummy cell DMC at high temperatures are combined to form a current that is mirrored by the current mirror CM and output from the output-side PMOS transistor PM2 that constitutes the current mirror CM. The current mirror CM is used as a current source in the sense amplifier SA provided in the configuration shown in Figure 12.

[0051] Here, we will specifically explain the sense amplifier SA using Figure 13. As shown in Figure 13, the sense amplifier SA includes a constant current source CI, an NMOS transistor NM1, an NMOS transistor NM2, an inverter IV1, a PMOS transistor PM3, and an inverter IV2.

[0052] The drain of NMOS transistor NM1 is connected to the drain of PMOS transistor PM3 at node N1. The source of PMOS transistor PM3 is connected to the power supply voltage application terminal. The source of NMOS transistor NM1 is connected to the gate of NMOS transistor NM2. The drain of NMOS transistor NM2 is connected to the output terminal of inverter IV1 and the gate of NMOS transistor NM1. The source of NMOS transistor NM2 is connected to the ground potential application terminal. Node N1 is connected to the input terminal of inverter IV2.

[0053] The constant current source CI is connected to node N1 and supplies current for data sensing. The constant current source CI is configured, for example, by a current mirror.

[0054] The source of the NMOS transistor NM1 is connected to one end of the read data line DL_RD. The other end of the read data line DL_RD is connected to one end of the bit line BL via the Y-line selection switch YS. A predetermined number of memory cells MC are connected to the bit line BL.

[0055] The operation of the sense amplifier SA will be explained using the timing chart shown in Figure 14. In Figure 14, the waveform examples of the sense amplifier enable signal SAENB, the Y-line selection signal YDEC, the voltage of the word line WL, the pre-charge enable signal PCENB applied to the gate of the PMOS transistor PM3, and the voltage of the bit line BL are shown in order from top to bottom.

[0056] First, at timing t1, both the sense amplifier enable signal SAENB and the precharge enable signal PCENB are switched from high level to low level. This initiates the precharging of the read data line DL_RD.

[0057] Then, at timing t2, when the Y-line selection signal YDEC is switched from a low level to a high level, the Y-line selection switch YS is turned ON, and bit line BL is selected. At this time, precharging of bit line BL begins, and the voltage of bit line BL rises.

[0058] Then, at timing t3, the voltage of the word line WL corresponding to the memory cell MC to be read is switched from a low level to a high level.

[0059] Then, at timing t4, when the precharge enable signal PCENB is switched from a low level to a high level, the PMOS transistor PM3 is switched to the off state and the sense operation begins. If the data "1" is written to the memory cell MC to be read, no current flows to the memory cell MC, so the voltage of the bit line BL does not drop (solid line in Figure 14). Therefore, the sense amplifier output signal SAOUT output from inverter IV2 is maintained at a low level.

[0060] On the other hand, if the data "0" is written to the memory cell MC to be read, current flows through that memory cell MC. Since the current flowing through that memory cell is greater than the current supplied by the constant current source CI, the voltage of the bit line BL decreases (dashed line in Figure 14). Such minute voltage changes in the bit line BL (read data line DL_RD) are amplified by the NMOS transistors NM1 and NM2 and sent to node N1. As a result, the sense amplifier output signal SAOUT is switched from a low level to a high level.

[0061] In the configuration of the third comparative example (Figure 12), a current mirror CM is provided as a current source in the sense amplifier SA, and this current source supplies a combined current of the reference current Iref and the leakage current Icell.

[0062] As a result, as shown in Figure 12, for example, if the data "1" is written to the memory cell MC to be read, even if a leakage current IL flows to a memory cell MC that is not the target of reading, the leakage current IL is canceled by the leakage current Icell of the dummy cell DMC during the sense operation, thus suppressing a drop in the bit line BL voltage. Therefore, the accidental reading of "0" from the memory cell MC to be read is suppressed.

[0063] However, in this third comparative example, the current supplied during the sense operation increases, which may reduce the sense speed when reading "0" from the memory cell MC to be read.

[0064] <5. Embodiments of the Disclosure> Based on the above explanation, embodiments of this disclosure will now be described. Figure 1 shows a schematic layout diagram of the memory device MDV10 before improvement on the left, and a schematic layout diagram of the memory device MDV1 according to the improved embodiment of this disclosure on the right. Figure 1 shows the orthogonal X and Y directions. Figure 1 is a plan view taken in a direction perpendicular to the X and Y directions.

[0065] As shown on the left side of Figure 1, the memory device MDV10 before improvement has a memory array 10, an X decoder 20, a Y decoder 30, and a sense amplifier area 40. In contrast, the improved memory device MDV1 has an upper memory array 1A, a lower memory array 1B, an upper X decoder 2A, a lower X decoder 2B, a Y decoder 3, and a sense amplifier area 4.

[0066] In other words, in the embodiments of this disclosure, the memory array is divided into two banks. The upper memory array 1A (bank A) and the lower memory array 1B (bank B) are arranged in the Y direction. The Y decoder 3 is located on one side of the lower memory array 1B in the Y direction and on the other side of the upper memory array 1A in the Y direction. That is, the Y decoder 3 is positioned sandwiched in the Y direction by the upper memory array 1A and the lower memory array 1B. If the capacity of the memory array 10 in the memory device MDV10 before improvement is 1 Mbit, then in order to maintain the capacity of the memory device, if the capacities of the upper memory array 1A and the lower memory array 1B in the improved memory device MDV1 are divided equally, for example, then the capacities of each will be 512 Kbit.

[0067] Furthermore, the upper X decoder 2A is positioned adjacent to one side in the X direction of the upper memory array 1A, and the lower X decoder 2B is positioned adjacent to one side in the X direction of the lower memory array 1B. The sense amplifier region 4 is positioned sandwiched in the Y direction by the upper X decoder 2A and the lower X decoder 2B, and is positioned adjacent to one side in the X direction of the Y decoder 3.

[0068] Figure 2A is a circuit diagram showing a partial configuration of the memory device MDV1 according to the present disclosure.

[0069] In the memory device MDV1, the bit lines extending in the Y direction are separated into two systems: the upper bit line BL_A and the lower bit line BL_B. The upper bit line BL_A traverses the upper memory array 1A. A predetermined number of memory cells MC_A (e.g., 256) are connected to one upper bit line BL_A. The lower bit line BL_B traverses the lower memory array 1B. A predetermined number of memory cells MC_B (e.g., 256) are connected to one lower bit line BL_B.

[0070] In both the upper memory array 1A and the lower memory array 1B, a cell unit is composed of memory cells with a predetermined number of bits, which serve as the unit for reading (data read) and writing (data write). The predetermined number of bits is, for example, 38 bits. The cell unit is formed by arranging a number of memory cells MC_A and MC_B in the X direction that corresponds to the predetermined number of bits.

[0071] A word line WL_A extending in the X direction from the upper X decoder 2A traverses the upper memory array 1A. A single word line WL_A is connected to each control terminal (read gate) of the selection transistor ST_A, which are aligned in the X direction.

[0072] A word line WL_B extending in the X direction from the lower X decoder 2B traverses the lower memory array 1B. A single word line WL_B is connected to each control terminal (read gate) of the selection transistor ST_B, which are aligned in the X direction.

[0073] A selection line SL extending in the Y direction traverses the upper memory array 1A and the lower memory array 1B. One selection line SL is connected to the first terminals of selection switches SW_A and SW_B, which are aligned in the Y direction. The second terminals of one selection switch SW_A or SW_B are connected to the control gates of memory transistors MT_A and MT_B, which are aligned in the X direction in a number corresponding to the predetermined number of bits. The control terminals of selection switches SW_A and SW_B are connected to word lines WL_A and WL_B.

[0074] The upper Y-line selection switch YS_A and the lower Y-line selection switch YS_B are provided on the Y decoder 3. The first end of the upper Y-line selection switch YS_A is connected to the upper bit line BL_A. The second end of the upper Y-line selection switch YS_A is connected to the upper read data line DL_RD_A. The first end of the lower Y-line selection switch YS_B is connected to the lower bit line BL_B. The second end of the lower Y-line selection switch YS_B is connected to the lower read data line DL_RD_B.

[0075] In the memory device MDV1, a switch circuit SWC is provided. The switch circuit SWC includes an NMOS transistor NM_A, an NMOS transistor NM_B, an inverter IV21, and a NOR circuit NO11.

[0076] The first terminal of NMOS transistor NM_A is connected to one end of the upper lead data line DL_RD_A. The first terminal of NMOS transistor NM_B is connected to one end of the lower lead data line DL_RD_B. The second terminals of NMOS transistor NM_A and NMOS transistor NM_B are connected to sense amplifier SA via lead data line DL_RD. The gate of NMOS transistor NM_A is connected to the output terminal of inverter IV21. The gate of NMOS transistor NM_B and the input terminal of inverter IV21 are connected to the output terminal of NOR circuit NO11.

[0077] One input terminal of NOR circuit NO11 receives the up / down selection signal A. The other input terminal of NOR circuit NO11 receives the selection signal SRWL_SEL. When the selection signal SRWL_SEL is low level, the input of the up / down selection signal A becomes active. In this case, when the up / down selection signal A is high level, the gate voltage of NMOS transistor NM_A becomes high level and the gate voltage of NMOS transistor NM_B becomes low level, so NMOS transistor NM_A is ON and NMOS transistor NM_B is OFF. In this case, the sense amplifier SA and the upper lead data line DL_RD_A are connected.

[0078] On the other hand, when the up / down selection signal A is low level, the gate voltage of NMOS transistor NM_A becomes low level, and the gate voltage of NMOS transistor NM_B becomes high level, resulting in NMOS transistor NM_A being in the off state and NMOS transistor NM_B being in the on state. In this case, the sense amplifier SA and the lower lead data line DL_RD_B are connected.

[0079] Thus, the switch circuit SWC selects either the upper read data line DL_RD_A or the lower read data line DL_RD_B based on the upper / lower selection signal A.

[0080] The selection signal SRWL_SEL, as shown in Figure 1, is a signal for accessing a special memory area 1AA, separate from the usual memory area, which is included in the upper memory array 1A. Memory area 1AA stores, for example, device identification data (such as the manufacturer's code), trimming data for analog value correction, and shipping history information. When accessing memory area 1AA, the selection signal SRWL_SEL is set to a high level, which turns on the NMOS transistor NM_A and selects the upper read data line DL_RD_A.

[0081] The upper Y-line selection switch YS_A and the lower Y-line selection switch YS_B are switched on / off by the Y-line selection signal YDEC, which is obtained after decoding the Y-direction address signal.

[0082] During data reading, the upper read data line DL_RD_A is selected by the switch circuit SWC, and if the upper Y-line selection switch YS_A is turned ON by the Y-line selection signal YDEC, the sense amplifier SA can precharge the upper read data line DL_RD_A and the upper bit line BL_A. During the sense operation after precharging, data is read depending on whether or not current flows to the memory cell MC_A to be read in the upper memory array 1A.

[0083] On the other hand, if the lower read data line DL_RD_B is selected by the switch circuit SWC and the lower Y-line selection switch YS_B is turned ON by the Y-line selection signal YDEC, the sense amplifier SA can precharge the lower read data line DL_RD_B and the lower bit line BL_B. During the sense operation after precharging, data is read out depending on whether or not current flows to the memory cell MC_B to be read in the lower memory array 1B.

[0084] In the memory device MDV1, a column latch section 34 is provided. Figure 2B shows the circuit configuration of the column latch section 34. The column latch section 34 includes a depletion-type NMOS transistor 341, a latch section 342, and switches 343 and 344. The drain of the NMOS transistor 341 is connected to the drain of the PMOS transistor HV_PM. The source of the PMOS transistor HV_PM is connected to the application terminal of the charge pump output voltage CPout, which is output from a charge pump (not shown). The drain of the NMOS transistor 341 is also connected to the output terminal of the read voltage source 35. The latch section 342 includes inverters 342A and 342B. The output terminal of inverter 342A is connected to the gate of the NMOS transistor 341. The input terminal of inverter 342B is connected to the output terminal of inverter 342A. The output terminal of inverter 342B is connected to the input terminal of inverter 342A. The first terminal of switch 343 is connected to the output terminal of inverter 342B. The second terminal of switch 343 is connected to the terminal to which the ground potential is applied. The first terminal of switch 344 is connected to the gate of NMOS transistor 341. The second terminal of switch 344 is connected to the terminal to which the ground potential is applied. Switch 343 is controlled on / off by the Y-line selection signal YDEC. Switch 344 is controlled on / off by the reset signal RST.

[0085] During data reading, switch 343 is ON and switch 344 is OFF, so the output of latch unit 342 (gate voltage of NMOS transistor 341) is set to a high level, and NMOS transistor 341 is turned ON. At this time, PMOS transistor HV_PM is OFF, and a predetermined reading voltage (e.g., 1.4V) is output from the read voltage source 35. This applies the predetermined voltage to the selection line SL. In other words, the column latch unit 34 can select a column by applying a predetermined reading voltage (e.g., 1.4V) to the selection line SL. The cell units to be read can be selected by word lines WL_A, WL_B and selection line SL.

[0086] The sense amplifier SA is placed in the sense amplifier area 4 in a number corresponding to the number of bits in the cell (for example, 38). Accordingly, the read data line DL_RD, the upper read data line DL_RD_A, and the lower read data line DL_RD_B are also provided in a number corresponding to the number of bits (for example, 38). The upper bit line BL_A, the upper Y-line selection switch YS_A, the lower bit line BL_B, and the lower Y-line selection switch YS_B are provided in the above number for each cell. This makes it possible to read the data with the number of bits in the cell.

[0087] Next, the configuration for data writing in the memory device MDV1 will be described. In the memory device MDV1, the Y decoder 3 includes an NMOS transistor NM11, an NMOS transistor NM12, a data latch circuit 32, a PMOS transistor PM_A, and a PMOS transistor PM_B.

[0088] One end of the write data line DL_WR is connected to the first end of the NMOS transistor NM11. The second end of the NMOS transistor NM11 is connected to the first end of the NMOS transistor NM12. The data latch circuit 32 has inverters 321 and 322. The input end of inverter 321 is connected to the output end of inverter 322, and the output end of inverter 321 is connected to the input end of inverter 322. The second end of the NMOS transistor NM12 is connected to the data latch circuit 32.

[0089] Figure 3 shows the configuration of the signals input to the gates of NMOS transistors NM11 and NM12. The output terminal of NOR circuit NO21 is connected to the gate of NMOS transistor NM11. The page set enable signal PGS_ENB is input to one input terminal of NOR circuit NO21. The output terminal of inverter IV31 is connected to the other input terminal of NOR circuit NO21. The Y-line selection signal YDEC is input to the input terminal of inverter IV31. In addition, the load signal LOAD is input to the gate of NMOS transistor NM12.

[0090] As a result, when the page set enable signal PGS_ENB is low level, the Y-line selection signal YDEC is high level, and the load signal LOAD is high level, both NMOS transistors NM11 and NM12 are turned on. At this time, the write data signal SWR (Figure 2A) input to the write data line DL_WR is applied to the data latch circuit 32, and the data according to the write data signal SWR is set. Even if the NMOS transistor NM11 switches to the off state, the data is latched by the data latch circuit 32.

[0091] The data latch circuit 32 is connected to the gates of PMOS transistors PM_A and PM_B. When low-level data is latched, PMOS transistors PM_A and PM_B are turned ON. On the other hand, when high-level data is latched, PMOS transistors PM_A and PM_B are turned OFF.

[0092] The memory device MDV1 is provided with high-voltage pulse generation units 31A and 31B, NOR circuits NO1 and NO2, and inverter IV11. The high-voltage pulse generation units 31A and 31B are circuits that output high-voltage pulses during the write process, which will be described later. The output terminal of the high-voltage pulse generation unit 31A is connected to the first terminal of the PMOS transistor PM_A, and the output terminal of the high-voltage pulse generation unit 31B is connected to the first terminal of the PMOS transistor PM_B.

[0093] The charge pump output voltage CPout, which is output from a charge pump (not shown), is stepped down by a two-stage NMOS transistor NM10 to obtain the stepped-down voltage VPPMV. This stepped-down voltage VPPMV is supplied to the high-voltage pulse generation units 31A and 31B.

[0094] The output terminal of NOR circuit NO1 is connected to the high-voltage pulse generation unit 31B. The output terminal of NOR circuit NO2 is connected to the high-voltage pulse generation unit 31A. The up / down selection signal A is input to one input terminal of NOR circuit NO1 and is inverted by inverter IV11 before being input to one input terminal of NOR circuit NO2. The light discharge signal WR_DIS is input to the other input terminal of NOR circuits NO1 and NO2.

[0095] When the write discharge signal WR_DIS is at a low level, the input of the upper / lower selection signal A becomes active, and it is possible to select which of the high-voltage pulse generation units 31A or 31B to operate according to the level of the upper / lower selection signal A. In other words, the upper / lower selection signal A selects whether to perform write processing on the upper memory array 1A or the lower memory array 1B. Also, when the write discharge signal WR_DIS becomes high level, it becomes possible to output 0V after generating high voltage in whichever of the high-voltage pulse generation units 31A or 31B is operated, and discharge is performed on the bit lines BL_A and BL_B to which high voltage has been applied.

[0096] Here, Figure 4 is a timing chart schematically showing the waveforms of each signal during data writing. In Figure 4, from top to bottom, the following are shown: charge pump output voltage CPout, voltage of selected word line WL, voltage of selected line SL, step-down voltage VPPMV, high-voltage output voltages VPP_WT_A and VPP_WT_B output from high-voltage pulse generation units 31A and 31B, voltages of bit lines BL_A and BL_B when writing data "0" to the memory cell, and voltages of bit lines BL_A and BL_B when writing data "1" to the memory cell. Also, in Figure 4, the high voltage generated by the charge pump is assumed to be 17V as an example.

[0097] During data writing, erase and write operations are performed consecutively. During the erase operation, the charge pump output voltage CPout rises from the power supply voltage Vcc to 17V. At this time, the step-down voltage VPPMV is stepped down from 17V by, for example, 3V by the two-stage NMOS transistor NM10, to 14V. Of the high-voltage pulse generation units 31A and 31B, the one whose operation is selected by the upper / lower selection signal A outputs high-voltage output voltages VPP_WT_A and VPP_WT_B, which are 0V.

[0098] At this time, since low-level data is latched by the data latch circuit 32, the PMOS transistors PM_A and PM_B are turned ON, and 0V is applied to the bit lines BL_A and BL_B. Also, in the column latch section 34, the NMOS transistor 341 is turned ON, and the PMOS transistor HV_PM is turned ON, so 17V is applied to the selected line SL. As a result, in the memory cells MC_A and MC_B to be written, the selection transistors ST_A and ST_B are turned ON, and a high voltage (17V in this case) is applied to the control gates of the memory transistors MT_A and MT_B. Consequently, electrons are injected into the floating gates of the memory transistors MT_A and MT_B in the memory cells MC_A and MC_B to be written, and the memory transistors MT_A and MT_B are put into an erased state.

[0099] After the erase process, during the write process, the charge pump output voltage CPout rises again from the power supply voltage Vcc to 17V. At this time, the step-down voltage VPPMV becomes 14V. Of the high-voltage pulse generation units 31A and 31B, the one whose operation is selected by the up / down selection signal A outputs high-voltage output voltages of 14V, VPP_WT_A and VPP_WT_B. In other words, high-voltage pulses are generated during the write process.

[0100] When writing data "0" to the memory cell to be written, the data latch circuit 32 latches low-level data, so the PMOS transistors PM_A and PM_B are turned ON, and 14V is applied to the bit lines BL_A and BL_B. In addition, a switch SLDIS (Figure 2B) is connected to the selection line SL to bring the selection line SL to ground potential, and when the switch SLDIS is turned ON (both NMOS transistor 341 and PMOS transistor HV_PM are turned OFF), 0V is applied to the selected selection line SL. As a result, the selection transistors ST_A and ST_B in the memory cells MC_A and MC_B to be written are turned ON, and 0V is applied to the control gates of the memory transistors MT_A and MT_B. Consequently, electrons are drawn from the floating gates of the memory transistors MT_A and MT_B in the memory cells MC_A and MC_B to be written, and the memory transistors MT_A and MT_B are set to the write state ("0").

[0101] On the other hand, when writing data "1" to the memory cell to be written, the data latch circuit 32 latches high-level data, so the PMOS transistors PM_A and PM_B are turned off and the bit lines BL_A and BL_B are opened. Consequently, electrons are not drawn from the floating gates of the memory transistors MT_A and MT_B in the memory cells MC_A and MC_B to be written, and the memory transistors MT_A and MT_B are maintained in the erased state ("1").

[0102] Furthermore, in the memory device MDV1, the Y decoder 3 has a clamp circuit 33. The clamp circuit 33 has NMOS transistors 331, 332, and 333. A clamping voltage VN is applied to the first terminal of NMOS transistor 331. A data latch circuit 32 is connected to the gate of NMOS transistor 331. The second terminal of NMOS transistor 331 is connected to the first terminals of NMOS transistors 332 and 333, respectively. The second terminal of NMOS transistor 332 is connected to the second terminal of PMOS transistor PM_A. The second terminal of NMOS transistor 333 is connected to the second terminal of PMOS transistor PM_B.

[0103] When writing data "1" to the memory cell to be written, the data latch circuit 32 latches high-level data during the write process, and the PMOS transistors PM_A and PM_B are in the off state. At this time, the NMOS transistor 331 is turned on, and when the high-voltage output voltages VPP_WT_A and VPP_WT_B reach a high voltage (14V), the NMOS transistors 332 and 333 turn on, and a clamping voltage VN is applied to the bit lines BL_A and BL_B. As a result, when a high voltage is applied to a bit line adjacent to bit lines BL_A and BL_B, the voltage of bit lines BL_A and BL_B can be clamped to below the clamping voltage VN, thereby suppressing the voltage rise of bit lines BL_A and BL_B.

[0104] The number of write data lines DL_WR is provided in a number corresponding to the number of bits in the cell (for example, 38 lines). In addition, the number of NMOS transistors NM11, NM12, data latch circuit 32, PMOS transistors PM_A, PM_B, and clamp circuit 33 is provided in a number corresponding to the number of bits in the cell (for example, 38 units). During data writing, erase and write operations are performed on the cell unit. At this time, after erasing all bits in the cell unit, write operations are performed only on the desired bits.

[0105] In the configuration shown in Figure 3, NMOS transistors NM11 and NM12 are provided in the data set path, but the configuration shown in Figure 5 may also be used. In the configuration shown in Figure 5, NMOS transistor NM12 is omitted, and only NMOS transistor NM11 is provided. In this case, the output terminal of NOR circuit NO31 is connected to the gate of NMOS transistor NM11. The output terminal of OR circuit OR1 is connected to one input terminal of NOR circuit NO31. The output terminal of NAND circuit ND1 is connected to the other input terminal of NOR circuit NO31. The LOAD signal is input to one input terminal of NAND circuit ND1 and is inverted by inverter IV41 before being input to OR circuit OR1. The page set enable signal PGSET_ENB is input to the other input terminal of OR circuit OR1. The Y-line selection signal YDEC is input to the other input terminal of NAND circuit ND1.

[0106] As a result, when the LOAD signal is high, the page set enable signal PGSET_ENB is low, and the Y-line selection signal YDEC is high, the gate voltage of the NMOS transistor NM11 becomes high, turning on the NMOS transistor NM11 and performing data setting. In this way, by integrating the NMOS transistor into a single path for data setting, the number of elements can be reduced.

[0107] Figure 6 is a magnified view of a portion of the memory device MDV10 before improvement (magnification of the dashed area in Figure 1). As shown in Figure 6, in the Y decoder 30, the bit line area YMUX_BL, page buffer area PGBUF, logic area LOGIC, page set area YMUX_PGSET, column latch area COLLAT, and column drive area COLDRV are provided in this order from one side in the Y direction to the other side in the Y direction.

[0108] The bit line BL extending in the Y direction is connected to the memory cell MC included in the memory array 10. The Y-line selection switch YS, which is provided between the bit line BL and the read data line BL_RD, is located in the bit line region YMUX_BL.

[0109] In the data set path from the logic unit 50 to the data latch circuit 32, a write data line DL_WR, an NMOS transistor NM11, and an NMOS transistor NM12 are arranged. The data latch circuit 32, a PMOS transistor PM, and the NMOS transistor NM12 driven by the LOAD signal are provided in the page buffer area PGBUF. The PMOS transistor PM is driven by the data latch circuit 32 and is positioned between the bit line BL and the application terminal of the high-voltage output voltage VPP_WT.

[0110] The NMOS transistor NM11, driven by the page set enable signal and the Y line selection signal, is located in the page set area YMUX_PGSET. A page set line PGSL extending in the Y direction is connected between the NMOS transistors NM11 and NM12. Since this page set line PGSL is arranged in the X direction in a number corresponding to the number of bits per cell (for example, 38 lines), there was no space to pass the bit lines to the lower side (the other side in the Y direction) even when attempting to divide the memory array 10 into two in the Y direction.

[0111] Furthermore, in the page buffer area (PGBUF), the data latch circuit 32 is arranged in multiple stages (for example, four stages) in the Y direction, which meant there was no extra space to pass the bit lines downwards.

[0112] In contrast, Figure 7 is a partially enlarged view of the improved memory device MDV1 (an enlargement of the dashed area in Figure 1). As shown in Figure 7, in the Y decoder 3, the upper bit line area YMUX_BLA, the page buffer area PGBUF, the logic area LOGIC, the column latch area COLLAT, the column drive area DOLDRV, and the lower bit line area YMUX_BLB are provided in this order from one side in the Y direction to the other side in the Y direction.

[0113] The upper bit line BL_A, extending in the Y direction, crosses the upper memory array 1A and the upper bit line region YMUX_BLA. The upper Y line selection switch YS_A is located in the upper bit line region YMUX_BLA. The lower bit line BL_B, extending in the Y direction, crosses the lower memory array 1B and the lower bit line region YMUX_BLB. The lower Y line selection switch YS_B is located in the lower bit line region YMUX_BLB. The upper Y line selection switch YS_A and the lower Y line selection switch YS_B are connected to the switch circuit SWC via the upper read data line DL_RD_A and the lower read data line DL_RD_B, respectively. The switch circuit SWC is connected to the sense amplifier SA (located in the sense amplifier region 4) via the read data line DL_RD.

[0114] Thus, in the embodiments of this disclosure, the memory array is divided into two sections vertically, and the bit lines are separated vertically. Then, the switch circuit SWC and the upper and lower Y-line selection switches enable reading of two separate data streams. As a result, even if the memory device MDV1 has a large capacity, the number of memory cells connected to each of the upper and lower bit lines is reduced. Therefore, leakage current at high temperatures is reduced, and data corruption due to leakage current can be suppressed. This improves data corruption tolerance during data reading and ensures operation at high temperatures (e.g., 150°C) with a large capacity memory.

[0115] Furthermore, because the wiring length of both the upper and lower bit lines is shortened, the parasitic capacitance to the sub-bit associated with the bit lines is reduced, improving the sense speed during data reading. Consequently, the operating frequency of the memory device MDV1 can be increased (e.g., from 10 to 20 MHz).

[0116] Furthermore, since the wiring length of each bit line is shortened, the parasitic capacitance between adjacent bit lines is reduced, and interference between bit lines can be suppressed. Also, when outputting data at a specified address, for example, when reading 38 bits (32 bits + 6 bits ECC) of data, in this embodiment, it is not necessary to read the data in two separate steps as in the first comparative example described above, but the 38 bits of data are read simultaneously, thus securing a section for reading the data.

[0117] Furthermore, as in the second comparative example, there is no need to pass bit lines for the other memory array through one memory array, thus enabling miniaturization. In this way, according to the embodiments of the present disclosure, it is possible to improve data read characteristics while achieving miniaturization and increased capacity.

[0118] Furthermore, in the embodiments of this disclosure, by providing PMOS transistors PM_A and PM_B and high-voltage pulse generation units 31A and 31B as the data writing configuration, it becomes possible to perform data writing in two separate systems. Since the capacitance to the sub and leakage current can be reduced in each of the upper and lower bit lines, the desired voltage boost can be achieved by the charge pump even at a low power supply voltage, enabling low power supply voltage reduction (e.g., 2.5 → 1.7V) for large-capacity memory.

[0119] Furthermore, in this embodiment of the disclosure, the NMOS transistor NM12 is arranged adjacent to the data latch circuit 32. Compared to the previous version (Figure 6), the page set line PGSL is eliminated by integrating the NMOS transistor 11 adjacent to the NMOS transistor 12 into the page buffer area PGBUF. This makes it possible to pass the lower bit line BL_B through the Y decoder 3. Also, in this embodiment of the disclosure, as in the previous version, the data latch circuit 32 is arranged in multiple stages in the Y direction in the page buffer area PGBUF, but space is secured to pass the lower bit line BL_B.

[0120] In other words, if the memory array is simply divided into two halves vertically in the configuration before improvement, it is necessary to add a Y decoder for the lower memory array, which leads to an increase in chip area. However, with the embodiment of this disclosure, the increase in chip area can be suppressed. The same applies when adopting the configuration shown in Figure 5 (with the removal of the NMOS transistor NM12).

[0121] Furthermore, it is desirable that the wiring length from sense amplifier SA to the upper Y-line selection switch YS_A (the path via the read data line DL_RD, switch circuit SWC, and upper read data line DL_RD_A) and the wiring length from sense amplifier SA to the lower Y-line selection switch YS_B (the path via the read data line DL_RD, switch circuit SWC, and lower read data line DL_RD_B) be equal. This helps to suppress differences in sense speed during data reading between the upper and lower systems.

[0122] <6. Others> Furthermore, various technical features relating to this disclosure can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered illustrative and not restrictive in all respects, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0123] <7. Addendum> As described above, for example, the memory device (MDV1) relating to this disclosure is, An upper memory array (1A) is configured such that memory cells (MC_A) are arranged in a matrix in the orthogonal X and Y directions, A lower memory array (1B) is configured such that memory cells (MC_B) are arranged in a matrix in the X and Y directions, and is positioned on the other side in the Y direction from the upper memory array. A Y decoder (3) is configured to be sandwiched between the upper memory array and the lower memory array in the Y direction in a plan view, SenseAmp (SA) and, Switch circuit (SWC), Equipped with, The upper bit line (BL_A) connected to the memory cell of the upper memory array extends in the Y direction between the upper memory array and the Y decoder. The lower bit line (BL_B) connected to the memory cell of the lower memory array extends in the Y direction between the lower memory array and the Y decoder. The aforementioned Y decoder is The upper Y-line selection switch (YS_A) connected to the upper bit line, A lower Y-line selection switch (YS_B) is connected to the lower bit line and is located on the other side in the Y direction from the upper Y-line selection switch, It has, The switch circuit is configured to allow switching between conduction between the sense amplifier and the upper Y-line selection switch and conduction between the sense amplifier and the lower Y-line selection switch (first configuration).

[0124] Furthermore, the first configuration described above further includes a first high-voltage pulse generation unit (31A) and a second high-voltage pulse generation unit (32A) configured to generate high-voltage pulses during light processing, The aforementioned Y decoder (3) is Data latch circuit (32), A first transistor (PM_A) includes a control terminal driven by data latched by the data latch circuit, a first terminal connected to the output terminal of the first high-voltage pulse generation unit, and a second terminal connected to the upper bit line (BL_A), A second transistor (PM_B) includes a control terminal driven by data latched by the data latch circuit, a first terminal connected to the output terminal of the second high-voltage pulse generation unit, and a second terminal connected to the lower bit line (BL_B), A configuration having the following is also possible (second configuration).

[0125] Furthermore, in the second configuration described above, the Y decoder (3) has a first switch (NM12) and a second switch (NM11) arranged on the path through which data is set in the data latch circuit (32), The first switch is driven by a load signal (LOAD) and is located adjacent to the data latch circuit. The second switch may be driven by a page set enable signal (PGS_ENB) and a Y-line selection signal (YDEC), and may be configured to be located adjacent to the first switch (third configuration).

[0126] Furthermore, in the second configuration described above, the Y decoder (3) has a third switch (NM11) located on the path through which data is set in the data latch circuit (32), The third switch may be driven by a load signal (LOAD), a page set enable signal (PGS_ENB), and a Y-line selection signal (YDEC), and may be configured to be located adjacent to the data latch circuit (fourth configuration).

[0127] Furthermore, in any of the second to fourth configurations described above, the Y decoder (3) may be configured to have a clamp circuit (33) that is configured to apply a clamp voltage (VN) to the upper bit line (BL_A) or the lower bit line (BL_B) when a high voltage is generated by the first high-voltage pulse generation unit (31A) or the second high-voltage pulse generation unit (31B) when the first transistor (PM_A) and the second transistor (PM_B) are in the off state (fifth configuration).

[0128] Furthermore, in any of the first to fifth configurations described above, the wiring length from the sense amplifier (SA) to the upper Y-wire selection switch (YS_A) via the switch circuit (SWC) and the wiring length from the sense amplifier to the lower Y-wire selection switch (YS_B) via the switch circuit may be set to be equal (sixth configuration). [Industrial applicability]

[0129] This disclosure can be used in memory devices for various applications. [Explanation of symbols]

[0130] 1A Upper memory array 1B Lower memory array 2A Upper X Decoder 2B Lower X Decoder 3 Y Decoder 4. Sense Amplifier Area 5. Logic Section 31A, 31B High-voltage pulse generation unit 32. Data latch circuit 33. Clamp Circuit 34 Column latch section 35 Lead voltage source BL_A upper bit line BL_B lower bit line YS_A Upper Y-wire selection switch YS_B Lower Y-wire selection switch DL_RD Read Data Line DL_RD_A Upper Read Data Line DL_RD_B Lower Read Data Line DL_WR write dataline NM10, NM11, NM12 NMOS transistors MC_A, MC_B memory cells MT_A, MT_B memory transistors PM_A, PM_B PMOS transistors ST_A, ST_B Selection Transistor SW_A, SW_B selection switch SA SenseAmp SWC Switch Circuit WL_A, WL_B Wordline SL Selection Line

Claims

1. An upper memory array configured such that memory cells are arranged in a matrix in orthogonal X and Y directions, A lower memory array is configured such that memory cells are arranged in a matrix in the X and Y directions, and is positioned on the other side in the Y direction from the upper memory array, A Y decoder is configured to be sandwiched between the upper memory array and the lower memory array in the Y direction in a plan view, SenseAmp and Switch circuit and Equipped with, The upper bit line connected to the memory cell of the upper memory array extends in the Y direction between the upper memory array and the Y decoder. The lower bit line connected to the memory cell of the lower memory array extends in the Y direction between the lower memory array and the Y decoder. The aforementioned Y decoder is An upper Y-line selection switch connected to the upper bit line, A lower Y-line selection switch is connected to the lower bit line and is located on the other side in the Y direction from the upper Y-line selection switch, It has, The switch circuit is configured to switch between continuity between the sense amplifier and the upper Y-line selection switch, and continuity between the sense amplifier and the lower Y-line selection switch, and is a memory device.

2. The system further comprises a first high-voltage pulse generation unit and a second high-voltage pulse generation unit configured to generate high-voltage pulses during light processing, The aforementioned Y decoder is Data latch circuit, A first transistor including a control terminal driven by data latched by the data latch circuit, a first terminal connected to the output terminal of the first high-voltage pulse generation unit, and a second terminal connected to the upper bit line, A second transistor comprising a control terminal driven by data latched by the data latch circuit, a first terminal connected to the output terminal of the second high-voltage pulse generation unit, and a second terminal connected to the lower bit line, A memory device according to claim 1, having the following features.

3. The Y decoder has a first switch and a second switch arranged on the path through which data is set in the data latch circuit. The first switch is driven by a load signal and is located adjacent to the data latch circuit. The memory device according to claim 2, wherein the second switch is driven by a page set enable signal and a Y line selection signal and is located adjacent to the first switch.

4. The Y decoder has a third switch located on the path through which data is set in the latch circuit. The memory device according to claim 2, wherein the third switch is driven by a load signal, a page set enable signal, and a Y-line selection signal, and is located adjacent to the data latch circuit.

5. The memory device according to claim 2, wherein the Y decoder has a clamp circuit configured to apply a clamping voltage to the upper bit line or the lower bit line when a high voltage is generated by the first high-voltage pulse generation unit or the second high-voltage pulse generation unit while the first transistor and the second transistor are in the off state.

6. The memory device according to any one of claims 1 to 5, wherein the wiring length from the sense amplifier through the switch circuit to the upper Y-line selection switch is equal to the wiring length from the sense amplifier through the switch circuit to the lower Y-line selection switch.

Images