A method for manufacturing a semiconductor device and a semiconductor device manufactured by that method.

Abstract

To provide a manufacturing method of a semiconductor device, in which a post is arranged.SOLUTION: A manufacturing method of a semiconductor device includes steps of: providing a lower mold; arranging a plurality of semiconductor chips on the lower mold; arranging a plurality of first metal members on the lower mold, each first metal member being arranged to both sides of each semiconductor chip; providing an upper mold that faces the lower metal mold, and houses each semiconductor chip and each first metal member; filling a material between the lower metal mold and the upper metal mold; and removing the upper metal mold, the lower metal mold, and the first metal member, and forming a plurality of penetration holes in a seal material that is positioned on both sides of the semiconductor chip.SELECTED DRAWING: Figure 3H

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with posts arranged thereon.

Background Art

[0002] Currently, power modules molded with epoxy resin have product structure features designed on the mold. However, for products with different structural features, it is necessary to design corresponding different molds. That is, due to the lack of mold sharing in use, the manufacturing cost of the mold becomes high. Also, when trying to manufacture a product with more complex structural features, it is often limited by the performance of the mold process.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Provide a method for manufacturing a semiconductor device with posts arranged thereon.

Means for Solving the Problems

[0004] Provided is a method for manufacturing a semiconductor device, including steps of providing a lower mold according to an embodiment of the present disclosure, arranging a plurality of semiconductor chips on the lower mold, arranging a plurality of first metal members on the lower mold, the first metal members being arranged on both sides of the semiconductor chips, providing an upper mold facing the lower mold and accommodating the semiconductor chips and the first metal members, filling a sealing material between the lower mold and the upper mold, and removing the upper mold, the lower mold, and the first metal members to form a plurality of through holes in the sealing material located on both sides of the semiconductor chips.

[0005] In some embodiments, the step of arranging a plurality of semiconductor chips and a plurality of first metal members on the lower mold includes the steps of providing a carrier, arranging a tape on the carrier, arranging the semiconductor chips and the first metal members on the tape, and arranging the carrier on the lower mold.

[0006] In some embodiments, the step of arranging a plurality of semiconductor chips on the lower mold includes the steps of providing carriers, placing the semiconductor chips on the carriers, and transferring the semiconductor chips from the carriers onto the lower mold. In some embodiments, the method for manufacturing the semiconductor device further includes the step of fixing the semiconductor chips on the lower mold with a plurality of second metal members arranged on the lower mold. In some embodiments, the step of arranging a plurality of first metal members on the lower mold includes the steps of fixing the first metal members to the upper mold, and aligning the upper mold and the lower mold.

[0007] In some embodiments, the method for manufacturing the semiconductor device further includes the step of cutting the sealing material to form a plurality of semiconductor devices, each semiconductor device further including the semiconductor chip, the sealing material covering the semiconductor chip, and through holes penetrating the sealing material. In some embodiments, in each semiconductor device, the sealing material has a first sidewall and a second sidewall, the second sidewall being located on the opposite side of the semiconductor chip from the first sidewall, and the first and second sidewalls forming an angle of 90 degrees with respect to the horizontal plane.

[0008] The present disclosure provides a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device according to one embodiment of this disclosure.

[0009] In some embodiments, the sealing material has a first sidewall and a second sidewall, the second sidewall being located on the opposite side of the semiconductor chip from the first sidewall, and the first and second sidewalls forming a 90-degree angle with respect to the horizontal plane.

[0010] In some embodiments, the configuration further includes a plurality of positioning holes located on both sides of the semiconductor chip, wherein the positioning holes are located closer to the semiconductor chip than the through-holes.

[0011] This disclosure demonstrates that when manufacturing products of different sizes or with different structural characteristics, it is not necessary to design different molds; in other words, the same mold can be used for different products, and the required products can be manufactured simply by designing a structurally removable post and a subsequent cutting process. The process technology disclosed herein enhances mold commonality and reduces mold development costs. Furthermore, since it is not necessary to design the structural characteristics of the product on the mold, the structural strength of the mold is improved, and the durability of the mold is enhanced. In addition, this disclosure overcomes the limitations of conventional manufacturing processes by easily manufacturing products with vertical sides using a post-release cutting molding technique.

[0012] The present invention can be better understood from the following detailed description with reference to the accompanying drawings. In accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features have been arbitrarily enlarged or reduced for clarity in the description. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present disclosure. [Figure 3A] Figure 3A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3B] Figure 3B is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3C] Figure 3C is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3D] Figure 3D is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3E] Figure 3E is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3F] Figure 3F is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3G] Figure 3G is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3H] Figure 3H is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4A] Figure 4A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4B] Figure 4B is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4C] Figure 4C is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4D] Figure 4D is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4E] Figure 4E is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4F] Figure 4F is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0014] The following disclosure provides various different embodiments for implementing different features of the present disclosure. For the sake of simplifying the description, the following disclosure describes specific examples of each component and its arrangement, and these specific examples do not limit them. For example, in an embodiment of the present disclosure, if it is described that a first feature component is formed on or above a second feature component, it may mean that it includes an embodiment in which the above-mentioned first feature component and the second feature component are in direct contact, and it may also mean that an additional feature component is formed between the above-mentioned first feature component and the second feature component so that the above-mentioned first feature component and the second feature component do not directly contact each other.

[0015] Additional steps may be performed before, during, or after the illustrated method, and in other embodiments of the illustrated method, some steps may be replaced or omitted.

[0016] Furthermore, (in the following detailed description), spatially relative terms such as "lower", "below", "bottom", "upper", "above", "top" and words similar thereto are used to simplify the description for describing the relationship between one element or feature and another (plural) element or (plural) feature in the figure. The spatially relative terms are intended to encompass different directions of the device being used or operated in addition to the directions depicted in the figures. The device may be oriented in other directions (rotated 45 degrees, or in other directions), and the spatially relative descriptions used herein may be interpreted accordingly. In some embodiments of the present disclosure, terms such as "opposite" that approach each other, unless otherwise defined, can refer to the structures directly contacting each other or not directly contacting each other, and the terms related to this opposite and pressing can include a relationship where two structures are movable or two structures are fixed.

[0017] As used herein, the terms "about," "approximately," "substantially," "essentially," "same," and "similar" generally indicate that a characteristic value is within + / - 15%, or within + / - 10%, or within + / - 5%, or within + / - 3%, or within + / - 2%, or within + / - 1%, or within + / - 0.5% of the recited value. The recited values herein are approximate values, i.e., where no specific description of "about," "approximately," "substantially," or "essentially" is given, or where no specific indication of "about," "approximately," "substantially," etc. is given, the meaning of "about," "approximately," "substantially," or "essentially" may be implied.

[0018] As used herein, the terms "first," "second," "third," etc. are used to describe various components, parts, regions, layers, and / or sections, but it should be understood that these terms should not be construed as limiting. These terms can only be used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Thus, on the premise of not departing from the technology of the present disclosure, hereinafter, the first component, part, region, layer, or section can be referred to as the second component, part, region, layer, or section.

[0019] Unless otherwise defined, all terms, including technical and scientific terms used herein, have the same meaning as commonly understood by one of ordinary skill in the art. As will be understood, terms defined in commonly used dictionaries should be interpreted as having a meaning that conforms to the relevant technology of the present disclosure and the context or background, and should not be interpreted in an idealized or overly formal manner unless otherwise defined.

[0020] As shown in FIG. 1, a semiconductor device 10 including a mold-cladding is provided according to an embodiment of the present disclosure. FIG. 1 is a schematic cross-sectional view of the semiconductor device 10 including the mold-cladding.

[0021] As shown in Figure 1, the semiconductor device 10 including the mold cladding includes a lower mold 12, a carrier 14, a tape 16, a plurality of semiconductor chips 18, a plurality of first metal members 20, a sealing material 22, and an upper mold 24. The semiconductor chips 18 are placed on the lower mold 12. The carrier 14 is placed between the lower mold 12 and the semiconductor chips 18. The tape 16 is placed between the carrier 14 and the semiconductor chips 18. The first metal members 20 are placed on the lower mold 12 and are located on both sides of the semiconductor chips 18. More specifically, the semiconductor chips 18 and the first metal members 20 are placed on the tape 16 and are in contact with the tape 16. The sealing material 22 is filled between the lower mold 12 and the upper mold 24. The first metal members 20 penetrate the sealing material 22. The upper mold 24 and the lower mold 12 face each other and house the semiconductor chips 18 and the first metal members 20.

[0022] In some embodiments, the carrier 14 may include metal, but the disclosure is not limited thereto, and other suitable rigid materials having heat resistance, pressure resistance, and support properties are also applicable to the present invention. In some embodiments, the tape 16 may include heat-resistant tape, but the disclosure is not limited thereto, and other suitable materials having heat resistance, pressure resistance, and adhesive properties are also applicable to the present invention.

[0023] In some embodiments, the semiconductor chip 18 may include a power component, but this disclosure is not limited thereto. In some embodiments, the semiconductor chip 18 may include a substrate 26, a first metal layer 28, a second metal layer 30, a conductive component 32, and a chip 33. The first metal layer 28 and the second metal layer 30 are arranged on opposite sides of the substrate 26, the first metal layer 28 is in contact with the tape 16, the conductive component 32 is arranged on the second metal layer 30 and connected to an external circuit (not shown), and the chip 33 is arranged on the second metal layer 30 as shown in Figure 1.

[0024] In some embodiments, the first metal member 20 may include a columnar metal structure, for example, a cylindrical metal structure, but the present invention is not limited thereto, and other suitable three-dimensional shapes are also applicable to this disclosure and can be designed according to product requirements. In some embodiments, there may be a plurality of first metal members 20 between adjacent semiconductor chips 18, for example, an even number of first metal members 20 between adjacent semiconductor chips 18 such that the semiconductor device formed after cutting has symmetrical through-holes for subsequent screw mounting, but the present disclosure is not limited thereto, and other suitable positions and quantities of first metal members 20 are also applicable to this disclosure and can be designed according to product requirements.

[0025] In some embodiments, the sealing material 22 may include a solid molding material, a liquid molding material, an anisotropic conductive film (ACF), or a sheet molding material, but the disclosure is not limited thereto, and other suitable molding materials may also be applicable to the disclosure.

[0026] As shown in Figure 2, a semiconductor device 100 including a mold cladding is provided according to one embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view of the semiconductor device 100 including a mold cladding.

[0027] As shown in Figure 2, the semiconductor device 100 including the mold cladding includes a lower mold 120, a plurality of semiconductor chips 180, a plurality of first metal members 200, a plurality of second metal members 210, a sealing material 220, and an upper mold 240. The semiconductor chips 180 are placed on the lower mold 120. The first metal structures 200 are placed on the lower mold 120 and are located on both sides of the semiconductor chips 180. The second metal members 210 are placed on the lower mold 120 and are located on both sides of the semiconductor chips 180. More specifically, the semiconductor chips 180, the first metal members 200, and the second metal members 210 are placed on the lower mold 120 and are in contact with the lower mold 120, with the second metal members 210 being closer to the semiconductor chips 180 than the first metal members 200. The sealing material 220 is filled between the lower mold 120 and the upper mold 240. The first metal members 200 penetrate the sealing material 220. The upper mold 240 and the lower mold 120 face each other and house the semiconductor chip 180, the first metal member 200, and the second metal member 210.

[0028] In some embodiments, the semiconductor chip 180 may include a power component, but this disclosure is not limited thereto. In some embodiments, the semiconductor chip 180 may include a substrate 260, a first metal layer 280, a second metal layer 300, a conductive component 320, and a chip 330. The first metal layer 280 is located below the substrate 260, the second metal layer 300 is located above the substrate 260, the first metal layer 280 is in contact with the lower mold 120, the conductive component 320 is located on the second metal layer 300 and connected to an external circuit (not shown), and the chip 330 is located on the second metal layer 300 as shown in Figure 2.

[0029] In some embodiments, the first metal member 200 may include a columnar metal structure, for example, a cylindrical metal structure, but the present invention is not limited thereto, and other suitable three-dimensional shapes are also applicable to this disclosure and can be designed according to product requirements. In some embodiments, there may be a plurality of first metal members 200 between adjacent semiconductor chips 180, for example, an even number of first metal members 200 between adjacent semiconductor chips 180 such that the semiconductor device formed after cutting has symmetrical through-holes for subsequent screw mounting, but the present disclosure is not limited thereto, and other suitable positions and quantities of first metal members 200 are also applicable to this disclosure and can be designed according to product requirements.

[0030] In some embodiments, the second metal member 210 may include a columnar metal structure, for example, a cylindrical metal structure, but the present invention is not limited thereto, and other suitable three-dimensional shapes are also applicable to this disclosure and can be designed according to product requirements. In this disclosure, the second metal member 210 is positioned at a specific location on the lower mold 120 and serves as a positioning post for transferring the semiconductor chip 180 onto the lower mold 120, so that the semiconductor chip 180 is smoothly positioned in a predetermined location on the lower mold 120.

[0031] In some embodiments, the sealing material 220 may include a solid molding material, a liquid molding material, an anisotropic conductive film (ACF), or a sheet molding material, but the disclosure is not limited thereto, and other suitable molding materials are also applicable to the disclosure.

[0032] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is provided with reference to Figures 3A to 3H. Figures 3A to 3H are schematic cross-sectional views of the method for manufacturing a semiconductor device.

[0033] As shown in Figure 3A, a carrier 14 is provided. The tape 16 is attached to the carrier 14.

[0034] As shown in Figure 3B, the semiconductor chip 18 is attached to the tape 16. The semiconductor chip 18 includes a substrate 26, a first metal layer 28, a second metal layer 30, a conductive component 32, and a chip 33. The first metal layer 28 is located below the substrate 26, and the second metal layer 30 is located above the substrate 26. The first metal layer 28 is in contact with the tape 16, the conductive component 32 is located on the second metal layer 30 for connection of subsequent external circuits, and the chip 33 is located on the second metal layer 30.

[0035] As shown in Figure 3C, multiple first metal members 20 are attached to the tape 16 so that the first metal members 20 are located on both sides of the semiconductor chip 18. The positions where the first metal members 20 are attached to the tape 16 are positions where through holes will be formed later.

[0036] As shown in Figure 3D, a lower mold 12 is provided. A carrier 14 on which the tape 16, semiconductor 18, and first metal member 20 are placed is positioned on the lower mold 12, that is, the semiconductor chip 18 and the first metal member 20 are positioned on the lower mold 12.

[0037] As shown in Figure 3E, an upper mold 24 is provided, and the upper mold 24 and the lower mold 12 face each other to house the semiconductor chip 18 and the first metal member 20. After the upper mold 24 and the lower mold 12 are pressed together, sealing material 22 is injected and filled between the lower mold 12 and the upper mold 24.

[0038] As shown in Figure 3F, after filling with the sealing material 22, the upper mold 24, lower mold 12, first metal member 20, carrier 14, and tape 16 are removed, and multiple through holes 34 are formed in the sealing material 22 located on both sides of the semiconductor chip 18.

[0039] As shown in Figure 3G, the sealing material 22 is cut, for example by laser cutting, to form a plurality of first semiconductor devices 36. Each first semiconductor device 36 includes a semiconductor chip 18, a sealing material 22 covering the semiconductor chip 18, and a through hole 34 penetrating the sealing material 22.

[0040] As shown in Figure 3H, in each first semiconductor device 36, the encapsulating material 22 has a first sidewall 22a and a second sidewall 22b, the second sidewall 22b is located on the opposite side of the semiconductor chip 18 from the first sidewall 22a, and the first sidewall 22a and the second sidewall 22b make a 90-degree angle with the horizontal plane P. The first angle α1 between the first sidewall 22a of the encapsulating material 22 and the horizontal plane P is 90 degrees, and the second angle α2 between the second sidewall 22b of the encapsulating material 22 and the horizontal plane P is 90 degrees. At this point, the manufacturing of the disclosed semiconductor device is completed.

[0041] Figures 4A to 4F provide a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. Figures 4A to 4F are schematic cross-sectional views of the method for manufacturing a semiconductor device.

[0042] As shown in Figure 4A, a carrier 140 is provided. Multiple semiconductor chips 180 are arranged on the carrier 140. The semiconductor chip 180 includes a substrate 260, a first metal layer 280, a second metal layer 300, a conductive component 320, and a chip 330. The first metal layer 280 and the second metal layer 300 are arranged on both sides of the substrate 260, the conductive component 320 is arranged on the second metal layer 300 for connection of subsequent external circuits, and the chip 330 is arranged on the second metal layer 300.

[0043] As shown in Figure 4B, a lower mold 120 is provided. Multiple second metal members 210 are positioned at specific locations on the lower mold 120 and serve as positioning posts for transferring the semiconductor chip 180 from the carrier 140 onto the lower mold 120. The second metal members 210 positioned on the lower mold 120 transfer the semiconductor chip 180 onto the lower mold 120 and position the semiconductor chip 180 in a predetermined location on the lower mold 120.

[0044] As shown in Figure 4C, an upper mold 240 is provided. A first metal member 200 is fixed to the upper mold 240. The upper mold 240 and the lower mold 120, to which the first metal member 200 is fixed, face each other and house the semiconductor chip 180, the first metal member 200, and the second metal member 210. That is, the semiconductor chip 180, the first metal member 200, and the second metal member 210 are placed on the lower mold 120, with the first metal member 200 and the second metal member 210 located on either side of the semiconductor chip 180, and the second metal member 210 being closer to the semiconductor chip 180 than the first metal member 200. The position of the first metal member 200 is such that a through hole will be formed thereafter. After the upper mold 240 and the lower mold 120 are pressed together, a sealing material 220 is injected and filled between the lower mold 120 and the upper mold 240.

[0045] As shown in Figure 4D, after filling with the sealing material 220, the upper mold 240, lower mold 120, first metal member 200, and second metal member 210 are removed, forming a plurality of through holes 340 and a plurality of positioning holes 380 within the sealing material 220. The through holes 340 and positioning holes 380 are located on both sides of the semiconductor chip 180, respectively, with the positioning holes 380 being closer to the semiconductor chip 180 than the through holes 340.

[0046] As shown in Figure 4E, the sealing material 220 is cut, for example by laser cutting, to form a plurality of second semiconductor devices 360. Each second semiconductor device 360 ​​includes a semiconductor chip 180, a sealing material 220 covering the semiconductor chip 180, a through hole 340 penetrating the sealing material 220, and a positioning hole 380 adjacent to the semiconductor chip 180.

[0047] As shown in Figure 4F, in each second semiconductor device 360, the encapsulating material 220 has a first sidewall 220a and a second sidewall 220b, the second sidewall 220b is located on the opposite side of the semiconductor chip 180 from the first sidewall 220a, and the first sidewall 220a and the second sidewall 220b make a 90-degree angle with the horizontal plane P. The first angle β1 between the first sidewall 220a of the encapsulating material 220 and the horizontal plane P is 90 degrees, and the second angle β2 between the second sidewall 220b of the encapsulating material 220 and the horizontal plane P is 90 degrees. At this point, the manufacturing of the disclosed semiconductor device is completed.

[0048] This disclosure demonstrates that when manufacturing products of different sizes or with different structural characteristics, it is not necessary to design different molds; in other words, the same mold can be used for different products, and the required products can be manufactured simply by designing a structurally removable post and a subsequent cutting process. The process technology disclosed herein enhances mold commonality and reduces mold development costs. Furthermore, since it is not necessary to design the structural characteristics of the product on the mold, the structural strength of the mold is improved, and the durability of the mold is enhanced. In addition, this disclosure overcomes the limitations of conventional manufacturing processes by easily manufacturing products with vertical sides using a post-release cutting molding technique.

[0049] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to accomplish the same objectives and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures will not deviate from the spirit and scope of the present disclosure, and that they may be modified, substituted, and replaced herein in various ways without departing from the spirit and scope of the present disclosure. Accordingly, the scope of protection must be determined through the claims. Furthermore, although several embodiments of the present disclosure are disclosed above, they are not intended to limit the scope of the present disclosure.

[0050] References to features, benefits, or similar language throughout this Specification do not imply that all features and benefits that may be realized in this Disclosure should or may be realized in any single embodiment of this Disclosure. Rather, the language referring to features and benefits should be understood to mean that certain features, benefits, or characteristics described in relation to an embodiment are included in at least one embodiment of this Disclosure. Accordingly, discussions of features and benefits, as well as similar language, throughout this Specification may, but not necessarily, refer to the same embodiment.

[0051] Furthermore, in one or more embodiments, the described features, benefits, and characteristics of this disclosure may be combined in any suitable manner. Those skilled in the art will recognize, based on the description herein, that this disclosure can be implemented without one or more specific features or benefits of a particular embodiment. In other examples, additional features and benefits that may not be present in all embodiments of this disclosure may be recognized in a particular embodiment. [Explanation of Symbols]

[0052] Semiconductor devices including 10,100 mold cladding 12, 120 Lower mold 14,140 carriers 16 tapes 18, 180 Multiple semiconductor chips 20,200 Multiple first metal members 22, 220 Sealing material 22a, 220a First sidewall of the sealing material 22b, 220b Second sidewall of the sealing material 24, 240 Upper mold 26,260 circuit boards 28, 280 1st metal layer 30, 300 second metal layer 32,320 conductive components 33,330 chips 34, 340 through holes 36 First Semiconductor Device 210 Second metal member 360 Second Semiconductor Device 380 positioning holes P Horizontal plane α1, β1 First angle between the first side wall of the sealing material and the horizontal plane α2, β2 Second clamping angle between the second sidewall of the sealing material and the horizontal plane

Claims

1. Steps include providing the lower mold, The steps of arranging a plurality of semiconductor chips on the lower mold, A plurality of first metal members are arranged on the lower mold, and the first metal members are steps located on both sides of the semiconductor chip. A step of providing an upper mold that faces the lower mold and houses the semiconductor chip and the first metal member, A step of filling the space between the lower mold and the upper mold with sealing material, The steps include removing the upper mold, the lower mold, and the first metal member, and forming a plurality of through holes located on both sides of the semiconductor chip within the sealing material, A method for manufacturing a semiconductor device, comprising the step of cutting the sealing material to form a plurality of semiconductor devices, wherein each semiconductor device includes the semiconductor chip, the sealing material covering the semiconductor chip, and through holes penetrating the sealing material.

2. The step of arranging multiple semiconductor chips and multiple first metal members on the lower mold is: Steps to provide a career Steps of placing the tape on the carrier, The steps of placing the semiconductor chip and the first metal member on the tape, A method for manufacturing a semiconductor device according to claim 1, comprising the step of arranging the carrier on the lower mold.

3. The step of placing multiple semiconductor chips on the lower mold is: Steps to provide a career The steps of placing the semiconductor chip on the carrier, A method for manufacturing a semiconductor device according to claim 1, comprising the step of transferring the semiconductor chip from the carrier onto the lower mold.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor chip is fixed on the lower mold by a plurality of second metal members arranged on the lower mold.

5. The step of placing a plurality of first metal members on the lower mold is: The steps of fixing the first metal member to the upper mold, A method for manufacturing a semiconductor device according to claim 3, comprising the step of the upper mold and the lower mold facing each other.

6. The method for manufacturing a semiconductor device according to claim 5, wherein in each semiconductor device, the sealing material has a first side wall and a second side wall, the second side wall is located on the opposite side of the semiconductor chip from the first side wall, and the first side wall and the second side wall have an angle of 90 degrees with respect to the horizontal plane.

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