Calibration method for calculating the electrical characteristics of semiconductor devices, adjustment semiconductor devices used for calibration, and semiconductor devices.
The calibration method for semiconductor devices improves accuracy by using an adjustment device with enhanced heat dissipation structures to manage self-heating, addressing the challenge of inaccurate electrical characteristic calculations and performance degradation.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2024-12-06
- Publication Date
- 2026-05-20
AI Technical Summary
Existing semiconductor device calibration methods face challenges in accurately calculating electrical characteristics due to self-heating, which affects carrier mobility and reduces circuit performance such as switching speed.
A calibration method involving a semiconductor device with enhanced heat dissipation properties, including an adjustment semiconductor device with additional heat-dissipating wiring structures, is used to improve the accuracy of electrical characteristic calculations by adjusting physical constants like carrier mobility.
The method enhances the accuracy of electrical characteristic calculations and suppresses the degradation of circuit performance by effectively managing self-heating effects.
Smart Images
Figure 0007863169000001_ABST
Abstract
Description
Technical Field
[0001] The present invention particularly relates to a calibration method in the calculation of electrical characteristics of semiconductor devices such as transistors, an adjustment semiconductor device used for calibration, and a semiconductor device.
Background Art
[0002] Conventionally, as part of the circuit design of a semiconductor device, TCAD (Technology Computer Aided Design) may be performed on the semiconductor device targeted for circuit design to optimize the device structure of the semiconductor device (see, for example, Patent Document 1).
[0003] In the TCAD described in Patent Document 1, electrical characteristics such as current-voltage characteristics are calculated. Also, for a prototype of the semiconductor device targeted for circuit design, electrical characteristics such as current-voltage characteristics are measured. Then, the calculated value of the electrical characteristic and the measured value of the electrical characteristic are compared, and if the difference is not within the allowable range, calibration is performed. In calibration, for example, physical constants such as carrier mobility (or sometimes referred to as "electron mobility") are adjusted.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
[0006] This invention has been made in view of the above circumstances. Specifically, its objective is to provide a calibration method for calculating the electrical characteristics of a semiconductor device that can improve the accuracy of calculating the electrical characteristics of the semiconductor device, a calibration semiconductor device used for calibration, and a semiconductor device that can suppress the degradation of circuit performance. [Means for solving the problem]
[0007] To achieve the above objective, a calibration method for calculating the electrical characteristics of a semiconductor device according to one aspect of the present invention, a regulating semiconductor device used for calibration, and a semiconductor device have the following features.
[0008] One embodiment of the present invention, made to solve the above problems, (1) A calibration method for calculating the electrical characteristics of a target semiconductor device, which is a semiconductor device that is the subject of circuit design, The aforementioned target semiconductor device includes a target main body portion containing semiconductor elements, and a target wiring portion stacked on the target main body portion for supplying current to the semiconductor elements. A first step of measuring values relating to the electrical characteristics of an adjustment semiconductor device, which is a semiconductor device comprising an adjustment main body having substantially the same structure as the target main body and an adjustment wiring section having higher heat dissipation than the target wiring section; A second step involves adjusting predetermined physical constants, including carrier mobility, used in a first simulation for calculating values related to the electrical characteristics of the aforementioned adjustable semiconductor device. A third step involves calculating values related to the electrical characteristics of the adjustment semiconductor device using the first simulation, A fourth step involves determining whether the difference between the first measured value of the electrical characteristics obtained in the first step and the first calculated value of the electrical characteristics obtained in the third step is within a predetermined tolerance range. If the determination result in the fourth step is within the tolerance range, the fifth step involves measuring the values related to the electrical characteristics of the target semiconductor device, A sixth step involves adjusting predetermined physical constants, including carrier mobility, used in a second simulation to calculate values related to the electrical characteristics of the target semiconductor device, using the carrier mobility of the adjustment semiconductor device in the most recently performed second step; A seventh step involves calculating values related to the electrical characteristics of the target semiconductor device using the second simulation, The method is characterized by having an eighth step of determining whether the difference between the second measured value of the electrical characteristics obtained in the fifth step and the second calculated value of the electrical characteristics obtained in the seventh step is within a predetermined tolerance range. According to the calibration method described in (1) above, the first step of the calibration process (steps 1 to 2) is performed on an adjustment semiconductor device, which is a semiconductor device comprising an adjustment main body having substantially the same structure as the target main body of the target semiconductor device, and an adjustment wiring section with higher heat dissipation than the target wiring section. This improves the accuracy of physical constants with temperature coefficients, such as carrier mobility. Then, by performing a second step of the calibration process (steps 3 to 5), the accuracy of the second simulation for the target semiconductor device, which is more susceptible to the effects of self-heating than the adjustment semiconductor device, is improved, as is the accuracy of the final calculation of the electrical characteristic values of the target semiconductor device 1.
[0009] (2) A calibration semiconductor device used in the calibration method for calculating the electrical characteristics of the semiconductor device described in (1) above, The semiconductor element relating to the adjustment main body comprises a gate electrode, an active region, and an element isolation film. The active region and the element isolation film are formed in a state where they are joined together and facing each other in the horizontal direction. The gate electrode is formed at the boundary between the active region and the element isolation film, spanning both the active region and the element isolation film. The adjustment wiring portion is formed on the upper surface of the gate electrode. The adjustment wiring section includes a metal, columnar plug. The number of plugs included in the adjustment wiring section is greater than the number of metal, columnar plugs included in the target wiring section. The multiple plugs may be formed in the active region and the element isolation film area in a plan view on the upper surface of the gate electrode. In this embodiment, in particular, the number of plugs included in the adjustment wiring section is greater than the number of metal, columnar plugs included in the target wiring section, and in a plan view, the multiple plugs are formed not only in the area of the element isolation film on the upper surface of the gate electrode but also in the area of the active region, so the heat dissipation performance of the adjustment semiconductor device can be made higher than that of the target semiconductor device. (3) The adjustment semiconductor device described in (2) above, Wiring is connected to the upper ends of all plugs included in the adjustment wiring section, and a metal, columnar plug may be formed on top of the wiring. This embodiment allows for even higher heat dissipation of the adjustment semiconductor device. (4) The adjustment semiconductor device described in (2) above, The formation positions of some of the plugs included in the adjustment wiring section in a plan view may be substantially the same as the formation positions of all the plugs included in the target wiring section in a plan view. According to this embodiment, the heat dissipation of the adjustment semiconductor device can be further increased, and the structural identity between the target semiconductor device 1 and the adjustment semiconductor device can be enhanced, thereby improving the accuracy of the final calculation of the electrical characteristic values of the target semiconductor device 1.
[0010] (5) A semiconductor device comprising a semiconductor element and a wiring layer laminated on the semiconductor element for energizing the semiconductor element, The semiconductor element includes a gate electrode, an active region, and an element isolation film, The active region and the element isolation film are formed in a state of being joined to each other facing in the horizontal direction, The gate electrode is formed across the active region and the element isolation film on the boundary between the active region and the element isolation film, The wiring layer includes a plurality of metal and columnar plugs, The plurality of plugs are formed in the ranges of the active region and the element isolation film in a plan view on the upper surface of the gate electrode. According to this aspect, in particular, since the plurality of plugs are formed not only in the range of the element isolation film but also in the range of the active region on the upper surface of the gate electrode, the heat dissipation property of the semiconductor device can be enhanced. As a result, a decrease in the drain current due to self-heating can be suppressed, and a decrease in circuit performance such as switching speed can be suppressed. [Advantages of the Invention]
[0011] By the calibration method in the electrical characteristic calculation of the semiconductor device according to the present invention and the adjustment semiconductor device used for calibration, the accuracy of the electrical characteristic value calculation of the semiconductor device can be improved. Further, by the semiconductor device according to the present invention, a decrease in circuit performance such as switching speed can be suppressed. [Brief Description of the Drawings]
[0012] [Figure 1] It is a flowchart of a calibration method in the electrical characteristic calculation of a semiconductor device. [Figure 2A] It is a plan view of a target semiconductor device. [Figure 2B] It is a diagram showing a schematic structure of a cross section taken along line A-A of FIG. 2A. [Figure 2C] It is a diagram showing a schematic structure of a cross section taken along line B-B of FIG. 2B excluding an interlayer insulating film for wiring. [Figure 3A] It is a plan view of the semiconductor device for adjustment. [Figure 3B] It is a diagram showing a schematic structure of the O-O cross section of FIG. 3A. [Figure 3C] It is a diagram showing a schematic structure of the P-P cross section of FIG. 3B excluding the first interlayer insulating film. [Figure 3D] It is a diagram showing a schematic structure of the Q-Q cross section of FIG. 3B excluding the first interlayer insulating film and the second interlayer insulating film.
Embodiments for Carrying Out the Invention
[0013] (First Embodiment) Hereinafter, a calibration method in the electrical characteristic calculation of the semiconductor device according to the first embodiment of the present invention, and an adjustment semiconductor device used for calibration will be described with reference to the drawings.
[0014] First, FIG. 1 is a flowchart of a calibration method in the electrical characteristic calculation of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the calibration method is roughly divided into a first-stage calibration step (step S1) and a second-stage calibration step (step S2).
[0015] The first-stage calibration step is performed on the adjustment semiconductor device 2 described later. On the other hand, the second-stage calibration step is performed on the target semiconductor device 1 described later. The adjustment semiconductor device 2 has a heat dissipation structure added to the basic structure of the target semiconductor device 1. That is, the adjustment semiconductor device 2 is based on the target semiconductor device 1 and has higher heat dissipation than the target semiconductor device 1. The target semiconductor device 1 and the adjustment semiconductor device 2 are manufactured under the same conditions. The target semiconductor device 1 and the adjustment semiconductor device 2 will be described later.
[0016] First, the carrier mobility, as a physical constant, is determined by performing a first-stage calibration process (step S1) on the adjustment semiconductor device 2 at a preset room temperature. Next, the physical constants, including the carrier mobility, are determined on the target semiconductor device 1 by performing a second-stage calibration process (step S2) at the room temperature used in the first-stage calibration process (step S1), using the carrier mobility determined in the first-stage calibration process (step S1).
[0017] The first-stage calibration process includes a first electrical characteristic value measurement step (step S11), a first physical constant adjustment step (step S12), a first electrical characteristic value calculation step (step S13), and a first electrical characteristic value comparison step (step S14). The second-stage calibration process includes a second electrical characteristic value measurement step (step S21), a second physical constant adjustment step (step S22), a second electrical characteristic value calculation step (step S23), and a second electrical characteristic value comparison step (step S24).
[0018] In the first electrical characteristic value measurement step (step S11), predetermined values related to electrical characteristics (electrical characteristic values), such as the threshold value and drain current of the adjustment semiconductor device 2, are measured at a predetermined room temperature.
[0019] In the first physical constant adjustment step (step S12), predetermined physical constants such as carrier mobility, gate capacitance, wiring resistivity, diffusion constant of impurities during manufacturing, and relative permittivity of the oxide film of the adjustment semiconductor device 2, which will be used (in simulation) in the subsequent first electrical characteristic value calculation step (step S13), are adjusted and provisionally determined. However, in the first physical constant adjustment step (step S12) of the first stage calibration process, the physical constants are not adjusted, and default values are used.
[0020] In the first electrical characteristic value calculation step (step S13), the electrical characteristic values of the adjustment semiconductor device 2 are calculated by performing TCAD on the adjustment semiconductor device 2. It is assumed that, prior to performing the first electrical characteristic value calculation step (step S13), structural conditions such as the gate length and gate oxide thickness of the LDMOS (Laterally Diffused MOS) constituting the adjustment main body 20 included in the adjustment semiconductor device 2 (described later), as well as process conditions such as the dielectric constant of the silicon oxide film, the dose and energy of ion implantation into the source and drain, and the annealing temperature and time, are provided.
[0021] In the first electrical characteristic value comparison step (step S14), various electrical characteristic values measured in the first electrical characteristic value measurement step (step S11) (first electrical characteristic measured values) are compared with various electrical characteristic values calculated in the first electrical characteristic value calculation step (step S13) (first electrical characteristic calculated values), and it is determined whether the difference between various first electrical characteristic measured values and first electrical characteristic calculated values (first specific electrical difference) is within the range of the permissible error predetermined for each type of electrical characteristic.
[0022] In the first electrical characteristic value comparison step (step S14), if it is determined that all types of first specific electrical differences are within the allowable error range, the first calibration step (step S1) is completed and the process proceeds to the second calibration step (step S2).
[0023] On the other hand, if it is determined in the first electrical characteristic value comparison step (step S14) that any type of first specific electrical difference is outside the range of the allowable error, the process returns to the first physical constant adjustment step (step S12). In other words, the process from the first physical constant adjustment step (step S12) to the first electrical characteristic value comparison step (step S14) is repeated until it is determined that all types of first specific electrical differences are within the range of the allowable error.
[0024] In the second and subsequent first physical constant adjustment steps (step S12), some or all of the physical constants are adjusted and provisionally determined, taking into account the most recently performed first electrical specific difference.
[0025] Furthermore, if it is determined in the first electrical characteristic value comparison step (step S14) that all types of first specific electrical differences are within the allowable error range, the various physical constants provisionally determined in the most recent first physical constant adjustment step (step S12) are determined to be the various physical constants of the adjustment semiconductor device 2. In particular, regarding carrier mobility, as will be described later, the adjustment semiconductor device 2 has higher heat dissipation than the target semiconductor device 1, and the effect of self-heating is considered to be extremely small, so the room temperature at that time is fixed as the temperature of the carrier mobility.
[0026] In the second electrical characteristic value measurement step (step S21), the electrical characteristic values of the target semiconductor device 1 are measured at the same room temperature as in the first electrical characteristic value measurement step (step S11).
[0027] In the second physical constant adjustment step (step S22), predetermined physical constants such as the gate capacitance, wiring resistivity, diffusion constant of impurities during manufacturing, and relative permittivity of the oxide film of the target semiconductor device 1 (in simulation) used in the subsequent second electrical characteristic value calculation step (step S23) are adjusted and provisionally determined. However, in the first second physical constant adjustment step (step S22) in the second calibration step, the physical constants are not adjusted, and the various physical constants determined in the first calibration step are used.
[0028] In the second electrical characteristic value calculation step (step S23), the electrical characteristic values of the target semiconductor device 1 are calculated by performing TCAD on the target semiconductor device 1. It is assumed that, prior to performing the second electrical characteristic value calculation step (step S23), structural conditions such as the gate length and gate oxide thickness of the LDMOS constituting the target main body 10 included in the target semiconductor device 1 (described later), as well as process conditions such as the dielectric constant of the silicon oxide film, the dose and energy of ion implantation into the source and drain, and the annealing temperature and time, are provided. Furthermore, the structural conditions such as the gate length and gate oxide thickness of the LDMOS constituting the target main body 10 included in the target semiconductor device 1, the dielectric constant of the silicon oxide film, the dose and energy of ion implantation into the source and drain, and the annealing temperature and time are the same as those of the LDMOS constituting the adjustment main body 20 included in the adjustment semiconductor device 2, the dielectric constant of the silicon oxide film, the dose and energy of ion implantation into the source and drain, and the annealing temperature and time.
[0029] In the second electrical characteristic value comparison step (step S24), the electrical characteristic values measured in the second electrical characteristic value measurement step (step S21) (second electrical characteristic measured values) are compared with the electrical characteristic values calculated in the second electrical characteristic value calculation step (step S23) (second electrical characteristic calculated values), and it is determined whether the difference between each type of second electrical characteristic measured value and the second electrical characteristic calculated value (second electrical specific difference) is within the range of the permissible error predetermined for each type of electrical characteristic.
[0030] In the second electrical characteristic value comparison step (step S24), if it is determined that all types of second specific electrical differences are within the allowable error range, the second-stage calibration step (step S2) is completed, and the calibration method is finished.
[0031] On the other hand, if it is determined in the second electrical characteristic value comparison step (step S24) that any type of second specific electrical difference is outside the range of the allowable error, the process returns to the second physical constant adjustment step (step S22). In other words, the process from the second physical constant adjustment step (step S22) to the second electrical characteristic value comparison step (step S24) is repeated until it is determined that all types of second specific electrical differences are within the range of the allowable error.
[0032] In the second and subsequent second physical constant adjustment steps (step S22), some or all physical constants are adjusted and provisionally determined, taking into account the most recently performed second electrical specific difference. However, the carrier mobility remains unchanged from the value provisionally determined in the first physical constant adjustment step (step S12) performed at the end of the first stage calibration step (step S1).
[0033] Furthermore, if it is determined in the second electrical characteristic value comparison step (step S24) that all types of second specific electrical differences are within the allowable error range, the various physical constant parameters provisionally determined in the most recent second physical constant adjustment step (step S22) are determined as the various physical constant parameters of the target semiconductor device 1.
[0034] Next, the target semiconductor device 1 and the adjustment semiconductor device 2 will be described. First, the target semiconductor device 1 will be described. Figure 2A is a plan view of the target semiconductor device 1, Figure 2B is a diagram showing the schematic structure of the AA cross-section of Figure 2A, and Figure 2C is a diagram showing the BB cross-section of Figure 2B, which shows the schematic structure excluding the interlayer film of the wiring described later. For convenience, in the following, the front-to-back direction, left-to-right direction, and up-and-down direction will be defined based on "front," "right," and "up" as described in Figures 2A, 2B, and 2C, but the relationship between these directions and the orientation of the target semiconductor device 1 is not limited to the embodiments described below.
[0035] The target semiconductor device 1 comprises a target main body portion 10 and a target wiring portion 11. More specifically, the target semiconductor device 1 has a two-layer structure in which the target wiring portion 11 is formed on the upper surface of the target main body portion 10.
[0036] The target main body 10 consists of a known N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The target main body 10 includes a support substrate 101, an SOI substrate insulating film 102, a drift layer 103, a P-type diffusion layer 104, an element isolation film 105, a drain 106, a source 107, a gate electrode 108, and a gate insulating film 109. In Figure 2B, the gate electrode 108 and the gate insulating film 109 appear to be included in the target wiring section 11 in terms of arrangement, but this is for convenience only, and they are actually included in the target main body 10.
[0037] The support substrate 101 is formed in the lowest layer of the target main body 10, extending from both the left and right ends. An SOI substrate insulating film 102 is laminated on the support substrate 101. The SOI substrate insulating film 102 is also formed extending from both the left and right ends of the target main body 10. A drift layer 103 and a P-type diffusion layer 104 are laminated on the SOI substrate insulating film 102.
[0038] Relatively speaking, the drift layer 103 is positioned on the right side, and the P-type diffusion layer 104 is positioned on the left side. The drift layer 103 and the P-type diffusion layer 104 are formed in a state where they face each other and are joined in the left-right direction, on the opposite side from the element isolation film 105, which will be described later. The left-right length of the drift layer 103 is longer than the left-right length of the P-type diffusion layer 104.
[0039] An element isolation film 105 is formed on the upper surface of the drift layer 103, approximately in the center in the left-right direction. That is, the element isolation film 105 is formed in such a manner that it is fitted onto the upper side of the drift layer 103, so that the cross-sectional shape of the drift layer 103 is approximately a horizontally elongated U-shape. In other words, the drift layer 103, which is the active region, and the element isolation film 105 are formed in a state where they are facing each other and joined in the left-right direction.
[0040] A drain 106 is formed on the upper surface of the right end of the drift layer 103. In other words, the drift layer 103 is joined to the drain 106 at the upper surface of its right end.
[0041] The upper surface of the drain 106 and the upper surface of the element isolation film 105 are flush. The element isolation film 105 is bonded to the drain 106 and the drift layer 103 on its right side.
[0042] The upper surface of the left end of the drift layer 103 and the upper surface of the element isolation film 105 are flush. The element isolation film 105 is bonded to the drift layer 103 on its left side.
[0043] A source 107 is formed on the upper surface of approximately the left half of the P-type diffusion layer 104. The source 107 consists of an N-type source 107A and a P-type source 107B. Relatively, the N-type source 107A is positioned on the right side, and the P-type source 107B is positioned on the left side. The N-type source 107A and the P-type source 107B are joined to each other. Furthermore, the N-type source 107A and the P-type source 107B are joined to the P-type diffusion layer 104 at their bottom surfaces. The left-right length of the N-type source 107A and the left-right length of the P-type source 107B are approximately the same. Also, the thickness of the N-type source 107A and the P-type source 107B are approximately the same.
[0044] The upper surfaces of the N-type source 107A, the P-type source 107B, and the P-type diffusion layer 104 are flush. Therefore, the N-type source 107A is bonded to the P-type diffusion layer 104 on its right side.
[0045] A gate electrode 108 is laminated on the upper surfaces of the P-type diffusion layer 104, the drift layer 103, and the device isolation film 105 via a gate insulating film 109. In other words, the gate electrode 108 is formed across the device isolation film 105 and the drift layer 103 at the boundary (junction surface) between the device isolation film 105 and the active region, the drift layer 103. More specifically, the gate electrode 108 laminated on the gate insulating film 109 is formed across the left half of the upper surface of the device isolation film 105 and the entire left upper surface of the P-type diffusion layer 104, and further extends to the right half of the upper surface of the P-type diffusion layer 104 in the left-right direction.
[0046] In the first embodiment, the support substrate 101 is made of P-type silicon, the drain 106 is made of N-type semiconductor, the N-type source 107A is made of N-type semiconductor, the P-type source 107B is made of P-type semiconductor, and the gate electrode 108 is made of polycrystalline silicon. The drift layer 103 is a so-called "N-well" and is made of N-type semiconductor. The P-type diffusion layer 104 is a so-called "P-body" and is made of P-type semiconductor. The SOI substrate insulating film 102, the device isolation film 105, and the gate insulating film 109 are made of silicon oxide (SiO2).
[0047] For example, the thickness of the P-type diffusion layer 104 is 0.3 to 3 μm, and the charge density during ion implantation of the P-type diffusion layer 104 is 5E15 to 3E16 / cm². 2 Similarly, the thickness of the drift layer 103 is 0.3 to 3 μm, and the charge density on the surface of the drift layer 103 is 5E15 to 3E16 / cm². 2 Furthermore, the charge density on the surface of drain 106 and N-type source 107A is 5E19~5E20 / cm³. 2 Furthermore, the charge density on the surface of the P-type source 107B is 5E19~5E20 / cm³. 2 Therefore, the P-type diffusion layer 104 and the P-type source 107B are fixed at the same potential, resulting in a so-called "butting contact."
[0048] Furthermore, the thickness of the element isolation film 105 is 0.3 to 1 μm, and the thickness of the gate insulating film 109 is 0.1 to 0.5 μm. The SOI substrate insulating film 102 consists of a buffer oxide film with a thickness of 100 nm to 500 nm and an N-type silicon layer with a thickness of 0.3 μm to 3 μm formed on its surface.
[0049] The target wiring section 11 is a known general wiring structure. Specifically, the target wiring section 11 has a plug 111, wiring 112, and an inter-wire layer film 113.
[0050] The plug 111 is formed in a columnar shape that extends vertically. The plug 111 includes multiple (three in the first embodiment) gate plugs 111A, multiple (five in the first embodiment) drain plugs 111B, and multiple (five in the first embodiment) source plugs 111C.
[0051] Multiple gate plugs 111A (three in the first embodiment) are each formed on the upper right end of the gate electrode 108, in other words, on the upper surface of the element isolation film 105 via the gate insulating film 109 and the gate electrode 108, and are arranged side by side, spaced apart from each other in the front-to-back direction. Multiple drain plugs 111B (five in the first embodiment) are each formed on the upper surface of the drain 106, and are arranged side by side, spaced apart from each other in the front-to-back direction. Multiple source plugs 111C (five in the first embodiment) are each formed spanning the upper surface of the N-type source 107A and the upper surface of the P-type source 107B, and are arranged side by side, spaced apart from each other in the front-to-back direction.
[0052] Wiring 112 includes gate wiring 112A, drain wiring 112B, and source wiring 112C. Gate wiring 112A is connected to the upper end of all gate plugs 111A. Drain wiring 112B is connected to the upper end of all drain plugs 111B. Source wiring 112C is connected to the upper end of all source plugs 111C.
[0053] However, the plan view shapes of the gate wiring 112A, drain wiring 112B, and source wiring 112C are set appropriately within a range where the gate wiring 112A, drain wiring 112B, and source wiring 112C do not short-circuit with each other, and the gate wiring 112A, drain wiring 112B, and source wiring 112C do not short-circuit with each other. The solid lines and dashed lines (dotted lines) related to the gate wiring 112A, drain wiring 112B, and source wiring 112C shown in Figures 2B and 2C represent the range where the wiring is formed.
[0054] The inter-wire layer film 113 is deposited to a position higher than the upper surface of the wiring 112. The inter-wire layer film 113 is substantially filled in the upper part of the target main body 10, excluding the plug 111 and the wiring 112. In other words, the inter-wire layer film 113 insulates between the gate plug 111A, the drain plug 111B, and the source plug 111C, between the gate wiring 112A, the drain wiring 112B, and the source wiring 112C, and between the plug 111 and the wiring 112.
[0055] In the first embodiment, the gate plug 111A, drain plug 111B, and source plug 111C are so-called "tungsten plugs" and are mainly made of tungsten. However, a barrier metal made of titanium nitride or the like is formed at the bottom of the gate plug 111A, drain plug 111B, and source plug 111C to a predetermined thickness. The gate wiring 112A, drain wiring 112B, and source wiring 112C are made of aluminum. The inter-wiring layer film 113 is made of silicon oxide film.
[0056] Next, the adjustment semiconductor device 2 will be described. Figure 3A is a plan view of the adjustment semiconductor device 2, Figure 3B shows the schematic structure of the OO cross-section of Figure 3A, Figure 3C shows the P-P cross-section of Figure 3B, excluding the first interconnection film 213 which will be described later, and Figure 3D shows the Q-Q cross-section of Figure 3B, excluding the first interconnection film 213 and the second interconnection film 223 which will be described later. For convenience, in the following, the front-to-back direction, left-to-right direction, and up-and-down direction will be defined based on "front," "right," and "up" as described in Figures 3A, 3B, 3C, and 3D, but the relationship between these directions and the orientation of the adjustment semiconductor device 2 is not limited to the embodiments described below.
[0057] The adjustment semiconductor device 2 comprises an adjustment main body 20, an adjustment first wiring section 21, an adjustment second wiring section 22, and an adjustment third wiring section 23. More specifically, the adjustment semiconductor device 2 has a four-layer structure in which the adjustment first wiring section 21, the adjustment second wiring section 22, and the adjustment third wiring section 23 are stacked in order on top of the adjustment main body 20.
[0058] The adjustment body 20 consists of a known N-channel power MOSFET and has the same structure as the target body 10. Therefore, the adjustment body 20 has a support substrate 201, SOI substrate insulating film 202, drift layer 203, P-type diffusion layer 104, element isolation film 105, drain 106, source 107, gate electrode 108, and gate insulating film 209 that are configured identically to the support substrate 101, SOI substrate insulating film 202, drift layer 203, P-type diffusion layer 204, element isolation film 205, drain 206, source 207, gate electrode 208, and gate insulating film 209 of the target body 10 in terms of shape, dimensions, and material.
[0059] Furthermore, the drift layer 203, which is the active region, and the element isolation film 205 are formed in a state where they are joined to each other in the horizontal direction. Moreover, the drift layer 203 and the P-type diffusion layer 204 are formed in a state where they are joined to each other in the left-right direction, on the opposite side from the element isolation film 205, which will be described later. The gate electrode 208 is formed on the boundary (junction surface) between the element isolation film 205 and the drift layer 203, which is the active region, and extends across the element isolation film 205 and the drift layer 203, and also into the P-type diffusion layer 204.
[0060] The first adjustment wiring section 21 is a known general wiring structure. Specifically, the first adjustment wiring section 21 has a first plug 211, a first wiring 212, and a first wiring interlayer film 213.
[0061] The first plug 211 is formed in a columnar shape that extends vertically. The first plug 211 includes a plurality of (49 in the first embodiment) first gate plugs 211A, a plurality of (5 in the first embodiment) first drain plugs 211B, and a plurality of (5 in the first embodiment) first source plugs 211C.
[0062] Multiple (49 in the first embodiment) first gate plugs 211A are formed two-dimensionally across the entire upper surface of the gate electrode 208, and are scattered apart from each other in a grid pattern consisting of seven plugs at approximately equal intervals in the left-right direction and seven plugs at approximately equal intervals in the front-back direction. That is, multiple first gate plugs 211A are formed on the upper surfaces of the drift layer 203, the P-type diffusion layer 204, and the element isolation film 205, respectively, via the gate electrode 208 and the gate insulating film 209.
[0063] Among the multiple (49 in the first embodiment) first gate plugs 211A, the three central positions in the front-to-back direction at the right end are the same as the positions where gate plugs 111A are formed on the upper surface of the gate electrode 108 related to the target wiring section 11. Furthermore, each first gate plug 211A has the same structure as the gate plug 111A of the target wiring section 11. Therefore, in the adjustment first wiring section 21, first gate plugs 211A are formed on the upper surface of the gate electrode 208 at the positions of the gate plugs 111A related to the target wiring section 11 and at other locations.
[0064] Multiple (five in the first embodiment) first drain plugs 211B are formed on the upper surface of the drain 206 and are arranged side by side, spaced apart from each other in the front-to-back direction. The positions where the first drain plugs 211B are formed on the upper surface of the drain 206 are the same as the positions where the drain plugs 111B are formed on the upper surface of the drain 106 related to the target wiring section 11. Furthermore, each first drain plug 211B has the same structure as the drain plug 111B of the target wiring section 11.
[0065] Multiple (five in the first embodiment) first source plugs 211C are formed spanning the upper surface of the N-type source 107A and the upper surface of the P-type source 107B, and are arranged side by side, spaced apart from each other along the front-to-back direction. The positions where the first source plugs 211C are formed on the upper surface of the source 207 are the same as the positions where the source plugs 111C are formed on the upper surface of the source 107 relating to the target wiring section 11. Furthermore, each first source plug 211C has the same structure as the source plug 111C of the target wiring section 11.
[0066] The first wiring 212 includes a first gate wiring 212A, a first drain wiring 212B, and a first source wiring 212C. The first gate wiring 212A is connected to the upper end of all first gate plugs 211A. The first drain wiring 212B is connected to the upper end of all first drain plugs 211B. The first source wiring 212C is connected to the upper end of all first source plugs 211C.
[0067] Furthermore, the plan view shapes of the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C are set appropriately within a range where the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C do not short-circuit with each other, and the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C do not short-circuit with each other. In Figures 3B and 3C, the solid lines and dashed lines (dotted lines) relating to the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C represent the range in which the wiring is formed.
[0068] Furthermore, the lateral length of the area where the first gate wiring 212A is formed is longer than the lateral length of the gate electrode 208, and the longitudinal length of the area where the first gate wiring 212A is formed is longer than the longitudinal length of the gate electrode 208. In the first embodiment, the left end of the area where the first gate wiring 212A is formed and the left end of the gate electrode 208 are aligned at approximately the same position. On the other hand, the right end of the area where the first gate wiring 212A is formed is located to the right of the right end of the gate electrode 208. Also, the front end of the area where the first gate wiring 212A is formed is located in front of the front end of the gate electrode 208, and the rear end of the area where the first gate wiring 212A is formed is located behind the rear end of the gate electrode 208.
[0069] The first wiring interlayer film 213 is deposited in the vertical direction up to approximately the same position as the lower surface of the first wiring 212. The first wiring interlayer film 213 is substantially filled in the portion of the adjustment body 20 excluding the upper first plug 211 and the first wiring 212. In other words, the first wiring interlayer film 213 insulates the first gate plug 211A, the first drain plug 211B, and the first source plug 211C, and the first plug 211 and the first wiring 212.
[0070] In the first embodiment, the first gate plug 211A, the first drain plug 211B, and the first source plug 211C are so-called "tungsten plugs" and are mainly made of tungsten. However, a barrier metal made of titanium nitride or the like is formed to a predetermined thickness at the bottom of the first gate plug 211A, the first drain plug 211B, and the first source plug 211C. The first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C are made of aluminum. The first interlayer film 213 is made of silicon oxide.
[0071] The second adjustment wiring section 22 is a known general wiring structure. Specifically, the second adjustment wiring section 22 has a second plug 221, a second wiring 222, and a second wiring interlayer film 223.
[0072] The second plug 221 is formed in a columnar shape that extends vertically. The second plug 221 has multiple (72 in the first embodiment) second gate plugs 221A. The second adjustment wiring section 22 does not have anything equivalent to the first drain plug 211B and the first source plug 211C in the first adjustment wiring section 21.
[0073] Multiple (72 in the first embodiment) second gate plugs 221A are formed two-dimensionally across the entire upper surface of the first gate wiring 212A, and are scattered apart from each other in a grid pattern consisting of 8 at equal intervals in the left-right direction and 9 at equal intervals in the front-back direction. Of these, 49 positions, consisting of 7 rows excluding the rightmost row in the left-right direction, and 7 rows excluding the frontmost and rearmost rows in the front-back direction, are the same as the positions where the first gate plugs 211A are formed on the upper surface of the gate electrode 208 related to the adjustment first wiring section 21. Therefore, in the adjustment second wiring section 22, second gate plugs 221A are formed on the upper surface of the first gate plugs 211A related to the adjustment first wiring section 21, both at the positions of each first gate plug 211A related to the adjustment first wiring section 21 and at other locations. Furthermore, the shape of each second gate plug 221A is substantially the same as the shape of each first gate plug 211A of the adjustment first wiring section 21.
[0074] The second wiring 222 has a second gate wiring 222A. The second gate wiring 222A is connected to the upper end of all second gate plugs 221A. The second adjustment wiring section 22 does not have anything equivalent to the first drain plug 211B and the first source plug 211C in the first adjustment wiring section 21, and therefore naturally does not have anything equivalent to the first drain wiring 212B and the first source wiring 212C in the first adjustment wiring section 21.
[0075] Furthermore, the plan view shape of the second gate wiring 222A shall be set appropriately within a range that does not cause a short circuit. The solid lines related to the second gate wiring 222A shown in Figures 3B and 3C represent the range in which the wiring is formed.
[0076] The second wiring interlayer film 223 is deposited in the vertical direction up to approximately the same position as the lower surface of the second wiring 222. The second wiring interlayer film 223 is substantially filled in the portion between the lower surface of the first wiring 212 relating to the adjustment first wiring section 21 and the lower surface of the second wiring 222 relating to the adjustment second wiring section 22, excluding the first wiring 212 and the second plug 221. In other words, the second wiring interlayer film 223 insulates between the first wiring 212, between the second gate plugs 221A, between the second plug 221 and the first wiring 212, and between the second plug 221 and the second wiring 222.
[0077] In the first embodiment, the second gate plug 221A is made of tungsten. The second gate wiring 222A is made of aluminum. The second wiring interlayer film 223 is made of silicon oxide film.
[0078] The third adjustment wiring section 23 is a known general wiring structure. Specifically, the third adjustment wiring section 23 has a third plug 231, a third wiring 232, and a third wiring interlayer film 233.
[0079] The third plug 231 has the same structure as the second plug 221 related to the adjustment second wiring section 22. That is, the third plug 231 has multiple (72 in the first embodiment) third gate plugs 231A. These multiple (72 in the first embodiment) third gate plugs 231A are formed two-dimensionally across the entire upper surface of the second gate wiring 222A, and are scattered apart from each other in a grid pattern consisting of eight equally spaced in the left-right direction and nine equally spaced in the front-back direction. In a plan view, the positions where the multiple (72 in the first embodiment) third gate plugs 231A are formed are substantially the same as the positions where the multiple (72 in the first embodiment) second gate plugs 221A are formed.
[0080] The third wiring 232 has substantially the same structure as the second wiring 222 related to the adjustment second wiring section 22. That is, the third wiring 232 has a third gate wiring 232A. The shape of the third wiring 232 in plan view is substantially the same as the second wiring 222 related to the adjustment second wiring section 22 in plan view. The solid line related to the third gate wiring 232A shown in Figure 3B represents the area where the wiring is formed.
[0081] The third wiring interlayer film 233 is deposited to a position higher than the upper surface of the third wiring 232. The third wiring interlayer film 233 is substantially filled in the portion of the second wiring 222 related to the adjustment second wiring section 22 that is above the lower surface of the second wiring 222, the third plug 231, and the third wiring 232. In other words, the third wiring interlayer film 233 insulates between the second wiring 222, between the third gate plugs 231A, between the third wiring 232, between the third plug 231 and the second wiring 222, and between the third plug 231 and the third wiring 232.
[0082] In Figure 3B, the first inter-layer film 213 is shown to be deposited to approximately the same height as the lower surface of the first wiring 212, the second inter-layer film 223 is shown to be deposited to approximately the same height as the lower surface of the second wiring 222, and the third inter-layer film 233 is shown to be deposited to a position higher than the upper surface of the third wiring 232. However, structurally, the inter-layer films 213, 223, and 233 may be treated as a single unit without clearly distinguishing between them.
[0083] Next, the heat dissipation properties of the target semiconductor device 1 and the adjustment semiconductor device 2 will be described. When a voltage is applied to the gate electrodes 108 and 208, a current flows between the SOI substrate insulating film 102 and 202 and the element isolation film 105 and 205 of the drift layers 103 and 203, causing the drift layers 103 and 203 to self-heat.
[0084] Incidentally, the thermal conductivity of SiO2, which is the silicon oxide film constituting the SOI substrate insulating film 102·202, the element isolation film 105·205, and the gate insulating film 109·209, as well as the wiring interlayer film 113, the first wiring interlayer film 213, the second wiring interlayer film 223, and the third wiring interlayer film 233, is 1.38 W / m·k, while the thermal conductivity of silicon constituting most of the drift layer 103·203 and the gate electrode 108·208 is 160 W / m·k. In other words, the thermal conductivity of the element isolation film 105·205, etc., is very low, both relatively and absolutely, compared to the thermal conductivity of the drift layer 103·203, etc. Therefore, considering only the main body portion 10 of the target semiconductor device 1 and the adjustment main body portion 20 of the adjustment semiconductor device 2, heat dissipation from the drift layer 103·203 is difficult because the drift layer 103·203 is sandwiched between silicon oxide films on the top and bottom. Therefore, when the drift layers 103 and 203 generate their own heat, the internal temperature of the drift layers 103 and 203 rises.
[0085] On the other hand, the thermal conductivity of the tungsten contained in plugs 111 and 211 is 198 W / m·k, and the thermal conductivity of the aluminum constituting plugs 221 and 231, and wiring 112, 212, 222, and 232 is 236 W / m·k. In other words, the thermal conductivity of plugs 111 and 211, and wiring 112 and 212, is very high, both relatively and absolutely, compared to the thermal conductivity of element isolation films 105 and 205. Therefore, the heat generated by self-heating in the drift layers 103 and 203 is dissipated through gate electrodes 108 and 208, drains 106 and 206, and sources 107 and 207.
[0086] Comparing the target semiconductor device 1 and the adjustment semiconductor device 2, the structure of the drain plug 111B and the structure of the first drain plug 211B are identical, the number of drain plugs 111B and the number of first drain plugs 211B are identical, the structure of the source plug 111C and the structure of the first source plug 211C are identical, and the number of source plugs 111C and the number of first source plugs 211C are identical. Therefore, the heat dissipation of the drain plug 111B and source plug 111C portion of the target wiring section 11 is the same as the heat dissipation of the first drain plug 211B and first source plug 211C portion of the adjustment first wiring section 21.
[0087] However, although the structure of the gate plug 111A and the structure of the first gate plug 211A are identical, the number of first gate plugs 211A is approximately 16 times the number of gate plugs 111A, and the first gate plugs 211A are also formed on the upper surface of the drift layer 203, which is the active region, and the P-type diffusion layer 204. Therefore, the heat dissipation of the portion of the first gate plug 211A related to the adjustment first wiring section 21 is much higher than the heat dissipation of the portion of the gate plug 111A related to the target wiring section 11. Furthermore, while the target semiconductor device 1 does not have a structure to improve heat dissipation on the target wiring section 11, the adjustment semiconductor device 2 has adjustment second wiring section 22 and adjustment third wiring section 23 formed on the adjustment first wiring section 21, where second gate plugs 221A and third gate plugs 231A, which have a higher thermal conductivity than the first gate plug 211A, are formed in greater numbers than the first gate plug 211A. Therefore, the heat dissipation performance of the adjustment semiconductor device 2 is significantly higher than that of the target semiconductor device 1 in relation to the self-heating in the drift layers 103 and 203.
[0088] As described above, according to the calibration method for calculating the electrical characteristics of the target semiconductor device 1 according to the first embodiment, the target semiconductor device 1 is a semiconductor device which includes a target main body 10 including an LDMOS (semiconductor element), a target wiring section 11 stacked on the target main body 10 for supplying current to the LDMOS (semiconductor element), an adjustment main body 20 having substantially the same structure as the target main body 10, and an adjustment first wiring section 21 having higher heat dissipation than the target wiring section 11, and is a semiconductor device which is a adjustment semiconductor device 2, a first electrical characteristic value measurement step (first step) for measuring the electrical characteristic values of the adjustment semiconductor device 2, a first physical constant adjustment step (second step) for adjusting predetermined physical constants including carrier mobility used in a first simulation for calculating the electrical characteristic values of the adjustment semiconductor device 2, a first electrical characteristic value calculation step (third step) for calculating the electrical characteristic values of the adjustment semiconductor device 2 by the first simulation, and the first electrical characteristic value measurement value obtained in the first electrical characteristic value measurement step (first step) and the first electrical characteristic value calculation step (third step) obtained in the first electrical characteristic value calculation step (third step) The process includes: a first electrical characteristic value comparison step (4th step) to determine whether the difference between the calculated electrical characteristic value and the calculated electrical characteristic value is within a predetermined tolerance range; a second electrical characteristic value measurement step (5th step) to measure the electrical characteristic value of the target semiconductor device 1 if the determination result in the first electrical characteristic value comparison step (4th step) is within the tolerance range; a second physical constant adjustment step (6th step) to adjust predetermined physical constants, including carrier mobility, used in a second simulation to calculate the electrical characteristic value of the target semiconductor device 1 using the carrier mobility of the adjustment semiconductor device 2 in the most recently performed first physical constant adjustment step (2nd step); a second electrical characteristic value calculation step (7th step) to calculate the electrical characteristic value of the target semiconductor device 1 by the second simulation; and a second electrical characteristic value comparison step (8th step) to determine whether the difference between the second electrical characteristic measurement value obtained in the second electrical characteristic value measurement step (5th step) and the second electrical characteristic calculation value obtained in the second electrical characteristic value calculation step (7th step) is within a predetermined tolerance range.First, by performing a first-stage calibration process (step S1: first electrical characteristic value measurement process to first electrical characteristic value comparison process) on an adjustment semiconductor device 2, which is a semiconductor device comprising an adjustment main body 20 having substantially the same structure as the target main body 10 of the target semiconductor device 1, and an adjustment first wiring section 21 with higher heat dissipation than the target wiring section 11, the accuracy of physical constants having a temperature coefficient, such as carrier mobility, can be improved. Then, by performing a second-stage calibration process (step S2: second electrical characteristic value measurement process to second electrical characteristic value measurement process) using the physical constants obtained in the first-stage calibration process (step S1: first electrical characteristic value measurement process to first electrical characteristic value comparison process), the accuracy of the second simulation for the target semiconductor device 1, which is more susceptible to the effects of self-heating than the adjustment semiconductor device 2, can be improved, as well as the accuracy of the final electrical characteristic value calculation of the target semiconductor device 1.
[0089] Furthermore, the LDMOS (semiconductor element) constituting the adjustment main body 20 of the adjustment semiconductor device 2 comprises a gate electrode 208, an active region which is a drift layer 203, a P-type diffusion layer 204, and an element isolation film 205. The drift layer 203 and the element isolation film 205 are formed in a state where they are joined to each other in the horizontal direction, and the gate electrode 208 is formed on the boundary between the drift layer 203 and the element isolation film 205, straddling the drift layer 203 and the element isolation film 205. A first adjustment wiring section 21 is formed on the upper surface of the gate electrode 208. The first adjustment wiring section 21 includes metal, columnar first gate plugs 211A. The number of first gate plugs 211A included in the first adjustment wiring section 21 is greater than the number of metal, columnar gate plugs 111A included in the target wiring section 11. Multiple first gate plugs 211A are formed in the drift layer 203 and the element isolation film 205 in a plan view on the upper surface of the gate electrode 208. Therefore, the heat dissipation performance of the adjustment semiconductor device 2 can be made higher than that of the target semiconductor device 1.
[0090] Furthermore, a first gate wiring 212A is connected to the upper end of all first gate plugs 211A included in the adjustment first wiring section 21, and a metal, columnar second gate plug 221A is formed on top of the first gate wiring 212A. Therefore, the heat dissipation of the adjustment semiconductor device 2 can be further improved. In addition, the formation positions of some of the first gate plugs 211A included in the adjustment first wiring section 21 in a plan view are substantially the same as the formation positions of all gate plugs 111A included in the target wiring section 11 in a plan view. Therefore, while further improving the heat dissipation of the adjustment semiconductor device 2, the structural identity between the target semiconductor device 1 and the adjustment semiconductor device 2 can be enhanced, thereby improving the accuracy of the final calculation of the electrical characteristic values of the target semiconductor device 1.
[0091] Furthermore, when the adjustment semiconductor device 2 is used as a semiconductor device that is used normally (incorporated into a product), the drift layer 203 and the element isolation film 205 are formed in a state where they are joined to each other in the horizontal direction, the gate electrode 208 is formed straddling the drift layer 203 and the element isolation film 205 at the boundary between the drift layer 203 and the element isolation film 205, and the adjustment first wiring section 21 includes a plurality of metal, columnar first gate plugs 211A, and the plurality of first gate plugs 211A are formed in the area of the drift layer 203 and the element isolation film 205 in a plan view on the upper surface of the gate electrode 208.Therefore, the decrease in drain current due to self-heating can be suppressed, and the decrease in circuit performance such as switching speed can be suppressed.
[0092] (modified version) The present invention has been described above based on the embodiments. These embodiments are illustrative, and it will be understood by those skilled in the art that various modifications are possible in the combination of these components, and that such modifications also fall within the scope of the present invention.
[0093] For example, in the first embodiment, the target main body 10 has a support substrate 101, an SOI substrate insulating film 102, a drift layer 103, a P-type diffusion layer 104, an element isolation film 105, a drain 106, a source 107, a gate electrode 108, and a gate insulating film 109. However, its structure and layout are not limited to the first embodiment and may be modified as appropriate.
[0094] Furthermore, while the calibration target is the target semiconductor device 1, which includes a target main body 10 consisting of an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the semiconductor elements constituting the target main body 10 are not limited to N-channel power MOSFETs. For example, other types of transistors such as P-channel power MOSFETs and bipolar transistors may be used as the target main body 10 for calibration, and may even be used as the adjustment main body 20 of the adjustment semiconductor device 2. Alternatively, power MOS transistors using the surface layer of semiconductors, such as drain-extended MOS or IGBTs (Insulated Gate Bipolar Transistors), may be used as the target main body 10 for calibration, and may even be used as the adjustment main body 20 of the adjustment semiconductor device 2. In addition, the calibration target may also be applied to P-channel LDMOS (Laterally Double Diffused MOS).
[0095] Furthermore, in the first embodiment, the number of first drain plugs 211B and first source plugs 211C is the same as the number of drain plugs 111B and source plugs 111C, but the number of one or both of the first drain plugs 211B and first source plugs 211C may be greater than the number of drain plugs 111B and source plugs 111C.
[0096] Furthermore, in the first embodiment, the formation position of the first gate plug 211A completely includes the formation position of the gate plug 111A, but while satisfying the condition that the number of first gate plugs 211A is greater than the number of gate plugs 111A, it may be partially included or not included at all.
[0097] Furthermore, although the adjustment semiconductor device 2 includes three wiring layers, the first adjustment wiring section 21 to the third adjustment wiring section 23, the number of wiring layers may be one or more, as long as the parts other than the adjustment main body section 20 have higher heat dissipation than the target wiring section 11.
[0098] Furthermore, although the target main body 10 is equipped with an SOI substrate insulating film 102, the SOI substrate insulating film 102 may be replaced with a bulk silicon substrate. The same applies to the SOI substrate insulating film 202 of the adjustment main body 20.
[0099] Furthermore, although each wire was made of aluminum in the first embodiment, it may also be made of copper. Since the thermal conductivity of copper is 398 W / m·k, copper is more effective in reducing the effects of self-heating. However, aluminum is more advantageous from the standpoint of manufacturing cost. [Explanation of Symbols]
[0100] 1...Target semiconductor device, 2...Semiconductor device for adjustment 10...Target main unit, 11...Target wiring unit 20...Main body part for adjustment, 21...First wiring part for adjustment, 22...Second wiring part for adjustment, 23...Third wiring part for adjustment 101...Support substrate, 102...SOI substrate insulating film, 103...Drift layer, 104...P-type diffusion layer, 105...Element isolation film, 106...Drain, 107...Source, 108...Gate electrode, 109...Gate insulating film 111... Plug, 111A... Gate plug, 111B... Drain plug, 111C... Source plug, 112A... Gate wiring, 112B... Drain wiring, 112C... Source wiring, 113... Interlayer film 201...Support substrate, 202...SOI substrate insulating film, 203...Drift layer, 204...P-type diffusion layer, 205...Element isolation film, 206...Drain, 207...Source, 208...Gate electrode, 209...Gate insulating film 211...First plug, 211A...First gate plug, 211B...First drain plug, 211C...First source plug, 212A...First gate wiring, 212B...First drain wiring, 212C...First source wiring, 213...First wiring interlayer 221...Second plug, 221A...Second gate plug, 222A...Second gate wiring, 223...Second wiring interlayer 231...Third plug, 231A...Third gate plug, 232A...Third gate wiring, 233...Third wiring interlayer
Claims
1. A calibration method for calculating the electrical characteristics of a target semiconductor device, which is a semiconductor device that is the subject of circuit design, The aforementioned target semiconductor device includes a target main body portion containing semiconductor elements, and a target wiring portion stacked on the target main body portion for supplying current to the semiconductor elements. A first step of measuring values relating to the electrical characteristics of an adjustment semiconductor device, which is a semiconductor device including an adjustment main body having substantially the same structure as the target main body and an adjustment wiring section having higher heat dissipation than the target wiring section; A second step involves adjusting predetermined physical constants, including carrier mobility, used in a first simulation for calculating values related to the electrical characteristics of the aforementioned adjustable semiconductor device. A third step involves calculating values related to the electrical characteristics of the adjustment semiconductor device using the first simulation, A fourth step involves determining whether the difference between the first measured value of the electrical characteristics obtained in the first step and the first calculated value of the electrical characteristics obtained in the third step is within a predetermined tolerance range. If the result of the determination in the fourth step is within the tolerance range, the fifth step involves measuring the value related to the electrical characteristics of the target semiconductor device, A sixth step involves adjusting predetermined physical constants, including carrier mobility, used in a second simulation to calculate values related to the electrical characteristics of the target semiconductor device, using the carrier mobility of the adjustment semiconductor device in the most recently performed second step; A seventh step involves calculating values related to the electrical characteristics of the target semiconductor device using the second simulation, A calibration method for calculating the electrical characteristics of a semiconductor device, characterized by comprising an eighth step of determining whether the difference between the second measured value of the electrical characteristics obtained in the fifth step and the second calculated value of the electrical characteristics obtained in the seventh step is within a predetermined tolerance range.
2. A calibration semiconductor device used in a calibration method for calculating the electrical characteristics of a semiconductor device according to claim 1, The semiconductor element relating to the adjustment body comprises a gate electrode, an active region, and an element isolation film. The active region and the element separation film are formed in a state where they are facing each other and joined in the horizontal direction. The gate electrode is formed at the boundary between the active region and the element isolation film, spanning both the active region and the element isolation film. The adjustment wiring portion is formed on the upper surface of the gate electrode. The adjustment wiring section includes a metal, columnar plug. The number of plugs included in the adjustment wiring section is greater than the number of metal, columnar plugs included in the target wiring section. A semiconductor device for adjustment, characterized in that multiple plugs are formed in the active region and the element isolation film in a plan view on the upper surface of the gate electrode.
3. A semiconductor device for adjustment according to claim 2, An adjustable semiconductor device characterized in that wiring is connected to the upper end of all plugs included in the adjustment wiring section, and a metal, columnar plug is formed on said wiring.
4. A semiconductor device for adjustment according to claim 2, An adjustment semiconductor device characterized in that the formation positions of some of the plugs included in the adjustment wiring section, in a plan view, are substantially the same as the formation positions of all the plugs included in the target wiring section, in a plan view.