Split-array architecture for analog neural memory in deep learning artificial neural networks

Abstract

To provide a split-array architecture for an analog neural memory in a deep learning artificial neural network to split the array of non-volatile memory cells in the analog neural memory in the deep learning artificial neural network into a plurality of parts and operate them in parallel.SOLUTION: In a vector matrix multiplication (VMM) system 3500, specified operations are divided among different sets of circuits. An array 3501a is operated by a column decoder 3505 and an output circuit 3509, an array 3501b is operated by a column decoder 3507 and an output circuit 3511, an array 3501c is operated by a column decoder 3506 and an output circuit 3510, and an array 3501d is operated by a column decoder 3508 and an output circuit 3512. This enables a plurality of read operations and / or program operations to be performed simultaneously on all four arrays at once.SELECTED DRAWING: Figure 35

Description

Technical Field

[0001] (Claim of Priority) This application claims priority to U.S. Provisional Patent Application No. 63 / 190,228, filed May 18, 2021, and entitled "Split Array Architecture for Analog Neural Memory in a Deep Learning Artificial Neural Network", and U.S. Patent Application No. 17 / 461,901, filed Aug. 30, 2021, and entitled "Split Array Architecture for Analog Neural Memory in a Deep Learning Artificial Neural Network", which are hereby incorporated by reference.

[0002] (Field of the Invention) Disclosed are numerous embodiments for splitting an array into multiple parts in an analog neural memory within a deep learning artificial neural network, where each part interacts with a specific circuit dedicated to that part and other circuits shared with one or more other parts.

Background Art

[0003] An artificial neural network mimics a biological neural network (the central nervous system of an animal, particularly the brain), can depend on a large number of inputs, and is used to estimate or approximate a generally unknown function. An artificial neural network generally includes layers of interconnected "neurons" that exchange messages with each other.

[0004] Figure 1 shows an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple layers of inputs. Typically, there are hidden layers of one or more neurons and output layers of neurons that provide the output of the neural network. At each level, neurons make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved by digital supercomputers or dedicated graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses required.

[0006] The applicant previously disclosed in U.S. Patent Application No. 15 / 594,439, incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and then generate a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including a spaced source region and drain region formed in a semiconductor substrate with a channel region extending therebetween, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons in the floating gate. The plurality of memory cells is configured to multiply the stored weight values by the first plurality of inputs to generate the first plurality of outputs. Non-volatile memory cell

[0007] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("'130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed insulated above a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0008] By applying a high-voltage positive voltage to the word line terminal 22, erasure is performed on the memory cell 210 (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim (FN) tunnel.

[0009] The memory cell 210 is programmed by source-side injection (SSI) using hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are applied to the floating gate). The electron current flows from the drain region 16 towards the source region 14. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain area 16 and the word line terminal 22 (turning on the portion of the channel area 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel area 18 below the floating gate 20 is also turned on, and current flows through the channel area 18, which is detected as the erased state, or the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel area below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel area 18, which is detected as the programmed state, or the "0" state.

[0011] Table 1 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 110 to perform read, erase, and program operations. [Table 1]

[0012] Other types of flash memory cells are also known, including other split-gate memory cell configurations. For example, Figure 3 shows a four-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. [Table 2]

[0014] Figure 4 shows a different type of flash memory cell, a 3-gate memory cell 410. Memory cell 410 is identical to memory cell 310 in Figure 3, except that memory cell 410 does not have a separate control gate. The erase operation (erasure occurs through the use of an erase gate) and read operation are the same as those in Figure 3, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage must be applied to the source line to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. [Table 3]

[0016] Figure 5 shows a different type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that a floating gate 20 extends above the entire channel region 18, and a control gate 22 (where coupled to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, and programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 to the drain region 16, and by a read operation similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase-change memory), MRAM (magnetoresistive random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon tube) memory, OTP (bilevel or multilevel one-time programmable), and CeRAM (strongly correlated electron memory).

[0019] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a completely programmed state. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely programmed state to a completely erased state, and vice versa. This means that the cell memory is analog, or can store at least one of a number of discontinuous values ​​(such as 16 or 64 different values), which allows every cell in the memory array to be tuned very precisely and individually, and makes the memory array ideal for memory and fine-tuning of the synaptic weights of a neural network. Neural networks using non-volatile memory cell arrays

[0021] Figure 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array in this embodiment. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1 going from input layer S0 to layer C1 scans the input image with an overlapping 3x3 pixel filter (kernel), applying different sets of weights to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different sets of weights to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0023] In this example, layer C1 contains 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared across all scans used to generate this first map) can identify circular edges, and a second map (generated using a second set of weights different from the first) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0024] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or use the max function), reduce dependence on edge positions, and reduce data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0025] Each layer of a synapse is implemented using an array or part of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for that purpose. The vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Input to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the weights stored in it by the inputs, adds them up for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing operational amplifier or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential summer 38 is configured to perform the summing of positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then fed to an activation function block 39, which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summing operational amplifier 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in this case, a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in this case, an output ADC is provided to convert the output analog level to digital bits).

[0031] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0032] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is then provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as the synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. Vector Matrix Multiplication (VMM) Array

[0033] Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0034] In the VMM array 900, control gate lines such as the control gate line 903 extend in the vertical direction (thus, the reference array 902 in the row direction is orthogonal to the control gate line 903), and erase gate lines such as the erase gate line 904 extend in the horizontal direction. Here, the input to the VMM array 900 is provided to the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 900 appears on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current of each source line (SL0 and SL1 respectively) performs a summation function of all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, are preferably configured to operate in the subthreshold region.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids = Io * e (Vg-Vth) / nVt = w * Io * e (Vg) / nVt Where w = e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k * T / q, where k is the Boltzmann constant, T is the Kelvin temperature, q is the electron charge, n is the slope factor = 1+(Cdep / Cox), Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n - 1) * Vt 2It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV logarithmic converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector matrix multiplier (VMM) array with current input, the output current is as follows: Iout=wa * Io * e (Vg) / nVt That is to say Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt In the formula, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the transistor threshold voltage is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows: Vth = Vth0 + gamma(SQRT|Vsb-2) * φF)-SQRT|2 * φF|) In the formula, Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0040] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region. Ids=beta * (Vgs-Vth) * Vds; beta = u * Cox * Wt / L W=α(Vgs-Vth) In other words, the weight W in the linear region is proportional to (Vgs - Vth).

[0041] Word lines, control gate lines, bit lines, or source lines can be used as inputs to memory cells operating within the linear region. Bit lines or source lines can be used as outputs to memory cells.

[0042] For IV linear converters, a memory cell (such as a reference memory cell or peripheral memory cell) or transistor operating in the linear domain can be used to linearly convert input / output currents into input / output voltages.

[0043] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 * beta * (Vgs-Vth) 2 ;beta=u * Cox * Wt / L W ∝ (Vgs - Vth) 2 That is, the weight W is (Vgs - Vth) 2 It is proportional to.

[0044] Word lines, control gates, or erase gates can be used as inputs to memory cells operating within a saturation region. Bit lines or source lines can be used as outputs to output neurons.

[0045] Alternatively, the memory cells of the VMM array described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturated) for each layer or multilayer of a neural network.

[0046] Other embodiments for the VMM array 32 shown in Figure 7 are described in U.S. Patent Application No. 15 / 826,345, which is incorporated herein by reference. As described in the above application, source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2, and used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to the word lines WL0, WL1, WL2, and WL3), and then adds all the results (memory cell currents) to generate the output of each bit line (BL0~BLN), which becomes the input to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. The current in each bit line BL0 to BLN is a function of the sum of the currents from all non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. [Table 5]

[0050] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of a first nonvolatile reference memory cell, and a reference array 1102 of a second nonvolatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000 except that the word lines in the VMM array 1100 extend in the vertical direction. Here, the input is the word lines (WLA0, WLB0, WLA1, WLB 1 The outputs are provided to WLA2, WLB2, WLA3, and WLB3, and appear on the source lines (SL0, SL1) during read operations. The current on each source line is a function of the sum of all currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. [Table 6]

[0052] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1212 includes corresponding multiplexer 1205 and cascoding transistor 1204, respectively, to ensure a constant voltage across the bit lines (such as BLR0) of the first and second non-volatile reference memory cells during read operations. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line acts as a function of the sum of all currents from the memory cells connected to that particular bit line.

[0054] The VMM array 1200 implements one-way tuning of non-volatile memory cells within the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (for example, if an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (known as page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. [Table 7]

[0056] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1300 is a memory array 1303 of nonvolatile memory cells, First non-volatile reference memory cell Reference array 130 1 andThe VMM array 1300 comprises a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3, as well as the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using individual EG lines. As shown, the reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), and these voltages are applied to the memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0 to BLN, and each bit line sums up all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. [Table 8]

[0058] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2200, inputs INPUT0...., INPUT N This is the bit line BL0, ...BLN Each signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3 respectively, and outputs OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0060] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0061] Figure 25 shows a neuron VMM array 2500 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method]. Alternatively, the inputs are control gates CG0, ..., CG M It can be received.

[0062] Figure 26A shows a neuron VMM array 2600 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n These are the vertical control gate lines CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] Figure 26B shows neuron VMM array 2620, an alternative design to VMM array 2600 where the word lines are vertical instead of horizontal. In this instance, inputs may be received on vertical word lines WL0 and WL1, and outputs OUTPUT1 and OUTPUT2 are generated on horizontal source lines SL0 and SL1.

[0064] Figure 26C shows neuron VMM array 2640, an alternative design to VMM array 2600 where the erase gate lines are vertical instead of horizontal. In this instance, inputs may be received on vertical erase gate lines EG0, EG1, and outputs OUTPUT1 and OUTPUT2 are generated on horizontal source lines SL0 and SL1.

[0065] Figure 27 shows a neuron VMM array 2700 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N These are bit lines BL0, ..., BL N The signals are received by the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, which are coupled to each other. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0066] Figure 28 shows a neuron VMM array 2800, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Received to, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N These are generated respectively. Alternatively, the inputs are control gates CG0, ..., CG M It can be received.

[0067] Figure 29 shows a neuron VMM array 2900 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received by OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL N Each is generated, and each source line SL i It is coupled to the source lines of all memory cells in column i. Alternatively, the input is the word lines WL0, ..., WL M It can be received.

[0068] Figure 30 shows a neuron VMM array 3000, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received by OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL NEach bit line BL is generated in its respective place. i It is coupled to the bit lines of all memory cells in column i. Long-term and short-term memory

[0069] Prior art includes the concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0070] Figure 14 shows an exemplary LSTM1400. In this example, the LSTM1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1402 receives the input vector x1, the output vector (hidden state) h0 from cell 1401, and the cell state c0 from cell 1401, and generates the output vector h1 and the cell state vector c1. Cell 1403 receives the input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402, and generates the output vector h2 and the cell state vector c2. Cell 1404 receives the input vector x3, the output vector (hidden state) h2 from cell 1403, and the cell state c2 from cell 1403, and generates the output vector h3. Additional cells can also be used, and an LSTM with four cells is just one example.

[0071] Figure 15 shows an exemplary implementation of LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates the cell state vector c(t) and output vector h(t).

[0072] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each applying a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0073] Figure 16 shows an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the reader's convenience, the same numbering method used for LSTM cell 1500 is used for LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each correspond to multiple VMM arrays 1601 and activation function circuit block 160. 2 Including. Therefore, it is found that VMM arrays are particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, as well as adder device 1509, are implemented in digital or analog form. Activation function block 1602 can be implemented in digital or analog form.

[0074] Figure 17 shows an alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500). In Figure 17, sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (including the activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, and a value f(t) * Register 1704 for storing c(t-1) when its value is output from multiplier device 1703 via multiplexer 1710, and value i(t) * Register 1705 for storing u(t) when its value is output from multiplier device 1703 via multiplexer 1710, and value o(t) * The set includes register 1706 and multiplexer 1709 for storing c~(t) when its value is output from multiplier device 1703 via multiplexer 1710.

[0075] While an LSTM cell 1600 includes multiple sets of VMM arrays 1601 and their respective activation function blocks 1602, an LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in embodiments of the LSTM cell 1700. Compared to the LSTM cell 1600, the LSTM cell 1700 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than the LSTM cell 1600.

[0076] It can be further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, in the embodiments described later, we attempt to minimize the circuitry required outside the VMM array itself. Gated regression unit

[0077] Analog VMM implementations can be used in gated recurrent unit (GRU) systems. A GRU is a gate mechanism within an iterative neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0078] Figure 18 shows an exemplary GRU1800. In this example, the GRU1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and produces output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and produces output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and produces output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0079] Figure 19 shows an exemplary implementation of a GRU cell 1900 that can be used in cells 1801, 1802, 1803, and 1804 of Figure 18. The GRU cell 1900 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding two vectors, and a complementary device 1908 for subtracting the input from 1 to produce an output.

[0080] Figure 20 shows GRU cell 2000, an example of an implementation of GRU cell 1900. For the reader's convenience, the same numbering method used in GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, the sigmoid function devices 1901 and 1902, and the tanh device 1903, each contain multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are used in particular in GRU cells used in specific neural network systems. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0081] Figure 21 shows an alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900). In Figure 21, GRU cell 2100 utilizes VMM array 2101 and activation function block 2102, and when configured as a sigmoid function, it applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In Figure 21, the sigmoid function devices 1901 and 1902, and the tanh device 1903, share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding two vectors, a complementary device 2109 for subtracting the input from 1 to generate an output, a multiplexer 2104, and a value h(t-1) * Register 2106 for holding r(t) when its value is output from multiplier device 2103 via multiplexer 2104, and value h(t-1) * A register 2107 holds the value of z(t) when its value is output from the multiplier device 2103 via the multiplexer 2104, and the value h^(t) * The system includes a register 2108 for holding (1-z((t)) when its value is output from the multiplier device 2103 via the multiplexer 2104.

[0082] While GRU cell 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in embodiments of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because it requires only one-third the space for the VMM and activation function blocks.

[0083] It is further understood that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as totalizer and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, in the embodiments described later, we attempt to minimize the circuitry required outside the VMM array itself.

[0084] The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is required to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0085] For each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W = W+ - W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells.

[0086] Each non-volatile memory cell used in an analog neuromorphic memory system must hold a very specific and precise amount of charge, i.e., the number of electrons, within its floating gate, corresponding to the erasure / programming process. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0087] VMM systems need to increase throughput and reduce latency as much as possible while reducing the overall amount of space required for memory cells and support circuits. [Overview of the project]

[0088] Numerous embodiments are disclosed for dividing an array into multiple parts in an analog neural memory within a deep learning artificial neural network, each part interacting with specific circuits dedicated to that part and other circuits shared with one or more other parts.

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[0128] [Brief explanation of the drawing]

[0129] [Figure 1] This is a diagram illustrating an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This diagram illustrates various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 7] This is a block diagram illustrating a vector matrix multiplication system. [Figure 8] This is a block diagram illustrating an exemplary artificial neural network that utilizes one or more vector matrix multiplication systems. [Figure 9] Another embodiment of the vector matrix multiplication system is shown. [Figure 10] Another embodiment of the vector matrix multiplication system is shown. [Figure 11] Another embodiment of the vector matrix multiplication system is shown. [Figure 12] Another embodiment of the vector matrix multiplication system is shown. [Figure 13] Another embodiment of the vector-matrix multiplication system is shown. [Figure 14] This demonstrates prior art long- and short-term memory systems. [Figure 15] This shows an example cell used in long- and short-term memory systems. [Figure 16] Figure 15 shows one embodiment of an exemplary cell. [Figure 17] Another embodiment of the exemplary cell shown in Figure 15 is presented. [Figure 18] This shows a prior art gated regression unit system. [Figure 19] An exemplary cell for use in a gated regressive unit system is shown. [Figure 20] Figure 19 shows one embodiment of an exemplary cell. [Figure 21] Another embodiment of the exemplary cell in Figure 19 is shown. [Figure 22] Another embodiment of the vector-matrix multiplication system is shown. [Figure 23] Another embodiment of the vector-matrix multiplication system is shown. [Figure 24] Another embodiment of the vector-matrix multiplication system is shown. [Figure 25] Another embodiment of the vector-matrix multiplication system is shown. [Figure 26A] Another embodiment of the vector-matrix multiplication system is shown. [Figure 26B] Another embodiment of the vector-matrix multiplication system is shown. [Figure 26C] Another embodiment of the vector-matrix multiplication system is shown. [Figure 27] Another embodiment of the vector-matrix multiplication system is shown. [Figure 28] Another embodiment of the vector-matrix multiplication system is shown. [Figure 29] Another embodiment of the vector-matrix multiplication system is shown. [Figure 30] Another embodiment of the vector-matrix multiplication system is shown. [Figure 31] This demonstrates a vector-matrix multiplication system. [Figure 32] This document presents one embodiment of a split vector matrix multiplication system. [Figure 33] This document describes one embodiment of a split array vector matrix multiplication system. [Figure 34] Another embodiment of the split array vector matrix multiplication system is shown. [Figure 35] Another embodiment of the split array vector matrix multiplication system is shown. [Figure 36] Another embodiment of the split array vector matrix multiplication system is shown. [Figure 37]This shows one embodiment of a split array within a vector matrix multiplication system. [Figure 38] Another embodiment of a split array within a vector matrix multiplication system is shown. [Figure 39] Exemplary layouts of single arrays and split arrays within a vector matrix multiplication system are shown. [Modes for carrying out the invention]

[0130] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. Overview of the VMM System

[0131] Figure 31 shows a block diagram of the VMM system 3100. The VMM system 3100 comprises a VMM array 3101, a row decoder 3102, a high-voltage decoder 3103, a column decoder 3104, a bit line driver 3105, an input circuit 3106, an output circuit 3107, a control logic 3108, and a bias generator 3109. The VMM system 3100 further comprises a high-voltage generation block 3110, which includes a charge pump 3111, a charge pump regulator 3112, and a high-voltage level generator 3113. The VMM system 3100 further comprises an algorithm controller 3114 (program / erase, or also known as weight adjustment), an analog circuit 3115, a control engine 3116 (which may include special functions such as arithmetic functions, startup functions, and embedded microcontroller logic), and a test control logic 3117. The systems and methods described below may be implemented in the VMM system 3100.

[0132] The input circuit 3106 may include circuits such as a DAC (digital-to-analog converter), DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), AAC (analog-to-analog converter such as a current-to-voltage converter, logarithmic converter), PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3106 may implement normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3106 may implement a temperature compensation function for the input level. The input circuit 3106 may implement activation functions such as ReLU or sigmoid. The output circuit 3107 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog output to digital bits), AAC (analog-to-analog converter such as a current-to-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time modulated pulse converter), current-to-voltage converter, or any other type of converter. The output circuit 3107 may implement activation functions such as ReLU or sigmoid. The output circuit 3107 may implement statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) of the neuron output. The output circuit 3107 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) to improve the accuracy of the array (neuron) output, such as by keeping the array's power consumption nearly constant or keeping the IV slope nearly the same.

[0133] Figures 32 to 36 show embodiments of the VMM system that share some commonalities with the VMM system 3100, but also include some modifications.

[0134] Figure 32 shows the VMM system 3200. The VMM system 3200 comprises an array 3201, a shared row decoder 3202, a shared high-voltage decoder 3203, column decoders 3204 and 3205, a (row) input circuit 3220, output circuits 3206 and 3207, and a shared bit line driver 3208. The shared row decoder 3202 is coupled to all rows in the array 3201 and applies a voltage to selected rows. The shared high-voltage decoder 3203 can be selectively coupled to all rows in the array 3201. The shared high-voltage decoder 3203 optionally comprises a control-gate high-voltage decoder 3231 that can be selectively coupled to all rows in the array, and a shared erase-gate high-voltage decoder 3232 that can be selectively coupled to all rows in the array. The input circuit 3220 is similar to, for example, the input circuit 3106 in Figure 31. The circuits and functions of output circuits 3206 and 3207 are similar to, for example, the circuits and functions of output circuit 3107 in Figure 31. Unlike VMM system 3100, VMM system 3200 divides specific operations between different sets of circuits. Specifically, half of the columns in array 3201 (e.g., all odd columns) are operated by column decoder 3204 and output circuit 3206, and the other half of the columns in array 3201 (e.g., all even columns) are operated by column decoder 3205 and output circuit 3207. Thus, output circuit 3206 is coupled to column decoder 3204 to produce a first output from one or more columns in the first half of the columns during a read operation, and output circuit 3207 is coupled to column decoder 3207 to produce a second output from one or more columns in the second half of the columns during a read operation. In this embodiment, during a program or erase operation, all columns are coupled to multiple shared bit line drivers 3208. This allows multiple bit lines to be read in parallel. In other words, multiple bit lines coupled to the column decoder 3204 and output circuit 3206, and multiple bit lines coupled to the column decoder 3205 and output circuit 3207, are simultaneously enabled by multiple shared bit line drivers 3208 for read operations. This increases the throughput for reading the array 3201. Alternatively, read operations do not need to be simultaneous.

[0135] Optionally, referring further to Figure 39, continuous diffusion can be implemented between the upper and lower halves of the array.

[0136] Figure 33 shows the VMM system 3300. The VMM system 3300 comprises arrays 3301a and 3301b, row decoder 3302, shared high-voltage decoder 3303, column decoders 3304 and 3305, input circuit 3320, current-to-voltage converter circuits 3306 and 3307, shared analog-to-digital converter (ADC) 3308, and shared bit line driver 3309. The current-to-voltage converter circuit 3306 or 3307 and the shared ADC circuit 3308 are part of the output circuit 3207 in Figure 32.

[0137] Unlike the VMM system 3100, the VMM system 3300 divides specific operations between different sets of circuits. Specifically, array 3301a is operated by a column decoder 3304 and a current-to-voltage converter 3306, while array 3301b is operated by a column decoder 3305 and a current-to-voltage converter 3307. This allows multiple read operations and / or program operations to be performed simultaneously, and the read or program operations may be performed concurrently for one or more cells in array 3301a and one or more cells in array 3301b.

[0138] Both current-to-voltage converter circuits 3306 and 3307 are coupled to a shared analog-to-digital converter 3308 used in a time-division multiplexed manner during read operations, and to a shared bit-line driver 3309 used during program and erase operations. For example, during a read operation, array 3301a is enabled and coupled to column decoder 3304 and current-to-voltage converter circuit 3306, while simultaneously, array 3301b is enabled and coupled to column decoder 3305 and current-to-voltage converter circuit 3307. The output voltages from current-to-voltage converter circuits 3306 and 3307 are sampled and held (S / H) by, for example, an S / H capacitor in the shared ADC 3308, and these array output voltages are digitized (converted) by the time-division multiplexed shared ADC 3308 (because they are shared between current-to-voltage converter circuits 3306 and 3307). For example, two sets of S / H capacitors are used for one ADC shared between two current-to-voltage converter circuits. In another embodiment, one ADC can be used for N current-to-voltage converter circuits, in which case N sets of S / H capacitors are used.

[0139] The use of a shared ADC between two current-voltage converter circuits can also be applied to Figures 34 / 35 / 36.

[0140] Figure 34 shows the VMM system 3400. The VMM system 3400 comprises arrays 3401a and 3401b, a shared row decoder 3402, a shared high-voltage decoder 3403, column decoders 3404 and 3405, an input circuit 3420, output circuits 3406 and 3407, and a shared bit line driver 3408. Unlike the VMM system 3100, in the VMM system 3400, certain operations are divided among different sets of circuits. Specifically, array 3401a is operated by the column decoder 3404 and output circuit 3406, and array 3401b is operated by the column decoder 3405 and output circuit 3407. This allows multiple read operations and / or program operations to be performed simultaneously, and the read or program operations may be performed concurrently for one or more cells in array 3401a and one or more cells in array 3401b. Both arrays 3401a and 3401b are coupled to a shared bit line driver 3408, which is used during program and erase operations.

[0141] Figure 35 shows the VMM system 3500. The VMM system 3500 comprises arrays 3501a, 3501b, 3501c, and 3501d, row decoders 3502 and 3503, a shared high-voltage decoder 3504, column decoders 3505, 3506, 3507, and 3508, an input circuit 3520, output circuits 3509, 3510, 3511, and 3512, and shared bit line drivers 3513 and 3514. The shared high-voltage decoder 3504 can be selectively coupled to all rows in arrays 3501a, 3501b, 3501c, and 3501d. Row decoder 3502 is shared by arrays 3501a and 3501b, coupled to all rows in these arrays, and applies a voltage to selected rows; row decoder 3503 is shared by arrays 3501c and 3501d, coupled to all rows in these arrays, and applies a voltage to selected rows.

[0142] In the VMM system 3500, specific operations are divided among different sets of circuits. Specifically, array 3501a is operated by column decoder 3505 and output circuit 3509, array 3501b is operated by column decoder 3507 and output circuit 3511, array 3501c is operated by column decoder 3506 and output circuit 3510, and array 3501d is operated by column decoder 3508 and output circuit 3512. This allows multiple read operations and / or program operations to be executed simultaneously on all four arrays at once, and read or program operations can be executed concurrently on one or more cells in array 3501a, one or more cells in array 3501b, one or more cells in array 3501c, and one or more cells in array 3501d. Both arrays 3501a and 3501b are selectively coupled to the shared bit line driver 3513 during program and erase operations. Both arrays 3501c and 3501d are selectively coupled to the shared bit line driver 3514 during program and erase operations.

[0143] For example, the column decoder 3505 and output circuit 3509 can perform a first read operation to generate a first output from one or more rows in array 3501a, the column decoder 3506 and output circuit 3510 can perform a second read operation to generate a second output from one or more rows in array 3501c, the column decoder 3507 and output circuit 3511 can perform a third read operation to generate a third output from one or more rows in array 3501b, and the column decoder 3508 and output circuit 3512 can perform a fourth read operation to generate a fourth output from one or more rows in array 3501d. The first and third read operations can be performed in parallel as an option. The second and fourth read operations can be performed in parallel as an option.

[0144] Figure 36 shows the VMM system 3600. The VMM system 3600 comprises arrays 3601a, 3601b, 3601c, and 3601d, row decoder 3621, control gate decoders 3602 and 3603, shared high-voltage decoder 3604, column decoders 3605, 3606, 3607, and 3608, output circuits 3609, 3610, 3611, and 3612, and shared bit line drivers 3613 and 3614. In the VMM system 3600, specific operations are divided among different sets of circuits. Specifically, array 3601a is operated by a column decoder 3605 and an output circuit 3609, array 3601b is operated by a column decoder 3607 and an output circuit 3611, array 3601c is operated by a column decoder 3606 and an output circuit 3610, and array 3601d is operated by a column decoder 3608 and an output circuit 3612. This allows multiple read and / or program operations to be performed simultaneously on all four arrays at once, and the read or program operation may be performed concurrently on one or more cells in array 3601a, one or more cells in array 3601b, one or more cells in array 3601c, and one or more cells in array 3601d. Both arrays 3601a and 3601b are selectively coupled to a shared bit line driver 3613 during program and erase operations. Both arrays 3601c and 3601d are selectively coupled to the shared bit line driver 3614 during program and erase operations.

[0145] Figures 32 to 36 show that reading is performed by the row input of the control gate. Alternatively, reading can be performed by the word line or the erase gate. The input circuits 3220 in Figure 32, 3320 in Figure 33, 3420 in Figure 34, 3520 in Figure 35, and 3620 in Figure 36 are similar to the input circuit 3106 in Figure 31. The output circuits 3206 / 3207 in Figure 32, and 3406 / in Figure 34 are similar. 3407 Figure 35 3511 / 3512 / 3509 / 3510, and Figure 36 3611 / 3612Circuits / 3609 / 3610 are the same as output circuit 3107 in Figure 31.

[0146] Figure 37 shows a portion of the VMM array 3700. The VMM array 3700 comprises rows 3701, 3702, 3703, 3704, 3705, 3706, 3707, and 3708. Rows 3701, 3702, 3705, and 3706 share an erase gate line (EG0) and a source line (SL0), while rows 3703, 3704, 3707, and 3708 share an erase gate line (EG1) and a source line (SL1). In addition, rows 3701 and 3703 share control gate lines (CG0 / CG2), rows 3702 and 3704 share control gate lines (CG1 / CG3), rows 3705 and 3707 share control gate lines (CG4 / CG6), and rows 3706 and 3708 share control gate lines (CG5 / CG7). These couplings allow different rows to share the decoder circuit. The array terminals are shared to reduce program or erase disturbance by reducing the amount of erase or program voltage stress on unselected cells.

[0147] In the arrays of Figures 37 and 38 (described below), the row inputs for VMM arrays 3700 and 3800 for neural readout operations (where multiple rows and multiple bit lines are simultaneously on) are located on word lines. If the input for neural readout is located on a control gate, the control gate cannot be shared among multiple rows within the same subarray or array bank.

[0148] Figure 38 shows a portion of array 3800. Array 3800 comprises sectors 3809 and 3819. Sector 3809 comprises rows 3801, 3802, 3803, 3804, 3805, 3806, 3807, and 3808. Sector 3819 comprises rows 3811, 3812, 3813, 3814, 3815, 3816, 3817, and 3818.

[0149] Rows 3801 (the first row) and 3811 (the second row) share control gate line (CG0) (i.e., the control gate terminals of each cell in these rows are connected to the same control gate line), rows 3802 and 3812 share control gate line (CG1) (i.e., the control gate terminals of each cell in these rows are connected to the same control gate line), rows 3803 and 3813 share control gate line (CG2) (i.e., the control gate terminals of each cell in these rows are connected to the same control gate line), and rows 3804 and 3814 share control gate line (CG3) (i.e., the control gate terminals of each cell in these rows are connected to the same control gate line). Rows 3805 and 3815 share the control gate line (CG4) (i.e., the control gate terminals of each cell in these rows are coupled to the same control gate line), rows 3806 and 3816 share the control gate line (CG5) (i.e., the control gate terminals of each cell in these rows are coupled to the same control gate line), rows 3807 and 3817 share the control gate line (CG6) (i.e., the control gate terminals of each cell in these rows are coupled to the same control gate line), and rows 3808 and 3818 share the control gate line (CG7) (i.e., the control gate terminals of each cell in these rows are coupled to the same control gate line). In other words, the control gates are shared between sectors. These couplings allow different rows to share the decoder circuit. The array terminals are shared so as to reduce program or erase disturb by reducing the amount of erase or program voltage stress on unselected cells.

[0150] Rows 3801 (the first row), 3802 (the third row), 3805, and 3806 share an erase gate line (EG0) (i.e., the erase gate terminals of each cell in these rows are connected to the same erase gate line) and a source line (SL0) (i.e., the source line terminals of each cell in these rows are connected to the same source line), and row 3803, 3804Rows 3807 and 3808 share an erase gate line (EG1) (i.e., the erase gate terminals of each cell in these rows are connected to the same erase gate line) and a source line (SL1) (i.e., the source line terminals of each cell in these rows are connected to the same source line), rows 3811, 3812, 3815 and 3816 share an erase gate line (EG0) (i.e., the erase gate terminals of each cell in these rows are connected to the same erase gate line) and a source line (SL0) (i.e., the source line terminals of each cell in these rows are connected to the same source line), row 3813, 3814 Rows 3817 and 3818 share an erase gate line (EG1) (i.e., the erase gate terminals of each cell in these rows are connected to the same erase gate line) and a source line (SL1) (i.e., the source line terminals of each cell in these rows are connected to the same source line).

[0151] Figure 39 shows some exemplary layouts of single arrays 3901 (such as array 3101 in Figure 31 and array 3201 in Figure 32) and split arrays 3902 (such as arrays 3301a and 3301b in Figure 33, arrays 3401a and 3401b in Figure 34, arrays 3501a, 3501b, 3501c, and 3501d in Figure 35, and arrays 3601a, 3601b, 3601c, and 3601d in Figure 36). Split arrays 3902 follow the same design as array 3901, except that certain contacts and metal connections 3904 are removed (or not formed) to create subarrays 3903a and 3903b. A few dummy rows at the interface are disabled by grounding word lines and control gates, etc. This maintains process uniformity by the front-end layer (i.e., continuous column diffusion within columns and continuous row diffusion within source lines), ensuring that the polysilicon is continuous and uniform between two arrays of non-volatile memory cells (electrically isolated arrays). This also results in reduced area overhead compared to physical isolation of different arrays.

[0152] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is an analog neural memory, A first array of multiple non-volatile memory cells arranged in multiple rows and multiple columns, A second array of multiple non-volatile memory cells arranged in multiple rows and multiple columns, A third array of multiple non-volatile memory cells arranged in multiple rows and multiple columns, A fourth array of multiple non-volatile memory cells arranged in multiple rows and multiple columns, A first row decoder coupled to multiple rows of the first array and the second array, A second row decoder coupled to multiple rows of the third array and the fourth array, A first column decoder coupled to the first array, A second column decoder coupled to the second array, A third column decoder coupled to the third array, A fourth column decoder coupled to the fourth array, A first shared bit line driver is coupled to the first column decoder and the second column decoder during program operation, A second shared bit line driver is coupled to the third column decoder and the fourth column decoder during program operation, A first output circuit coupled to the first column decoder for generating a first output from one or more rows in the first array during a first read operation, A second output circuit coupled to the second column decoder for generating a second output from one or more rows in the second array during a second read operation, A third output circuit coupled to the third column decoder for generating a third output from one or more rows in the third array during a third read operation, An analog neural memory comprising: a fourth output circuit coupled to the fourth column decoder for generating a fourth output from one or more rows in the fourth array during a fourth read operation.

2. The analog neural memory according to claim 1, wherein the first read operation and the third read operation are performed in parallel.

3. The analog neural memory according to claim 1, wherein the second read operation and the fourth read operation are performed in parallel.

4. The analog neural memory according to claim 1, wherein each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit comprises a current-voltage converter.

5. The analog neural memory according to claim 4, wherein each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit further comprises an analog-to-digital converter coupled to the current-to-voltage converter.

6. The analog neural memory according to claim 1, wherein a shared high-voltage decoder is selectively coupled to all rows in the array.

7. The analog neural memory according to claim 1, wherein the first array, the second array, the third array, and the fourth array each include continuous column diffusion between columns.

8. The analog neural memory according to claim 1, wherein the first array, the second array, the third array, and the fourth array are formed from a single physical array and are separated from each other by a portion of the physical array that does not have metal contacts.

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