Apparatus and method for executing a spiking neural network, and spiking neuromorphic system

Abstract

A device for executing a spiking neural network, wherein: spike data input to the device is constituted from a plurality of spikes; the device comprises circuits (301, 302) that generate a membrane potential displacement relative to each of the spikes having variable weights and constituting the spike data, the membrane potential displacement being adjusted according to the weights, and the circuits generating a new spike if an integral value of the membrane potential displacement exceeds a threshold value; in the spike data, the input data is expressed as a spike pattern; and the spike pattern is defined by using at least two from among the number of spikes constituting the spike data, the widths of the spikes, and the amplitudes of the spikes.

Description

Technical Field

[0001] The present disclosure relates to an apparatus and method for executing a spiking neural network, and a spiking neuromorphic system.

Background Art

[0002] A neuromorphic system is a system that realizes a neural network in hardware. A neuromorphic system may also be referred to as a neuromorphic system. Among neuromorphic systems, in particular, a system that models biological neurons more precisely than an artificial neural network (ANN) has attracted attention. This system is called a spiking neural network (SNN).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0005] One aspect of this disclosure aims to provide an apparatus and method for executing a spiking neural network that can improve processing speed, as well as a spiking neuromorphic system. [Means for solving the problem]

[0006] To solve the above problems, an apparatus according to one aspect of the present disclosure is an apparatus for executing a spiking neural network, wherein the spike data input to the apparatus consists of a plurality of spikes, the apparatus has variable weights, generates a membrane potential displacement adjusted according to the weights for each spike constituting the spike data, and generates a new spike when the integral value of the membrane potential displacement exceeds a threshold, the spike data is data in which the input data is represented as a spike pattern, and the spike pattern is defined using at least two of the following: the number of spikes constituting the spike data, the width of each spike constituting the spike data, and the amplitude of each spike constituting the spike data.

[0007] Another aspect of the present disclosure relates to a method for running a spiking neural network, the method being a method for converting input data into spike data to be input to a device for running a spiking neural network, the spike data to be input to the device being composed of a plurality of spikes, the device being a circuit having variable weights that generates a membrane potential displacement adjusted according to the weights for each spike constituting the spike data, and generating a new spike when the integral value of the membrane potential displacement exceeds a threshold, the spike data being data in which the input data is represented as a spike pattern, the spike pattern being defined using at least two parameters from the number of spikes constituting the spike data, the width of each spike constituting the spike data, and the amplitude of each spike constituting the spike data. [Effects of the Invention]

[0008] According to one aspect of this disclosure, processing speed can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] A conceptual diagram illustrating a spiking neural network model. [Figure 2] A diagram for explaining how the membrane potential Vmem increases or decreases discontinuously. [Figure 3] A diagram showing examples of the circuit configurations of a synaptic circuit and a neuron circuit. [Figure 4] A diagram showing the electrical characteristics of a memcapacitor and a schematic configuration of the memcapacitor. [Figure 5] A diagram for explaining an example of the present embodiment. [Figure 6] A diagram for explaining an example of the present embodiment. [Figure 7] A diagram for explaining an example of the present embodiment. [Figure 8] A diagram for explaining an example of the present embodiment. [Figure 9] A diagram for explaining an example of the present embodiment. [Figure 10] A diagram for explaining an example of the present embodiment. [Figure 11] A diagram for explaining an example of the present embodiment. [Figure 12] A diagram for explaining an example of the present embodiment. [Figure 13] A diagram for explaining an example of the present embodiment. [Figure 14] A diagram for explaining an example of the present embodiment. [Figure 15] A diagram for explaining an example of the present embodiment. [Figure 16] A diagram for explaining an example of the present embodiment. [Figure 17] A diagram for explaining an example of the present embodiment. [Figure 18] A diagram for explaining an example of the present embodiment. [Figure 19] A diagram for explaining an example of the present embodiment. [Figure 20] A diagram for explaining an example of the present embodiment. [Figure 21] A diagram for explaining an example of the present embodiment. [Figure 22] A diagram for explaining an example of the present embodiment. [Figure 23] A diagram for explaining other embodiments of the present disclosure. [Figure 24]A diagram illustrating other embodiments of this disclosure. [Figure 25] A diagram illustrating further embodiments of this disclosure. [Modes for carrying out the invention]

[0010] <Background leading to this disclosure> Traditionally, artificial intelligence has relied on high-performance hardware to run complex and lengthy software. This has resulted in problems with the massive size of the hardware and the enormous power consumption. Neuromorphic systems, which mimic the brain, offer the potential for miniaturization and lower power consumption. In particular, spiking neuromorphic systems, which use spikes for signal transmission, are based on the same principles as the brain and are expected to achieve high performance, including previously unknown brain functions.

[0011] In spiking neuromorphic systems, the physical representation of the transmitted signal is called coding. Conventional spiking neuromorphic systems have used coding that uses only the number of spikes. If coding that uses spike width and spike amplitude in addition to the number of spikes can be used, the processing speed for the same amount of information can be improved, resulting in a significant reduction in processing time. Furthermore, a significant increase in the amount of information processed can be expected for the same processing time.

[0012] The Disclosers have diligently studied how to enable coding that uses spike width and spike amplitude in addition to spike count, and as a result, have made this disclosure which enables coding that uses spike count, spike width and spike amplitude in combination.

[0013] <Embodiment> Hereinafter, with reference to the attached drawings, an apparatus and method for implementing a spiking neural network according to the embodiments of this disclosure, as well as a spiking neuromorphic system, will be described in detail.

[0014] (Mechanism of neuronal firing) First, let's explain the mechanism of neuronal firing in a spiking neural network. Figure 1 shows a model of a spiking neural network. A neural network consists of multiple neurons and multiple synapses. Neurons are connected to each other by synapses. Figure 1 shows multiple synapses s1, s2, and s3 connecting a single neuron n1 to the neuron preceding it. Although not shown in Figure 1, neuron n1 is also connected to the neuron following it by a synapse.

[0015] As shown in Figure 1, multiple synapses s1, s2, and s3 are connected to neuron n1. Spikes x1 and x4 are input to neuron n1 via synapse s1. In the example in Figure 1, the input time of spike x1 is denoted as T1. The input time of spike x4 is denoted as T4. Spike x3 is input to neuron n1 via synapse s2. The input time of spike x3 is denoted as T3. Spike x2 is input to neuron n1 via synapse s3. The input time of spike x2 is denoted as T2.

[0016] Furthermore, let W1 be the weight of synapse s1. Weight W1 is a positive weight. Synapse s1 is an excitatory synapse. Let W2 be the weight of synapse s2. Weight W2 is a negative weight. Synapse s2 is an inhibitory synapse. Let W3 be the weight of synapse s3. Weight W3 is a positive weight. Synapse s3 is an excitatory synapse. Each synapse multiplies the input spike by its weight and outputs a membrane potential displacement adjusted according to the weight to the neuron. For example, taking synapse s2 as an example, the three spikes x3 input to synapse s2 are multiplied by the weight W2 of synapse s2, and a membrane potential displacement adjusted according to the weight W2 is output to neuron n1. Membrane potential displacement will be explained later.

[0017] The state of neuron n1 is represented by an internal variable called membrane potential. Let Vmem be the membrane potential of neuron n1. When a spike is input to neuron n1, the membrane potential Vmem increases or decreases discontinuously. Figure 2 shows how the membrane potential Vmem increases or decreases discontinuously. In the example in Figure 2, when spike x1 is input to synapse s1 at time T1, synapse s1 is an excitatory synapse, so the membrane potential Vmem increases. Next, when spike x2 is input to synapse s3 at time T2, synapse s3 is an excitatory synapse, so the membrane potential Vmem increases. When spike x3 is input to synapse s2 at time T3, synapse s2 is an inhibitory synapse, so the membrane potential Vmem decreases. Next, when spike x4 is input to synapse s1 at time T4, synapse s1 is an excitatory synapse, so the membrane potential Vmem increases.

[0018] In other words, each time a spike is input to neuron n1 via a synapse, neuron n1 displaces the membrane potential Vmem in accordance with that spike. Neuron n1 then integrates the displacement of the membrane potential Vmem. Hereafter, the displacement of the membrane potential Vmem when one spike is input to neuron n1 will be referred to as the membrane potential displacement. Let the membrane potential displacement be ΔVmem.

[0019] Neuron n1 maintains a threshold, denoted as Vth. In the example in Figure 2, neuron n1 fires when the integral of the membrane potential displacement ΔVmem reaches the threshold Vth. Let T5 be the firing time of neuron n1. This integral is the membrane potential Vmem at time T5, when all of the spikes x1, x2, x3, and x4 have been input.

[0020] When neuron n1 fires, it outputs a spike y to the subsequent neuron, as shown in Figure 1. After neuron n1 fires, its membrane potential Vmem is reset.

[0021] (Synaptic circuits and neuronal circuits) Next, the configurations of the synaptic and neuron circuits according to this embodiment will be described. Figure 3 shows examples of the configurations of the synaptic circuit 301 and neuron circuit 302 according to this embodiment. Synaptic circuit 301 is an example of the hardware configuration of synapses s1, s2, and s3 illustrated in Figure 1. Neuron circuit 302 is an example of the hardware configuration of neuron n1 illustrated in Figure 1. In other words, synaptic circuit 301 and neuron circuit 302 are examples of circuits that generate new spikes. Multiple such circuits are an example of a device for executing a spiking neural network. Furthermore, a system consisting of multiple synaptic circuits 301 and multiple neuron circuits 302 is an example of a spiking neuromorphic system.

[0022] The following will first describe the configuration of the synaptic circuit 301, then the configuration of the neuron circuit 302, and finally, the operation of the interconnected synaptic circuit 301 and neuron circuit 302.

[0023] 1. Configuration of synaptic circuit 301 As shown in Figure 3, the synaptic circuit 301 includes a first input terminal X1, a second input terminal X2, an output terminal A, a first capacitor c1, a first switching element t1, a second switching element t2, a third switching element t3, a fourth switching element t4, a fifth switching element t5, a sixth switching element t6, and a second capacitor c2.

[0024] The first input signal is input to the first input terminal X1. The second input signal is input to the second input terminal X2. The first input signal is the inverted version of the first input signal. The first input signal and the second input signal are complementary.

[0025] An output signal is output from output terminal A. A third capacitor CM is connected between output terminal A and ground potential.

[0026] The first capacitor c1 is a mem capacitor with variable electrical characteristics. Figure 4 shows the electrical characteristics of the mem capacitor and its schematic configuration. The mem capacitor has the electrical characteristics indicated by reference numeral 401 in Figure 4. The mem capacitor has the schematic configuration indicated by reference numeral 402 in Figure 4.

[0027] A memcapacitor, as shown by the hysteresis characteristic indicated by reference numeral 401 in Figure 4, is a passive element that not only stores electric charge in a capacitor but also possesses electrical properties in which the capacitance value of the capacitor changes according to the history of the applied voltage. A memcapacitor is a memory element. As a memory element, a memcapacitor holds analog data. Memcapacitors can be used as non-volatile memory.

[0028] The memcapacitor, as shown in the schematic configuration indicated by reference numeral 402 in Figure 4, comprises a Pt layer 42 arranged on a base 41, a bismuth lanthanum titanate (BLT) layer 43 arranged on the Pt layer 42, and an Au layer 44 arranged on the BLT layer 43. The Pt layer 42 is the negative electrode. The Au layer 44 is the positive electrode. When a voltage V is applied between the Pt layer 42 and the Au layer 44, a charge Q is accumulated in the BLT layer 43. This application of voltage V changes the capacitance value of the capacitor consisting of the Pt layer 42, the BLT layer 43, and the Au layer 44. Since the memcapacitor is a known element, further details are omitted.

[0029] The second capacitor c2 has a fixed capacitance value.

[0030] The first switching element t1 is a p-type MOSFET. The first switching element t1 turns on when the gate-source voltage is below the threshold voltage. The gate is connected to the second input terminal X2, and the source is connected to the first input terminal X1.

[0031] The second switching element t2 is a p-type MOSFET. The second switching element t2 turns on when the gate-source voltage is below the threshold voltage. The gate is connected to the first input terminal X1, and the drain is connected to the second input terminal X2.

[0032] The third switching element t3 is an n-type MOSFET. The third switching element t3 turns on when the gate-source voltage is greater than or equal to the threshold voltage. The gate is connected to the second input terminal X2 via the second capacitor c2, the source is connected to the source of the second switching element t2, and the drain is connected to the first input terminal X1 via the first capacitor c1.

[0033] The fourth switching element t4 is an n-type MOSFET. The fourth switching element t4 turns on when the gate-source voltage is greater than or equal to a threshold voltage. The gate is connected to the first input terminal X1 via the first capacitor c1, the source is connected to the second input terminal X2 via the second capacitor c2, and the drain is connected to the drain of the first switching element t1.

[0034] The fifth switching element t5 is a p-type MOSFET. The fifth switching element t5 turns on when the gate-source voltage is below the threshold voltage. The gate is connected to the second input terminal X2 via the second capacitor c2, the source is connected to the first input terminal X1 via the first capacitor c1, and the drain is connected to the output terminal A.

[0035] The sixth switching element t6 is a p-type MOSFET. The sixth switching element t6 turns on when the gate-source voltage is below the threshold voltage. The gate is connected to the first input terminal X1 via the first capacitor c1, the source is connected to the output terminal A, and the drain is connected to the second input terminal X2 via the second capacitor c2.

[0036] Here, the absolute values ​​of the weights W1, W2, and W3 exemplified in Figure 1 are expressed using the variable capacitance values ​​of the mem capacitor described above.

[0037] Furthermore, the synaptic circuit 301 shown in Figure 3 represents an excitatory synapse. In other words, in the synaptic circuit 301 shown in Figure 3, the sign of the weight expressed using the capacitance value of the first capacitor c1 is positive. To represent an inhibitory synapse, in the synaptic circuit 301 shown in Figure 3, the first switching element t1 is replaced with an n-type MOSFET, the second switching element t2 is replaced with an n-type MOSFET, the third switching element t3 is replaced with a p-type MOSFET, the fourth switching element t4 is replaced with a p-type MOSFET, the fifth switching element t5 is replaced with an n-type MOSFET, and the sixth switching element t6 is replaced with an n-type MOSFET. In this modified configuration, the sign of the weight expressed using the capacitance value of the first capacitor c1 is negative.

[0038] 2. Configuration of Neuron Circuit 302 As shown in Figure 3, the neuron circuit 302 includes a third capacitor CM, a seventh switching element t11, a first inverter element IN1, a second inverter element IN2, a third inverter element IN3, a fourth inverter element IN4, a fourth capacitor c11, a fifth capacitor c12, a sixth capacitor c13, and an output terminal Y.

[0039] The third capacitor CM has a fixed capacitance value. As described above, the third capacitor CM is connected between the output terminal A of the synaptic circuit 301 and the ground potential. The output terminal A of the synaptic circuit 301 can be considered the input terminal of the neuron circuit 302. Here, the membrane potential Vmem exemplified in Figure 1 is expressed using the potential of the third capacitor CM.

[0040] The seventh switching element t11 ​​is an n-type MOSFET. The seventh switching element t11 ​​turns on when the gate-source voltage is greater than or equal to the threshold voltage. The gate is connected to the output terminal Y, the source is connected to ground potential, and the drain is connected to ground potential via the third capacitor CM.

[0041] The first inverter element IN1 receives an input signal from its input side and outputs an output signal from its output side. The output signal is the inverted signal of the input signal. The input side is connected to the third capacitor CM, and the output side is connected to ground potential via the fourth capacitor c11.

[0042] The second inverter element IN2 receives an input signal from its input side and outputs an output signal from its output side. The output signal is the inverted signal of the input signal. The input side is connected to the fourth capacitor c11, and the output side is connected to ground potential via the fifth capacitor c12.

[0043] The third inverter element IN3 receives an input signal from its input side and outputs an output signal from its output side. The output signal is the inverted signal of the input signal. The input side is connected to the fifth capacitor c12, and the output side is connected to ground potential via the sixth capacitor c13.

[0044] The fourth inverter element IN4 receives an input signal from its input side and outputs an output signal from its output side. The output signal is the inverted signal of the input signal. The input side is connected to the sixth capacitor c13, and the output side is connected to the output terminal Y.

[0045] The fourth capacitor c11 has a fixed capacitance value. The fourth capacitor c11 is connected between the ground potential and the input side of the second inverter element IN2.

[0046] The fifth capacitor c12 has a fixed capacitance value. The fifth capacitor c12 is connected between the ground potential and the input side of the third inverter element IN3.

[0047] The sixth capacitor c13 has a fixed capacitance value. The sixth capacitor c13 is connected between the ground potential and the input side of the fourth inverter element IN4.

[0048] 3. Operation of synaptic circuit 301 A spike is input to the first input terminal X1. The spikes input to the first input terminal X1 correspond to spikes x1, x2, x3, and x4 as exemplified in Figure 1. A spike that is the inverted version of the spike input to the first input terminal X1 is input to the second input terminal X2. The spikes input to the first input terminal X1 and the spikes input to the second input terminal X2 are complementary. Hereinafter, the spike input to the second input terminal X2 will be referred to as the inverted spike.

[0049] The spike input to the first input terminal X1 is a voltage spike. Furthermore, the voltage spike input to the first input terminal X1 is a positive voltage. Additionally, the positive voltage input to the first input terminal X1 is greater than or equal to the threshold voltages of the third switching element t3 and the fourth switching element t4. Hereinafter, the spike input to the first input terminal X1 will be referred to as the first spike.

[0050] The inverting spike input to the second input terminal X2 is a voltage spike. The voltage spike input to the second input terminal X2 is a negative voltage. Furthermore, the negative voltage input to the second input terminal X2 is below the threshold voltage of the first switching element t1, the second switching element t2, the fifth switching element t5, and the sixth switching element t6. Hereinafter, the inverting spike input to the second input terminal X2 will be referred to as the second spike.

[0051] As mentioned above, the first and second spikes are complementary. Therefore, the timing of the rise of the first spike coincides with the timing of the fall of the second spike. Also, the timing of the fall of the first spike coincides with the timing of the rise of the second spike.

[0052] Although not shown in the diagram, a first spike generator that generates the first spike is connected to the first input terminal X1 of the synapse circuit 301. A second spike generator that generates the second spike is connected to the second input terminal X2 of the synapse circuit 301.

[0053] The first spike generator converts input data, such as an image, into spike data consisting of multiple spikes. In other words, the first spike generator is a device that encodes input data, such as an image, into spike data as binary numbers. The first spike generator outputs each spike that makes up the converted spike data to the first input terminal X1. Each spike corresponds to the first spike.

[0054] The second spike generator converts input data, such as an image, into spike data consisting of multiple spikes. In other words, the second spike generator is a device that encodes input data, such as an image, into spike data as binary numbers. The second spike generator outputs each spike that makes up the converted spike data to the second input terminal X2. Each spike corresponds to the second spike.

[0055] The first spike generator and the second spike generator perform the above-described encoding on the same input data.

[0056] Furthermore, the spike data encoded by the first spike generator is represented as a spike pattern. The spike pattern is defined using at least two of the following: the number of spikes that make up the spike data, the width of each spike that makes up the spike data, and the amplitude of each spike that makes up the spike data. The same applies to the spike data encoded by the second spike generator.

[0057] Details regarding the configurations and encoding processes of the first and second spike generators will be omitted.

[0058] When a first spike is input to the first input terminal X1 and a second spike is input to the second input terminal X2, the synaptic circuit 301 operates as follows:

[0059] 1) When the first spike rises and the second spike falls, a positive voltage is applied to the first input terminal X1, while a negative voltage is applied to the second input terminal X2. As a result, the first switching element t1 turns on, the second switching element t2 turns off, the third switching element t3 turns off, the fourth switching element t4 turns on, the fifth switching element t5 turns on, and the sixth switching element t6 turns off.

[0060] In this case, the second capacitor c2 is subjected to a potential difference between the positive voltage input to the first input terminal X1 and the negative voltage input to the second input terminal X2. This potential difference charges the second capacitor c2. Also, the discharge of the first capacitor c1 charges the third capacitor CM. Since the first capacitor c1 has a variable capacitance, i.e., stores an amount of charge corresponding to its weight, the film potential displacement ΔVmem of the third capacitor CM is adjusted according to the weight of the first capacitor c1.

[0061] 2) When the first spike falls and the second spike rises, a negative voltage is applied to the first input terminal X1, while a positive voltage is applied to the second input terminal X2. As a result, the first switching element t1 turns off, the second switching element t2 turns on, the third switching element t3 turns on, the fourth switching element t4 turns off, the fifth switching element t5 turns off, and the sixth switching element t6 turns on.

[0062] In this case, the first capacitor c1 is subjected to a potential difference between the negative voltage input to the first input terminal X1 and the positive voltage input to the second input terminal X2. This potential difference charges the first capacitor c1. Additionally, the discharge of the second capacitor c2 charges the third capacitor CM. Since the second capacitor c2 stores a charge corresponding to its fixed capacitance, the film potential displacement ΔVmem of the third capacitor CM is corresponding to the displacement of the second capacitor c2.

[0063] In this way, the synaptic circuit 301 controls the on / off state of the first switching elements t1 to the sixth switching elements t6, and transfers charge to the third capacitor CM by charging and discharging the first capacitor c1 and the second capacitor c2, respectively. This charge transfer increases the potential of the third capacitor CM, i.e., the membrane potential Vmem. From this, it can be said that the synaptic circuit 301 constitutes a charge pump circuit that generates an increase in the membrane potential Vmem.

[0064] Furthermore, the membrane potential Vmem increases each time a first spike is input to the first input terminal X1 and a second spike is input to the second input terminal X2. Therefore, when multiple first spikes are input to the first input terminal X1 and multiple second spikes are input to the second input terminal X2, the membrane potential Vmem increases at the timing of each spike input, i.e., it increases discontinuously. As mentioned above, the synaptic circuit 301 represents an excitatory synapse. If the circuit configuration represents an inhibitory synapse, the potential of the third capacitor CM, i.e., the membrane potential Vmem, decreases at the timing of each spike input, i.e., it decreases discontinuously.

[0065] 4. Operation of Neuron Circuit 302 Each time the membrane potential Vmem of the third capacitor CM increases, the membrane potential displacement ΔVmem is integrated. This integrated value is the membrane potential Vmem at the point in time when the membrane potential Vmem increased.

[0066] The threshold Vth illustrated in Figure 1 is expressed using the threshold of the first inverter element IN1. When the film potential Vmem of the third capacitor exceeds the threshold of the first inverter element IN1, the signal is transmitted in the order of the first inverter element IN1, the second inverter element IN2, the third inverter element IN3, and the fourth inverter element IN4. The signal output from the fourth inverter element IN4 to output terminal Y becomes a new spike.

[0067] Furthermore, the new spike output to output terminal Y is also input to the gate of the seventh switching element t11. When a spike is input to the gate of the seventh switching element t11, it turns on and discharges the third capacitor CM. The discharge of the third capacitor CM resets it.

[0068] <Effects of this embodiment> The effects of this embodiment will be described below using examples.

[0069] (Example 1) As shown in Figure 5, a simple network was constructed by combining the neuron circuit n11, the first synaptic circuit s11, and the second synaptic circuit s12, and circuit simulations were performed.

[0070] The first synaptic circuit s11 was given a positive weight. The first synaptic circuit s11 acts as an excitatory synapse, increasing the membrane potential Vmem of the neuron circuit n11. The second synaptic circuit s12 was given a negative weight. The second synaptic circuit s12 acts as an inhibitory synapse, decreasing the membrane potential Vmem of the neuron circuit n11.

[0071] Furthermore, the absolute value of the positive weight of the first synaptic circuit s11 is assumed to be greater than the absolute value of the negative weight of the second synaptic circuit s12.

[0072] Figure 6 shows the circuit simulation results. Reference numeral 601 indicates the voltage waveform of the spike data input to the input terminal x11 of the first synaptic circuit s11. Reference numeral 602 indicates the voltage waveform of the spike data input to the input terminal x12 of the second synaptic circuit s12. Reference numeral 603 indicates the membrane potential of the neuron circuit n11. Reference numeral 694 indicates the voltage waveform of the spike data output from the output terminal y11 of the neuron circuit n11.

[0073] As shown in Figure 6, the membrane potential of neuronal circuit n11 increases each time a spike is input to input terminal x11 of the first synaptic circuit s11. Conversely, the membrane potential of neuronal circuit n11 decreases each time a spike is input to input terminal x12 of the second synaptic circuit s12.

[0074] Since the absolute value of the positive weight of the first synaptic circuit s11 is greater than the absolute value of the negative weight of the second synaptic circuit s12, the membrane potential of neuron circuit n11 continues to increase and eventually reaches the threshold voltage of neuron circuit n11. Neuron circuit n11 generates a spike. After the spike is generated, the membrane potential of neuron circuit n11 is reset to its initial potential of 0V.

[0075] In Example 1, the spike data is defined using the number of spikes that make up the spike data. On the other hand, in Examples 2 to 5, which will be described later, as shown in Figure 7, the spike data is defined using not only the number of spikes SN that make up the spike data, but also the width SW of each spike that makes up the spike data and the amplitude SA of each spike that makes up the spike data.

[0076] The disclosers conducted circuit simulations and confirmed a positive correlation between spike width SW and membrane potential rise, as shown in Figure 8. Furthermore, the disclosers conducted circuit simulations and confirmed a positive correlation between spike amplitude SA and membrane potential rise, as shown in Figure 9.

[0077] (Example 2) In Example 2, encoding is performed by assigning the upper bits of the transmitted signal to a wide spike width and the lower bits to a narrow spike width. As shown in Figure 10, the membrane potential rise is 1:2, so the upper bits of the 2-bit transmitted signal can be assigned to a 200ns spike width and the lower bits to a 10ns spike width. More specifically, as shown in Figure 11, the 2-bit transmitted signals 00 to 11 are encoded with a combination of 200ns and 10ns spike widths.

[0078] Figure 12 shows the circuit simulation results using conventional encoding. Code 1201 shows the voltage waveform of the spike data input to input terminal x11 of the first synaptic circuit s11. Code 1202 shows the membrane potential of neuron circuit n11. Code 1203 shows the voltage waveform of the spike data output from output terminal y11 of neuron circuit n11.

[0079] Figure 13 shows the circuit simulation results for Example 2. Reference numeral 1301 indicates the voltage waveform of the spike data input to the input terminal x11 of the first synaptic circuit s11. Reference numeral 1302 indicates the membrane potential of the neuron circuit n11. Reference numeral 1303 indicates the voltage waveform of the spike data output from the output terminal y11 of the neuron circuit n11.

[0080] For example, when representing a 2-bit transmission signal 11, conventional encoding using only the number of spikes results in spike data composed of three spikes with a spike width of 10 ns. On the other hand, in Example 2, it is represented by spike data composed of one spike with a spike width of 200 ns and one spike with a spike width of 10 ns. According to the circuit simulation results, conventional encoding required an average of 7.3 spikes to generate one output spike, whereas in Example 2, 5.1 spikes were sufficient. This indicates that the processing time has been reduced. Theoretically, it should be 2 / 3 = 0.67, and the result obtained is approximately correct at 5.1 / 7.3 = 0.69.

[0081] Furthermore, the effect of reducing processing time becomes more pronounced as the number of bits in the transmitted signal increases. For example, when representing an 8-bit transmitted signal 11111111, conventional encoding represents it as spike data composed of 255 spikes of the same spike width. On the other hand, in Example 2, it is represented as spike data composed of 8 different spike widths. The processing time is reduced to 8 / 255.

[0082] (Example 3) In Example 3, encoding is performed by assigning the upper bits of the transmitted signal to a large spike amplitude and the lower bits to a small spike amplitude. As shown in Figure 14, the membrane potential rise is 1:2:4, so the upper bits of the 3-bit transmitted signal should be assigned to a 0.8V spike amplitude, the middle bit to a 0.42V spike amplitude, and the lower bit to a 0.4V spike amplitude. More specifically, as shown in Figure 15, the 3-bit transmitted signals 000 to 111 are encoded with a combination of spike widths of 0.8V, 0.42V, and 0.4V.

[0083] Figure 16 shows the circuit simulation results using conventional coding. Code 1601 shows the voltage waveform of the spike data input to the input terminal x11 of the first synaptic circuit s11. Code 1602 shows the membrane potential of the neuron circuit n11. Code 1603 shows the voltage waveform of the spike data output from the output terminal y11 of the neuron circuit n11.

[0084] Figure 17 shows the circuit simulation results for Example 3. Reference numeral 1701 indicates the voltage waveform of the spike data input to the input terminal x11 of the first synaptic circuit s11. Reference numeral 1702 indicates the membrane potential of the neuron circuit n11. Reference numeral 1703 indicates the voltage waveform of the spike data output from the output terminal y11 of the neuron circuit n11.

[0085] For example, when representing a 3-bit transmission signal 111, conventional coding using only the number of spikes results in spike data composed of seven spikes with an amplitude of 0.4V. On the other hand, in Example 3, it is represented by spike data composed of one spike with an amplitude of 0.8V, one spike with an amplitude of 0.42V, and one spike with an amplitude of 0.4V. According to circuit simulation results, conventional coding required an average of 10 spikes to generate one output spike, whereas the coding in Example 3 required only 5.4 spikes. This indicates a reduction in processing time. Theoretically, it should be 3 / 7 = 0.43, and 5.4 / 10 = 0.54, which is roughly the correct result.

[0086] Furthermore, as in Example 2, the effect of reducing processing time becomes more pronounced as the number of bits in the transmitted signal increases.

[0087] (Example 4) The difference between Example 4 and Example 3 is that the membrane potential rise is 1:4. As shown in Figure 18, since the membrane potential rise is 1:4, the upper bits of the 3-bit transmission signal can be assigned to a 0.8V spike amplitude, and the middle and lower bits to a 0.4V spike amplitude. More specifically, as shown in Figure 19, the 3-bit transmission signals 000 to 111 are encoded using a combination of 0.8V and 0.4V spike widths.

[0088] Figure 20 shows the circuit simulation results for Example 4. Reference numeral 2001 indicates the voltage waveform of the spike data input to the input terminal x11 of the first synaptic circuit s11. Reference numeral 2002 indicates the membrane potential of the neuron circuit n11. Reference numeral 2003 indicates the voltage waveform of the spike data output from the output terminal y11 of the neuron circuit n11.

[0089] For example, when representing a 3-bit transmission signal 111, conventional encoding using only the number of spikes results in spike data composed of 7 spikes with an amplitude of 0.4V. On the other hand, in Example 4, it is represented by spike data composed of 1 spike with an amplitude of 0.8V and 3 spikes with an amplitude of 0.4V. According to the circuit simulation results, conventional encoding required an average of 10 spikes to generate one output spike, as described in Example 3, whereas in Example 4, 6.8 spikes were sufficient. This indicates a reduction in processing time. Theoretically, it should be 4 / 7 = 0.57, and 6.8 / 10 = 0.68, which is roughly the correct result.

[0090] (Example 5) Example 5 performs encoding by assigning each bit of the transmitted signal to a different combination of spike width and spike amplitude.

[0091] The method for assigning each bit of the transmitted signal to different spike width and spike amplitude combinations can be chosen depending on the situation. Generally, generating circuits for different spike widths and spike amplitudes requires a certain amount of circuit area. Therefore, in applications where minimizing circuit area is desired, it is preferable to use fewer types of spike widths and spike amplitudes and group several bits together to assign them to a single spike width and spike amplitude.

[0092] On the other hand, in applications where it is desirable to improve processing speed even if the circuit area is increased, it is preferable to increase the variety of spike widths and spike amplitudes, and to assign each bit of the transmitted signal separately to different combinations of spike widths and spike amplitudes.

[0093] For example, Figure 21 shows a combination of spike width and spike amplitude that results in a membrane potential rise ratio of approximately 8:4:2:1. Figure 22 shows the circuit simulation results for Example 5. Reference numeral 2201 indicates the voltage waveform of the spike data input to input terminal x11 of the first synaptic circuit s11. Reference numeral 2202 indicates the membrane potential of neuron circuit n11.

[0094] <Other Embodiments> In the embodiments described above, the spike data was encoded as binary numbers, but this disclosure is not limited thereto. As shown in Figure 23, the spike data encoded as binary numbers, indicated by code 2301, can be represented as spike data consisting of a combination of four membrane potential rise widths, indicated by code 2302. That is, different intensities of the transmitted signal can be assigned to different spike widths and spike amplitudes.

[0095] More specifically, if one of the two parameters defining the spike pattern is the width of each spike that makes up the spike data, then the spike data can be encoded as the product of the number of spikes and the average spike intensity, and the width of each spike should be increased from small to large spike intensities.

[0096] Furthermore, if at least one of the two parameters defining the spike pattern is the amplitude of each spike that makes up the spike data, then the spike data can be encoded as the product of the number of spikes and the average value of the spike intensity, and the amplitude of each spike can be increased as the spike intensity increases from small to large.

[0097] Here, the spike intensity is expressed as a function f(SA,SW) that increases monotonically with respect to both the spike amplitude SA and the spike width SW. By appropriately setting the set of spike intensities, the ratio of membrane potential displacement to one weight can be set to 1:2:3:4 or 1:2:4:8.

[0098] Furthermore, the average spike intensity is the average of the sum of the spike intensities of each individual spike. More specifically, it is the sum of the spike intensities of each individual spike divided by the number of spikes. Therefore, the product of the number of spikes and the average spike intensity is the sum of the spike intensities. As shown in Figure 23, between the spike data indicated by symbol 2301 and the spike data indicated by symbol 2302, the numbers written below each spike, i.e., the sum of the spike intensities, are both 10. In other words, the sums are equal.

[0099] Furthermore, this disclosure is applicable to all neural networks and neuromorphic systems. For example, in a neural network combining multiple convolutional layers and several final fully connected layers, as shown in Figure 24, this disclosure is applicable to the fully connected layers.

[0100] <Further Other Embodiments> Figure 25 shows a circuit configuration for realizing synaptic and neuronal circuits according to further other embodiments of the present disclosure. As shown in Figure 25, the circuit 2500 according to this embodiment comprises a matrix array MX, a multiplexer group MP, a first selection transistor group PT, a second selection transistor group NT, a first selection circuit 2501, a second selection circuit 2502, a third selection circuit 2503, a voltage supply circuit 2504, and a control circuit 2505.

[0101] (Device configuration) The matrix array MX has 16 mem capacitors CM11 to CM44 arranged in a matrix at the intersections of each of the four bit lines B1 to B4 and each of the four word lines W1 to W4. Hereinafter, the four bit lines B1 to B4 will be collectively referred to as "bit line BG". The four word lines W1 to W4 will be collectively referred to as "word line WG". The 16 mem capacitors CM11 to CM44 will be collectively referred to as "mem capacitor CMG". In this embodiment, the number of bit lines BG is 4, the number of word lines WG is 4, and the number of mem capacitors CMG is 16, but this embodiment is not limited to these numbers.

[0102] The memcapacitor CMG is a memcapacitor having the electrical characteristics shown by reference numeral 401 in Figure 4 and the schematic configuration shown by reference numeral 402 in Figure 4. Since Figure 4 has already been explained, it will not be explained again here.

[0103] A mem capacitor CMG has two terminals. One terminal is connected to the bit line BG, and the other terminal is connected to the word line WG. For example, in the case of mem capacitor CM11, one terminal of mem capacitor CM11 is connected to the bit line B1, and the other terminal is connected to the word line W1.

[0104] The multiplexer group MP has four multiplexers M1 to M4. Hereinafter, the four multiplexers M1 to M4 will be collectively referred to as "multiplexer MG". In this embodiment, the number of multiplexers MG is set to four, but this embodiment is not limited to this number.

[0105] The multiplexer MG has four input terminals, one output terminal, and one control terminal. Based on a control signal input from the control terminal, the multiplexer MG selects one of four voltages input from each of the four input terminals. In this case, the multiplexer MG outputs the selected voltage from its output terminal. Alternatively, based on a control signal input from the control terminal, the multiplexer MG may choose not to output any of the four voltages mentioned above. In this case, the output terminal of the multiplexer MG is disconnected from all four input terminals.

[0106] The first selected transistor group PT has four p-type MOSFETs P1 to P4. Hereinafter, the four p-type MOSFETs P1 to P4 will be collectively referred to as "p-type MOSFETPG". In this embodiment, the number of p-type MOSFETPGs is set to four, but this embodiment is not limited to this number.

[0107] The source terminal of a p-type MOSFET PG is connected to the power supply potential Vdd, and the drain terminal is connected to the bit line BG. For example, in the case of p-type MOSFET P1, the source terminal of p-type MOSFET P1 is connected to the power supply potential Vdd, and the drain terminal is connected to the bit line B1.

[0108] The second selection transistor group NT has four n-type MOSFETs N1 to N4. Hereafter, the four n-type MOSFETs N1 to N4 will be collectively referred to as "n-type MOSFET NG". In this embodiment, the number of n-type MOSFET NGs is set to four, but this embodiment is not limited to this number.

[0109] The source terminal of an n-type MOSFET NNG is connected to ground potential GND, and the drain terminal is connected to bit line BG. For example, in the case of n-type MOSFET N1, the source terminal of n-type MOSFET N1 is connected to ground potential GND, and the drain terminal is connected to bit line B1.

[0110] The first selection circuit 2501 outputs a control signal SP. This control signal SP is input to the gate terminal of the p-type MOSFETPG of the first selection transistor group PT. When the level of the control signal SP is low, the p-type MOSFETPG turns on. When the p-type MOSFETPG is on, the bit line BG is connected to the power supply potential Vdd via the p-type MOSFETPG.

[0111] The second selection circuit 2502 outputs a control signal SN. This control signal SN is input to the gate terminal of the n-type MOSFETNG of the second selection transistor group NT. When the level of the control signal SN is high, the n-type MOSFETNG turns on. When the n-type MOSFETNG turns on, the bit line BG is connected to ground potential GND via the n-type MOSFETNG.

[0112] The third selection circuit 2503 outputs control signals SM1 to SM4. Hereinafter, the four control signals SM1 to SM4 will be collectively referred to as "control signal SMG". In this embodiment, the number of control signal SMG is set to four, but this embodiment is not limited to this number. The control signal SMG is input to the control terminal of the multiplexer MG of the multiplexer group MP. In this embodiment, the multiplexer MG selects one of the four voltages, or selects not to output any of them, so the control signal SMG requires at least 3 bits. However, this embodiment is not limited to this.

[0113] The voltage supply circuit 2504 supplies voltages VL1 to VL4. Hereinafter, the four voltages VL1 to VL4 will be collectively referred to as "voltage VLG". In this embodiment, the number of voltage VLGs is set to four, but this embodiment is not limited to this number. Voltage VLGs are input to the four input terminals of the multiplexer MG of the multiplexer group MP.

[0114] The voltage supply circuit 2504 may generate the voltage VLG internally, or it may be supplied with the voltage VLG from an external source.

[0115] The control circuit 2505 comprehensively controls the first selection circuit 2501, the second selection circuit 2502, the third selection circuit 2503, and the voltage supply circuit 2504.

[0116] (device operation) Next, we will explain the operation of circuit 2500.

[0117] Based on instructions from the control circuit 2505, the voltage supply circuit 2504 supplies voltage VLG to the multiplexer MG of the multiplexer group MP. Voltages VL1 to VL4 are input to the four input terminals of the multiplexer MG, respectively. In this embodiment, voltage VL1 is the voltage of the ground potential GND, voltage VL2 is 1 / 4 of the power supply potential Vdd, voltage VL3 is 2 / 4, or 1 / 2, of the power supply potential Vdd, and voltage VL4 is 3 / 4 of the power supply potential Vdd. Voltages VL1 to VL4 correspond to the spike amplitudes of the four spikes input to the circuit 2500, respectively.

[0118] In this embodiment, the voltages VL1 to VL4 are defined as described above, but this embodiment is not limited to the above.

[0119] Based on instructions from control circuit 2505, the third selection circuit 2503 outputs the control signal SMG to the multiplexer MG of the multiplexer group MP. Control signals SM1 to SM4 are input to the respective control terminals of multiplexers M1 to M4.

[0120] The multiplexer MG selects one of the voltages VL1 to VL4 based on the control signal SMG and outputs the selected voltage from its output terminal. Since the output terminal of the multiplexer MG is connected to the word line WG, the voltage output from the output terminal of the multiplexer MG is applied to the word line WG.

[0121] Based on instructions from control circuit 2505, the first selection circuit 2501 sets the level of the control signal SP to a low level. When the level of the control signal SP is low, the p-type MOSFETPG of the first selection transistor group PT turns on. When the p-type MOSFETPG turns on, the voltage of the power supply potential Vdd is applied to the bit line BG via the p-type MOSFETPG.

[0122] In this way, when voltage VLG is applied to the word line WG and power supply potential Vdd is applied to the bit line BG, a potential difference between the voltage VLG applied to the word line WG and the power supply potential Vdd applied to the bit line BG is applied across the memcapacitor CMG. The memcapacitor CMG is charged by the application of this potential difference.

[0123] Here, we will explain the charging operation of the memcapacitor CMG in more detail. For the purposes of this explanation, we will use the memcapacitor CM22 as an example.

[0124] When voltage VL1 is output from the output terminal of multiplexer M2, voltage VL1 is applied to word line W2. On the other hand, a voltage of the power supply potential Vdd is applied to bit line B2, so the following potential difference (hereinafter referred to as the "first potential difference") is applied across the mem capacitor CM22. (Voltage at power supply potential Vdd) - (Voltage VL1) = (Voltage at power supply potential Vdd) Similarly, when a voltage VL2 is output from the output terminal of the multiplexer M2, the following potential difference (hereinafter referred to as the "second potential difference") will be applied across the mem capacitor CM22. (Voltage at power supply potential Vdd) - (Voltage VL2) = (Voltage at 3 / 4 of power supply potential Vdd) Similarly, when a voltage VL3 is output from the output terminal of the multiplexer M2, the following potential difference (hereinafter referred to as the "third potential difference") will be applied across the mem capacitor CM22. (Voltage at power supply potential Vdd) - (Voltage VL3) = (Voltage at half the power supply potential Vdd) Similarly, when a voltage VL4 is output from the output terminal of the multiplexer M2, the following potential difference (hereinafter referred to as the "fourth potential difference") will be applied across the mem capacitor CM22. (Voltage at power supply potential Vdd) - (Voltage VL4) = (Voltage at 1 / 4 of power supply potential Vdd) The memcapacitor CM22 accumulates charge corresponding to each of the first to fourth potential differences applied across its terminals.

[0125] On the other hand, if none of the voltages VL1 to VL4 are output from the output terminals of the multiplexer M2, no potential difference is applied across the memcapacitor CM22, and therefore no charge is accumulated in the memcapacitor CM22.

[0126] Returning to the explanation of the operation of circuit 2500, based on instructions from control circuit 2505, the first selection circuit 2501 raises the level of the control signal SP. The third selection circuit 2503 stops the output of the control signal SMG. The voltage supply circuit 2504 stops supplying voltages VL1 to VL4. The second selection circuit 2502 raises the level of the control signal SN.

[0127] When the control signal SN reaches a high level, the n-type MOSFETNG of the second selection transistor group NT turns on. When the n-type MOSFETNG turns on, the voltage at ground potential GND is applied to the bit line BG via the n-type MOSFETNG.

[0128] In this way, when the ground potential GND is applied to the bit line BG, the charge stored in the memcapacitor CMG is discharged toward the ground potential GND through the bit line BG and the n-type MOSFET NG.

[0129] Here, we will explain the discharge operation of the memcapacitor CMG in more detail. For the purposes of this explanation, we will use memcapacitors CM21 to CM24, connected to bit line B2, as an example.

[0130] One of the first to fourth potential differences described above is applied across the terminals of each of the memcapacitors CM21 to CM24. As a result, each of the memcapacitors CM21 to CM24 accumulates an amount of charge corresponding to the potential difference applied across its terminals.

[0131] When the n-type MOSFET N2 is turned on, a voltage equal to ground potential (GND) is applied to the bit line B2, causing the charge accumulated in each of the memcapacitors CM21 to CM24 to flow into ground potential (GND).

[0132] Let's return to the explanation of the operation of circuit 2500. As shown in Figure 25, the input terminals of inverter elements I1 to I4 are connected to each of the bit lines B1 to B4. Output signals O1 to O4 are output from the output terminals of inverter elements I1 to I4. Hereafter, the four inverter elements I1 to I4 will be collectively referred to as "inverter element IG". Also, the four output signals O1 to O4 will be collectively referred to as "output signal OX". In this embodiment, the number of inverter elements IG is set to four, but this embodiment is not limited to this number.

[0133] When the charge stored in the memcapacitor CMG is discharged toward the ground potential GND, a potential difference corresponding to the amount of stored charge is input to the input terminal of the inverter element IG connected to the bit line BG. The charge stored in the memcapacitor CMG gradually decreases as the charge is discharged. The potential difference also decreases as the charge stored in the memcapacitor CMG decreases. The inverter element IG outputs an output signal OX from its output terminal from the time the potential difference input to the input terminal exceeds the threshold of the inverter element IG until it falls below that threshold again. In other words, the more charge that is discharged, the longer the period during which the inverter element IG outputs the output signal OX. On the other hand, the less charge that is discharged, the shorter the period during which the inverter element IG outputs the output signal OX. The duration for which output signals O1 to O4 are output corresponds to the spike width of the four spikes output from circuit 2500. However, this embodiment is not limited to a configuration in which the duration for which output signals O1 to O4 are output corresponds to the spike width of the four spikes output from circuit 2500. For example, a circuit capable of accumulating the aforementioned spike width may be connected to the output terminal side of the inverter element IG. This circuit is realized by combining a time integrator circuit and a time comparator circuit. By connecting this circuit to the output terminal side of the inverter element IG, it becomes possible to construct a spiking neuron circuit by considering the spike width output from circuit 2500 as the membrane potential change.

[0134] (Variation 1) In circuit 2500, the voltage VL applied to the word line WG via the multiplexer MG was selected, but this embodiment is not limited to this. A DA converter may be used instead of the multiplexer MG. With a DA converter, multiple voltages can be generated from a single voltage, so it is not necessary to supply four voltages VL1 to VL4 from the voltage supply circuit 2504. One voltage can be supplied from the voltage supply circuit 2504 to the DA converter, and the four voltages VL1 to VL4 can be generated inside the DA converter. However, the circuit configuration of the DA converter is more complex than that of the multiplexer MG.

[0135] (Modification 2) In circuit 2500, voltages VL1 to VL4 correspond to the spike amplitudes of the four spikes input to circuit 2500, but this embodiment is not limited to this. By making the period during which voltage VLG is applied to the word line WG via the multiplexer MG correspond to the spike width, spike data combining spike amplitude and spike width can be constructed.

[0136] Furthermore, by associating the number of times voltage VLG is applied to the word line WG via the multiplexer MG with the number of spikes, it is possible to construct spike data that combines spike amplitude, spike width, and number of spikes.

[0137] (Variation 3) In circuit 2500, an inverter element IG is connected to the bit line BG, and the output signal OX of the inverter element IG is matched to the spike width of the four spikes output from circuit 2500. However, this embodiment is not limited to this. For example, in circuit 2500, an inverter element IG is connected to the bit line BG, but a current mirror circuit may be connected instead of the inverter element IG. This current mirror circuit outputs a current that is the same value as the current flowing through the bit line BG. By connecting the output terminal of this current mirror circuit to the input terminal of the neuron circuit 302 shown in Figure 3, a spiking neuromorphic system can be constructed by inputting the output current of the current mirror circuit into the neuron circuit 302.

[0138] (Modification 4) In circuit 2500, voltages VL1 to VL4 correspond to the spike amplitudes of the four spikes input to circuit 2500, but this embodiment is not limited to this. By making the period during which voltage VLG is supplied from voltage supply circuit 2504 to multiplexer MG correspond to the spike width, spike data combining spike amplitude and spike width can be constructed. [Explanation of Symbols]

[0139] 301 Synaptic circuit, 302 Neuron circuit, c1 First capacitor

Claims

1. A device for running a spiking neural network, The spike data input to the aforementioned device consists of multiple spikes, The aforementioned device is The system includes a circuit that has variable weights, generates a membrane potential displacement adjusted according to the weights for each spike constituting the spike data, and generates a new spike when the integral value of the membrane potential displacement exceeds a threshold. The aforementioned spike data is data in which the input data is represented as a spike pattern. The device wherein the spike pattern is defined using at least two of the following: the number of spikes constituting the spike data, the width of each spike constituting the spike data, and the amplitude of each spike constituting the spike data.

2. The apparatus according to claim 1, further comprising a charge pump circuit that, each time a spike constituting the spike data is input, controls a switching element to be turned on or off in response to the input of the spike, thereby causing a charge transition by charging and discharging a capacitor to generate the film potential displacement.

3. The apparatus according to claim 1 or 2, wherein the circuit further comprises a memcapacitor having variable electrical characteristics that indicate the weight.

4. A method for running a spiking neural network, The above method is a method for converting input data into spike data to be input to a device for running a spiking neural network. The spike data input to the aforementioned device consists of multiple spikes, The aforementioned device is The system includes a circuit that has variable weights, generates a membrane potential displacement adjusted according to the weights for each spike constituting the spike data, and generates a new spike when the integral value of the membrane potential displacement exceeds a threshold. The aforementioned spike data is data in which the input data is represented as a spike pattern. A method for defining the spike pattern using at least two parameters: the number of spikes constituting the spike data, the width of each spike constituting the spike data, and the amplitude of each spike constituting the spike data.

5. In a case where one of the at least two parameters defining the spike pattern is the width of each spike constituting the spike data, The aforementioned spike data is encoded as binary numbers. The method according to claim 4, wherein the width of each spike increases as you move from the least significant bit to the most significant bit of the binary number.

6. In a case where at least one of the two parameters defining the spike pattern is the amplitude of each spike constituting the spike data, The aforementioned spike data is encoded as binary numbers. The method according to claim 4 or 5, wherein the amplitude of each spike increases as you move from the least significant bit to the most significant bit of the binary number.

7. In a case where one of the at least two parameters defining the spike pattern is the width of each spike constituting the spike data, The aforementioned spike data is encoded as the product of the number of spikes and the average value of the spike intensity. The method according to claim 4, wherein the width of each spike increases as the spike strength increases from low to high.

8. In a case where at least one of the two parameters defining the spike pattern is the amplitude of each spike constituting the spike data, The aforementioned spike data is encoded as the product of the number of spikes and the average value of the spike intensity. The method according to claim 4 or 7, wherein the amplitude of each spike increases as the spike intensity increases from low to high.

9. The method according to claim 7, wherein the different spike intensities are assigned to different spike widths and / or different spike amplitudes.

10. Multiple neuronal circuits, Multiple synaptic circuits and Equipped with, Each of the plurality of neuronal circuits is connected to one or more of the plurality of synaptic circuits, and acquires spikes from each connected synaptic circuit. The apparatus according to claim 1 or 2 is a spiking neuromorphic system that realizes a combination of one synaptic circuit and one neuronal circuit connected to the synaptic circuit.

11. The aforementioned device is A matrix array in which multiple mem capacitors are arranged in a matrix at the intersections of multiple word lines and multiple bit lines, Multiple multiplexers, each of which selects one of a plurality of voltages input from each of a plurality of input terminals and applies the selected voltage to the corresponding word line, or selects not to output any of the plurality of voltages, A plurality of p-type MOSFETs are arranged between the power supply potential and the corresponding bit line, A plurality of n-type MOSFETs are arranged between the ground potential and the corresponding bit line. The apparatus according to claim 1 or 2, comprising:

12. The apparatus according to claim 11, wherein the apparatus outputs an output signal corresponding to the amount of charge stored in each of the mem capacitors connected to each of the plurality of bit lines.

13. The apparatus according to claim 11, wherein each of the voltages input to each of the multiplexers corresponds to the spike amplitude of the spikes input to the apparatus.

14. The apparatus according to claim 12, wherein the period during which each of the output signals is output corresponds to the spike width of the spike output from the apparatus.

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