Semiconductor devices, inverter circuits, drive systems, vehicles, and elevators.

Abstract

To provide a semiconductor device capable of improving a surge current tolerance.SOLUTION: A semiconductor device according to an embodiment includes a semiconductor chip having a transistor region and a diode region, a first conductor, and a second conductor. The semiconductor chip includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and a gate electrode. The transistor region is provided with a third electrode spaced apart from the first electrode and close to the diode region. One end of the first conductor is in contact with the first electrode, and one end of the second conductor is in contact with the third electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices, inverter circuits, drive devices, vehicles, and elevators. [Background technology]

[0002] Silicon carbide is expected to be a promising material for next-generation semiconductor devices. Compared to silicon, silicon carbide has superior physical properties, including a band gap three times larger, a breakdown field strength approximately ten times greater, and thermal conductivity approximately three times higher. By utilizing these properties, it is possible to realize, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high voltage resistance, low loss, and can operate at high temperatures.

[0003] A vertical MOSFET using silicon carbide has a built-in pn junction diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, it is possible to pass a freewheeling current using the built-in diode.

[0004] However, when a freewheel current is passed through using a body diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy, which increases the on-resistance of the MOSFET. This increase in on-resistance leads to a decrease in the reliability of the MOSFET. For example, by providing a unipolar Schottky Barrier Diode (SBD) as an internal diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. By providing an SBD as an internal diode in the MOSFET, the reliability of the MOSFET is improved.

[0005] In some cases, a large surge current may flow through a MOSFET, momentarily exceeding its steady state. When a large surge current flows, a large surge voltage is applied, causing heat generation and potentially destroying the MOSFET. The maximum allowable peak current value (I) of the surge current that a MOSFET can handle is... FSM) is called the surge current withstand capacity. In a MOSFET provided with an SBD, it is desirable to improve the surge current withstand capacity.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor device with improved surge current withstand capacity.

Means for Solving the Problems

[0008] The semiconductor device of the embodiment is a semiconductor chip comprising a plurality of transistor regions and at least one diode region, wherein the plurality of transistor regions include an n-type first silicon carbide region having a first surface and a second surface opposite to the first surface and having a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface. The diode region includes a silicon carbide layer, a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region, a second electrode in contact with the second surface, a gate electrode facing the second silicon carbide region, and a gate insulating layer provided between the gate electrode and the second silicon carbide region, wherein the at least one diode region is an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and provided between the first silicon carbide region and the first surface. A silicon carbide layer including a p-type fourth silicon carbide region, a plurality of second portions and a first electrode in contact with the fourth silicon carbide region, and a second electrode, wherein the area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface, and the first diode region, which is one of the plurality of diode regions, is one of the plurality of transistor regions. A semiconductor chip comprising: a transistor region and a second transistor region which is one of the plurality of transistor regions arranged in a first direction relative to the first transistor region, wherein the first transistor region has a third electrode provided on the first surface side of the silicon carbide layer and separated from the first electrode; a first conductor with one end in contact with the first electrode and applying a voltage to the first electrode; and a second conductor with one end in contact with the third electrode and applying a voltage to the third electrode. The first electrode in the first diode region, the first electrode in the first transistor region, and the first electrode in the second transistor region are physically continuous. . [Brief explanation of the drawing]

[0009] [Figure 1] A schematic diagram of the semiconductor device according to the first embodiment. [Figure 2] A schematic top view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 6] A schematic top view of the semiconductor device according to the first embodiment. [Figure 7] A schematic top view of the semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 9] A schematic top view of the semiconductor device of the first comparative example. [Figure 10] A schematic cross-sectional view of the semiconductor device of the first comparative example. [Figure 11] Equivalent circuit diagram of the semiconductor device of the first comparative example. [Figure 12] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view of the semiconductor device of the second comparative example. [Figure 14] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 15] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 16] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 17] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 18] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 19] A schematic cross-sectional view of a modified example of the first embodiment. [Figure 20] A schematic top view of the semiconductor device according to the second embodiment. [Figure 21] A schematic top view of the semiconductor device according to the third embodiment. [Figure 22] A schematic diagram of the drive unit of the fourth embodiment. [Figure 23]Schematic diagram of the vehicle according to the fifth embodiment. [Figure 24] Schematic diagram of the vehicle according to the sixth embodiment. [Figure 25] Schematic diagram of the elevator according to the seventh embodiment

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0011] - Also, in the following description, n + n, n - and p + p, p - When the notations of are used, the above notations represent the relative levels of impurity concentrations in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. In addition, the n + type and n - type may be simply referred to as the n-type, and the p + type and p - type may be simply referred to as the p-type. [[ID=]43]

[0012] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). In addition, the relative level of the impurity concentration can also be determined, for example, from the level of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Also, distances such as the depth and thickness of the impurity region can be obtained, for example, by SIMS. Further, distances such as the depth, thickness, width, and interval of the impurity region can be obtained, for example, from a composite image of an SCM image and an Atomic Force Microscope (AFM) image.

[0013] In this specification, unless otherwise specified, the impurity concentration in the semiconductor region refers to the maximum impurity concentration in that semiconductor region.

[0014] (First Embodiment) The semiconductor device of the first embodiment is a semiconductor chip including a plurality of transistor regions and at least one diode region, wherein the plurality of transistor regions have a first surface and a second surface opposite to the first surface, and include an n-type first silicon carbide region having a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface A silicon carbide layer including an elementary region, a first electrode in contact with a plurality of first portions, a second silicon carbide region, and a third silicon carbide region, a second electrode in contact with a second surface, a gate electrode facing the second silicon carbide region, and a gate insulating layer provided between the gate electrode and the second silicon carbide region, wherein at least one diode region includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a gate insulating layer provided between the first silicon carbide region and the first surface A semiconductor chip comprising: a silicon carbide layer including a p-type fourth silicon carbide region; a plurality of second portions and a first electrode in contact with the fourth silicon carbide region; a second electrode, wherein the area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface; a first diode region, which is one of a plurality of transistor regions, and a second transistor region, which is one of a plurality of transistor regions arranged in a first direction relative to the first transistor region, wherein the first transistor region has a third electrode provided on the first surface side of the silicon carbide layer and separated from the first electrode; a first conductor, one end of which is in contact with the first electrode and applies a voltage to the first electrode; and a second conductor, one end of which is in contact with the third electrode and applies a voltage to the third electrode.

[0015] The semiconductor device of the first embodiment is a discrete device 1000. The discrete device 1000 has one MOSFET 100 mounted on it using a encapsulating resin. The MOSFET 100 is an example of a semiconductor chip.

[0016] The MOSFET 100 included in the discrete device 1000 is a planar gate type vertical MOSFET using silicon carbide. MOSFET 100 is a Double Implantation MOSFET (DIMOSFET), for example, in which the body region and source region are formed by ion implantation. Furthermore, MOSFET 100 is a MOSFET equipped with an SBD (Shottky Barrier Diode) as an internal diode. MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0017] Figures 1(a) and 1(b) are schematic diagrams of a semiconductor device according to the first embodiment. Figure 1(a) is a top view of the discrete device 1000. Figure 1(b) is a cross-sectional view of KK' in Figure 1(a).

[0018] The discrete device 1000 comprises a MOSFET 100, a first bonding wire 110a (first conductor), a second bonding wire 110b, a third bonding wire 110c, a fourth bonding wire 110d (second conductor), a metal bed 120 (first metal layer), a first metal lead 130a (second metal layer), a second metal lead 130b, a third metal lead 130c, a fourth metal lead 130d (third metal layer), and a sealing resin 145.

[0019] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode pad 22, gate wiring 24, and a sense electrode pad 25 (third electrode).

[0020] The MOSFET 100 is mounted on the metal bed 120. The MOSFET 100 is connected to the metal bed 120.

[0021] The metal bed 120 faces the drain electrode 14 of the MOSFET 100. The metal bed 120 is an example of a first metal layer. The metal bed 120 is in contact with the drain electrode 14. The metal bed 120 is electrically connected to the drain electrode 14.

[0022] The metal bed 120 is a metal. For example, the metal bed 120 is a copper alloy or an iron-nickel alloy.

[0023] The first metal lead 130a extends in a first direction. The first metal lead 130a is an example of the second metal layer.

[0024] The first metal lead 130a is an electrode terminal. The first metal lead 130a has the function of applying a voltage to the semiconductor chip 100 from outside the discrete device 1000.

[0025] The first metal lead 130a is a metal. The first metal lead 130a is, for example, a copper alloy or an iron-nickel alloy.

[0026] The second metal lead 130b extends in the first direction. The second metal lead 130b is an electrode terminal. The second metal lead 130b has the function of applying a voltage to the semiconductor chip 100 from outside the discrete device 1000.

[0027] The second metal lead 130b is a metal. The second metal lead 130b is, for example, a copper alloy or an iron-nickel alloy.

[0028] The third metal lead 130c extends in the first direction. The third metal lead 130c is an electrode terminal. The third metal lead 130c has the function of applying a voltage to the semiconductor chip 100 from outside the discrete device 1000. The third metal lead 130c is connected to the metal bed 120.

[0029] The third metal lead 130c is a metal. The third metal lead 130c is, for example, a copper alloy or an iron-nickel alloy.

[0030] The fourth metal lead 130d extends in the first direction. The fourth metal lead 130d is an example of the third metal layer.

[0031] The fourth metal lead 130d is an electrode terminal. The fourth metal lead 130d has the function of applying a voltage to the semiconductor chip 100 from outside the discrete device 1000.

[0032] The fourth metal lead 130d is a metal. The fourth metal lead 130d is, for example, a copper alloy or an iron-nickel alloy.

[0033] The first bonding wire 110a has one end connected to the source electrode 12 and the other end connected to the first metal lead 130a. The first bonding wire 110a is an example of the first conductor.

[0034] The first bonding wire 110a electrically connects the source electrode 12 and the first metal lead 130a. The first bonding wire 110a has the function of applying the voltage applied to the first metal lead 130a to the source electrode 12.

[0035] The first bonding wire 110a is a metal. The first bonding wire 110a is, for example, aluminum, copper, or gold.

[0036] The second bonding wire 110b has one end connected to the source electrode 12 and the other end connected to the first metal lead 130a. The second bonding wire 110b electrically connects the source electrode 12 and the first metal lead 130a. The second bonding wire 110b has the function of applying the voltage applied to the first metal lead 130a to the source electrode 12.

[0037] The second bonding wire 110b is a metal. The second bonding wire 110b is, for example, aluminum, copper, or gold.

[0038] The third bonding wire 110c has one end connected to the gate electrode pad 22 and the other end connected to the second metal lead 130b. The third bonding wire 110c electrically connects the gate electrode pad 22 and the second metal lead 130b. The third bonding wire 110c has the function of applying the voltage applied to the second metal lead 130b to the gate electrode pad 22.

[0039] The third bonding wire 110c is a metal. The third bonding wire 110c is, for example, aluminum, copper, or gold.

[0040] The fourth bonding wire 110d has one end connected to the sense electrode pad 25 and the other end connected to the fourth metal lead 130d. The fourth bonding wire 110d is an example of the second conductor.

[0041] The fourth bonding wire 110d electrically connects the sense electrode pad 25 and the fourth metal lead 130d. The fourth bonding wire 110d has the function of applying the voltage applied to the fourth metal lead 130d to the sense electrode pad 25.

[0042] The fourth bonding wire 110d is a metal. The fourth bonding wire 110d is, for example, aluminum, copper, or gold.

[0043] The sealing resin 145 covers the MOSFET 100, the first bonding wire 110a, the second bonding wire 110b, the third bonding wire 110c, the fourth bonding wire 110d, and the bed 120. The sealing resin 145 has the function of protecting the MOSFET 100, the first bonding wire 110a, the second bonding wire 110b, the third bonding wire 110c, the fourth bonding wire 110d, and the metal bed 120. The sealing resin 145 is, for example, an epoxy resin.

[0044] A source voltage, for example, is applied to the first metal lead 130a from outside the MOSFET 100. The first metal lead 130a functions, for example, as a source terminal.

[0045] A gate voltage, for example, is applied to the second metal lead 130b from outside the MOSFET 100. The second metal lead 130b functions, for example, as a gate terminal.

[0046] A third metal lead 130c is subjected to, for example, a drain voltage from outside the MOSFET 100. The third metal lead 130c functions, for example, as a drain terminal.

[0047] A source voltage, for example, is applied to the fourth metal lead 130d from outside the MOSFET 100. An ammeter, for example, is also connected to the fourth metal lead 130d. The fourth metal lead 130d functions, for example, as a current sense terminal.

[0048] Figures 2(a) and 2(b) are schematic top views of a semiconductor device according to the first embodiment. Figure 2(a) is a diagram showing the arrangement of each region of the MOSFET 100. Figure 2(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 100.

[0049] Figure 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 is a cross-sectional view AA' of Figure 2(a).

[0050] Figure 4 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 is a cross-sectional view of BB' in Figure 2(a).

[0051] Figures 5(a) and 5(b) are schematic cross-sectional views of a semiconductor device according to the first embodiment. Figure 5(a) is a cross-sectional view of CC' in Figure 2(a). Figure 5(b) is a cross-sectional view of DD' in Figure 2(a).

[0052] As shown in Figure 2(a), the MOSFET 100 comprises a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a diode region 102a (first diode region), a diode region 102b, and a peripheral region 103. Transistor region 101a is an example of the first transistor region. Transistor region 101b is an example of the second transistor region. Diode region 102a is an example of the first diode region.

[0053] Hereinafter, transistor regions 101a, 101b, 101c, and 101d may be referred to individually or collectively simply as transistor region 101. Similarly, diode regions 102a and 102b may be referred to individually or collectively simply as diode region 102.

[0054] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0055] The peripheral region 103 surrounds the transistor region 101 and the diode region 102. The peripheral region 103 is provided with a gate electrode pad 22 and gate wiring 24.

[0056] In the peripheral region 103, for example, a termination structure is provided to improve the breakdown voltage of the MOSFET 100. The termination structure that improves the breakdown voltage of the MOSFET 100 is, for example, a resurf or a guard ring.

[0057] The diode region 102 is provided between the two transistor regions 101. For example, the diode region 102a is provided between the transistor region 101a and the transistor region 101b. The transistor region 101b is provided in a first direction parallel to the first plane P1 with respect to the transistor region 101a.

[0058] For example, the diode region 102b is provided between the transistor region 101c and the transistor region 101d. The transistor region 101d is provided in a first direction relative to the transistor region 101c.

[0059] The width of the diode region 102 in the first direction is, for example, 30 μm or more. For example, the width of the diode region 102a in the first direction is 30 μm or more.

[0060] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, gate wiring 24, and a sense electrode pad 25.

[0061] Within the silicon carbide layer 10, n + Drain region 26 of type n - Type drift region 28 (first silicon carbide region), p-type body region 30 (second silicon carbide region), p-type p-region 32 (fourth silicon carbide region), n + The n-type source region 34 (third silicon carbide region), the n-type first bottom region 36, and the n-type second bottom region 38 are included.

[0062] The drift region 28 includes a plurality of first parts 28a and a plurality of second parts 28b. The body region 30 includes a low-concentration part 30a and a high-concentration part 30b. The p region 32 includes a low-concentration part 32a and a high-concentration part 32b.

[0063] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

[0064] The silicon carbide layer 10 comprises a first surface ("P1" in Figure 3) and a second surface ("P2" in Figure 3). The first surface P1 and the second surface P2 face each other. Hereinafter, the first surface may be referred to as the front surface and the second surface as the back surface. Hereinafter, "depth" refers to the depth relative to the first surface.

[0065] The first surface P1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0066] n + The drain region 26 is provided on the back side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 26 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0067] n - A drift region 28 of this type is provided between the drain region 26 and the first surface P1. A drift region 28 is provided between the source electrode 12 and the drain electrode 14. A drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0068] The drift region 28 is located on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 28 is lower than the n-type impurity concentration in the drain region 26. The n-type impurity concentration in the drift region 28 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 17 cm -3 The following applies: The thickness of the drift region 28 is, for example, between 5 μm and 150 μm.

[0069] The drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b. The first portions 28a are tangent to the first surface P1. The first portions 28a are sandwiched between two body regions 30. The first portions 28a function as the n-type semiconductor region of the SBD. The first portions 28a extend, for example, in a second direction.

[0070] The second portion 28b is tangent to the first surface P1. The second portion 28b is sandwiched between two p-regions 32. The second portion 28b functions as an n-type semiconductor region of the SBD. The second portion 28b extends, for example, in a second direction.

[0071] The p-type body region 30 is provided between the drift region 28 and the first surface P1. A portion of the body region 30 functions as the channel region of the MOSFET 100. The body region 30 functions as the p-type semiconductor region of the pn junction diode.

[0072] The body region 30 includes a low-concentration portion 30a and a high-concentration portion 30b. The high-concentration portion 30b is provided between the low-concentration portion 30a and the first surface P1. The p-type impurity concentration in the high-concentration portion 30b is higher than the p-type impurity concentration in the low-concentration portion 30a.

[0073] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the low-concentration portion 30a is, for example, 1 × 10⁻⁶. 16 cm -3 The above 5 x 10 17 cm -3The following applies: The p-type impurity concentration in the high-concentration portion 30b is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0074] The depth of the body region 30 is, for example, 0.3 μm or more and 1.0 μm or less.

[0075] The body region 30 is fixed at the potential of the source electrode 12.

[0076] The p-type p-region 32 is provided between the drift region 28 and the first surface P1. The p-region 32 functions as the p-type semiconductor region of the pn junction diode.

[0077] The p-region 32 includes a low-concentration portion 32a and a high-concentration portion 32b. The high-concentration portion 32b is located between the low-concentration portion 32a and the first surface P1. The p-type impurity concentration in the high-concentration portion 32b is higher than that in the low-concentration portion 32a.

[0078] The p-region 32 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the low-concentration portion 32a is, for example, 1 × 10⁻⁶. 16 cm -3 The above 5 x 10 17 cm -3 The following applies: The p-type impurity concentration in the high-concentration portion 32b is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0079] The concentration of p-type impurities in the low-concentration portion 32a of the p-region 32 is substantially equal to, for example, the concentration of p-type impurities in the low-concentration portion 30a of the body region 30.

[0080] The concentration of p-type impurities in the high-concentration portion 32b of the p-region 32 is substantially equal to, for example, the concentration of p-type impurities in the high-concentration portion 30b of the body region 30.

[0081] The width of the p region 32 in the first direction is, for example, greater than the width of the body region 30 in the first direction. The depth of the p region 32 is, for example, between 0.3 μm and 1.0 μm.

[0082] The p region 32 is fixed at the potential of the source electrode 12.

[0083] n + The source region 34 of the mold is provided between the body region 30 and the first surface P1. The source region 34 is provided between the low-density portion 30a of the body region 30 and the first surface P1. + The source region 34 of type , for example, extends in a second direction.

[0084] Source region 34 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 34 is higher than the concentration of n-type impurities in drift region 28.

[0085] The n-type impurity concentration in source region 34 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following conditions apply: The depth of the source region 34 is shallower than the depth of the body region 30. For example, the depth of the source region 34 is between 0.1 μm and 0.3 μm.

[0086] The n-type first bottom region 36 is provided between the drift region 28 and the body region 30. The first bottom region 36 is in contact with, for example, the drift region 28 and the body region 30. The width of the first bottom region 36 in the first direction is substantially the same as, for example, the width of the body region 30 in the first direction.

[0087] The first bottom region 36 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the first bottom region 36 is higher than the n-type impurity concentration in the drift region 28.

[0088] The n-type impurity concentration in the first bottom region 36 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 2 x 10 17 cm-3 The following applies: The thickness of the first bottom region 36 is, for example, 0.4 μm or more and 1.5 μm or less.

[0089] The n-type second bottom region 38 is provided between the drift region 28 and the p region 32. The second bottom region 38 is, for example, in contact with the drift region 28 and the p region 32. The width of the second bottom region 38 in the first direction is, for example, substantially the same as the width of the p region 32 in the first direction.

[0090] The second bottom region 38 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the second bottom region 38 is higher than that in the drift region 28. The n-type impurity concentration in the second bottom region 38 is substantially the same as, for example, that of the first bottom region 36.

[0091] The n-type impurity concentration in the second bottom region 38 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 2 x 10 17 cm -3 The following applies: The thickness of the second bottom region 38 is, for example, 0.4 μm or more and 1.5 μm or less.

[0092] The gate electrode 18 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate electrode 18 extends in a second direction parallel to the first surface P1 and perpendicular to the first direction. Multiple gate electrode 18s are arranged parallel to each other in the first direction. The gate electrode 18 has a so-called stripe shape.

[0093] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0094] The gate electrode 18 faces, for example, the portion of the body region 30 that is in contact with the first surface P1. The gate electrode 18 also faces, for example, the portion of the drift region 28 that is in contact with the first surface P1.

[0095] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 30. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region 28.

[0096] The gate insulating layer 16 is, for example, silicon oxide. For the gate insulating layer 16, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0097] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 has the function of electrically isolating the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0098] The source electrode 12 is provided on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface P1.

[0099] The source electrode 12 is in contact with the first portion 28a of the drift region 28, the second portion 28b of the drift region 28, the body region 30, the p region 32, and the source region 34.

[0100] The source electrode 12 has a first region 12a on the transistor region 101 and a second region 12b on the diode region 102.

[0101] The source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a layered structure of titanium (Ti) and aluminum (Al).

[0102] The body region 30, the p region 32, and the portion of the source electrode 12 in contact with the source region 34 are, for example, made of metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. The portion of the source electrode 12 in contact with the first portion 28a and the second portion 28b of the drift region 28 is not provided with metal silicide.

[0103] The junction between the body region 30, the p region 32, and the source region 34 and the source electrode 12 is, for example, an ohmic junction. The junction between the first portion 28a and the second portion 28b of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0104] The drain electrode 14 is provided on the side of the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface P2. The drain electrode 14 is in contact with the drain region 26.

[0105] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0106] The junction between the drain region 26 and the drain electrode 14 is, for example, an ohmic junction.

[0107] The gate electrode pad 22 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate electrode pad 22 is provided on the interlayer insulating layer 20. The gate electrode pad 22 is provided to achieve an electrical connection between the outside and the gate electrode 18.

[0108] The gate wiring 24 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate wiring 24 is connected to the gate electrode pad 22. The gate wiring 24 is electrically connected to the gate electrode 18.

[0109] A portion of the gate wiring 24 extends in a first direction parallel to the first plane P1. Another portion of the gate wiring 24 extends in a second direction parallel to the first plane P1 and perpendicular to the first direction.

[0110] The gate electrode pad 22 and gate wiring 24 contain metal. The metal forming the gate electrode pad 22 and gate wiring 24 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The gate electrode pad 22 and gate wiring 24 are formed from, for example, the same metallic material as the source electrode 12.

[0111] The gate wiring 24 between the two source electrodes 12 extends in a first direction. The source electrode 12 is sandwiched between the two gate wirings 24 extending in the first direction. The source electrode 12 is sandwiched between the two gate wirings 24 extending in a second direction.

[0112] The sense electrode pad 25 is provided on the side of the first surface P1 of the silicon carbide layer 10. The sense electrode pad 25 is provided in only one transistor region among a plurality of transistor regions 101, for example. The sense electrode pad 25 is provided in the first transistor region 101a, for example. The sense electrode pad 25 is provided adjacent to the diode region 102.

[0113] The sense electrode pad 25 is spaced apart from the source electrode 12. The distance between the sense electrode pad 25 and the source electrode 12 is smaller than, for example, the distance between the sense electrode pad 25 and the gate wiring 24. The minimum distance between the sense electrode pad 25 and the source electrode 12 is smaller than, for example, the minimum distance between the sense electrode pad 25 and the gate wiring 24.

[0114] The sense electrode pad 25 is in contact with the first portion 28a of the drift region 28, the second portion 28b of the drift region 28, the body region 30, the p region 32, and the source region 34.

[0115] The sense electrode pad 25 is provided to detect (sense) a short circuit between the source electrode 12 and the sense electrode pad 25. The sense electrode pad 25 is also provided to detect (sense) the amount of ON current flowing through the MOSFET 100.

[0116] The sense electrode pad 25 contains a metal. The metal forming the sense electrode pad 25 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The sense electrode pad 25 is formed from the same metallic material as, for example, the source electrode 12, the gate electrode pad 22, and the gate wiring 24.

[0117] The area of ​​the sense electrode pad 25 is, for example, 10% or less of the area of ​​the source electrode 12.

[0118] As shown in Figure 3, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. Within the silicon carbide layer 10 of the transistor region 101, n + Drain region 26 of type n - Type drift region 28 (first silicon carbide region), p-type body region 30 (second silicon carbide region), n + The source region 34 (third silicon carbide region) of the n-type transistor is included, as is the first bottom region 36 of the n-type transistor. Additionally, the drift region 28 of the transistor region 101 includes multiple first portions 28a.

[0119] In the transistor region 101, the source electrode 12, the first portion 28a of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. In addition, the source electrode 12, the body region 30, the first bottom region 36, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

[0120] The first distance (d1 in Figures 5(a) and 5(b)) between two adjacent first portions 28a with the body region 30 in between is, for example, 3 μm or more and 30 μm or less.

[0121] As shown in Figure 4, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). Within the silicon carbide layer 10 of the diode region 102, n + Drain region 26 of type n -The diode region 102 includes a drift region 28 of type n (first silicon carbide region), a p-type p-region 32 (fourth silicon carbide region), and a second bottom region 38 of type n. The drift region 28 of the diode region 102 also includes multiple second portions 28b.

[0122] In the diode region 102, the source electrode 12, the second portion 28b of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. In addition, the source electrode 12, the p region 32, the second bottom region 38, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

[0123] The second distance (d2 in Figures 5(a) and 5(b)) between two adjacent second portions 28b with the p region 32 in between is, for example, 3 μm or more and 30 μm or less. The second distance d2 between two adjacent second portions 28b with the p region 32 in between is substantially equal to the first distance d1 between two adjacent first portions 28a with the body region 30 in between. The first distance d1 and the second distance d2 are distances in the first direction.

[0124] Figure 6 is a schematic top view of a semiconductor device according to the first embodiment. Figure 6 shows the pattern of the body region 30 projected onto the first surface P1 and the pattern of the p region 32 projected onto the first surface P1. The patterns of the body region 30 and the p region 32 in Figure 6 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

[0125] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. In other words, in a region of a predetermined size, the occupancy rate of the p region 32 projected onto the first surface P1 is greater than the occupancy rate of the body region 30 projected onto the first surface P1. The above occupancy rate is, for example, the occupancy rate of the transistor region 101 and the diode region 102 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0126] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times or less of the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1.

[0127] The above unit area is not particularly limited, as long as it is a size that allows for a comparison of the average occupancy rate of the body region 30 of the transistor region 101 and the average occupancy rate of the p region 32 of the diode region 102. For example, the above unit area could be 30 μm × 30 μm = 900 μm. 2 That is the case.

[0128] Furthermore, the contact area per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. In other words, the contact resistance per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0129] Figure 7 is a schematic top view of the semiconductor device of the first embodiment. Figure 8 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Figure 8 is a cross-sectional view LL' of Figure 7. Figure 7 shows the shape of the sense electrode pad 25 and the source electrode 12 around the sense electrode pad 25.

[0130] The sense electrode pad 25 is provided in the first transistor region 101a. The sense electrode pad 25 is provided in the vicinity of the first diode region 102a. The sense electrode pad 25 is provided, for example, adjacent to the first diode region 102a.

[0131] The sense electrode pad 25 is separated from the source electrode 12. The sense electrode pad 25 is separated from the first region 12a of the source electrode 12. In addition, the sense electrode pad 25 is separated from the second region 12b of the source electrode 12.

[0132] The distance between the sense electrode pad 25 and the first diode region 102a (dx in Figure 7) is, for example, 100 μm or less.

[0133] The distance between the sense electrode pad 25 and the source electrode 12 is, for example, 100 μm or less. The distance between the sense electrode pad 25 and the first region 12a of the source electrode 12 (dy in Figure 7) is, for example, 100 μm or less. Also, the distance between the sense electrode pad 25 and the second region 12b of the source electrode 12 (dz in Figure 7) is, for example, 100 μm or less.

[0134] The distance between the sense electrode pad 25 and the source electrode 12 is smaller than, for example, the distance between the gate wiring 24 and the source electrode 12. The minimum distance between the sense electrode pad 25 and the source electrode 12 is smaller than, for example, the minimum distance between the sense electrode pad 25 and the gate wiring 24.

[0135] The sense electrode pad 25 is in contact with the first portion 28a of the drift region 28, the second portion 28b of the drift region 28, the body region 30, the p region 32, and the source region 34.

[0136] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0137] Figures 9(a) and 9(b) are schematic top views of the semiconductor device of the first comparative example. Figure 9(a) is a diagram showing the arrangement of each region of the MOSFET 901 of the first comparative example. Figure 9(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET of the first comparative example. Figures 9(a) and 9(b) correspond to Figures 2(a) and 2(b) of the first embodiment.

[0138] Figure 10 is a schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 10 is a cross-sectional view of GG' in Figure 9(a). Figure 10 corresponds to Figure 5(a) of the first embodiment.

[0139] The MOSFET of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not have a diode region 102.

[0140] In the transistor region 101 of the MOSFET 100 of the first comparative example, a MOSFET and an SBD are provided, similar to the MOSFET 100 of the first embodiment.

[0141] Figure 11 is an equivalent circuit diagram of the semiconductor device of the first comparative example. Between the source electrode 12 and the drain electrode 14, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes.

[0142] For example, consider a case where a MOSFET is used as a switching element connected to an inductive load. When the MOSFET 901 is off, a load current caused by the inductive load may apply a voltage that makes the source electrode 12 positive relative to the drain electrode 14. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0143] The forward voltage (Vf) at which forward current begins to flow through an SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, forward current flows through the SBD first.

[0144] The forward voltage (Vf) of an SBD is, for example, 1.0V. The forward voltage (Vf) of a pn junction diode is, for example, 2.5V.

[0145] The SBD operates unipolar. Therefore, even when a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy.

[0146] Figures 12(a) and 12(b) are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 12(a) and 12(b) are schematic cross-sectional views of the semiconductor device of the first comparative example. Figures 12(a) and 12(b) correspond to Figure 10.

[0147] Figures 12(a) and 12(b) show the currents flowing through the built-in diode of the MOSFET901 of the first comparative example. Figure 12(a) shows the state where forward current flows only through the SBD, and Figure 12(b) shows the state where forward current flows through both the SBD and the pn junction diode.

[0148] Specifically, Figure 12(a) shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 12(b) shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0149] In Figures 12(a) and 12(b), the dotted arrows indicate the current flowing through the SBD. In Figure 12(b), the solid arrows indicate the current flowing through the pn junction diode.

[0150] As shown in Figure 12(a), the current flowing through the SBD wraps around to the bottom of the body region 30. As a result, electrostatic potential wraps around to the drift region 28 opposite the bottom of the body region 30. This electrostatic potential wraps around to the drift region 28, which is the opposite of the bottom of the body region 30, and reduces the voltage applied between the body region 30 and the drift region 28.

[0151] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the body region 30. In other words, the forward voltage (Vf) of the pn junction diode of MOSFET 901 in the first comparative example can be made higher compared to the case where an SBD is not provided. As a result, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0152] The forward voltage (Vf) of the pn junction diode in the first comparative example MOSFET901 depends on the distance between two adjacent SBDs in the first direction. By reducing the distance between two adjacent SBDs in the first direction, the forward voltage (Vf) of the pn junction diode in the first comparative example MOSFET901 can be increased.

[0153] In some cases, a large surge current exceeding the steady state may be applied to the MOSFET instantaneously. The surge current flows from the source electrode 12 towards the drain electrode 14.

[0154] When a large surge current flows, a large surge voltage is applied, causing the MOSFET to overheat and eventually break down. The maximum allowable peak current value (I) of the surge current that can be tolerated by the MOSFET. FSM This is referred to as surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability.

[0155] When a large surge voltage is applied to MOSFET901 in the first comparative example, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

[0156] When the voltage applied across the pn junction of a pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 12(b).

[0157] Figure 13 is a schematic cross-sectional view of the semiconductor device of the second comparative example. Figure 13 corresponds to Figure 10 of the first comparative example.

[0158] The MOSFET902 in the second comparative example differs from the MOSFET901 in the first comparative example in that its transistor region does not contain an SBD. The built-in diode in the MOSFET902 in the second comparative example is only a pn junction diode.

[0159] Figure 14 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 14 is a diagram showing the voltage-current characteristics of the built-in diodes of MOSFET901 of the first comparative example and MOSFET902 of the second comparative example.

[0160] As shown in Figure 14, in the second comparative example, MOSFET 902, current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf2 of the pn junction diode is applied. On the other hand, in the first comparative example, MOSFET 901, current flows through the SBD until the forward voltage Vf1 of the pn junction diode is applied. In the first comparative example, MOSFET 901, current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf1 of the pn junction diode is applied.

[0161] Since MOSFET 901 of the first comparative example operates unipolar up to the forward voltage Vf1, the slope of the current increase is smaller compared to MOSFET 902 of the second comparative example. Therefore, the maximum allowable peak current value I of MOSFET 902 of the second comparative example is FSM Compared to 2, the maximum allowable peak current value I of the MOSFET901 in the first comparative example FSM 1 becomes smaller. In other words, the surge current withstand capability of MOSFET901 in the first comparative example becomes smaller than the surge current withstand capability of MOSFET902 in the second comparative example.

[0162] Figures 15(a) and 15(b) are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 15(a) and 15(b) are schematic cross-sectional views of the MOSFET 100 of the first embodiment. Figures 15(a) and 15(b) correspond to Figure 5(a).

[0163] Figures 15(a) and 15(b) show the currents flowing through the built-in diodes of the MOSFET 100 in the first embodiment. Figure 15(a) shows the state where forward current flows only through the SBD, and Figure 15(b) shows the state where forward current flows through both the SBD and the pn junction diode.

[0164] Specifically, Figure 15(a) shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 15(b) shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0165] In Figures 15(a) and 15(b), the dotted arrows indicate the current flowing through the SBD. In Figure 15(b), the solid arrows indicate the current flowing through the pn junction diode.

[0166] In the diode region 102, the second distance d2 between two adjacent second portions 28b separated by the p region 32 is substantially equal to the first distance d1 between two adjacent first portions 28a separated by the body region 30 in the transistor region 101. In other words, the diode region 102 has second portions 28b spaced at the same intervals as the first portions 28a in the transistor region 101. To put it another way, the diode region 102 has SBD regions spaced at the same intervals as the transistor region 101.

[0167] Therefore, as shown in Figure 15(a), in the diode region 102, the current flowing through the SBD flows around to the bottom of the p region 32. As a result, it becomes less likely for the forward voltage (Vf) of the pn junction diode to be exceeded at the bottom of the p region 32. The forward voltage (Vf) of the pn junction diode in the diode region 102 is increased by the presence of the SBD region.

[0168] When the voltage applied across the pn junction of a pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 15(b).

[0169] In the MOSFET 100 of the first embodiment, the occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0170] Furthermore, the contact area per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. In other words, the contact resistance per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0171] Therefore, the current flowing through the pn junction diode in diode region 102 is greater than the current flowing through the pn junction diode in transistor region 101.

[0172] Furthermore, the large current flowing through the pn junction diode in diode region 102 causes carrier propagation and heat propagation to the adjacent transistor region 101. Consequently, conductivity modulation in the transistor region 101 adjacent to diode region 102 is promoted. Therefore, the current flowing through the pn junction diode in the transistor region 101 adjacent to diode region 102 becomes larger.

[0173] Figure 16 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 15 is a diagram showing the voltage-current characteristics of the built-in diodes of MOSFET 901 of the first comparative example, MOSFET 902 of the second comparative example, and MOSFET 100 of the first embodiment.

[0174] As shown in Figure 16, in the first embodiment, current flows through the SBD until the forward voltage Vf3 of the pn junction diode is applied to the MOSFET 100. In the first embodiment, when a voltage equal to or greater than the forward voltage Vf3 of the pn junction diode is applied to the MOSFET 100, current flows through the pn junction diode.

[0175] In the first embodiment, an SBD region is provided in the diode region 102 of the MOSFET 100 at the same interval as the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode of the MOSFET 100 in the first embodiment is equivalent to the forward voltage Vf1 of the pn junction diode of the MOSFET in the first comparative example.

[0176] On the other hand, in the MOSFET 100 of the first embodiment, the current after the forward voltage Vf3 of the pn junction diode is exceeded is greater than the current after the forward voltage Vf1 of the pn junction diode is exceeded in the MOSFET 901 of the first comparative example. This is because the current flowing through the pn junction diode in the diode region 102 and the pn junction diode in the transistor region 101 adjacent to the diode region 102 is greater than in the MOSFET 901 of the first comparative example.

[0177] The current increases after the forward voltage Vf3 of the pn junction diode, which reduces the maximum allowable peak current value I of the MOSFET 100 in the first embodiment. FSM 3 is the maximum allowable peak current value I of the MOSFET903 in the third comparative example. FSM It becomes larger compared to 1. In other words, the surge current withstand capability of MOSFET 100 in the first embodiment is greater than that of MOSFET 901 in the first comparative example.

[0178] As described above, the surge current withstand capability of the MOSFET 100 of the first embodiment is improved by including a diode region 102 provided between transistor regions 101.

[0179] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is preferably 1.2 times or more and 3 times or less of the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. Exceeding the lower limit further improves the surge current withstand capability. Also, below the upper limit suppresses the decrease in the forward voltage Vf3 and suppresses the decrease in reliability.

[0180] The inventors' failure analysis revealed that one of the causes of chip failure due to surge current is a short circuit between the source electrode 12 and the gate wiring 24. This short circuit occurs when the source electrode 12 adjacent to the gate wiring 24 melts and flows laterally, coming into contact with the gate wiring 24.

[0181] It was found that short circuits between the source electrode 12 and the gate wiring 24 are particularly likely to occur between the gate wiring 24 of the source electrode 12 in the diode region 102. In other words, it was found that short circuits between the source electrode 12 and the gate wiring 24 are particularly likely to occur between the second region 12b and the gate wiring 24 of the source electrode 12.

[0182] The reason why a short circuit is likely to occur between the second region 12b and the gate wiring 24 is thought to be that the surge current flowing through the diode region 102 is larger than that flowing through the transistor region 101, resulting in greater heat generation. In other words, it is thought that the increased heat generation makes the source electrode 12 more likely to melt.

[0183] Therefore, for example, a MOSFET in which melting of the second region 12b has already occurred due to its use can be understood as a MOSFET with low surge current withstand capability. Since MOSFETs with low surge current withstand capability have reduced reliability, it is desirable to replace them before failure occurs.

[0184] Figures 17 and 18 are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figure 17 corresponds to Figure 7. Figure 18 corresponds to Figure 8.

[0185] The MOSFET 100 of the discrete device 1000 in the first embodiment includes a sense electrode pad 25 for detecting a short circuit between the source electrode 12 and the sense electrode pad 25. The sense electrode pad 25 is provided in close proximity to the diode region 102 in which the source electrode 12 is prone to melting.

[0186] For example, in discrete device 1000, a source voltage is applied to a fourth metal lead 130d connected to a sense electrode pad 25. The current flowing through the fourth metal lead 130d is then monitored by an ammeter external to discrete device 1000.

[0187] Consider the case where the second region 12b of the first diode region 102a melts and shorts with the sense electrode pad 25, as shown by the dotted circles in Figures 17 and 18. In this case, current flows from the sense electrode pad 25 to the second region 12b, increasing the current flowing through the fourth metal lead 130d.

[0188] Therefore, a short circuit between the second region 12b of the source electrode 12 and the sense electrode pad 25 can be detected. In other words, a decrease in the reliability of the MOSFET 100, i.e., a decrease in the reliability of the discrete device 1000, can be detected.

[0189] If a decrease in the reliability of discrete device 1000 is detected, an early failure of discrete device 1000 can be predicted. Therefore, for example, discrete device 1000 may be replaced with a new discrete device.

[0190] As described above, it is possible to predict a decrease in the reliability of the discrete device 1000.

[0191] From the viewpoint of early detection of melting of the source electrode 12, the distance between the sense electrode pad 25 and the first diode region 102a (dx in Figure 7) is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 10 μm or less.

[0192] From the viewpoint of early detection of melting of the source electrode 12, the distance between the sense electrode pad 25 and the source electrode 12 is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 10 μm or less.

[0193] From the viewpoint of early detection of melting of the source electrode 12, the distance between the sense electrode pad 25 and the second region 12b of the source electrode 12 (dz in Figure 7) is preferably 100 μm or less, more preferably 50 μm or less, and even more preferably 10 μm or less.

[0194] From the viewpoint of early detection of melting of the source electrode 12, it is preferable that the distance between the sense electrode pad 25 and the source electrode 12 is smaller than the distance between the gate wiring 24 and the source electrode 12. By making the distance between the sense electrode pad 25 and the source electrode 12 shorter than the distance between the gate wiring 24 and the source electrode 12, melting of the source electrode 12 can be detected before the gate wiring 24 and the source electrode 12 short-circuit.

[0195] Furthermore, the MOSFET 100 of the discrete device 1000 in the first embodiment is equipped with a sense electrode pad 25, which allows the ON current of the MOSFET 100 to be detected (sensed).

[0196] From the viewpoint of reducing the amount of on-current flowing through the sense electrode pad 25 and facilitating detection of the on-current amount by an ammeter, the area of ​​the sense electrode pad 25 is preferably 10% or less of the area of ​​the source electrode 12, and more preferably 5% or less.

[0197] (modified version) The semiconductor device of the modified embodiment of the first embodiment differs from the semiconductor device of the first embodiment in that the third electrode does not come into contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region.

[0198] Figure 19 is a schematic cross-sectional view of a modified example of the first embodiment. Figure 19 corresponds to Figure 7 of the first embodiment.

[0199] In the discrete device of the modified embodiment of the first embodiment, the MOSFET 101 includes the sense electrode pad 25, which does not come into contact with the first portion 28a of the drift region 28, the second portion 28b of the drift region 28, the body region 30, the p region 32, and the source region 34.

[0200] In the modified semiconductor device of the first embodiment, no on-current flows to the sense electrode pad 25. Therefore, current flows to the sense electrode pad 25 only when the second region 12b of the first diode region 102a melts and shorts with the sense electrode pad 25. Consequently, the detection accuracy of the melting of the source electrode 12 is improved.

[0201] As described above, the first embodiment and its modifications enable the realization of a discrete device with improved surge current withstand capability. Furthermore, the first embodiment enables the realization of a discrete device in which a decrease in reliability can be foreseen.

[0202] (Second embodiment) The semiconductor device of the second embodiment includes a plurality of transistor regions and at least one diode region, wherein the plurality of transistor regions include a silicon carbide layer having a first surface and a second surface facing the first surface and a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, and a n-type third silicon carbide region provided between the second silicon carbide region and the first surface, a first electrode in contact with the plurality of first portions, the second silicon carbide region and the third silicon carbide region, a second electrode in contact with the second surface, a gate electrode facing the second silicon carbide region, and a gate insulating layer provided between the gate electrode and the second silicon carbide region, and at least one diode region has a plurality of second portions in contact with the first surface. A silicon carbide layer includes an n-type first silicon carbide region and a p-type fourth silicon carbide region provided between the first silicon carbide region and a first surface; a plurality of second portions and a first electrode in contact with the fourth silicon carbide region and a second electrode, wherein the area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface; and a first diode region, which is one of at least one diode region, is provided between a first transistor region, which is one of a plurality of transistor regions, and a second transistor region, which is one of a plurality of transistor regions provided in a first direction relative to the first transistor region; and the first transistor region has a third electrode provided on the side of the first surface of the silicon carbide layer and separated from the first electrode.

[0203] The semiconductor device of the second embodiment has the same configuration as the MOSFET 100 of the first embodiment. The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that it is a semiconductor chip, whereas the semiconductor device of the first embodiment is a discrete device. Hereafter, descriptions that overlap with the first embodiment may be omitted.

[0204] Figures 20(a) and 20(b) are schematic top views of the semiconductor device according to the second embodiment. Figure 20(a) is a diagram showing the arrangement of each region of the MOSFET 200 according to the second embodiment. Figure 20(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 200.

[0205] The MOSFET200 of the second embodiment has the same configuration as the MOSFET100 of the first embodiment. The MOSFET200 is a semiconductor chip. The MOSFET200 is an example of a semiconductor device.

[0206] According to the MOSFET 200 of the second embodiment, surge current withstand capability is improved, similar to the MOSFET 100 of the first embodiment. Furthermore, by incorporating it into a discrete device, for example, as in the MOSFET 100 of the first embodiment, it becomes possible to predict a decrease in reliability.

[0207] As described above, the second embodiment realizes a MOSFET with improved surge current withstand capability. Furthermore, the second embodiment realizes a MOSFET in which a decrease in reliability can be predicted.

[0208] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that it comprises eight transistor regions and ten diode regions. Hereafter, descriptions that overlap with the content of the first or second embodiment may be omitted.

[0209] Figures 21(a) and 21(b) are schematic top views of the semiconductor device according to the third embodiment. Figure 21(a) is a diagram showing the arrangement of each region of the MOSFET 300 according to the third embodiment. Figure 21(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 300.

[0210] The MOSFET300 comprises a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a transistor region 101e, a transistor region 101f, a transistor region 101g, a transistor region 101h, a diode region 102a (first diode region), a diode region 102b, a diode region 102c, a diode region 102d, a diode region 102e, a diode region 102f, a diode region 102g, a diode region 102h, a diode region 102i, a diode region 102j, and a peripheral region 103. Transistor region 101a is an example of the first transistor region. Transistor region 101b is an example of the second transistor region. Diode region 102a is an example of the first diode region.

[0211] According to the MOSFET 300 of the third embodiment, surge current withstand capability is improved, similar to the MOSFET 100 of the first embodiment. Furthermore, by incorporating it into a discrete device, for example, as in the MOSFET 100 of the first embodiment, it becomes possible to foresee a decrease in reliability.

[0212] As described above, the third embodiment realizes a MOSFET with improved surge current withstand capability. Furthermore, the third embodiment realizes a MOSFET in which a decrease in reliability can be predicted.

[0213] (Fourth embodiment) The inverter circuit and drive device of the fourth embodiment is an inverter circuit and drive device comprising the semiconductor device of the first embodiment.

[0214] Figure 22 is a schematic diagram of the drive unit of the fourth embodiment. The drive unit 500 comprises a motor 140 and an inverter circuit 150.

[0215] The inverter circuit 150 consists of three semiconductor modules 150a, 150b, and 150c, each using a MOSFET 100 from the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0216] According to the fourth embodiment, the characteristics of the inverter circuit 150 and the drive unit 500 are improved by providing a MOSFET 100 with improved characteristics.

[0217] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0218] Figure 23 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 600 of the fifth embodiment is a railway vehicle. The vehicle 900 is equipped with a motor 140 and an inverter circuit 150.

[0219] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 600.

[0220] According to the fifth embodiment, the characteristics of the vehicle 600 are improved by providing a MOSFET 100 with improved characteristics.

[0221] (Sixth embodiment) The vehicle of the sixth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0222] Figure 24 is a schematic diagram of a vehicle according to the sixth embodiment. The vehicle 700 of the sixth embodiment is an automobile. The vehicle 700 includes a motor 140 and an inverter circuit 150.

[0223] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0224] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 700.

[0225] According to the sixth embodiment, the characteristics of the vehicle 700 are improved by providing a MOSFET 100 with improved characteristics.

[0226] (Seventh Embodiment) The elevator of the seventh embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0227] Figure 25 is a schematic diagram of the elevator according to the seventh embodiment. The elevator 800 of the seventh embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoisting machine 616, a motor 140, and an inverter circuit 150.

[0228] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0229] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the hoisting machine 616, causing the cage 610 to rise and fall.

[0230] According to the seventh embodiment, the characteristics of the elevator 800 are improved by providing a MOSFET 100 with improved characteristics.

[0231] In the first to third embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0232] In the first to third embodiments, the case in which the gate electrode 18 has a so-called stripe shape was described as an example, but the shape of the gate electrode 18 is not limited to a stripe shape. For example, the shape of the gate electrode 18 may be a grid shape.

[0233] In the first to third embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, while nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, arsenic (As), antimony (Sb), etc., can also be applied.

[0234] In the first to third embodiments, the case where the conductor is a bonding wire was described as an example, but the conductor may also be, for example, a clip used in clip bonding.

[0235] In the first embodiment, the semiconductor device was described as a discrete device, but the semiconductor device may also be a module device on which multiple semiconductor chips are mounted.

[0236] The number of transistor regions 101 and diode regions 102, and the arrangement of transistor regions 101 and diode regions 102, are not limited to the forms of the first to third embodiments.

[0237] Furthermore, although the fourth to seventh embodiments were described using a configuration comprising the MOSFET 100 of the first embodiment as an example, it is also possible to use a configuration comprising the MOSFET of the second or third embodiment.

[0238] Furthermore, while the fourth to seventh embodiments described the application of the semiconductor device of the present invention to vehicles and elevators as examples, it is also possible to apply the semiconductor device of the present invention to, for example, a power conditioner for a solar power generation system.

[0239] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0240] 10. Silicon carbide layer 12 Source electrode (first electrode) 14. Drain electrode (second electrode) 16 Gate insulating layer 18 Guard gate 25. Sense electrode pad (third electrode) 28. Drift region (first silicon carbide region) 28a Part 1 28b Second part 30 Body region (second silicon carbide region) 32 p region (fourth silicon carbide region) 34. Source region (third silicon carbide region) 100 MOSFETs (semiconductor chips) 101 Transistor Region 101a Transistor region (first transistor region) 101b Transistor region (second transisttor region) 102 Diode region 102a Diode region (first diode region) 110a First bonding wire (first conductor) 110d Fourth bonding wire (second conductor) 120 Metal bed (first metal layer) 130a First metal lead (second metal layer) 130d Fourth metal lead (third metal layer) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 600 Driving device 700 Vehicle 800 Vehicle 900 Elevator 1000 Discrete device (semiconductor device) P1 First surface P2 Second surface d1 First distance d2 Second distance

Claims

1. A semiconductor chip comprising multiple transistor regions and at least one diode region, The plurality of transistor regions are A silicon carbide layer comprising: an n-type first silicon carbide region having a first surface and a second surface facing the first surface, and having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode region, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in a first direction relative to the first transistor region. The first transistor region is a semiconductor chip having a third electrode provided on the side of the first surface of the silicon carbide layer and separated from the first electrode. A first conductor having one end in contact with the first electrode and applying a voltage to the first electrode, A second conductor, one end of which is in contact with the third electrode, and which applies a voltage to the third electrode, Equipped with, A semiconductor device in which the first electrode in the first diode region, the first electrode in the first transistor region, and the first electrode in the second transistor region are physically continuous.

2. A first metal layer facing the second electrode and electrically connected to the second electrode, The second metal layer to which the other end of the first conductor is in contact, The other end of the second conductor is in contact with the third metal layer, The semiconductor device according to claim 1, further comprising

3. The semiconductor device according to claim 1, wherein the third electrode is in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region.

4. The semiconductor device according to claim 1, wherein the distance between the third electrode and the at least one diode region is 100 μm or less.

5. The semiconductor device according to claim 1, wherein the distance between the third electrode and the first electrode is 100 μm or less.

6. The semiconductor device according to claim 1, wherein the area of ​​the third electrode is 10% or less of the area of ​​the first electrode.

7. The semiconductor device according to claim 1, wherein the first conductor and the second conductor are bonding wires.

8. A semiconductor chip comprising a plurality of transistor regions and at least one diode region, The plurality of transistor regions are A silicon carbide layer comprising: an n-type first silicon carbide region having a first surface and a second surface facing the first surface, and having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode region, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in a first direction relative to the first transistor region. The first transistor region is a semiconductor chip having a third electrode provided on the side of the first surface of the silicon carbide layer and separated from the first electrode. A first conductor having one end in contact with the first electrode and applying a voltage to the first electrode, A second conductor, one end of which is in contact with the third electrode, and which applies a voltage to the third electrode, Equipped with, A semiconductor device wherein the contact area per unit area between the first electrode and the fourth silicon carbide region is greater than the contact area per unit area between the first electrode and the second silicon carbide region.

9. The semiconductor device according to claim 1, wherein the second distance between two adjacent second portions separated by the fourth silicon carbide region is equal to the first distance between two adjacent first portions separated by the second silicon carbide region.

10. It comprises multiple transistor regions and at least one diode region, The plurality of transistor regions are A silicon carbide layer comprising: an n-type first silicon carbide region having a first surface and a second surface facing the first surface, and having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode region, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in a first direction relative to the first transistor region. The first transistor region has a third electrode provided on the side of the first surface of the silicon carbide layer and separated from the first electrode. A semiconductor device in which the first electrode in the first diode region, the first electrode in the first transistor region, and the first electrode in the second transistor region are physically continuous.

11. The semiconductor device according to claim 10, wherein the third electrode is in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region.

12. The semiconductor device according to claim 10, wherein the distance between the third electrode and the at least one diode region is 100 μm or less.

13. The semiconductor device according to claim 10, wherein the distance between the third electrode and the first electrode is 100 μm or less.

14. The semiconductor device according to claim 10, wherein the area of ​​the third electrode is 10% or less of the area of ​​the first electrode.

15. comprising a plurality of transistor regions and at least one diode region, The plurality of transistor regions are A silicon carbide layer comprising: an n-type first silicon carbide region having a first surface and a second surface facing the first surface, and having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode region, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in a first direction relative to the first transistor region. The first transistor region has a third electrode provided on the side of the first surface of the silicon carbide layer and separated from the first electrode. A semiconductor device wherein the contact area per unit area between the first electrode and the fourth silicon carbide region is greater than the contact area per unit area between the first electrode and the second silicon carbide region.

16. The semiconductor device according to claim 10, wherein the second distance between two adjacent second portions separated by the fourth silicon carbide region is equal to the first distance between two adjacent first portions separated by the second silicon carbide region.

17. An inverter circuit comprising a semiconductor device according to any one of claims 1 to 16.

18. A drive device comprising a semiconductor device according to any one of claims 1 to 16.

19. A vehicle comprising a semiconductor device according to any one of claims 1 to 16.

20. An elevator comprising a semiconductor device according to any one of claims 1 to 16.

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