Trap compensation in field-effect transistors

Abstract

The circuit includes a field effect transistor, a FET, a reference transistor having an output coupled to the output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal to the reference transistor in response to a change in a drain current of the reference transistor due to carrier trapping, and to apply the input signal to an input of the reference transistor, and a summing node coupled to the input of the FET and the input of the reference transistor, the summing node summing the input signal with the input signal of the FET to compensate for carrier trapping effects.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 17 / 395,035, filed on August 5, 2021, with the title "COMPENSATION OF TRAPPING IN FIELD EFFECT TRANSISTORS", the disclosure of which is hereby incorporated by reference in its entirety.

[0002] This disclosure relates to transistor structures, and more particularly, to high electron mobility transistors.

Background Art

[0003] Narrow bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used in semiconductor devices for low-power applications and, in the case of Si, for low-frequency applications. However, these semiconductor materials may not be very suitable for high-power and / or high-frequency applications because, for example, they have a relatively narrow bandgap (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and a relatively small breakdown voltage.

[0004] Interest in applications and devices for high power, high temperature, and / or high frequency has focused on wide bandgap semiconductor materials such as silicon carbide (3.2 eV at room temperature for 4H-SiC) and group III nitrides (e.g., 3.36 eV at room temperature for GaN). These materials can have a higher breakdown field strength and a higher electron saturation velocity than GaAs and Si.

[0005] A particularly interesting device for high-power and / or high-frequency applications is the high-electron-mobility transistor (HEMT), also known as the modulation-doped field-effect transistor (MODFET). In HEMT devices, a two-dimensional electron gas (2DEG) can be formed at the heterojunction of two semiconductor materials with different bandgap energies, where the material with the narrower bandgap has a higher electron affinity than the material with the wider bandgap. The 2DEG is an undoped accumulation layer within the material with the narrower bandgap, for example, 10 13 Career / cm 2 It can contain relatively high sheet electron concentrations exceeding [a certain value]. Furthermore, electrons generated in semiconductors with wider band gaps can move to 2DEG, and relatively high electron mobility is possible due to the reduced scattering of ionized impurities. This combination of relatively high carrier concentration and carrier mobility allows HEMTs to obtain relatively large transconductance, and in high-frequency applications, they may exhibit superior performance compared to metal-semiconductor field-effect transistors (MESFETs).

[0006] HEMTs fabricated from gallium nitride / aluminum gallium nitride (GaN / AlGaN) material systems can generate high RF output due to a combination of material properties, including a relatively large breakdown field, a relatively wide band gap, a relatively large conduction band offset, and / or a relatively large saturation electron drift rate. The majority of electrons within the 2DEG may be due to polarization within the AlGaN.

[0007] Figure 1A shows a conventional gallium nitride-based HEMT structure. This structure comprises a substrate 10, which may be a semi-insulating 4H silicon carbide (SiC) substrate. Optional buffer layers, nucleation layers, and / or transition layers (not shown) can be provided on the substrate 10. A channel layer 20 is provided on the substrate 10. The channel layer 20 may be a group III nitride such as GaN. A barrier layer 22 is provided on the channel layer 20. The barrier layer 22 has a band gap larger than that of the channel layer 20, and the channel layer 20 may have a greater electron affinity than the barrier layer 22. The barrier layer 22 may be AlN, AlInN, AlGaN, or AlInGaN, and has sufficient thickness, as well as sufficiently high Al content and doping, to induce a considerable carrier concentration at the interface between the channel layer 20 and the barrier layer 22. This induced carrier concentration forms a two-dimensional electron gas (2DEG) that provides a conductive channel within the device. The conductivity of the 2DEG channel can be adjusted by applying a voltage to the gate contact 32 formed on the barrier layer 22.

[0008] Figure 1A further shows a capping layer 24 on the barrier layer 22, with the gate contact 32 located within a recess 36 that penetrates the capping layer 24. The capping layer 24 physically separates the top (outer) surface of the device from the channel, thereby reducing the skin effect of the device. The capping layer 24 can be blanket-formed on the barrier layer 22, formed by epitaxial growth, and / or deposition. The capping layer 24 can typically have a thickness of about 2 nm to about 500 nm.

[0009] As further shown in Figure 1A, an ohmic source / drain contact 30 is provided on the barrier layer 22, and a gate recess is provided through the cap layer 24, exposing a portion of the barrier layer 22. A gate contact 32 is formed within the recess and contacts the exposed portion of the barrier layer 22. The gate contact 32 may be a "T" shaped gate as shown in Figure 1A.

[0010] Charges trapped within semiconductor devices such as GaN HEMT devices can cause nonlinear distortions in the output signals generated by transistor amplifiers using these devices. While we do not wish to be limited to any particular theory, it is currently believed that charges can be injected from the device's gate contacts into the barrier and / or channel layers of the HEMT device, and that such charges can be trapped in the barrier and / or channel layers. These trapped charges can cause long-term memory effects in the device, potentially resulting in highly nonlinear behavior.

[0011] Several attempts have been made to address the carrier trap behavior in GaN-based HEMT devices. For example, Figure 1B shows an open-loop analog feedforward circuit to compensate for long-term memory effects caused by self-bias induced by electronic traps in a GaN HEMT-based power amplifier. The circuit includes an envelope detector that detects the envelope of an RF input signal. The envelope is rectified, and the rectified envelope is fed into an RC network that acts as an electronic trap model, and a gate bias voltage V is applied to the HEMT of the amplifier. GG It generates a compensation signal that is added to the original signal.

[0012] While the concept of trap compensation using gate modulation has been proven in principle, existing methods have several limitations. For example, existing methods use open-loop techniques that cannot detect the dynamic behavior of traps. Existing methods also assume that the trap behavior of a device depends only on the waveform applied to the device, and that the relationship between trap behavior and the input waveform is constant, but this assumption is not always true in actual applications. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] U.S. Patent No. 6,849,882 [Patent Document 2] U.S. Patent No. 7,230,284 [Patent Document 3] U.S. Patent No. 7,501,669 [Patent Document 4] U.S. Patent No. 7,126,426 [Patent Document 5] U.S. Patent No. 7,550,783 [Patent Document 6] U.S. Patent No. 7,573,078 [Patent Document 7] U.S. Patent Application Publication No. 2005 / 0253167 [Patent Document 8] U.S. Patent Application Publication No. 2006 / 0202272 Specification [Patent Document 9] U.S. Patent Application Publication No. 2008 / 0128752 [Patent Document 10] U.S. Patent Application Publication No. 2010 / 0276698 [Patent Document 11] U.S. Patent Application Publication No. 2012 / 0049973 [Patent Document 12] U.S. Patent Application Publication No. 2012 / 0194276 [Patent Document 13] U.S. Patent No. 9,847,411 [Overview of the Initiative] [Means for solving the problem]

[0014] The circuit according to some embodiments includes a field effect transistor (FET), a reference transistor having an output coupled to the output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal to the reference transistor according to the drain current of the reference transistor and apply the input signal to the input of the reference transistor, and an addition node coupled to the input of the FET and the input of the reference transistor, the addition node adding the input signal to the input signal of the FET.

[0015] The drain terminal of the FET can be RF-coupled to the drain terminal of the reference transistor via a coupling capacitor. The circuit can further include an RF shunt capacitor between the gate terminal of the reference transistor and ground. The gate terminal of the reference transistor can be DC-coupled to the gate terminal of the FET.

[0016] In some embodiments, the circuit can further include a buffer between the gate terminal of the reference transistor and the gate terminal of the FET. The buffer can include an operational amplifier circuit in a voltage follower configuration.

[0017] The circuit can further include a low-pass filter between the gate of the reference transistor and the gate of the FET.

[0018] In some embodiments, the circuit can further include a drain current monitoring circuit configured to detect the level of the drain current flowing into the reference transistor, the drain current monitoring circuit being coupled to the active bias circuit.

[0019] The circuit can further include a low-pass filter between the reference transistor and the drain current monitoring circuit.

[0020] The reference transistor and FET may include a group III nitride-based high electron mobility transistor. In some embodiments, the reference circuit and FET may be formed on a single substrate and share a common epitaxial structure.

[0021] Reference transistors and FETs can be biased with a common drain bias voltage.

[0022] In some embodiments, the active bias circuit may be configured to control the gate voltage of a reference transistor in order to maintain a constant drain current flowing through the reference transistor. The active bias circuit may be configured to generate an input signal to the reference transistor in order to generate an input signal to the reference transistor in response to a change in the drain current of the reference transistor caused by carrier trapping in the reference transistor.

[0023] Transistor amplifiers according to several embodiments include a power field-effect transistor (FET) having a source terminal, a drain terminal, and a gate terminal; a reference transistor having a source terminal, a drain terminal, and a gate terminal; an RF coupling capacitor connected between the drain terminal of the reference transistor and the drain terminal of the power FET; a drain current detection circuit coupled to the drain terminal of the reference transistor and configured to detect changes in the drain current of the reference transistor; and an active bias circuit coupled to the drain current detection circuit and configured to generate an input signal to the reference transistor in response to changes in the drain current of the reference transistor. The input signal is applied to the gate of the reference transistor, and the input signal is added to the RF input signal of the power FET.

[0024] The reference transistor and power FET can be biased with a reduced conduction angle bias, such as Class A operation or Class AB operation.

[0025] The transistor amplifier may further include an RF shunt capacitor between the gate terminal of the reference transistor and ground. The gate terminal of the reference transistor may be DC-coupled to the gate terminal of the power FET.

[0026] In some embodiments, the transistor amplifier may further include a buffer between the gate terminal of a reference transistor and the gate terminal of a power FET. The buffer may include an operational amplifier circuit in a voltage follower configuration.

[0027] A transistor amplifier may further include a low-pass filter located between the gate of the reference transistor and the gate of the power FET.

[0028] Methods according to several embodiments for compensating for the trap effect in a field-effect transistor (FET) include the steps of: detecting a change in the drain current of a reference transistor coupled to the FET; generating an input signal to the reference transistor in response to the change in the drain current of the reference transistor; applying the input signal to the input of the reference transistor; and adding the input signal as a compensation signal to the RF input signal of the FET. [Brief explanation of the drawing]

[0029] [Figure 1A] This is a cross-sectional view of a conventional transistor device. [Figure 1B] This is a diagram of a conventional open-loop circuit for compensating for the carrier trap effect in a transistor device. [Figure 2] These are schematic diagrams of closed-loop circuits that compensate for carrier trapping effects in transistor devices, based on several embodiments. [Figure 3] These are schematic diagrams of closed-loop circuits that compensate for carrier trapping effects in transistor devices, based on several embodiments. [Figure 4]These are schematic diagrams of closed-loop circuits that compensate for carrier trapping effects in transistor devices, based on several embodiments. [Figure 5A] This graph shows the simulation results for the gate voltage and drain current of a transistor device with and without trap compensation. [Figure 5B] This is a graph showing the RF envelope of a transistor device with and without trap compensation, based on simulation results. [Figure 6] This flowchart illustrates the operation of compensating for trap effects in transistor devices, based on several embodiments. [Figure 7] This is a schematic diagram showing the layout of a monolithic integrated circuit comprising a power transistor device and a circuit for compensating for the trapping effect in the power transistor device, according to several embodiments. [Figure 8] This is an IV plot of the transistors in an active-bias circuit, showing circuits from several embodiments. [Figure 9A] This is a schematic block diagram of a multi-amplifier circuit in which an RF transistor amplifier incorporating the transistor device described in the embodiment may be used. [Figure 9B] This is a schematic block diagram of a multi-amplifier circuit in which an RF transistor amplifier incorporating the transistor device described in the embodiment may be used. [Figure 9C] This is a schematic block diagram of a multi-amplifier circuit in which an RF transistor amplifier incorporating the transistor device described in the embodiment may be used. [Figure 10] This is a schematic diagram of an MMIC amplifier equipped with a HEMT transistor, based on several embodiments. [Figure 11A] This is a schematic cross-sectional view showing an exemplary package for an RF transistor amplifier die according to several embodiments. [Figure 11B] This is a schematic cross-sectional view showing an exemplary package for an RF transistor amplifier die according to several embodiments. [Modes for carrying out the invention]

[0030] Hereinafter, embodiments of the concept of the present invention will be described with reference to the accompanying drawings. Some embodiments described herein are self-aligned gates, and in some embodiments, provide transistor devices comprising a field plate positioned laterally from the gate such that the field plate does not overlap the gate perpendicularly. In some embodiments, the field plate is recessed toward the barrier layer in a recessed region. In yet another embodiment, the field plate can be connected to a source outside the active area of ​​the device using a connection that does not extend beyond the gate of the device.

[0031] While terms indicating order, such as first, second, and third, may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be called the second element, and similarly, the second element may be called the first element.

[0032] Furthermore, relational terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the drawings. Relational terms should be understood as being intended to encompass various orientations of the device, in addition to the orientation depicted in the drawings. For example, if a device in one of the drawings is turned upside down, a mechanism described as being on the “lower” side of an element will be oriented towards the “upper” side of that element. Thus, the exemplary term “lower” can describe both downward and upward orientations, depending on the specific orientation of the device. Similarly, if a device in one of the drawings is turned upside down, an element described as being “lower” or “below” another element will be oriented “above” that other element. Thus, the exemplary terms “lower” or “below” can describe both upward and downward orientations.

[0033] The terms used in describing the disclosures herein are for the sole purpose of describing specific embodiments and are not intended to limit the disclosure. The singular forms “an” and “the,” when used in the descriptions of the disclosure and in the appended claims, are also intended to include the plural forms unless the context clearly indicates otherwise. The terms “and / or,” when used herein, should be understood to refer to and encompass any possible combination of one or more related enumerated items. It will be further understood that, when used in this specification, the terms “equipped (third-person singular present)” and “equipped (present participle)” identify the presence of a described step, process, mechanism, element, and / or component, but do not exclude the presence or addition of any other step, process, mechanism, element, component, and / or group thereof.

[0034] This specification describes embodiments of the Disclosure with reference to schematic cross-sectional views of idealized embodiments of the Disclosure. Therefore, variations from the shapes shown in the figures should be expected, for example, as a result of manufacturing techniques and / or tolerances. The embodiments of the Disclosure should not be construed as being limited to specific shapes of the regions shown herein, and should include, for example, shapes resulting from manufacturing. The regions shown in the drawings are schematic in nature, and the shapes of the regions are not intended to represent the actual shapes of the regions of the device, nor are they intended to limit the scope of the Disclosure unless otherwise specified. Furthermore, for illustrative purposes, lines shown as straight, horizontal, or vertical in the drawings below will often be inclined, curved, non-horizontal, or non-vertical. Additionally, element thicknesses are intended to be schematic in nature.

[0035] All terms used in the disclosure of the embodiments of this disclosure, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art, unless otherwise defined, and are not necessarily limited to any specific definition known at the time of this disclosure. Such terms may, therefore, include equivalent terms created thereafter. It should be further understood that terms as defined in commonly used dictionaries should be interpreted as having the meaning consistent with the meaning of the term in the context of this specification and the related art.

[0036] Existing methods for addressing trap compensation in Group III nitride HEMT-based transistor amplifiers, as described above, employ open-loop techniques that cannot detect dynamic trap behavior. Several embodiments described herein provide closed-loop solutions that detect trap effects in a reference transistor and compensate for trap effects in the power transistor based on the detected trap effects.

[0037] Several embodiments provide analog closed-loop circuits that directly track the complex and irregular trap behavior that can be observed, particularly in Group III nitride HEMT transistors, and generate corresponding compensation signals applied to the transistor gate. In this method, the gate bias voltage is compensated based on changes in the trap behavior during operation, rather than simply tracking the input waveform.

[0038] Figures 2 and 3 are schematic diagrams of closed-loop circuits that compensate for carrier trapping effects in transistor devices according to several embodiments. Referring to Figures 2 and 3, a circuit 100 that compensates for trapping effects according to several embodiments is schematically shown. Circuit 100 includes a power field-effect transistor (FET) 110 that receives an RF input signal at an RF input node 112. The power FET 110 amplifies the RF input signal and the amplified output signal is passed over a load R L Output to [this location].

[0039] A reference FET 114 is provided for trap monitoring and compensation. The reference FET 114 is biased substantially similarly to the power FET 110, thereby ensuring that it has the same or similar trap characteristics as the power FET. In some embodiments, the reference FET 114 and the power FET 110 may be formed on a common substrate using the same epitaxial structure to ensure similar trap behavior in both devices. Circuit 100 may, in some embodiments, be fabricated as a monolithic microwave integrated circuit (MMIC), as will be discussed in more detail below. Both the reference FET 114 and the power FET 110 may include Group III nitride-based HEMT devices.

[0040] The output (drain) of the main power FET 110 is RF-coupled to the output (drain) of the reference FET 114 via the coupling capacitor 126, thereby ensuring that the reference FET 114 and the power FET 110 have the same or similar drain lags.

[0041] Circuit 100 monitors the variation in the drain current at the reference FET 114, and the variation in the drain current represents the carrier trapping effect in the FET. The signal representing the variation in the drain current is input to an active bias circuit 120, which generates a compensation signal applied to the gate of the power FET 110.

[0042] The active bias circuit 120 generates a compensation signal and applies it to the input (gate) of the reference FET 114 to maintain the drain current at a constant level and compensate for the trapping effect. The input (gate) of the reference FET 114 is DC coupled to the input (gate) of the power FET 110 via the summing node 117, so that the power FET 110 receives the same compensation signal, thereby compensating for the trapping effect inside the power FET 110.

[0043] Referring to Figure 3, the power FET 110 may comprise multiple unit cells connected in parallel, while the reference FET 114 may comprise fewer unit cells than the power FET 110. In some embodiments, the reference FET 114 may comprise only one unit cell. The gate inputs of the reference FET 114 and the power FET 110 may be DC coupled via an isolation circuit 130, such as a buffer or voltage follower circuit. A drain bias voltage (e.g., 48V) may be applied to the power FET 110 via a matching and RF choke network 122. A similar drain bias voltage may be applied to the reference FET 114.

[0044] In some embodiments, the gate of the reference FET 114 may be RF shorted to attenuate the drain current modulation by input waveforms that could otherwise adversely affect the drain current modulation due to carrier traps.

[0045] Circuit 100 includes a closed-loop trap compensation circuit that tracks the carrier trap effect in the power FET 110 and can compensate for this effect by applying a compensation signal to the gate of the power FET 110 during device operation.

[0046] Figure 4 is a detailed schematic circuit diagram of a closed-loop circuit 100 that compensates for carrier trap effects in a transistor device, according to several embodiments. Referring to Figure 4, the circuit 100 includes a power FET 110 that receives an RF input signal at an RF input node 112. The power FET 110 amplifies the RF input signal and outputs the amplified output signal from the output (drain) node of the power FET 110 to a connected load RL via a DC blocking capacitor C21. The drain of the power FET 110 is biased by a matching / RF choke network 122.

[0047] A reference FET 114 is provided, and the output (drain) of the power FET 110 is RF coupled to the output (drain) of the reference FET 114 via coupling capacitors C12 and C126, thereby ensuring that the reference FET 114 and the power FET 110 have the same or similar drain lags. The reference FET 114 is biased via a drain current detection circuit 119, which has a resistor R18 and a capacitor C11 in parallel between the bias voltage and the drain. A low-pass filter, which has a capacitor C9 and an inductor L4, is provided between the drain of the reference FET 114 and the drain current detection circuit 119, filtering out RF energy from the input of the drain current detection circuit 119, thereby limiting the influence of the output RF waveform on the compensation circuit. A voltage proportional to the drain current appears at node 121 and is input to the active bias circuit 120.

[0048] The design of active bias circuits for controlling FETs is known in the art. In the embodiment shown in Figure 4, the active bias circuit comprises resistors R14, R20, R53, R12, R13, R17, and R16, as well as PNP transistors BJT7 and BJT6. However, the active bias circuit may be any preferred topology. The operation of the active bias circuit 120 is as follows, with a brief reference to Figure 8, which is a plot of the IV of the PNP transistor BJT7. The voltage across R18 is set to a constant voltage by a voltage divider consisting of R14 and R53. The current flowing through R18 is constant. When the drain current Idq of the reference FET 114 decreases due to a trap, a larger collector current Ic flows through the BJT7. The operating point of the BJT7 then shifts to the left in the IV plot in Figure 8, resulting in a smaller collector-emitter voltage Vce of the BJT7 and a larger gate voltage of the reference FET 114. The drain current Idq of the reference FET114 increases and returns, completing the closed loop. BJT6 is used to manage the current level of BJT7 instead of a resistor, and to avoid cutoff.

[0049] Referring again to Figure 4, the compensation signal is output from the active bias circuit and filtered by a low-pass filter comprising resistor R19, capacitor C10, and inductor L8 to attenuate residual RF energy. The compensation signal is supplied to the input (gate) of the reference FET 114 to maintain the drain current at a constant level, thereby compensating for changes in the drain current of the reference FET 114.

[0050] This creates a closed-loop trap compensation as shown in Figure 4, allowing circuit 100 to monitor and adjust the fluctuations in the drain current at the reference FET 114, which represent the carrier trap effect at FET 114.

[0051] The compensation signal supplied to the input (gate) of the reference FET 114 is also supplied to the input (gate) of the power FET 110. The input (gate) of the reference FET 114 is DC coupled to the input (gate) of the power FET 110, among other things, and added to the RF input signal input to the power FET 110 at the summing node 117. The input (gate) of the reference FET 114 is coupled to the summing node 117 via a DC coupling path that may optionally include an RF choke inductor L11 and / or a low-pass filter 123 comprising resistor R44, inductor L9, and capacitor C23, as shown in Figure 4. Isolation between the inputs of the reference FET 114 and the power FET 110 can be achieved by a buffer circuit 132. The buffer circuit 132 can be implemented using an operational amplifier configured as a voltage follower, among other things, as shown in Figure 4.

[0052] In some embodiments, the gate of the reference FET 114 may be RF shorted via an RF shorting network 135 comprising a shunt capacitor C30 to attenuate drain current modulation by input waveforms that could otherwise adversely affect drain current modulation due to carrier traps.

[0053] Since the power FET 110 receives the same compensation signal as the reference FET 114, the trapping effect in the power FET 110 is compensated.

[0054] The exemplary values ​​for the circuit elements shown in Figure 4 are shown in Table 1 below. [Table 1]

[0055] Figure 5A is a graph of simulation results showing the gate voltage and drain current of a transistor device with and without trap compensation. Specifically, for three different phase conditions, the drain current is plotted at 1 μs (left) and 20 μs (right) in the two upper graphs of Figure 5A, and the gate voltage is plotted at 1 μs (left) and 20 μs (right) in the two lower graphs of Figure 5A.

[0056] To obtain the simulation results shown in Figure 5A, the circuit in Figure 4 was simulated using a GaN HEMT model of the reference FET 114 with a gate width of 0.05 mm and an Idq of 1 mA (110 mA / mm), and a GaN HEMT model of the power FET with a gate width of 3.6 mm and an Idq of 36 mA (10 mA / mm). The reference FET 114 and power FET 110 were biased to operate with a narrow conduction angle bias, such as in Class AB mode.

[0057] In Figure 5A, curve 501 represents the results for a model without traps or trap compensation, curve 502 represents the results for a model with traps but without trap compensation, and curve 503 represents the results for a model with traps and trap compensation due to closed-loop gate modulation according to several embodiments. As can be seen from Figure 5A, the drain current is almost identical to the simulation result for the model without traps (curve 501) when trap compensation is performed according to several embodiments (curve 503). The effect of trap compensation can be seen in the gate voltage graph, where the gate voltage when trap compensation is performed is significantly different from the gate voltage when trap compensation is not performed (curves 501 and 502).

[0058] Figure 5B is a graph of the simulation results from the simulation used to create Figure 5A, showing the RF envelope of a transistor device at 1 μs (left) and 40 μs (right) with and without trap compensation. Similar to Figure 5A, curve 501 represents the result of a model with no traps or trap compensation, curve 502 represents the result of a model with traps but no trap compensation, and curve 503 represents the result of a model with trap compensation, including traps and closed-loop gate modulation according to several embodiments. The RF envelope in the simulation with trap compensation (curve 503) is very close to the curve without traps (curve 501) and significantly different from the curve with traps but no trap compensation (curve 502).

[0059] These results clearly demonstrate that the trapping effect is compensated for in the power FET 110.

[0060] Figure 6 is a flowchart illustrating the operation of compensating for the trap effect in a transistor device according to several embodiments. Referring to Figure 6, a method for compensating for the trap effect in a field-effect transistor (FET) includes the steps of: detecting a change in the drain current of a reference transistor coupled to the FET (block 602); generating an input signal for the reference transistor in response to the change in the drain current of the reference transistor (block 604); applying the input signal to the input of the reference transistor (block 606); and adding the input signal as a compensation signal to the RF input signal of the FET (block 608).

[0061] Figure 7 is a schematic diagram showing the layout of a monolithic microwave integrated circuit (MMIC) 200 comprising a power FET 110, a reference FET 114, and a buffer circuit 132 for compensating for the trapping effect in the power FET 110, according to several embodiments. The power FET 110 and the reference FET 114 can, in particular, be formed on a common substrate 202 and have the same epitaxial structure. Gate pads and drain pads are provided on the MMIC 200 for both the power FET 110 and the reference FET 114, as well as for the operational amplifier used to implement the buffer circuit 132. A coupling capacitor 126 is provided between the drains of the power FET 110 and the reference FET 114.

[0062] Transistor devices with trapping effect compensation circuits as described herein can be used in amplifiers operating in a wide variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating such a transistor device as described herein may be configured to operate at frequencies above 1 GHz. In other embodiments, the RF transistor amplifier may be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, the RF transistor amplifier may be configured to operate at frequencies above 3.1 GHz. In yet another embodiment, the RF transistor amplifier may be configured to operate at frequencies above 5 GHz. In some embodiments, the RF transistor amplifier may be configured to operate in at least one of the frequency bands of 2.5–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 40–75 GHz, or a portion of these frequency bands.

[0063] While embodiments of the concept of the present invention have been discussed above in relation to HEMT devices, it will be understood that the concept of the present invention described herein can also be applied to other types of semiconductor devices, such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0064] RF transistor amplifiers incorporating the transistor devices described herein can be used in standalone RF transistor amplifiers and / or multiple RF transistor amplifiers. Examples of how some embodiments of RF transistor amplifiers can be used in applications comprising multiple amplifiers will be discussed with reference to Figures 9A-9C.

[0065] Referring to Figure 9A, an RF transistor amplifier 1000A is schematically shown, comprising an electrically series-connected preamplifier 1010 and a main amplifier 1030. As shown in Figure 9A, the RF transistor amplifier 1000A comprises an RF input 1001, a preamplifier 1010, an interstage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The interstage impedance matching network 1020 may comprise, for example, inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although not shown in Figure 9A, the RF transistor amplifier 1000A may further comprise an input matching network inserted between the RF input 1001 and the preamplifier 1010, and / or an output matching network inserted between the main amplifier 1030 and the RF output 1002. The RF transistor amplifier according to this embodiment can be used to implement either or both of the preamplifier 1010 and the main amplifier 1030.

[0066] Referring to Figure 9B, an RF transistor amplifier 1000B is schematically shown, comprising an RF input 1001, a pair of preamplifiers 1010-1 and 1010-2, a pair of interstage impedance matching networks 1020-1 and 1020-2, a pair of main amplifiers 1030-1 and 1030-2, and an RF output 1002. A distributor 1003 and a combiner 1004 are also provided. Preamplifiers 1010-1 and 1030-1 (connected in electrical series) are electrically connected in parallel with preamplifiers 1010-2 and 1030-2 (connected in electrical series). The RF transistor amplifier 1000B, like the RF transistor amplifier 1000A in Figure 9A, may further include an input matching network inserted between the RF input 1001 and preamplifiers 1010-1 and 1010-2, and / or an output matching network inserted between the main amplifiers 1030-1 and 1030-2 and the RF output and 1002.

[0067] As shown in Figure 9C, RF transistor amplifiers according to some embodiments can also be used to implement a Doherty amplifier. A Doherty amplifier circuit comprises a first and second (or more) power combining amplifier, as is known in the art. The first amplifier is called the “main” amplifier or “carrier” amplifier, and the second amplifier is called the “peaking” amplifier. The two amplifiers can be biased separately. For example, in one common embodiment of a Doherty amplifier, the main amplifier may include a Class AB or Class B amplifier, while the peaking amplifier may be a Class C amplifier. A Doherty amplifier can operate more efficiently than a balanced amplifier when operating at power levels with back-off from the saturation level. The RF signal input to the Doherty amplifier is divided (e.g., using a quadrature combiner) and the outputs of the two amplifiers are combined. The main amplifier is configured to turn on first (i.e., at lower input power levels), so that only the main amplifier operates at lower power levels. As the input power level increases towards the saturation level, the peaking amplifier is turned on, and the input RF signal is distributed between the main amplifier and the peaking amplifier.

[0068] The Doherty RF transistor amplifier 1000C, as shown in Figure 9C, comprises an RF input 1001, an input distributor 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The Doherty RF transistor amplifier 1000C is further equipped with a 90° transformer 1007 at the input of the peaking amplifier 1050 and a 90° transformer 1005 at the input of the main amplifier 1040, and may optionally be equipped with an input matching network and / or an output matching network (not shown). The main amplifier 1040 and / or the peaking amplifier 1050 can be implemented using any of the RF transistor amplifiers according to the embodiments described above.

[0069] The RF transistor amplifiers according to the embodiments may be formed as individual devices or as part of a monolithic microwave integrated circuit (MMIC). An MMIC refers to an integrated circuit that operates with radio and / or microwave frequency signals, in which all circuits are integrated on a single semiconductor chip for a specific function. An exemplary MMIC device is a transistor amplifier with associated matching circuits, power supply networks, etc., all implemented on a common substrate. An MMIC transistor amplifier typically comprises multiple unit-cell HEMT transistors connected in parallel.

[0070] Figure 10 is a plan view of an MMIC RF transistor amplifier 400 according to an embodiment of the concept of the present invention. The MMIC RF transistor amplifier 400 comprises an integrated circuit chip 430 housed in a package 410, as shown in Figure 10. The package 410 may include a protective enclosure that surrounds and protects the integrated circuit chip 430. The package 410 may be formed of, for example, a ceramic material.

[0071] Package 410 comprises input leads 412 and output leads 418. The input leads 412 can be attached to input lead pads 414, for example, by soldering. One or more input junction wires 420 can electrically connect the input lead pads 414 to input junction pads on the integrated circuit chip 430. The integrated circuit chip 430 comprises an input power supply network 438, an input impedance matching network 450, a first RF transistor amplification stage 460, an intermediate impedance matching network 440, a second RF transistor amplification stage 462, an output impedance matching stage 470, and an output power supply network 482.

[0072] The package 410 further comprises output leads 418 connected, for example, to output lead pads 416 by soldering. One or more output junction wires 490 can electrically connect the output lead pads 416 to output junction pads on the integrated circuit chip 430. The first RF transistor amplification stage 460 and / or the second RF transistor amplification stage 462 can be implemented using any of the RF transistor amplifiers according to embodiments of the concept of the present invention.

[0073] RF transistor amplifiers according to embodiments of the concept of the present invention can be designed to operate in a variety of different frequency bands. Such RF transistor amplifier dies may, in some embodiments, be configured to operate in at least one of the following frequency bands: 0.6–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 40–75 GHz, or a portion of these frequency bands. The techniques according to embodiments of the concept of the present invention may be particularly advantageous for RF transistor amplifiers operating at frequencies above 10 GHz.

[0074] Figures 11A and 11B are schematic cross-sectional views illustrating several exemplary ways in which an RF transistor amplifier die according to an embodiment of the concept of the present invention can be packaged to realize the packaged RF transistor amplifiers 600A and 600B, respectively.

[0075] Figure 11A is a schematic side view of a packaged group III nitride-based RF transistor amplifier 600A. The packaged RF transistor amplifier 600A comprises an RF transistor amplifier die 100 packaged in an open cavity package 610A, as shown in Figure 11A. The package 610A comprises a metal gate lead 622A, a metal drain lead 624A, a metal submount 630, a side wall 640, and a lid 642.

[0076] The submount 630 may include a material configured to assist in the thermal management of package 600A. The submount 630 may include, for example, copper and / or molybdenum. In some embodiments, the submount 630 may consist of multiple layers and / or include vias / interconnections. In exemplary embodiments, the submount 630 may be a multilayer copper / molybdenum / copper metal flange comprising a core-molybdenum layer with a copper-clad layer on one of its main surfaces. In some embodiments, the submount 630 may include a metal heat sink, which is part of the lead frame or metal slag. The sidewalls 640 and / or lid 642 may be formed of or include insulating material in some embodiments. The sidewalls 640 and / or lid 642 may be formed of or include ceramic material, for example.

[0077] The side wall 640 and / or lid 642 may, in some embodiments, be formed of, for example, Al2O3. The lid 642 can be bonded to the side wall 640 using epoxy adhesive. The side wall 640 can be attached to the submount 630, for example, by brazing. The gate lead 622A and drain lead 624A are configured to extend through the side wall 640, but embodiments of the concept of the present invention are not limited thereto.

[0078] The RF transistor amplifier die 100 is mounted on the upper surface of the metal submount 630 within an air-filled cavity 612 defined by a metal submount 630, a ceramic sidewall 640, and a ceramic lid 642. The gate and drain terminals of the RF transistor amplifier die 100 may be on the upper side of the structure, while the source terminal is on the lower side of the structure.

[0079] The gate lead 622A can be connected to the gate terminal of the RF transistor amplifier die 100 by one or more junction wires 654. Similarly, the drain lead 624A can be connected to the drain terminal of the RF transistor amplifier die 100 by one or more junction wires 654. The source terminal can be mounted to a metal submount 630 using, for example, a conductive die attachment material (not shown). The metal submount 630 may have electrical connections to the source terminal 126 and may also function as a heat dissipation structure to dissipate heat generated within the RF transistor amplifier die 100.

[0080] Heat is generated primarily on the upper part of the RF transistor amplifier die 100, where relatively high current densities are generated, for example, in the channel region of a unit cell transistor. This heat can be transferred to the source terminal through the source via 146 and the semiconductor layer structure of the device, and then to the metal submount 630.

[0081] Figure 11B is a schematic side view of a differently packaged, group III nitride-based RF transistor amplifier 600B. RF transistor amplifier 600B differs from RF transistor amplifier 600A in that it has a different package 610B. Package 610B includes a metal submount 630, as well as a metal gate 622B and drain lead 624B. RF transistor amplifier 600B also includes a plastic outer covering 660 that at least partially surrounds the RF transistor amplifier die 100, leads 622B, 624B, and the metal submount 630.

[0082] Many variations are possible in the features of the above embodiments. Transistor structures having features that can be used in embodiments of the present invention are disclosed in Patent Documents 1 to 13 by the same applicant, and the contents of each of Patent Documents 1 to 13 are fully incorporated herein by reference.

[0083] While embodiments of the concept of the present invention have been described in considerable detail with reference to specific configurations of the embodiments, other types are also possible. The field plate and gate can also have many different shapes and can be connected to the source contact in many different ways. Therefore, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. Field-effect transistors (FETs) and A reference transistor having an output coupled to the output of the FET, An active bias circuit is coupled to the reference transistor and configured to generate an input signal to the reference transistor according to the drain current of the reference transistor, and to directly apply the input signal to the input of the reference transistor, An adder node coupled to the input of the FET and the input of the reference transistor, which adds the input signal to the RF input signal of the FET, wherein the input of the reference transistor is isolated from the RF input signal of the FET. A circuit equipped with this feature.

2. The circuit according to claim 1, wherein the FET and the reference transistor each have their own source terminal, drain terminal and gate terminal, the drain terminals of the FET and the reference transistor constitute the respective outputs of the FET and the reference transistor, and the drain terminal of the FET is RF coupled to the drain terminal of the reference transistor via a coupling capacitor.

3. An RF shunt capacitor located between the gate terminal of the reference transistor and ground, wherein the RF shunt capacitor isolates the input of the reference transistor from the RF input signal of the FET. The circuit according to claim 2, further comprising:

4. The circuit according to claim 2, wherein the gate terminal of the reference transistor is DC coupled to the gate terminal of the FET.

5. A buffer between the gate terminal of the reference transistor and the gate terminal of the FET. The circuit according to claim 4, further comprising:

6. The circuit according to claim 5, wherein the buffer includes an operational amplifier circuit in a voltage follower configuration.

7. A low-pass filter between the gate of the reference transistor and the gate of the FET. The circuit according to claim 4, further comprising:

8. A drain current monitoring circuit configured to detect the level of drain current flowing into the reference transistor and coupled to the active bias circuit. The circuit according to claim 1, further comprising:

9. Low-pass filter between the reference transistor and the drain current monitoring circuit The circuit according to claim 8, further comprising:

10. The circuit according to claim 1, wherein the reference transistor and the FET include a group III nitride-based high electron mobility transistor.

11. The circuit according to claim 10, wherein the reference transistor and the FET are formed on a single substrate and share a common epitaxial structure.

12. The circuit according to claim 1, wherein the reference transistor and the FET are biased with a common drain bias voltage.

13. The circuit according to claim 1, wherein the active bias circuit is configured to control the gate voltage of the reference transistor in order to maintain a constant drain current flowing through the reference transistor.

14. The circuit according to claim 1, wherein the active bias circuit is configured to generate the input signal in response to a change in the drain current of the reference transistor, and the change in the drain current of the reference transistor is caused by a carrier trap in the reference transistor.

15. A power field-effect transistor (power FET) having a source terminal, a drain terminal, and a gate terminal, A reference transistor having a source terminal, a drain terminal, and a gate terminal, An RF coupling capacitor connected between the drain terminal of the reference transistor and the drain terminal of the power FET, A drain current detection circuit is coupled to the drain terminal of the reference transistor and configured to detect changes in the drain current of the reference transistor. An active bias circuit coupled to the drain current detection circuit and configured to generate an input signal to the reference transistor in accordance with the change in the drain current of the reference transistor, A transistor amplifier comprising, The input signal is applied directly to the gate terminal of the reference transistor. The aforementioned input signal is added to the RF input signal of the power FET. A transistor amplifier in which the gate terminal of the reference transistor is isolated from the RF input signal of the power FET.

16. The transistor amplifier according to claim 15, wherein the reference transistor and the power FET are biased with a Class A or Class AB bias.

17. An RF shunt capacitor located between the gate terminal of the reference transistor and ground, wherein the gate terminal of the reference transistor is isolated from the RF input signal of the power FET. The transistor amplifier according to claim 15, further comprising:

18. The transistor amplifier according to claim 15, wherein the gate terminal of the reference transistor is DC coupled to the gate terminal of the power FET.

19. A buffer between the gate terminal of the reference transistor and the gate terminal of the power FET. The transistor amplifier according to claim 18, further comprising:

20. The transistor amplifier according to claim 19, wherein the buffer includes an operational amplifier circuit in a voltage follower configuration.

21. A low-pass filter between the gate of the reference transistor and the gate of the power FET. The transistor amplifier according to claim 18, further comprising:

22. The transistor amplifier according to claim 15, wherein the power FET and the reference transistor include a group III nitride-based high electron mobility transistor.

23. A method for compensating for the carrier trap effect in a field-effect transistor (FET), wherein the method is: A step of detecting a change in the drain current of a reference transistor, wherein the output of the reference transistor is coupled to the output of the FET, The steps include generating an input signal to the reference transistor in accordance with the change in the drain current of the reference transistor, The steps include: applying the input signal directly to the input of the reference transistor; A step of adding the input signal as a compensation signal to the RF input signal of the FET, wherein the input of the reference transistor is isolated from the RF input signal of the FET. Methods that include...

24. The method according to claim 23, wherein the FET and the reference transistor include a group III nitride-based high electron mobility transistor.

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