Semiconductor memory

Abstract

To provide a semiconductor storage device which can preferably charge a word line.SOLUTION: According to an embodiment, the semiconductor storage device includes: a plurality of memory cell transistors; a word line electrically connected to the gates of the memory cell transistors; and a voltage generation circuit for generating a first voltage applied on the word line. The voltage generation circuit outputs different pressure rise waveforms when rising the first voltage between at the time of a verifying operation and at the time of a reading operation.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] When charging a word line in a semiconductor memory device by a voltage generation circuit, it is desirable to reduce the peak value of the current consumed by the voltage generation circuit and to accelerate the end of charging.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device capable of suitably charging a word line.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor memory device includes a plurality of memory cell transistors, a word line electrically connected in common to gates of the plurality of memory cell transistors, and a voltage generation circuit that generates a first voltage applied to the word line. The voltage generation circuit outputs different boosting waveforms when boosting the first voltage during an erase verification operation and a read operation.

Brief Description of the Drawings

[0006] [Figure 1] It is a block diagram showing the configuration of a memory system of the first embodiment. [Figure 2] It is a circuit diagram showing the configuration of a memory cell array 11 of the first embodiment. [Figure 3] This is a circuit diagram showing the configuration of the voltage generation circuit 15 of the first embodiment. [Figure 4] This is a timing chart illustrating an example of the operation of the memory system according to the first embodiment. [Figure 5] This is a timing chart to further illustrate an example of the operation of the memory system of the first embodiment. [Figure 6] This is a timing chart to further illustrate an example of the operation of the memory system of the first embodiment. [Figure 7] This is a circuit diagram showing the configuration of the voltage generation circuit 15 of the second embodiment. [Figure 8] This is another circuit diagram showing the configuration of the voltage generation circuit 15 of the second embodiment. [Figure 9] This is a timing chart illustrating an example of the operation of the memory system in the second embodiment. [Figure 10] This is a timing chart to further illustrate an example of the operation of the memory system of the second embodiment. [Figure 11] This is a timing chart to further illustrate an example of the operation of the memory system of the second embodiment. [Figure 12] This is a timing chart illustrating an example of the operation of the memory system according to the third embodiment. [Figure 13] This is a timing chart to further illustrate an example of the operation of the memory system of the third embodiment. [Figure 14] This is a timing chart to further illustrate an example of the operation of the memory system of the third embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will now be described with reference to the drawings. In Figures 1 to 14, identical components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) Figure 1 is a block diagram showing the configuration of the memory system of the first embodiment.

[0009] The memory system of this embodiment comprises a NAND memory 1 and a memory controller 2. The NAND memory 1 is an example of a semiconductor memory device, and the memory controller 2 is an example of a controller. The NAND memory 1 comprises a memory cell array 11, a command register 12, an address register 13, a sequencer 14, a voltage generation circuit 15, a row decoder module 16, a sense amplifier module 17, and a temperature sensor 18.

[0010] The operation of NAND memory 1 is controlled by memory controller 2. Memory controller 2 operates in response to requests from a host device (not shown). For example, memory controller 2 controls the reading of data from NAND memory 1 in response to a read request from the host device. Memory controller 2 also controls the writing of data to NAND memory 1 in response to a write request from the host device. Furthermore, memory controller 2 controls the erasure of data from NAND memory 1 in response to an erase request from the host device.

[0011] The memory cell array 11 includes multiple block BLKs. Each block BLK is a collection of multiple memory cells capable of storing data non-volatilely. Block BLKs are used, for example, as data erasure units. Pages, on the other hand, are used, for example, as data writing and reading units. Figure 1 shows n+1 block BLKs from BLK_0 to BLK_n (where n is an integer greater than or equal to 1) as an example of block BLKs. The memory cell array 11 further includes multiple bit lines and multiple word lines. Each memory cell is associated with one bit line and one word line.

[0012] The command register 12 holds the command CMD received by the NAND memory 1 from the memory controller 2. The command CMD includes instructions for the sequencer 14 to execute operations such as read operations, write operations, and erase operations.

[0013] The address register 13 holds the address information ADD received by the NAND memory 1 from the memory controller 2. The address information ADD includes, for example, the block address BA and the column address CA. The block address BA and the column address CA are each used when selecting the block BLK and the bit line.

[0014] The sequencer 14 controls the operation of the entire NAND memory 1. For example, the sequencer 14 controls the operations of the voltage generation circuit 15, the row decoder module 16, and the sense amplifier module 17 based on the command CMD held in the command register 12. Thereby, a read operation, a write operation, an erase operation, etc. are executed based on the command CMD.

[0015] The voltage generation circuit 15 generates voltages used in a read operation, a write operation, an erase operation, etc. under the control of the sequencer 14. For example, the voltage generation circuit 15 applies the generated voltage to the signal line corresponding to the selected word line. Also, the voltage generation circuit 15 generates the power supply voltage of the temperature sensor 18 and applies the power supply voltage to the temperature sensor 18.

[0016] The row decoder module 16 selects the block BLK based on the block address BA held in the address register 13, and transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0017] The sense amplifier module 17 transfers the write data received from the memory controller 2 to the memory cell array 11 during a write operation. Also, during a read operation, the sense amplifier module 17 determines the value stored in each memory cell based on the voltage of the bit line, and transfers the result of the determination to the memory controller 2 as read data DAT.

[0018] The temperature sensor 18 detects the temperature of the NAND memory 1. Based on the detected temperature, the temperature sensor 18 generates temperature information and transmits this temperature information to the sequencer 14. The temperature information is used by the sequencer 14 to correct the voltage generated by the voltage generation circuit 15 during operations such as write, read, and erase.

[0019] Figure 2 is a circuit diagram showing the configuration of the memory cell array 11 of the first embodiment.

[0020] Figure 2 shows one of several block BLKs included in the memory cell array 11. Each block BLK in this embodiment includes several string units SU0 to SU3, as shown in Figure 2. Each of the string units SU0 to SU3 includes m+1 NAND strings NS (where m is an integer greater than or equal to 1) between m+1 bit lines BL0 to BLm and one source line SRC. Hereinafter, each of the string units SU0 to SU3 will also be referred to as "string unit SU," and each of the bit lines BL0 to BLm will also be referred to as "bit line BL."

[0021] In the string unit SU0, the NAND string NS between the bit line BL0 and the source line SRC is equipped with memory cell transistors (memory cells) MT0 to MT7 on the word lines WL0 to WL7. This NAND string NS is further equipped with a selection transistor STS on the source-side selection line SGS0 and a selection transistor STD on the drain-side selection line SGD0. In this embodiment, other NAND string NS in the memory cell array 11 have a similar structure. Hereinafter, each of the word lines WL0 to WL7 will also be referred to as "word line WL", each of the memory cell transistors MT0 to MT7 will also be referred to as "memory cell transistor MT", and each of the selection transistors STS and STD will also be referred to as "selection transistor ST".

[0022] Each block BLK in this embodiment includes multiple cell units CU. Each cell unit CU includes multiple memory cell transistors MT located on a single word line WL within a single string unit SU. Therefore, each cell unit CU in Figure 2 includes m+1 memory cell transistors MT. Each cell unit CU corresponds to one page. In each cell unit CU, each word line WL is electrically connected in common to the gates of each of the m+1 memory cell transistors MT.

[0023] Figure 3 is a circuit diagram showing the configuration of the voltage generation circuit 15 of the first embodiment.

[0024] As shown in Figure 3, the voltage generation circuit 15 comprises multiple charge pumps CP1 to CP4, multiple resistors R1 and R2, an operational amplifier AMP1, a state control circuit STCNTL, and multiple logic gates (AND gates) AND1 to AND4. Figure 3 further shows nodes NOUT and N1 within the voltage generation circuit 15.

[0025] When the voltage VIN is input to the voltage generation circuit 15, the voltage generation circuit 15 generates a voltage VOUT that is higher than voltage VIN and outputs voltage VOUT from node NOUT. Voltage VIN is supplied to the voltage generation circuit 15 from a voltage source in the NAND memory 1, for example. Voltage VOUT is used, for example, in read operations, write operations, erase operations, etc. Voltage VIN is an example of a second voltage.

[0026] The voltage BIN shown in Figure 3 is output from the sequencer 14 and input to the voltage generation circuit 15. Voltage BIN is a signal used by the sequencer 14 to control the operation of the voltage generation circuit 15. As will be described later, the waveform of voltage VOUT changes to follow the waveform of voltage BIN. Therefore, the sequencer 14 can change the waveform of voltage VOUT by controlling the waveform of voltage BIN. Voltage VOUT is an example of the first voltage.

[0027] Next, referring to Figure 3, we will describe the details of each component within the voltage generation circuit 15.

[0028] Charge pump CP1 has an input terminal to which the voltage VIN is input, an input terminal to which the signal PCLK1 is input, and an output terminal that can be electrically connected to node NOUT. The same applies to charge pumps CP2 to CP4. However, charge pumps CP2 to CP4 each have an input terminal to which signals PCLK2 to PCLK4 are input instead of signal PCLK1. Hereafter, each of charge pumps CP1 to CP4 will also be referred to as "charge pump CP," and each of signals PCLK1 to PCLK4 will also be referred to as "signal PCLK."

[0029] Each charge pump CP performs a boost operation as long as the signal PCLK input to that charge pump CP is the clock signal CLK and the boost operation of all charge pump CPs is not collectively disabled by the sequencer 14. For example, if the voltage VOUT is higher than the threshold for collectively disabling boost operation, the boost operation of all charge pump CPs is collectively disabled by the sequencer 14. If the signal PCLK input to a charge pump CP is the clock signal CLK and that charge pump CP is designated as a pump capable of boost operation by the state control circuit STCNTL, the state of that charge pump CP is called "active". An active charge pump CP performs a boost operation as long as the boost operation of all charge pump CPs is not collectively disabled by the sequencer 14.

[0030] On the other hand, each charge pump CP stops boosting its voltage if the signal PCLK input to it is not the clock signal CLK, or if the boosting operation of all charge pump CPs is collectively prohibited by the sequencer 14. If the signal PCLK input to a charge pump CP is not the clock signal CLK, or if that charge pump CP is designated as a pump that cannot perform boosting operations by the state control circuit STCNTL, the state of that charge pump CP is called "inactive". An inactive charge pump CP stops boosting its voltage even if the boosting operation of all charge pump CPs is not collectively prohibited by the sequencer 14. An example of when the signal PCLK input to a charge pump CP is not the clock signal CLK is when the value of the signal PCLK is maintained at a low (L) level, as will be described later.

[0031] Resistor R1 is located between node NOUT and node N1. Resistor R2 is located between node N1 and the ground node. Therefore, resistors R1 and R2 are located in series between node NOUT and the ground node. In this embodiment, resistor R2 is a variable resistor. The value of resistor R2 can be changed by the voltage BIN. The relationship VOUT = {(R1+R2) / R2}VMON holds between voltages VOUT and VMON.

[0032] The operational amplifier AMP1 has a non-inverting input terminal to which a reference voltage VREF is input, an inverting input terminal to which a voltage VMON is input, and an output terminal to which the signal FLG1 is output. The signal FLG1 is generated based on the comparison result of the reference voltage VREF and the voltage VMON. For example, if the voltage VMON is less than the reference voltage VREF, the value of the signal FLG1 will be at a high (H) level. On the other hand, if the voltage VMON is greater than or equal to the reference voltage VREF, the value of the signal FLG1 will be at a low (L) level.

[0033] The state control circuit STCNTL has an input terminal to which the signal FLG1 from the operational amplifier AMP1 is input, an input terminal to which the clock signal CLK is input, and output terminals to which signals EN1 to EN4 are output to logic gates AND1 to AND4, respectively. The state control circuit STCNTL uses the clock signal CLK to calculate the period NH during which the value of signal FLG1 is maintained at a high level, and the period NL during which the value of signal FLG1 is maintained at a low level. The state control circuit STCNTL further generates signals EN1 to EN4 based on periods NH and NL. Signals EN1 to EN4 each specify whether the charge pumps CP1 to CP4 are active or inactive. Hereafter, each of signals EN1 to EN4 will also be referred to as "signal EN".

[0034] When the value of signal EN is at the H level, signal EN specifies that the charge pump CP should be activated. On the other hand, when the value of signal EN is at the L level, signal EN specifies that the charge pump CP should be deactivated. The state control circuit STCNTL controls the number Nu of signals EN1 to EN4 that have a value at the H level, based on the periods NH and NL. The state of the state control circuit STCNTL transitions between four states S1 to S4 depending on the number Nu. States S1 to S4 correspond to states with a number Nu of 1 to 4, respectively.

[0035] Logic gate AND1 has an input terminal to which signal EN1 is input, an input terminal to which clock signal CLK is input, and an output terminal to which signal PCLK1 is output to charge pump CP1. Signal PCLK1 represents the result of the AND operation between signal EN1 and clock signal CLK. For example, if the value of signal EN1 is at a high level, signal PCLK1 will be the clock signal CLK. On the other hand, if the value of signal EN1 is at a low level, the value of signal PCLK1 will remain at a low level. The same applies to logic gates AND2 to AND4. However, logic gates AND2 to AND4 each have an input terminal to which signals EN2 to EN4 are input instead of signal EN1, and an output terminal to which signals PCLK2 to PCLK4 are output instead of signal PCLK1. Hereafter, each of logic gates AND1 to AND4 will also be referred to as "logic gate AND".

[0036] Figure 4 is a timing chart illustrating an example of the operation of the memory system according to the first embodiment.

[0037] As described above, the memory cell array 11 includes multiple memory cells, multiple word lines, multiple bit lines, etc. (Figure 2). During a read operation, data is read from the selected cell among these memory cells. Memory cells other than the selected cell are called unselected cells. During a read operation, a low voltage is applied to the word line electrically connected to the selected cell (selected word line), and a high voltage is applied to the word line electrically connected to the unselected cell (unselected word line). This makes it possible to read data only from the selected cell among the selected and unselected cells.

[0038] During the read operation, the sequencer 14 outputs a voltage BIN, and the voltage generation circuit 15 outputs a voltage VOUT that changes according to the voltage BIN. Voltage VOUT is supplied to each word line. As a result, each word line is charged by voltage VOUT, and the voltage of each word line rises. Consequently, the selected word line is supplied with the low voltage mentioned above, and the unselected word line is supplied with the high voltage mentioned above.

[0039] Figure 4(a) shows the time variation of the voltage BIN output to generate the voltage VOUT for the unselected word line during a read operation. Code A1 shows the time variation of the voltage BIN during the 1st Read, and code A2 shows the time variation of the voltage BIN during the 2nd Read. Code T indicates the start time of charging (start time of voltage boosting) of the word line.

[0040] As an example, consider a case where data is read from the memory cell array 11, and then data is read from the memory cell array 11 again. In this case, if the period between the former read and the latter read is short, the voltage on the word line will not have returned to zero when the latter read occurs. A read that starts before the voltage on the word line returns to zero is called a 2nd Read. On the other hand, a read that starts when the voltage on the word line is zero is called a 1st Read.

[0041] During the read operation, the sequencer 14 of this embodiment controls the waveform of the voltage BIN for unselected word lines so that the voltage BIN for unselected word lines changes in a different manner than the voltage BIN for unselected word lines when the 2nd Read is performed. Therefore, in Figure 4(a), the voltage BIN indicated by symbol A2 changes in a different manner than the voltage BIN indicated by symbol A1.

[0042] Specifically, the waveform indicated by symbol A2 has a shape obtained by vertically shifting the waveform indicated by symbol A1. Therefore, the rise timing, rise period, and rise rate of the voltage BIN indicated by symbol A2 are the same as the rise timing, rise period, and rise rate of the voltage BIN indicated by symbol A1 at any given time. Both the voltage BIN indicated by symbol A1 and the voltage BIN indicated by symbol A2 rise in a step-like manner. On the other hand, the value of the voltage BIN indicated by symbol A2 at the start of charging is higher than the value of the voltage BIN indicated by symbol A1 at the start of charging. In Figure 4(a), since the voltage BIN rises in a step-like manner, the rise period of the voltage BIN is the time width of one step of the voltage BIN, and the rise rate of the voltage BIN is the value obtained by dividing the voltage rise amount of one step of the voltage BIN by the time width of one step of the voltage BIN.

[0043] In Figure 4(a), the waveform indicated by the symbol A2 has a shape obtained by vertically shifting the waveform indicated by the symbol A1 without changing it at all. However, the waveform indicated by the symbol A2 may also have a shape obtained by modifying the waveform indicated by the symbol A1 and vertically shifting it. An example of such a waveform is shown in Figure 4(b), which will be described later.

[0044] Figure 4(b) shows the waveforms indicated by symbols A1 and A2, as well as the waveforms indicated by symbols B1, B2, C1, and C2. Symbols B1 and B2 both show the time change of the voltage VOUT during the 2nd Read. Symbols C1 and C2 both show the time change of the voltage on the word line far from node NOUT during the 2nd Read. However, symbols B1 and C1 show the voltage when the voltage BIN for the 1st Read, indicated by symbol A1, is used, and symbols B2 and C2 show the voltage when the voltage BIN for the 2nd Read, indicated by symbol A2, is used.

[0045] The waveform of voltage VOUT changes in accordance with the waveform of voltage BIN. Therefore, in Figure 4(b), the voltage VOUT indicated by the symbol B1 rises in accordance with the voltage BIN indicated by the symbol A1, and has a waveform that oscillates around the waveform of voltage BIN indicated by the symbol A1. Similarly, the voltage VOUT indicated by the symbol B2 rises in accordance with the voltage BIN indicated by the symbol A2, and has a waveform that oscillates around the waveform of voltage BIN indicated by the symbol A2.

[0046] However, the voltage VOUT, indicated by symbol B1, and the word line voltage, indicated by symbol C1, do not rise while these voltages are higher than the voltage BIN, indicated by symbol A1. This phenomenon occurs because the word line voltage does not return to zero when the 2nd Read starts charging. As a result, the completion of word line charging is delayed.

[0047] On the other hand, the voltage VOUT, indicated by symbol B2, and the word line voltage, indicated by symbol C2, have been rising since the start of charging the 2nd Read. This is because, at the start of charging the 2nd Read, not only the word line voltage but also the voltage BIN, indicated by symbol A2, is sufficiently high. This makes it possible to shorten the time it takes to complete charging the word line.

[0048] Figure 5 is a timing chart to further illustrate an example of the operation of the memory system of the first embodiment.

[0049] Figures 5(a), 5(b), and 5(c) show the time variation of the voltage BIN output to generate the voltage VOUT for the unselected word line during a read operation. The example shown in Figure 5(a) is the same as the example shown in Figure 4(a), but is shown for comparison with the examples shown in Figures 5(b) and 5(c). Figures 5(a), 5(b), and 5(c) further show the time variation of the voltage VOUT for the unselected word line during a read operation.

[0050] In Figure 5(b), the rate of increase of the voltage BIN indicated by symbol A2 is higher than the rate of increase of the voltage BIN indicated by symbol A1 within a predetermined time from the start of charging. Specifically, when the voltage BIN indicated by symbol A1 rises for the first time, the voltage BIN indicated by symbol A2 rises for the fourth time. Also, from the start of charging up to this point, the voltage increase value when the voltage BIN indicated by symbol A2 rises once is the same as the voltage increase value when the voltage BIN indicated by symbol A1 rises once. Therefore, from the start of charging up to this point, the rate of increase of the voltage BIN indicated by symbol A2 is four times that of the voltage BIN indicated by symbol A1, and the rise period of the voltage BIN indicated by symbol A2 is one-quarter of the rise period of the voltage BIN indicated by symbol A1. This makes it possible to speed up the completion of charging of the word line during the 2nd Read. Note that the above values ​​of "four times" and "one-quarter" are merely examples, and other values ​​may also be used.

[0051] In Figure 5(b), the changes in voltage BIN, indicated by symbols A1 and A2, are reflected in the changes in voltage VOUT, indicated by symbols B1 and B2, respectively. Therefore, the rate of increase, the number of increases, and the voltage increase value of voltage BIN correspond to the rate of increase, the number of increases, and the voltage increase value of the average value of voltage VOUT, respectively. Furthermore, the period of increase in voltage BIN corresponds to the period during which the average value of voltage VOUT remains constant. Here, the average value of voltage VOUT is the average of the voltage VOUT values ​​during one oscillation of voltage VOUT, for example, the average of the maximum and minimum values ​​of voltage VOUT during one oscillation of voltage VOUT. In Figure 5(b), from the start of charging to the above point, the rate of increase of the average value of voltage VOUT, indicated by symbol B2, is four times the rate of increase of the average value of voltage VOUT, indicated by symbol B1, and the period during which the average value of voltage VOUT, indicated by symbol B2, remains constant is one-quarter of the period during which the average value of voltage VOUT, indicated by symbol B2, remains constant.

[0052] Furthermore, the change in voltage BIN, indicated by symbols A1 and A2, is reflected in the change in voltage VOUT, indicated by symbols B1 and B2, respectively, as is the case in Figure 5(a) above and in Figure 5(c) below, and also in the second and third embodiments below. For example, the voltage BIN at the start of charging corresponds to the average value of the voltage VOUT at the start of charging. At the start of charging in Figure 5(a), the average value of voltage VOUT, indicated by symbol B2, is higher than the average value of voltage VOUT, indicated by symbol B1.

[0053] In Figure 5(c), the rate of increase of the voltage BIN indicated by symbol A2 is higher than the rate of increase of the voltage BIN indicated by symbol A1 within a predetermined time from the start of charging. Specifically, when the voltage BIN indicated by symbol A1 rises for the first time, the voltage BIN indicated by symbol A2 rises for the second time. Also, from the start of charging up to this point, the voltage increase value when the voltage BIN indicated by symbol A2 rises once is twice the voltage increase value when the voltage BIN indicated by symbol A1 rises once. Therefore, from the start of charging up to this point, the rate of increase of the voltage BIN indicated by symbol A2 is four times the rate of increase of the voltage BIN indicated by symbol A1, and the rise period of the voltage BIN indicated by symbol A2 is half the rise period of the voltage BIN indicated by symbol A1. This makes it possible to speed up the completion of charging of the word line during the 2nd Read. Note that the above values ​​of "four times" and "half" are merely examples, and other values ​​may also be used.

[0054] The voltage BIN rise period is the time from the point in time when the voltage BIN rises to the point in time when the voltage BIN rises again. The voltage BIN rise rate is the increase in voltage BIN within a unit of time.

[0055] Figure 6 is a timing chart to further illustrate an example of the operation of the memory system of the first embodiment.

[0056] Figures 6(a) and 6(c) show the voltage changes during the 2nd Read and 1st Read when time R2 is short, respectively. Figures 6(b) and 6(d) show the voltage changes during the 2nd Read and 1st Read when time R2 is long, respectively. Time R2 represents the time required to charge the word line. Figures 6(a) to 6(d) each show the time variation of the voltages of the drain-side selected line (SGD), the unselected word line (WLn+1~), and the selected word line (SEL WL).

[0057] If time R2 is short, a Read Disturb due to drain-side boost occurs in the 1st Read, as shown in Figure 6(c). This problem can be suppressed by increasing time R2, as shown in Figure 6(d). However, increasing time R2 delays the completion of word line charging in the 2nd Read, as shown in Figure 6(b). According to this embodiment, as described above, it is possible to resolve this problem of delayed completion of charging.

[0058] As described above, the sequencer 14 of this embodiment controls the waveform of the voltage BIN for the unselected word line during a read operation so that the voltage BIN for the unselected word line changes in a different manner than the voltage BIN for the unselected word line during a 2nd Read. Therefore, according to this embodiment, it is possible to speed up the completion of charging of the word line.

[0059] The memory system of the second embodiment and the memory system of the third embodiment will be described below. The configuration and operation of the memory systems of the second and third embodiments are generally the same as those of the memory system of the first embodiment. The following description will focus on the differences between the memory system of the first embodiment and the memory systems of the second and third embodiments.

[0060] (Second Embodiment) Figure 7 is a circuit diagram showing the configuration of the voltage generation circuit 15 of the second embodiment.

[0061] The NAND memory 1 of this embodiment includes a voltage generation circuit 15, similar to the NAND memory 1 of the first embodiment. However, the charge pumps CP1 to CP4 in the voltage generation circuit 15 of this embodiment have the configuration shown in Figure 7.

[0062] Figure 7 shows the input terminal PMPIN and output terminal PMPOUT of the voltage generation circuit 15. In Figure 7, the voltage VIN is input to the input terminal PMPIN, and the voltage VOUT is output from the output terminal PMPOUT. The input terminal PMPIN is electrically connected to the input terminal of the charge pump CP1. The output terminal PMPOUT is electrically connected to the output terminal of the charge pump CP4. Figure 7 further shows the switches SW1 to SW9 within the voltage generation circuit 15.

[0063] Switch SW1 is located between the output terminal of charge pump CP1 and the input terminal of charge pump CP2. Switch SW2 is located between the output terminal of charge pump CP2 and the input terminal of charge pump CP3. Switch SW3 is located between the output terminal of charge pump CP3 and the input terminal of charge pump CP4.

[0064] Switch SW4 is electrically connected to input terminal PMPIN and is electrically connected to the node between switch SW1 and the input terminal of charge pump CP2. Switch SW5 is electrically connected to input terminal PMPIN and is electrically connected to the node between switch SW2 and the input terminal of charge pump CP3. Switch SW6 is electrically connected to input terminal PMPIN and is electrically connected to the node between switch SW3 and the input terminal of charge pump CP4.

[0065] Switch SW7 is electrically connected to the output terminal PMPOUT and is electrically connected to the node between the output terminal of charge pump CP1 and switch SW1. Switch SW8 is electrically connected to the output terminal PMPOUT and is electrically connected to the node between the output terminal of charge pump CP2 and switch SW2. Switch SW9 is electrically connected to the output terminal PMPOUT and is electrically connected to the node between the output terminal of charge pump CP3 and switch SW3.

[0066] In this embodiment, the sequencer 14 can switch the state of the voltage generation circuit 15 by switching the on / off states of switches SW1 to SW9. In Figure 7, switches SW1 to SW3 are open (off), and switches SW4 to SW9 are closed (on). As a result, the charge pumps CP1 to CP4 are electrically connected in parallel with each other, similar to the configuration shown in Figure 3. Hereafter, the connection state shown in Figure 7 will be referred to as the 4-parallel state.

[0067] Figure 8 is another circuit diagram showing the configuration of the voltage generation circuit 15 of the second embodiment.

[0068] The voltage generation circuit 15 shown in Figure 8 is the same as the voltage generation circuit 15 shown in Figure 7, but it is in a different state. In Figure 8, switches SW1, SW3, SW5, and SW8 are closed (on), and switches SW2, SW4, SW6, SW7, and SW9 are open (off). As a result, charge pumps CP1 and CP2 are electrically connected in series with each other, and charge pumps CP3 and CP4 are electrically connected in series with each other. Furthermore, the pair of charge pumps CP1 and CP2 and the pair of charge pumps CP3 and CP4 are electrically connected in parallel with each other. Hereafter, the connection state shown in Figure 8 will be referred to as the 2-parallel state.

[0069] The sequencer 14 in this embodiment can, for example, switch the state of the voltage generation circuit 15 from one of the 4-parallel state and 2-parallel state to the other of the 4-parallel state and 2-parallel state in conjunction with the operation of the timer. Note that the state of the voltage generation circuit 15 may also be switched by components other than the sequencer 14.

[0070] Figure 9 is a timing chart illustrating an example of the operation of the memory system in the second embodiment.

[0071] Figure 9(a) shows an example of the voltage BIN output to generate the voltage VOUT for the unselected word line during a read operation. In Figure 9(a), the symbol A1 shows an example of the time change of the voltage BIN during the 1st Read, specifically the time change of the voltage BIN when the state of the voltage generation circuit 15 switches from a 4-parallel state to a 2-parallel state. Figure 9(a) further shows the time change of the voltage VOUT for the unselected word line during a read operation.

[0072] During the read operation, the sequencer 14 of this embodiment controls the waveform of the voltage BIN for unselected word lines so that the voltage BIN for unselected word lines after the state of the voltage generation circuit 15 switches changes in a different manner than the voltage BIN for unselected word lines before the state of the voltage generation circuit 15 switches. Therefore, in Figure 9(a), the rise period of the voltage BIN for unselected word lines in the 2-parallel state is longer than the rise period of the voltage BIN for unselected word lines in the 4-parallel state. Furthermore, the rise period of the voltage BIN for unselected word lines at the time the state of the voltage generation circuit 14 switches from the 4-parallel state to the 2-parallel state is longer than the rise period of the voltage BIN for unselected word lines before and after the switch.

[0073] Specifically, in Figure 9(a), the voltage rise period of the unselected word line voltage BIN in the 4-parallel state is ΔT / 2, and the voltage rise period of the unselected word line voltage BIN in the 2-parallel state is ΔT. Therefore, the voltage rise period of the unselected word line voltage BIN in the 2-parallel state is twice that of the voltage rise period of the unselected word line voltage BIN in the 4-parallel state. Furthermore, the voltage rise period of the unselected word line voltage BIN at the time the voltage generation circuit 14 switches from the 4-parallel state to the 2-parallel state is 2ΔT. Therefore, the voltage rise period of the unselected word line voltage BIN at this point (2ΔT) is longer than the voltage rise period of the unselected word line voltage BIN before and after the switch (ΔT / 2 and ΔT). Also, in Figure 9(a), the voltage rise value when the unselected word line voltage BIN rises once is a constant value of ΔA.

[0074] In Figure 9(a), the period shown by the two dashed lines flanking the sign ΔT is the period during which the voltage BIN for the unselected word line is not increased. In this embodiment, when the state of the voltage generation circuit 15 switches from a 4-parallel state to a 2-parallel state, the sequencer 14 does not increase the voltage BIN for the unselected word line during the above period. As a result, the voltage increase period of the voltage BIN at the time the state of the voltage generation circuit 14 switches is 2ΔT.

[0075] Figure 9(b) shows another example of the voltage BIN output to generate the voltage VOUT for the unselected word line during a read operation. In Figure 9(b), the label A1 shows an example of the time change of the voltage BIN during the 1st Read, specifically the time change of the voltage BIN when the state of the voltage generation circuit 15 switches from a 4-parallel state to a 2-parallel state. Figure 9(b) further shows the time change of the voltage VOUT for the unselected word line during a read operation.

[0076] The waveform shown in Figure 9(b) is generally similar to the waveform shown in Figure 9(a). However, in Figure 9(b), the voltage rise of the voltage BIN for the unselected word line at the time the state of the voltage generation circuit 14 switches is ΔA / 2. Therefore, the rate of increase of the voltage BIN for the unselected word line at the time the state of the voltage generation circuit 14 switches ((ΔA / 2) / ΔT) is lower than the rate of increase of the voltage BIN for the unselected word line before and after the switch (ΔA / (ΔT / 2) or ΔA / ΔT).

[0077] In Figure 9(b), the period shown by the two dashed lines flanking the sign ΔT is the period during which the voltage rise of the voltage BIN for the unselected word line is reduced. In this embodiment, when the state of the voltage generation circuit 15 switches from a 4-parallel state to a 2-parallel state, the sequencer 14 reduces the voltage rise of the voltage BIN for the unselected word line from ΔA to ΔA / 2 during the above period. As a result, the rate of increase of the voltage BIN at the time the state of the voltage generation circuit 14 switches is (ΔA / 2) / ΔT.

[0078] Note that in Figure 9(b), the point at which the state of the voltage generation circuit 14 switches coincides with the point at which the voltage BIN rises, but it may be different from the point at which the voltage BIN rises. If the point at which the state of the voltage generation circuit 14 switches is different from the point at which the voltage BIN rises, then (ΔA / 2) / ΔT will be the rate of increase of the voltage BIN immediately after the state of the voltage generation circuit 14 switches, rather than the rate at which the state of the voltage generation circuit 14 switches. This can also be said for the voltage BIN rise period in Figure 9(a).

[0079] According to this embodiment, by changing the voltage BIN as shown in Figure 9(a) or Figure 9(b), it is possible to reduce the peak value of the current consumed by the voltage generation circuit 14. Details of this effect will be described later.

[0080] Figure 10 is a timing chart to further illustrate an example of the operation of the memory system of the second embodiment.

[0081] Figure 10 shows the waveforms indicated by symbols A1, B1, C1, D1, and E1 for the operation during the 1st Read of this embodiment. Furthermore, Figure 10 shows the waveforms indicated by symbols B1', C1', D1', and E1' for the operation during the 1st Read of a comparative example of this embodiment, corresponding to the waveforms indicated by symbols B1, C1, D1, and E1. Note that waveform A1 in Figure 10 shows the voltage BIN before the fluctuation of voltage BIN during the period indicated by symbol ΔT is eliminated, as in waveform A1 in Figure 9(a), or before the fluctuation of voltage BIN during the period indicated by symbol ΔT is reduced, as in waveform A1 in Figure 9(b).

[0082] In Figure 10, the symbol A1 indicates the voltage BIN for the unselected word line. The symbol B1 indicates the voltage VOUT for the unselected word line. The symbol C1 indicates the voltage of the unselected word line far from node NOUT. The symbol D1 indicates the current Icc generated by the charging of the unselected word line. The symbol E1 indicates the time average of the current Icc. Since the charging of the unselected word line is performed by the voltage generation circuit 14, the current Icc corresponds to the "current consumed by the voltage generation circuit 14" mentioned above.

[0083] In the waveform labeled D1', the current Icc fluctuates rapidly during the period indicated by the arrow. On the other hand, in the waveform labeled D1, the current Icc fluctuates more slowly during the period indicated by the arrow. This is due to the change in voltage BIN, as shown in Figure 9(a) or Figure 9(b). As can be seen from comparing the waveform labeled E1 and the waveform labeled E1', this embodiment makes it possible to reduce the peak value of the current (Icc) consumed by the voltage generation circuit 14.

[0084] Figure 11 is a timing chart to further illustrate an example of the operation of the memory system of the second embodiment.

[0085] Figure 11, similar to Figure 10, shows waveforms corresponding to the operation during the 1st Read in this embodiment, indicated by symbols A1, B1, and C1, and waveforms corresponding to the operation during the 1st Read in a comparative example of this embodiment, indicated by symbols B1' and C1'. Figure 11 further shows a waveform corresponding to the operation during the 1st Read in this embodiment, indicated by symbol F1. Figure 11 further shows a waveform corresponding to the waveform indicated by symbol F1', corresponding to the waveform indicated by symbol F1, for the operation during the 1st Read in a comparative example of this embodiment.

[0086] In Figure 11, the symbol F1 represents the clock signal CLK used within the voltage generation circuit 15. During the period ΔT' indicated by the arrow in the waveform of symbol F1, the frequency of the clock signal CLK is reduced by half. This makes it possible to reduce the peak value of the current consumed by the voltage generation circuit 14, similar to the control shown in Figures 9(a) and 9(b). Period ΔT' is the period immediately after the state of the voltage generation circuit 15 switches from a 4-parallel state to a 2-parallel state, similar to period T described above.

[0087] Now, let's compare Figures 9(a), 9(b), and 11.

[0088] In Figure 9(a), the period indicated by the symbol ΔT is the period during which the voltage BIN for the unselected word line is not increased. In Figure 9(b), the period indicated by the symbol ΔT is the period during which the voltage rise value of the voltage BIN for the unselected word line is reduced. According to this embodiment, by changing the voltage BIN as shown in Figure 9(a) or Figure 9(b), it is possible to reduce the peak value of the current consumed by the voltage generation circuit 14. In Figures 9(a) and 9(b), the frequency of the clock signal CLK during the period indicated by the symbol ΔT is the same as the frequency during the other periods.

[0089] On the other hand, in Figure 11, the frequency of the clock signal CLK during the period indicated by the sign ΔT' is half the frequency during the other periods. According to this embodiment, by changing the frequency of the clock signal CLK as shown in Figure 11, it is possible to reduce the peak value of the current consumed by the voltage generation circuit 14. In Figure 11, the rate of increase of voltage BIN during the period indicated by the sign ΔT' is the same as the rate of increase of voltage BIN during the other periods. Also, in Figure 11, the rate of increase of voltage BIN in the 2-parallel state is the same as the rate of increase of voltage BIN in the 4-parallel state.

[0090] As described above, the sequencer 14 of this embodiment controls the waveform of the voltage BIN for unselected word lines so that, during a read operation, the voltage BIN for unselected word lines after the state of the voltage generation circuit 15 switches changes in a different manner than the voltage BIN for unselected word lines before the state of the voltage generation circuit 15 switches. Furthermore, the sequencer 14 of this embodiment changes the voltage BIN for unselected word lines at the time the state of the voltage generation circuit 14 switches in the manner shown in Figure 9(a) or Figure 9(b). Therefore, according to this embodiment, it is possible to reduce the peak value of the current consumed by the voltage generation circuit 14.

[0091] (Third embodiment) Figure 12 is a timing chart illustrating an example of the operation of the memory system according to the third embodiment.

[0092] Each memory cell in this embodiment may be an Erase cell or a Random cell. An Erase cell is a memory cell that has been erased and no data has been written to it since. A Random cell is a memory cell that has data written to it. For example, if data is erased from a block and then data is written to a page within that block, each memory cell on that page becomes a Random cell. On the other hand, if data is erased from a block and no data is written to any page within that block afterward, each memory cell on that block becomes an Erase cell.

[0093] Figure 12(a) shows the waveforms indicated by symbols A1' and B1' for the operation of a comparative example of this embodiment during the 1st Read. In Figure 12(a), symbol A1' indicates the voltage BIN for the unselected word line, and symbol B1' indicates the voltage VOUT for the unselected word line. In Figure 12(a), the unselected cell electrically connected to the unselected word line is the Erase cell.

[0094] Figure 12(b) also shows the waveforms indicated by symbols A1' and B1' regarding the operation of the comparative example of this embodiment during the 1st Read. In Figure 12(b), symbol A1' indicates the voltage BIN for the unselected word line, and symbol B1' indicates the voltage VOUT for the unselected word line. In Figure 12(b), the unselected cell electrically connected to the unselected word line is a Random cell.

[0095] In this comparative example, the waveform of the voltage BIN shown in Figure 12(b) is the same as the waveform of the voltage BIN shown in Figure 12(a). The voltage of the unselected word line on the Erase cell is often lower in the first half of the charging period, while the voltage of the unselected word line on the Random cell is often lower in the second half of the charging period. This is because the Erase cell is easily turned on, and the load is detected earlier, while the Random cell is difficult to turn on, and the load is detected later. Therefore, even though the waveform of the voltage BIN shown in Figure 12(b) is the same as the waveform of the voltage BIN shown in Figure 12(a), the waveform of the voltage VOUT shown in Figure 12(b) is different from the waveform of the voltage VOUT shown in Figure 12(a). For example, the voltage VOUT shown in Figure 12(a) is lower during the period indicated by the arrow in Figure 12(a), and the voltage VOUT shown in Figure 12(b) is lower during the period indicated by the arrow in Figure 12(b).

[0096] Figure 12(c) shows three current waveforms I(Ideal), I(Erase), and I(Random) relating to the operation of a comparative example of this embodiment during the 1st Read. These represent the time average of the current Icc. Waveform I(Ideal) shows the ideal current waveform. Waveform I(Erase) shows the current waveform when the unselected cells consist more of Erase cells than Random cells. Waveform I(Random) shows the current waveform when the unselected cells consist more of Random cells than Erase cells. Waveform I(Erase) shows a high peak in the first half of the charging period, and waveform I(Random) shows a high peak in the second half of the charging period.

[0097] Note that waveforms like I(Erase) also occur during the verify read operation (erase verify) performed during the erase operation. Also, waveforms like I(Random) occur during the verify read operation performed during the write operation. Write This also occurs during verification. Therefore, the following controls for erase cells are also applicable to erase verification operations, and the following controls for random cells are also applicable to write verification operations. In write verification, data is read from each memory cell to confirm whether the data has been correctly written to each memory cell. In erase verification, data is read from each memory cell to confirm whether the data has been correctly erased from each memory cell.

[0098] Figure 13 is a timing chart to further illustrate an example of the operation of the memory system according to the third embodiment.

[0099] Figure 13(a) shows the waveforms indicated by symbols A1 and B1 relating to the operation during the 1st Read in this embodiment. In Figure 13(a), symbol A1 indicates the voltage BIN for the unselected word line, and symbol B1 indicates the voltage VOUT for the unselected word line. The voltages BIN and VOUT shown in Figure 13(a) are used when charging the unselected word line on the Erase cell. The operation mode of the sequencer 14 in this case is an example of the first mode. For the reasons mentioned above, the voltages BIN and VOUT shown in Figure 13(a) may also be used when charging the unselected word line during erase verification.

[0100] Figure 13(b) also shows waveforms related to the operation during the 1st Read in this embodiment, indicated by symbols A1 and B1. In Figure 13(b), symbol A1 indicates the voltage BIN for the unselected word line, and symbol B1 indicates the voltage VOUT for the unselected word line. The voltages BIN and VOUT shown in Figure 13(b) are used when charging the unselected word line on the Random cell. The operation mode of the sequencer 14 in this case is an example of the second mode. For the reasons mentioned above, the voltages BIN and VOUT shown in Figure 13(b) may also be used when charging the unselected word line during write verification.

[0101] Figure 13(a) further shows the waveform A1 shown in Figure 13(b) as "A1b" for comparison with Figure 13(b). Similarly, Figure 13(b) further shows the waveform A1 shown in Figure 13(a) as "A1a" for comparison with Figure 13(a).

[0102] During the read operation, the PLC 14 of this embodiment controls the waveform of the voltage BIN for the unselected cell based on information that allows it to determine whether the unselected cell is an Erase cell or a Random cell. For example, if the PLC 14 obtains information that a certain unselected cell is an Erase cell, it controls the waveform of the voltage BIN for that unselected cell as shown in Figure 13(a). On the other hand, if the PLC 14 obtains information that a certain unselected cell is a Random cell, it controls the waveform of the voltage BIN for that unselected cell as shown in Figure 13(b).

[0103] The PLC 14 in this embodiment acquires write information managed by the memory controller 2 as information that can determine whether an unselected cell is an Erase cell or a Random cell. The write information indicates whether or not a write operation has been performed on each memory cell. Before starting to charge an unselected word line, the PLC 14 acquires write information regarding the unselected cell on that unselected word line from the memory controller 2. Based on this write information, the PLC 14 controls the waveform of the voltage BIN for that unselected word line as shown in Figure 13(a) or Figure 13(b). The write information is an example of write status information. The write information is sent from the memory controller 2 to the NAND memory 1 along with a read command, for example.

[0104] In this embodiment, the PLC 14 may acquire information other than write information as information that can determine whether an unselected cell is an Erase cell or a Random cell. For example, the PLC 14 may acquire information (pattern information) regarding the write patterns written in multiple memory cells from the memory controller 2. In this case, the PLC 14 controls the waveform of voltage BIN based on this pattern information as shown in Figure 13(a) or Figure 13(b). This write information is also an example of information indicating whether or not a cell has been written.

[0105] In this embodiment, the sequencer 14 sets the voltage BIN at the start of charging for the Random cell higher than the voltage BIN at the start of charging for the Erase cell. In Figures 13(a) and 13(b), the time on the Y axis represents the start of charging. In Figures 13(a) and 13(b), the voltage BIN at the start of charging for the Erase cell is V-2v, and the voltage BIN at the start of charging for the Random cell is V (V and v are positive real numbers).

[0106] The sequencer 14 in this embodiment further sets the timing at which the rise period of the voltage BIN for the Random cell increases from t to 2t to an earlier timing than the timing at which the rise period of the voltage BIN for the Erase cell increases from t to 2t. In Figures 13(a) and 13(b), the voltage rise value when the voltage BIN rises once is always v. Therefore, the timing at which the rise rate of the voltage BIN for the Random cell decreases from v / t to v / 2t is earlier than the timing at which the rise rate of the voltage BIN for the Erase cell decreases from v / t to v / 2t. The value "v / t" is an example of the first value, and the value "v / 2t" is an example of the second value. This is also true for the timing at which the rise period of the voltage BIN increases from 2t to 3t.

[0107] In Figure 13(a), at the point when time 5t has elapsed, i.e., when the voltage BIN rises from V+2v to V+3v, the period of rise of the voltage BIN increases from t to 2t, and the rate of rise of the voltage BIN decreases from v / t to v / 2t. In Figure 13(b), at the point when time 3t has elapsed, i.e., when the voltage BIN rises from V+2v to V+3v, the period of rise of the voltage BIN increases from t to 2t, and the rate of rise of the voltage BIN decreases from v / t to v / 2t.

[0108] As shown in Figure 13(a), lowering the voltage BIN during the period close to the start of charging makes it possible to reduce the current Icc during that period. This is because a lower voltage BIN improves the efficiency of the charge pump CP, and the load is high in the period close to the start of charging in an Erase cell. Furthermore, as shown in Figure 13(b), lowering the voltage BIN during the period close to the end of charging makes it possible to reduce the rate of increase in the voltage BIN and reduce the current Icc during that period. This is because a lower voltage BIN improves the efficiency of the charge pump CP, and the load is high in the period close to the end of charging in a Random cell. When the voltage VOUT becomes higher than the voltage BIN, there is a period when the charge pump CP stops, so reducing the rate of increase in the voltage BIN makes it possible to reduce the average value of the current Icc. This makes it possible to lower the peaks of both waveform I(Erase) and waveform I(Random), bringing waveform I(Erase) and waveform I(Random) closer to waveform I(Ideal).

[0109] Note that the voltage BIN waveforms shown in Figure 13(a) and Figure 13(b) differ from each other in terms of the height of the charging start voltage and the timing of the decrease in the rise period, but they may differ from each other in other respects. For example, these waveforms may differ from each other in terms of the voltage rise value when the voltage BIN rises. Furthermore, these waveforms may differ from each other in the manner shown in Figures 14(a) and 14(b), which will be described later.

[0110] Figure 14 is a timing chart to further illustrate an example of the operation of the memory system of the third embodiment.

[0111] Figure 14(a) shows waveforms, indicated by symbols A1 and B1, relating to the operation during the 1st Read in a modified example of this embodiment. In Figure 14(a), symbol A1 indicates the voltage BIN for the unselected word line, and symbol B1 indicates the voltage VOUT for the unselected word line. The voltages BIN and VOUT shown in Figure 14(a) are used when charging the unselected word line on the Erase cell. The operation mode of the sequencer 14 in this case is an example of the first mode. For the reasons mentioned above, the voltages BIN and VOUT shown in Figure 14(a) may also be used when charging the unselected word line during erase verification.

[0112] Figure 14(b) also shows waveforms indicated by symbols A1 and B1, relating to the operation during the 1st Read of a modified example of this embodiment. In Figure 14(b), symbol A1 indicates the voltage BIN for the unselected word line, and symbol B1 indicates the voltage VOUT for the unselected word line. The voltages BIN and VOUT shown in Figure 14(b) are used when charging the unselected word line on the Random cell. The operation mode of the sequencer 14 in this case is an example of the second mode. For the reasons mentioned above, the voltages BIN and VOUT shown in Figure 14(b) may also be used when charging the unselected word line during write verification.

[0113] Figure 14(a) further shows the waveform A1 shown in Figure 14(b) as "A1b" for comparison with Figure 14(b). Similarly, Figure 14(b) further shows the waveform A1 shown in Figure 14(a) as "A1a" for comparison with Figure 14(a).

[0114] The waveforms indicated by symbols A1 and B1 in Figure 14(a) are the same as the waveforms indicated by symbols A1 and B1 in Figure 13(a). On the other hand, the waveforms indicated by symbols A1 and B1 in Figure 14(b) are generally the same as the waveforms indicated by symbols A1 and B1 in Figure 13(b), but in the part indicated by arrow P, the waveform indicated by symbol A1 in Figure 14(b) differs from the waveform indicated by symbol A1 in Figure 13(b).

[0115] In this modified example, the sequencer 14 sets the rate of increase of the voltage BIN at the start of charging for the Random cell to be higher than the rate of increase of the voltage BIN at the start of charging for the Erase cell. Immediately after the start of charging in Figure 14(a), the voltage BIN rises from V-2v to Vv in time t, so the rate of increase of the voltage BIN at the start of charging in Figure 14(a) is v / t. On the other hand, immediately after the start of charging in Figure 14(b), the voltage BIN rises from V-2v to V in a very short time, so the rate of increase of the voltage BIN at the start of charging in Figure 14(b) is higher than v / t.

[0116] According to the voltage BIN shown in Figure 14(a), by lowering the rate of increase of the voltage BIN in the period near the start of charging and lowering the voltage BIN in the period near the end of charging, it is possible to reduce the current Icc in the period near the start of charging. This is because a lower voltage BIN improves the efficiency of the charge pump CP, and in erase cells, the load is large in the period near the start of charging. Also, according to the voltage BIN shown in Figure 14(b), by increasing the rate of increase of the voltage BIN in the period near the start of charging and lowering the voltage BIN in the period near the end of charging, it is possible to reduce the rate of increase of the voltage BIN and lower the current Icc in the period near the end of charging. This is because a lower voltage BIN improves the efficiency of the charge pump CP, and in random cells, the load is large in the period near the end of charging. When the voltage VOUT becomes higher than the voltage BIN, there is a period when the charge pump CP stops, so reducing the rate of increase of the voltage BIN makes it possible to reduce the average value of the current Icc. This makes it possible to lower the peaks of both waveform I(Erase) and waveform I(Random), bringing them closer to waveform I(Ideal).

[0117] As described above, the sequencer 14 of this embodiment controls the waveform of the voltage BIN for the unselected cell based on information that the unselected cell is an erase cell or a random cell during the read operation. Therefore, according to this embodiment, it is possible to reduce the peak value of the current consumed by the voltage generation circuit 14 regardless of whether the unselected cell is an erase cell or a random cell.

[0118] In the first to third embodiments, the control of the voltage BIN waveform performed by the sequencer 14 during a read operation was described. However, as mentioned above, this control during the read operation can also be applied to the verify read operation (write verify) performed during a write operation and the verify read operation (erase verify) performed during an erase operation.

[0119] When applying the control of the third embodiment to write verification, when writing data to the first word line of the target block, many memory cells within the target block are often erase cells. Therefore, write verification in this case may be performed using the method shown in Figure 13(a) or Figure 14(a). This is also true for writes to word lines that occur shortly after the first write. On the other hand, when writing data to the last word line of the target block, many memory cells within the target block are random cells. Therefore, write verification in this case may be performed using the method shown in Figure 13(b) or Figure 14(b). This is also true for writes to word lines that occur shortly before the last write.

[0120] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the apparatus described herein without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of Symbols]

[0121] 1: NAND memory, 2: Memory controller, 11: Memory cell array, 12: Command register, 13: Address register, 14: Sequencer, 15: Voltage generation circuit, 16: Low decoder module, 17: Sense amplifier module, 18: Temperature sensor

Claims

1. Multiple memory cell transistors, A word line electrically connected in common to the gates of two or more memory cell transistors among the plurality of memory cell transistors, The system includes a voltage generation circuit that generates a first voltage applied to the word line, As the aforementioned word line, A first word line electrically connected to the first memory cell transistor among the plurality of memory cell transistors, The plurality of memory cell transistors comprises a second word line electrically connected to the second memory cell transistor, The voltage generation circuit outputs different boost waveforms when boosting the first voltage during the erase-verify operation and the read operation, to the second word line electrically connected to the second memory cell transistor, which is not subject to the erase-verify operation and the read operation, when an erase-verify operation and a read operation are performed on the first memory cell transistor.

2. The semiconductor memory device according to claim 1, wherein, during the read operation, the voltage applied to the second word line is set to be higher than the voltage applied to the first word line.

3. The semiconductor memory device according to claim 1, further comprising the voltage generation circuit, which, when the erase verify operation and write verify operation are performed on the first memory cell transistor, outputs different boost waveforms when boosting the first voltage on the second word line electrically connected to the second memory cell transistor which is not subject to the erase verify operation and the write verify operation.

4. The semiconductor memory device according to claim 1, wherein the voltage generation circuit further outputs different boosted waveforms when boosting the first voltage depending on whether or not there is a write operation in at least one of the plurality of memory cell transistors.

5. Multiple memory cell transistors, A word line that is electrically connected in common to the gates of each of the aforementioned plurality of memory cell transistors, The system includes a voltage generation circuit that generates a first voltage applied to the word line, The voltage generation circuit outputs different boost waveforms when boosting the first voltage during erase / verify operation and read operation. The voltage generation circuit further outputs different boosted waveforms depending on whether or not there is a write operation in at least one of the plurality of memory cell transistors when boosting the first voltage. The voltage generation circuit increases the time width over which the average value of the first voltage remains constant from the first width to the second width at the first timing in the first mode, and increases it from the first width to the second width at the second timing, which is earlier than the first timing, in the second mode. Semiconductor memory device.

6. The semiconductor memory device according to claim 5, wherein the voltage generation circuit sets the average value of the boost start voltage of the first voltage to a first value in the first mode, and to a second value higher than the first value in the second mode.

7. The semiconductor memory device according to claim 5, wherein the voltage generation circuit sets the average value of the boost start voltage of the first voltage in the first mode and the average value of the boost start voltage of the first voltage in the second mode to the same value.

8. The semiconductor memory device according to claim 5, wherein the voltage generation circuit sets the time interval for which the average value of the first voltage is kept constant to a first value from the start of the first voltage boost in the first mode, and sets it to the first value after the start of the first voltage boost in the second mode.

9. The semiconductor memory device according to claim 5, wherein the voltage generation circuit obtains from a controller that controls the semiconductor memory device information that allows it to determine whether or not there is a write operation in at least one of the plurality of memory cell transistors.

10. Multiple memory cell transistors, A word line electrically connected in common to the gates of two or more memory cell transistors among the plurality of memory cell transistors, The system includes a voltage generation circuit that generates a first voltage applied to the word line, As the aforementioned word line, A first word line electrically connected to the first memory cell transistor among the plurality of memory cell transistors, The plurality of memory cell transistors comprises a second word line electrically connected to the second memory cell transistor, The voltage generation circuit, when a second read is performed on the first memory cell transistor after a first read, increases the first voltage applied to the second word line electrically connected to the second memory cell transistor which is not subject to the second read, such that the first voltage at the time of the second read changes in a different manner than the first voltage at the time of the first read, in a semiconductor memory device.

11. The semiconductor memory device according to claim 10, wherein, during the second read operation, the voltage applied to the second word line is set to be higher than the voltage applied to the first word line.

12. Multiple memory cell transistors, A word line that is electrically connected in common to the gates of each of the aforementioned plurality of memory cell transistors, The system includes a voltage generation circuit that generates a first voltage applied to the word line, The voltage generation circuit increases the first voltage such that, when increasing the first voltage, the first voltage at the time of the second readout performed after the first readout changes in a different manner than the first voltage at the time of the first readout. The voltage generation circuit is, The average value of the first voltage at the start of the boost for the second readout is set higher than the average value of the first voltage at the start of the boost for the first readout, or The boost rate of the average value of the first voltage at the time of the second readout is set to be higher than the boost rate of the average value of the first voltage at the time of the first readout, within a predetermined time from the start of the boosting, or The time interval during which the average value of the first voltage remains constant during the second readout is set to be shorter than the time interval during which the average value of the first voltage remains constant during the first readout, within a predetermined time from the start of the voltage boost, or The number of times the average value of the first voltage is increased during the second readout is set to be greater than the number of times the average value of the first voltage is increased during the first readout, within a predetermined time from the start of the voltage boost. Semiconductor memory device.

13. Multiple memory cell transistors, A word line electrically connected in common to the gates of two or more memory cell transistors among the plurality of memory cell transistors, The system includes a voltage generation circuit that generates a first voltage applied to the word line, As the aforementioned word line, A first word line electrically connected to the first memory cell transistor among the plurality of memory cell transistors, The plurality of memory cell transistors comprises a second word line electrically connected to the second memory cell transistor, The voltage generation circuit, when a read operation is performed on the first memory cell transistor, increases the first voltage applied to the second word line electrically connected to the second memory cell transistor which is not subject to the read operation, such that the first voltage after the state of the voltage generation circuit is switched changes in a manner different from the first voltage before the state of the voltage generation circuit is switched, or the circuit operates in accordance with a clock signal after the state of the voltage generation circuit is switched, which changes in a manner different from the clock signal before the state of the voltage generation circuit is switched.

14. The semiconductor memory device according to claim 13, wherein, during the read operation, the voltage applied to the second word line is set to be higher than the voltage applied to the first word line.

15. Multiple memory cell transistors, A word line that is electrically connected in common to the gates of each of the aforementioned plurality of memory cell transistors, The system includes a voltage generation circuit that generates a first voltage applied to the word line, The voltage generation circuit, when boosting the first voltage, boosts the first voltage such that the first voltage after the state of the voltage generation circuit is switched changes in a different manner than the first voltage before the state of the voltage generation circuit is switched, or the clock signal after the state of the voltage generation circuit is switched operates in accordance with a clock signal that changes in a different manner than the clock signal before the state of the voltage generation circuit is switched. The voltage generation circuit is, The time interval during which the average value of the first voltage remains constant after the state of the voltage generation circuit is switched is set to be longer than the time interval during which the average value of the first voltage remains constant before the state of the voltage generation circuit is switched, or The time interval during which the average value of the first voltage remains constant at or immediately after the state switching of the voltage generation circuit is set to be longer than the time interval during which the average value of the first voltage remains constant before and after the state switching of the voltage generation circuit, or The boost range of the average value of the first voltage at the time of the voltage generation circuit state switching or immediately thereafter is set to be shorter than the boost range of the average value of the first voltage before and after the voltage generation circuit state switching, or The frequency of the clock signal at the time of or immediately after the switching of the state of the voltage generation circuit is set to be smaller than the frequency of the clock signal of the first voltage before and after the switching of the state of the voltage generation circuit. Semiconductor memory device.

16. The semiconductor memory device according to claim 15, wherein the voltage generation circuit includes a plurality of charge pumps to which a second voltage is input, and at least one of the plurality of charge pumps generates the first voltage and outputs the first voltage.

17. The semiconductor memory device according to claim 16, wherein the plurality of charge pumps can be electrically connected to each other by series or parallel connection, and the state of the voltage generation circuit can be switched so as to change the connection state of the plurality of charge pumps.

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