Method for manufacturing a semiconductor substrate, and method for suppressing the introduction of dislocations into a semiconductor substrate and growth layer.

Abstract

The problem to be solved by the present invention is to provide novel technology capable of suppressing the introduction of displacement to a growth layer. The present invention, which solves the abovementioned problem, pertains to a method for manufacturing a semiconductor substrate, the method including: a processing step for removing a portion of a base substrate and forming a pattern that includes a minor angle; and a crystal growth step for forming a growth layer on the base substrate where the pattern has been formed. In addition, the present invention pertains to a method for suppressing the introduction of displacement to a growth layer, the method including a processing step for removing a portion of the base substrate and forming a pattern that includes a minor angle prior to forming the growth layer on the base substrate.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, and a method for suppressing the introduction of dislocations into a growth layer.

Background Art

[0002] Conventionally, in a method for manufacturing a semiconductor substrate, a semiconductor substrate made of a desired semiconductor material has been manufactured by crystal-growing (so-called epitaxial growth) a semiconductor material on a base substrate.

[0003] In the above epitaxial growth, it has been regarded as a problem that dislocations in the base substrate are inherited by the growth layer, thereby introducing dislocations into the growth layer.

[0004] In Patent Document 1, an invention is disclosed in which a groove is provided in a silicon carbide (SiC) substrate, which is an example of a base substrate, to perform crystal growth along a direction orthogonal to the c-axis direction, and to suppress the inheritance of through dislocations existing in the SiC substrate and propagating in the c-axis direction.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, it can be understood that the above invention has room for improvement from the viewpoint of suppressing the introduction of new dislocations that may occur in the joining of crystal growth surfaces proceeding along a direction orthogonal to the c-axis direction.

[0007] The problem to be solved by the present invention is to provide a novel technique capable of suppressing the introduction of dislocations into a growth layer.

Means for Solving the Problems

[0008] The present invention, which solves the above-mentioned problems, is a method for manufacturing a semiconductor substrate, comprising a processing step of removing a portion of a base substrate to form a pattern including a sub-angle, and a crystal growth step of forming a growth layer on the base substrate on which the pattern is formed.

[0009] Thus, the present invention can suppress the introduction of dislocations into the growth layer by performing crystal growth on a substrate having a pattern including inferior angles.

[0010] In a preferred embodiment of the present invention, the crystal growth step involves forming the growth layer by performing a zippering bond on the substrate. Thus, the present invention makes it possible to achieve a zippering bond that can suppress the introduction of new dislocations by performing crystal growth on a substrate having a pattern including inferior angles.

[0011] In a preferred embodiment of the present invention, the crystal growth step is performed to form the growth layer by performing crystal growth along the c-axis and crystal growth along the a-axis. In this way, the present invention makes it possible to form a region in the growth layer that does not inherit dislocations from the underlying substrate.

[0012] In a preferred embodiment of the present invention, the crystal growth step is a step of growth by physical gas-phase transport. Thus, the present invention can realize the formation of a growth layer based on raw material transport driven by a temperature gradient or chemical potential.

[0013] In a preferred embodiment of the present invention, the base substrate and the growth layer are made of different materials.

[0014] In a preferred embodiment of the present invention, the processing step includes a through-hole forming step of removing a portion of the underlying substrate to form through-holes, and a strain layer removal step of removing the strain layer introduced by the through-hole forming step. In this way, the present invention facilitates the formation of a temperature gradient in the a-axis direction, which serves as a driving force in crystal growth progressing along the a-axis direction.

[0015] In a preferred embodiment of the present invention, the through-hole formation step is a step of forming through-holes by irradiating the substrate with a laser. Thus, the present invention makes it possible to form a pattern including sub-angles based on processing of the substrate without machining.

[0016] In a preferred embodiment of the present invention, the strain layer removal step is a step of removing the strain layer of the underlying substrate by heat treatment. In this way, the present invention can reduce the defect density in patterns including inferior angles.

[0017] In a preferred embodiment of the present invention, the underlying substrate is silicon carbide, and the strain layer removal step is a step of etching the underlying substrate in a silicon atmosphere. In this way, the present invention can planarize the upper and side walls in patterns containing inferior angles.

[0018] In a preferred embodiment of the present invention, the pattern is a regular m-gon, where m is a natural number greater than 2.

[0019] In a preferred embodiment of the present invention, the pattern is a 4n-sided polygon, which contains a reference figure that is a regular n-sided polygon and includes n vertices included in the vertices of the pattern, and includes a first line segment extending from each of the n vertices, and a second line segment that does not extend from any of the n vertices but is adjacent to the first line segment, where n is a natural number greater than 2, and the angle between two adjacent first line segments in the pattern is constant and equal to the angle between two adjacent second line segments in the pattern. Thus, the present invention can adjust the probability of dislocation introduction into the growth layer in the substrate and the mechanical strength of the substrate based on angle settings.

[0020] In a preferred embodiment of the present invention, the pattern includes the centroid of the reference figure and a third line segment connecting the intersections of two adjacent second line segments.

[0021] The present invention is a method for suppressing the introduction of dislocations into a growth layer, including a processing step of removing a part of the underlying substrate to form a pattern including a defective corner before forming the growth layer on the underlying substrate.

Advantages of the Invention

[0022] According to the disclosed technology, it is possible to provide a novel technology capable of suppressing the introduction of dislocations into the growth layer.

[0023] Other problems, features, and advantages will become apparent when reading the embodiments for carrying out the invention described below, together with the drawings and the claims.

Brief Description of the Drawings

[0024] [Figure 1] It is an explanatory diagram for explaining the steps of a method for manufacturing a semiconductor substrate according to an embodiment. [Figure 2] It is an explanatory diagram for explaining the steps of a method for manufacturing a semiconductor substrate according to an embodiment. [Figure 3] It is an explanatory diagram for explaining a crystal growth step according to an embodiment. [Figure 4] It is an explanatory diagram of a pattern according to an embodiment. [Figure 5] It is an explanatory diagram of a pattern according to Example 1. [Figure 6] It is an explanatory diagram of a strain layer removal step according to Example 1. [Figure 7] It is an explanatory diagram of a crystal growth step according to Example 1. [Figure 8] It is a Raman spectroscopy measurement result of the growth layer 20 according to Example 1. [Figure 9] It is an observation image of the mesa part after KOH etching according to Example 1. [Figure 10] It is an observation image of the wing part after KOH etching according to Example 1. [Figure 11] It is an observation image of the underlying substrate 10 according to Example 2. [Figure 12] It is an observation image of the growth layer 20 after KOH etching according to Example 2. [Figure 13] This is an observation image of the substrate 10 used in the comparative example. [Figure 14] This is an observation image of the growth layer 20 after KOH etching in the comparative example. [Modes for carrying out the invention]

[0025] A preferred embodiment of the semiconductor substrate manufacturing method according to the present invention will be described in detail below with reference to the attached drawings.

[0026] The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and can be modified as appropriate within the scope described in the claims.

[0027] The drawings attached to this specification are conceptual diagrams, and the relative dimensions of each component are not intended to limit the present invention.

[0028] In this specification, for the purpose of describing the invention, the terms "upper" and "lower" may be used based on the orientation of the drawings, but this does not limit the meaning of "upper" or "lower" in relation to the usage of the semiconductor substrate of the present invention.

[0029] In the following description of the embodiments and the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0030] Method for manufacturing semiconductor substrates Figures 1 and 2 show the steps of the semiconductor substrate manufacturing method according to the embodiment.

[0031] The semiconductor substrate manufacturing method according to this embodiment includes a processing step S10 in which a portion of the base substrate 10 is removed to form a pattern 100 including a sub-angle, and a crystal growth step S20 in which a growth layer 20 is formed on the base substrate 10 on which the pattern 100 is formed.

[0032] Furthermore, the processing step S10 in this embodiment can be understood, for example, as a brittle processing step that reduces the strength of the base substrate 10.

[0033] Furthermore, this embodiment can be understood as a method for suppressing the introduction of dislocations into the growth layer 20 by including a processing step of removing a part of the base substrate 10 and forming a pattern including inferior angles before forming the growth layer 20 on the base substrate 10.

[0034] The following describes each step of the embodiment in detail.

[0035] <Processing process S10> Processing step S10 is a step in which a portion of the base substrate 10 is removed to form a pattern 100 that includes an inferior angle.

[0036] Furthermore, it can be understood that the processing step S10 is a step in which a part of the base substrate 10 is removed to form a pattern 100 which is a periodic arrangement pattern.

[0037] In this specification, "removing a portion of the substrate 10" refers to removing a portion of the substrate 10, including at least the surface layer, by the method described later.

[0038] In this specification, "subordinate angle" refers to an angle less than 180° that is either acute or obtuse. Furthermore, in the description herein, "pattern 100 including a subordinate angle" corresponds to pattern 100 in which at least one of the angles constituting pattern 100 is a subordinate angle.

[0039] In the processing step S10 according to this embodiment, a through hole 11 is formed in the base substrate 10, which facilitates the formation of a temperature gradient in the a-axis direction. This makes it possible to achieve crystal growth that proceeds along the a-axis direction, driven by the temperature gradient.

[0040] Furthermore, the processing step S10 may be configured to form a recess in place of or in addition to the through hole 11. In this case, the processing step S10 processes the surface of the base substrate 10 into a mesa shape.

[0041] As shown in Figure 2, the processing step S10 according to this embodiment includes a through-hole forming step S11 in which through-holes 11 are formed in the base substrate 10, and a strain layer removal step S12 in which the strain layer 12 introduced by the through-hole forming step S11 is removed.

[0042] The base substrate 10 can naturally be made of any material commonly used in the manufacture of semiconductor substrates.

[0043] The material of the base substrate 10 is, for example, a known Group IV material such as silicon (Si), germanium (Ge), or diamond (C).

[0044] Furthermore, the material of the base substrate 10 is, for example, a known group IV-IV compound material such as SiC.

[0045] Furthermore, the material of the substrate 10 is a known group II-VI compound material such as zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), and cadmium telluride (CdTe).

[0046] Furthermore, the material of the substrate 10 is, for example, a known III-V compound material such as boron nitride (BN), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb).

[0047] Furthermore, the material of the base substrate 10 is, for example, an oxide material such as aluminum oxide (Al2O3) or gallium oxide (Ga2O3).

[0048] Furthermore, the material of the base substrate 10 is, for example, a metallic material such as copper (Cu) or nickel (Ni).

[0049] Furthermore, the base substrate 10 may have a configuration in which known additive atoms used according to its material are appropriately added.

[0050] Furthermore, the base substrate 10 may be a wafer or substrate processed from a bulk crystal, and may be a substrate including a growth layer formed by epitaxial growth.

[0051] <Through hole formation step S11> The through-hole formation step S11 is a step in which a portion of the base substrate 10 is removed to form a through-hole 11. As an example of this through-hole formation step S11, a means of forming the through-hole 11 can be described as irradiating the base substrate 10 with a laser L.

[0052] In this process, the through-hole formation step S11 forms the through-hole 11 by scanning the focal point of the laser L from the surface (corresponding to the top surface) to the bottom surface (corresponding to the bottom surface) of the substrate 10.

[0053] Furthermore, in the through-hole formation step S11, the laser L is irradiated onto the substrate 10 while scanning the substrate 10 in the in-plane direction.

[0054] Furthermore, in the through-hole formation step S11, instead of irradiating the substrate 10 with a laser L, the irradiation of the substrate 10 with a known ion beam (corresponding to FIB processing) can be used as a means of forming through-holes 11 in the substrate 10.

[0055] At this time, the ion species of the ion beam are Ga + These can be appropriately selected from known ion species. In addition, in the through-hole formation step S11, the ion beam may be extracted from a known ion source such as a raw material gas or a liquid metal ion source while applying an appropriate acceleration voltage.

[0056] Furthermore, in the through-hole formation step S11, instead of irradiating the substrate 10 with a laser L, a known dry etching method such as Deep-RIE (equivalent to plasma etching) on ​​the substrate 10 with a hard mask can be used as a means to form through-holes 11 in the substrate 10.

[0057] At this time, the material of the hard mask is SiN x A suitable material can be selected from known materials such as SF6 depending on the material of the substrate 10. In this case, the etchant used in dry etching can be selected from known gases such as SF6 depending on the material of the substrate 10.

[0058] <Strained layer removal process S12> The strain layer removal step S12 is a step in which the strain layer 12 formed on the substrate 10 by the through-hole formation step S11 is removed.

[0059] Furthermore, the strain layer removal step S12 can employ a means of etching the substrate 10 by heat treatment of the substrate 10.

[0060] Furthermore, the strain layer removal step S12 can employ means capable of removing the strain layer 12.

[0061] Furthermore, the strain layer removal step S12 is preferably a step of removing the strain layer 12 by thermal etching.

[0062] It is desirable that the through-hole formation process S11 and the strain layer removal process S12 each employ methods suitable for the material of the substrate 10.

[0063] For example, if the base substrate 10 is SiC, it is desirable that the strain layer removal step S12 uses a method of etching the base substrate 10 in a silicon atmosphere (corresponding to a Si atmosphere).

[0064] Furthermore, for example, if the base substrate 10 is SiC, the strain layer removal step S12 may be configured to use a method of etching the base substrate 10 in a hydrogen atmosphere.

[0065] <Crystal growth process S20> The crystal growth process S20 is a process in which a growth layer 20 is formed on the base substrate 10 after the processing process S10.

[0066] The material of the growth layer 20 may be the same as the underlying substrate 10 (corresponding to homoepitaxial growth), or it may be a different material from the underlying substrate 10 (corresponding to heteroepitaxial growth).

[0067] The material of the growth layer 20 may generally be a material that is grown epitaxially.

[0068] Furthermore, the material of the growth layer 20 may be the material of the substrate 10, a known material that can be used as the material of the substrate 10, or a known material that can be epitaxially grown on the substrate 10.

[0069] The materials for the base substrate 10 and the growth layer 20 are, for example, SiC and AlN, respectively. In other words, the base substrate 10 is a SiC substrate. In other words, the growth layer 20 is an AlN layer.

[0070] Furthermore, the crystal growth step S20 is preferably a step in which the growth layer 20 is formed based on the Physical Vapor Transport (PVT) method.

[0071] In the crystal growth process S20, known vapor phase growth methods (corresponding to vapor phase epitaxial methods) such as PVT, sublimation recrystallization, modified Rayleigh process, and chemical vapor transport (CVT) can be employed as the growth method for the growth layer 20.

[0072] Furthermore, the crystal growth process S20 can employ Physical Vapor Deposition (PVD) instead of PVT. Also, the crystal growth process S20 can employ Chemical Vapor Deposition (CVD) instead of CVT.

[0073] Furthermore, in the crystal growth process S20, known liquid-phase growth methods (corresponding to liquid-phase epitaxial methods) such as the TSSG method (Top-Seeded Solution Growth method) and the Metastable Solvent Epitaxy (MSE) method can be employed as the growth method for the growth layer 20.

[0074] Furthermore, the crystal growth process S20 can employ the CZ method (Czochralski method) as the growth method for the growth layer 20.

[0075] In the crystal growth process S20, a growth method can be appropriately selected and adopted depending on the materials of the base substrate 10 and the growth layer 20.

[0076] As shown in Figure 3, the crystal growth process S20 according to this embodiment is a process of placing the base substrate 10 and the semiconductor material 40 which will be the raw material for the growth layer 20 opposite each other in a crucible 30 having a semi-closed space and heating them.

[0077] In this specification, "semi-closed space" refers to a space in which vacuum can be created inside the container, but in which at least a portion of the vapor generated inside the container can be contained.

[0078] By heating this crucible 30 (base substrate 10 and semiconductor material 40), the raw material is transported from the semiconductor material 40 onto the base substrate 10 via the raw material transport space 31.

[0079] Furthermore, in the crystal growth process S20, a temperature gradient can be used as the driving force for transporting raw materials between the substrate 10 and the semiconductor material 40.

[0080] In the crystal growth process S20, vapors consisting of atomic species sublimated from the semiconductor material 40 are transported by diffusion through the raw material transport space 31 and condense in a supersaturated state on the substrate 10, which is set to a temperature lower than that of the semiconductor material 40.

[0081] Furthermore, the crystal growth process S20 can employ the chemical potential difference between the substrate 10 and the semiconductor material 40 as the driving force.

[0082] In the crystal growth process S20, vapors consisting of atomic species sublimated from the semiconductor material 40 are transported by diffusion through the raw material transport space 31 and condense in a supersaturated state on the substrate 10, which has a lower chemical potential than the semiconductor material 40.

[0083] Furthermore, the crystal growth process S20 is a process in which a land portion 21 is formed by performing crystal growth along the c-axis direction from the base substrate 10 (corresponding to c-axis dominant growth), and a wing portion 22 is formed by performing crystal growth along the a-axis direction from the land portion 21 (corresponding to a-axis dominant growth), thereby forming the growth layer 20. Note that a-axis dominant growth may include crystal growth along the a-axis direction from the side surface of the through hole 11 or the side surface of the recess.

[0084] The growth layer 20 includes the land portion 21 and the wing portion 22. The through hole 11 or recess in this embodiment is located directly below the wing portion 22.

[0085] In this specification, "c-axis dominant growth" and "a-axis dominant growth" can be appropriately controlled based on the heating conditions in the crystal growth process S20.

[0086] The above heating conditions, for example, include temperature gradients in the c-axis direction and the a-axis direction, and may include their history. This history corresponds to the progression and changes in the temperature gradient during heating.

[0087] Furthermore, the above heating conditions may include, for example, the back pressure and partial pressure of an inert gas, including nitrogen gas, and may include their history. This history corresponds to the changes and transitions of the back pressure, etc., during heating.

[0088] Furthermore, the above heating conditions may include, for example, the heating temperature and its history. This history refers to the progression and changes in the heating temperature, etc., during heating.

[0089] Furthermore, the crystal growth process S20 may involve switching between c-axis dominant growth and a-axis dominant growth, for example, based on the conditions and methods described in D. Dojima, et al., Journal of Crystal Growth, 483, 206 (2018).

[0090] Furthermore, the crystal growth process S20 may adjust the doping concentration of the growth layer 20 using a doping gas. Alternatively, the crystal growth process S20 may adjust the doping concentration of the growth layer 20 by using a semiconductor material 40 with a different doping concentration than that of the substrate 10.

[0091] Furthermore, the crystal growth process S20 is a process in which a zippering bond is performed on the base substrate 10 to form the growth layer 20.

[0092] Furthermore, a zippering joint corresponds to a joint between crystal growth planes along a center line that equally divides the angle between two adjacent sides in pattern 100.

[0093] Here, we can understand that in zippering bonding, the bonding of the crystal growth surfaces gradually occurs from the point corresponding to the intersection of the two sides mentioned above.

[0094] Furthermore, in zippering bonding, for example, it can be understood that the area of ​​bonding between crystal growth planes gradually expands from the point where bonding is already occurring between crystal growth planes.

[0095] The crystal growth step S20 is preferably a step of forming a growth layer 20 using a base substrate 10 having a pattern 100 that causes zippering bonding.

[0096] Here, the pattern 100 that results in a zippering joint refers, for example, to a pattern 100 in which the angle θ is set so that the area 101a is large.

[0097] Figure 4 is an explanatory diagram illustrating pattern 100 according to an embodiment.

[0098] The line segment indicated by pattern 100 represents the base substrate 10. There is no limit to the width of the line segment.

[0099] Pattern 100 preferably includes a lower angle.

[0100] Furthermore, pattern 100 may be configured in which predetermined figures are arranged periodically. Also, pattern 100 may be configured in which the predetermined figures and figures obtained by inverting or rotating the predetermined figures are arranged.

[0101] Furthermore, pattern 100 includes, as an example, a regular m-sided polygon. In this case, m is a natural number greater than 2. For example, m is 3 or 6.

[0102] Furthermore, Pattern 100 includes, as an example, a regular hexagonal displacement pattern that is 3-fold symmetric. The term "regular hexagonal displacement pattern" as used in this specification will be explained in detail with reference to Figure 4.

[0103] A regular hexagonal displacement is a dodecagon. Furthermore, a regular hexagonal displacement is composed of 12 line segments of equal length that are straight lines.

[0104] Pattern 100, which exhibits a regular hexagonal displacement, contains a reference figure 101 which is an equilateral triangle with an area of ​​101a and includes three vertices 104. These three vertices 104 are included in the vertices of pattern 100. Here, it can be understood that these three vertices 104 may be located on line segments that constitute pattern 100.

[0105] Pattern 100 includes a line segment 102 (corresponding to the first line segment) that extends from vertex 104 and includes vertex 104, and a line segment 103 (corresponding to the second line segment) that does not extend from vertex 104, does not include vertex 104, and is adjacent to line segment 102.

[0106] Here, the angle θ between two adjacent line segments 102 in pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in pattern 100.

[0107] In this specification, the term "displaced regular hexagon" can be understood as a dodecagon formed when a regular hexagon is displaced (deformed) while maintaining its area, based on an angle θ that indicates the degree of unevenness.

[0108] The angle θ is preferably greater than 60°, preferably 66° or more, preferably 80° or more, preferably 83° or more, preferably 120° or more, preferably 150° or more, and preferably 155° or more.

[0109] Furthermore, the angle θ is preferably 180° or less, preferably 155° or less, preferably 150° or less, preferably 120° or less, preferably 83° or less, preferably 80° or less, and preferably 66° or less.

[0110] The pattern 100 in this embodiment may be configured as a regular dodecagonal displacement shape that is six times symmetric, instead of a regular hexagonal displacement shape that is three times symmetric.

[0111] A regular dodecagonal variant is a 24-sided polygon. Furthermore, a regular dodecagonal variant is composed of 24 line segments of equal length that are straight lines.

[0112] The pattern 100, which exhibits a regular dodecagonal displacement, is a regular hexagon with an area of ​​101a and contains a base figure 101 that includes six vertices 104. These six vertices 104 are included in the vertices of pattern 100. The area 101a of the regular hexagon may be equal to or different from the area 101a of the regular triangle.

[0113] Furthermore, similar to the regular hexagonal displacement pattern, the angle θ between two adjacent line segments 102 in pattern 100 of the regular dodecagonal displacement pattern is constant and equal to the angle θ between two adjacent line segments 103 in pattern 100.

[0114] In other words, the term "displaced regular dodecagon" in this specification can be understood as a 24-sided polygon formed by displacing (deforming) a regular dodecagon while maintaining its area, based on an angle θ that indicates the degree of unevenness.

[0115] Furthermore, pattern 100 exhibits a 2n-gon displacement type, which is a 4n-gon formed by the displacement (deformation) of a regular 2n-gon based on an angle θ indicating the degree of unevenness, while maintaining the area of ​​the regular 2n-gon.

[0116] In this case, the 2n-gon displacement can be understood as containing a regular n-gon (corresponding to the reference figure 101). Here, a regular n-gon can be understood as containing n vertices. Note that when the angle θ = 180°, the regular 2n-gon displacement exhibits the characteristics of a regular 2n-gon.

[0117] The pattern 100 according to this embodiment may include a configuration that includes a regular 2n-gon displacement type (including a regular hexagonal displacement type and a regular dodecagonal displacement type).

[0118] Furthermore, in addition to the line segments constituting the regular 2n-gon displacement figure, pattern 100 may further include at least one line segment (corresponding to the third line segment) connecting the centroid of the reference figure 101 and the intersection point of two adjacent line segments 103 in the regular 2n-gon displacement figure.

[0119] Furthermore, in addition to the line segments constituting the regular 2n-gon displacement figure, pattern 100 may further include at least one line segment connecting the vertices 104 constituting the reference figure 101 and the intersection points of two adjacent line segments 103 in the regular 2n-gon displacement figure.

[0120] Furthermore, in addition to the line segments that constitute the regular 2n-gon displacement shape, pattern 100 may further include at least one line segment that constitutes the reference figure 101 included in the regular 2n-gon displacement shape.

[0121] Furthermore, one embodiment of the present invention is a configuration in which the base substrate is silicon carbide (SiC). Furthermore, one embodiment of the present invention is a configuration in which the base substrate 10 is a SiC substrate and the growth layer 20 is an aluminum nitride growth layer. However, one embodiment of the present invention does not include a configuration in which the base substrate 10 is a SiC substrate and the growth layer 20 is an aluminum nitride growth layer.

[0122] The present invention will be described more specifically with reference to Example 1, Example 2, and Comparative Examples.

[0123] Example 1 shows an example in which a growth layer 20, which is an AlN layer, is formed on a base substrate 10, which is a SiC substrate. The base substrate 10 according to Example 1 has a pattern 100 that includes a sub-angle and the above-mentioned regular hexagonal deformation.

[0124] Example 2 shows an example in which a growth layer 20, which is an AlN layer, is formed on a base substrate 10, which is a SiC substrate. The base substrate 10 in Example 2 has a pattern 100 that includes a sub-angle and equilateral triangular deformation.

[0125] The comparative example shows an example in which a growth layer 20, which is an AlN layer, is formed on a base substrate 10, which is a SiC substrate. The base substrate 10 according to Example 2 has a pattern 100 that does not include inferior angles.

[0126] Example 1 The following describes Example 1 in detail.

[0127] <Processing process> The processing step S10 in Example 1 is a step of removing a portion of the base substrate 10 under the following conditions to form a pattern 100 that includes an inferior angle.

[0128] (Substrate 10) Semiconductor material: 4H-SiC Board size: 10mm wide x 10mm high x 524μm thick Growth aspect: Si-face Off-axis: on-axis

[0129] (Through hole formation step S11) The through-hole formation step S11 in Example 1 is a step of irradiating the base substrate 10 with a laser L to form a through-hole 11.

[0130] (Laser processing conditions) Wavelength: 532nm Output power: 3W / cm 2 Spot diameter: 40 μm

[0131] (Pattern details) Figure 5 is an explanatory diagram illustrating the pattern 100 of the through-holes 11 formed in the through-hole formation process S11 according to Example 1. The areas shown in black indicate the through-holes 11, and the areas shown in white remain as the base substrate 10.

[0132] Furthermore, the pattern 100 illustrated in Figure 5 can be understood as a regular hexagonal displacement shape with an angle θ = 80°, and including the intersection of two adjacent line segments 103 and the line segment connecting the centroid of the reference figure 101.

[0133] In this example, the pattern 100 has a width of approximately 100 μm.

[0134] (Strained layer removal process S12) The strain layer removal step S12 in Example 1 is a step of removing the strain layer 12 formed on the substrate 10 by the through-hole formation step S11 by thermal etching.

[0135] Figure 6 is an explanatory diagram illustrating the strain layer removal process S12 according to Example 1. In the strain layer removal process S12 according to Example 1, the base substrate 10 is placed in a SiC container 50, and then the SiC container 50 is placed in a TaC container 60 and heated.

[0136] (SiC container 50) Material: Polycrystalline SiC Container size: Diameter 60mm x Height 4mm Distance between the base substrate 10 and the bottom surface of the SiC container 50: 2 mm

[0137] (Details of SiC container 50) As shown in Figure 6, the SiC container 50 is a fitted container comprising an upper container 51 and a lower container 52 that can be fitted together.

[0138] A minute gap 53 is formed in the fitting portion between the upper container 51 and the lower container 52, and this gap 53 is configured to allow exhaust (vacuuming) of the SiC container 50.

[0139] The SiC container 50 has an etching space 54 formed by aligning a portion of the SiC container 50, which is located on the lower temperature side of the temperature gradient, with the base substrate 10, which is located on the higher temperature side of the temperature gradient.

[0140] The etching space 54 is a space in which Si atoms and C atoms are transported from the substrate 10 to the SiC container 50 and etched, using the temperature difference between the substrate 10 and the bottom surface of the SiC container 50 as the driving force.

[0141] Furthermore, the SiC container 50 has a substrate holder 55 that holds the base substrate 10 in a hollow state to form an etching space 54.

[0142] Furthermore, depending on the direction of the temperature gradient of the heating furnace, the SiC container 50 may not require the substrate holder 55.

[0143] For example, if the SiC container 50 is configured such that the heating furnace creates a temperature gradient from the lower container 52 to the upper container 51, the substrate holder 55 may be omitted, and the base substrate 10 may be placed on the bottom surface of the lower container 52.

[0144] (TaC container 60) Material: TaC Container size: Diameter 160mm x Height 60mm Si vapor supply source 64 (Si compound): TaSi2

[0145] (Details of TaC container 60) The TaC container 60, like the SiC container 50, is a fitted container comprising an upper container 61 and a lower container 62 that can be fitted together, and is configured to accommodate the SiC container 50.

[0146] A small gap 63 is formed in the fitting portion between the upper container 61 and the lower container 62, and this gap 63 is configured to allow exhaust (vacuuming) of the TaC container 60.

[0147] The TaC container 60 has a Si vapor supply source 64 that can supply the vapor pressure of gaseous species containing Si element into the TaC container 60.

[0148] The Si vapor supply source 64 should be configured to generate vapor pressure of gaseous species containing Si element within the TaC container 60 during the heating process.

[0149] (Heating conditions) The base substrate 10, which was arranged under the conditions described above, was heat-treated under the following conditions. Heating temperature: 1800℃ Etching amount: 8 μm Furthermore, in the strain layer removal process S12, the heating time and temperature gradient are set appropriately to achieve the following etching amounts.

[0150] <Crystal growth process S20> The crystal growth step S20 in Example 1 is a step of forming a growth layer 20 on the substrate 10 after the processing step S10.

[0151] Figure 7 is an explanatory diagram illustrating the crystal growth process S20 according to Example 1. The crystal growth process S20 according to Example 1 is a process of placing the base substrate 10 in a crucible 30 and heating it in opposition to the semiconductor material 40.

[0152] (crucible 30) Material: TaC Container size: 10mm x 10mm x 1.5mm Distance between substrate 10 and semiconductor material 40: 1 mm

[0153] (Details of Crucible 30) The crucible 30 has a raw material transport space 31 between the base substrate 10 and the semiconductor material 40. Raw materials are transported from the semiconductor material 40 onto the base substrate 10 through this raw material transport space 31.

[0154] Figure 7(a) shows an example of a crucible 30 used in the crystal growth process S20. This crucible 30 is a fitted container that, like the SiC container 50 and the TaC container 60, comprises an upper container 32 and a lower container 33 that can be fitted together. A minute gap 34 is formed in the fitting portion between the upper container 32 and the lower container 33, and the crucible 30 is configured to be able to be evacuated (vacuumed) through this gap 34.

[0155] Furthermore, the crucible 30 has a substrate holder 35 that forms a raw material transport space 31. This substrate holder 35 is provided between the base substrate 10 and the semiconductor material 40, with the semiconductor material 40 on the high-temperature side and the base substrate 10 on the low-temperature side to form the raw material transport space 31.

[0156] Figures 7(b) and 7(c) show other examples of the crucible 30 used in the crystal growth process S20. The temperature gradient in Figures 7(b) and 7(c) is set in the opposite direction to the temperature gradient in Figure 7(a), with the substrate 10 positioned on the upper side. That is, similar to Figure 7(a), the semiconductor material 40 is positioned on the high-temperature side and the substrate 10 on the low-temperature side to form the raw material transport space 31.

[0157] Figure 7(b) shows an example in which a raw material transport space 31 is formed between the semiconductor material 40 and the substrate 10 by fixing the substrate 10 to the upper container 32.

[0158] Figure 7(c) shows an example in which a raw material transport space 31 is formed between the semiconductor material 40 and the upper container 32 by forming a through-window and placing the base substrate 10 therein. Alternatively, as shown in Figure 7(c), the raw material transport space 31 may be formed by providing an intermediate member 36 between the upper container 32 and the lower container 33.

[0159] Furthermore, the material of crucible 30 may be a high-melting-point material such as W (tungsten) instead of TaC.

[0160] (Semiconductor materials 40) Material: AlN sintered body Size: 20mm (width) x 20mm (height) x 5mm (thickness)

[0161] (Details of semiconductor material 40) The AlN sintered body of semiconductor material 40 was fabricated using the following procedure.

[0162] First, in Example 1, AlN powder was placed inside a frame of a TaC block. Next, in Example 1, an external force was mechanically applied to the AlN powder, causing it to be compacted. Then, in Example 1, the compacted AlN powder and the TaC block were placed in a pyrolysis carbon crucible and heated under the following conditions.

[0163] In the crystal growth process S20, the base substrate 10 and semiconductor material 40 were placed in the crucible 30 and heated under the following heating conditions.

[0164] (Heating conditions) Heating temperature: 2040℃ Heating time: 70h Growth thickness: 500 μm Temperature gradient: 6.7K / mm N2 gas pressure: 10kPa

[0165] Figure 8 shows the full width at half maximum (FWHM) of the E2 peak obtained by Raman spectroscopy for the growth layer 20 formed under the above conditions.

[0166] According to Figure 8, it can be seen that a poorly crystalline AlN layer is formed in the land portion 21, and a well-crystalline AlN layer is formed in the wing portion 22. Furthermore, it can be seen that the land portion 21 corresponds to the line segment of pattern 100.

[0167] Figure 9 shows an SEM image of the surface of the land portion 21 of the growth layer 20 formed under the above conditions, with dislocations exposed by the etch-pit method. This etch-pit method was performed based on KOH wet etching.

[0168] According to Figure 9, the land portion 21 in Example 1 is 1.5 × 10 8 cm -2 It can be understood that it has a dislocation density (corresponding to the etch pit density).

[0169] Figure 10 shows an SEM image of the surface of the wing portion 22 of the growth layer 20 formed under the above conditions, with dislocations of the wing portion 22 exposed by the etch pit method described above. The etch pit method was performed based on KOH wet etching.

[0170] According to Figure 10, the wing portion 22 in Example 1 is 1.2 × 10 6 cm -2 It can be understood that it has a dislocation density (corresponding to the etch pit density).

[0171] According to Figures 9 and 10, it can be seen that the introduction of dislocations to the wing portion 22 is suppressed during the formation of the growth layer 20 on the substrate 10.

[0172] Example 2 The following describes Example 2 in detail. Note that this specification omits descriptions of configurations and conditions common to Example 1 and other embodiments.

[0173] The base substrate 10 in Example 2 has recesses instead of through holes 11.

[0174] The pattern 100 according to Example 2 includes an equilateral triangle. Here, the line segments constituting the pattern 100 have a width of approximately 60 μm.

[0175] Figure 11 shows an SEM image of the substrate 10 after processing step S10 according to Example 2.

[0176] In the crystal growth process S20, the base substrate 10 and semiconductor material 40 were placed in the crucible 30 and heated under the following heating conditions.

[0177] (Heating conditions) Heating temperature: 1840℃ N2 gas pressure: 50kPa

[0178] Figure 12 shows an observation image obtained by SEM observation of the surface of the growth layer 20 formed under the above conditions, where dislocations of the growth layer 20 were exposed by the etch pit method. This etch pit method was performed based on KOH wet etching.

[0179] As shown in Figure 12, it can be seen that the introduction of dislocations to the wing portion 22 is suppressed during the formation of the growth layer 20 on the substrate 10 having a pattern 100 including a sub-angle.

[0180] Comparative Example The comparative examples will be described in detail below. Note that this specification omits descriptions of configurations and conditions common to Example 1 and the embodiments.

[0181] The base substrate 10 in the comparative example has recesses instead of through holes 11, similar to Example 2.

[0182] The pattern 100 in the comparative example does not contain any inferior angles or intersections. The line segments constituting pattern 100 in the comparative example are parallel to each other. Here, the line segments constituting pattern 100 have a width of approximately 60 μm.

[0183] Figure 13 shows an SEM image of the substrate 10 after processing step S10 according to the comparative example.

[0184] In the crystal growth process S20, the base substrate 10 and semiconductor material 40 were placed in the crucible 30 and heated under the following heating conditions.

[0185] (Heating conditions) Heating temperature: 1840℃ N2 gas pressure: 50kPa

[0186] Figure 14 shows an observation image obtained by SEM observation of the surface of the growth layer 20 formed under the above conditions, where dislocations of the growth layer 20 were exposed by the etch pit method. This etch pit method was performed based on KOH wet etching.

[0187] As shown in Figure 14, in the formation of the growth layer 20 on the substrate 10 having a pattern 100 that does not contain inferior angles, it can be seen that the introduction of dislocations to the wing portion 22 occurs particularly in the central portion of the wing portion 22 in Figure 14 (corresponding to the junction of the crystal growth surface).

[0188] Furthermore, according to Figures 12 and 14, it can be seen that the dislocation density in the bonding region of the crystal growth surface in the blade portion 22 of Example 2 (corresponding to the central region of the blade portion 22 in Figures 12 and 14) is kept lower compared to Comparative Example 1.

[0189] In the a-axis dominant growth shown in Figure 12, the joining of the crystal growth planes in the formation of the growth layer 20 was carried out in a zippering manner, which suppressed the introduction of new dislocations caused by the joining of the crystal growth planes.

[0190] According to the present invention, the introduction of dislocations into the growth layer 20 can be suppressed by including a processing step S10 in which a part of the base substrate 10 is removed to form a pattern 100 including a sub-angle, and a crystal growth step S20 in which a growth layer 20 is formed on the base substrate 10 on which the pattern 100 is formed.

[0191] 10 Substrate 11 Through hole 12 Strain layer 20 growth layer 21 Land Department 22 Wings 30 Crucible 31 Raw material transportation space 40 Semiconductor Materials 50 SiC container 60 TaC container S10 Processing process S11 Through-hole formation process S12 Strained layer removal process S20 Crystal growth process

Claims

1. The process includes a processing step of removing a portion of the underlying substrate to form a pattern including an inferior angle, and a crystal growth step of forming a growth layer on the underlying substrate on which the pattern has been formed. The growth layer is a crystal having a c-axis, The aforementioned crystal growth process is a process in which crystals are grown using a physical gas phase transport method. The crystal growth step is a method for manufacturing a semiconductor substrate in which the growth layer is formed by performing crystal growth along the c-axis and crystal growth along the a-axis.

2. The process includes a processing step of removing a portion of the underlying substrate to form a pattern including an inferior angle, and a crystal growth step of forming a growth layer on the underlying substrate on which the pattern has been formed. The growth layer is a crystal having a c-axis, The above-mentioned processing step is a method for manufacturing a semiconductor substrate, comprising a through-hole forming step of removing a portion of the underlying substrate to form through-holes, and a strain layer removal step of removing the strain layer introduced by the through-hole forming step.

3. The method for manufacturing a semiconductor substrate according to claim 2, wherein the through-hole formation step is a step of forming a through-hole by irradiating the underlying substrate with a laser.

4. The method for manufacturing a semiconductor substrate according to claim 2 or 3, wherein the strain layer removal step is a step of removing the strain layer of the underlying substrate by heat treatment.

5. A method for manufacturing a semiconductor substrate according to any one of claims 2 to 4, wherein the underlying substrate is silicon carbide, and the strain layer removal step is a step of etching the underlying substrate in a silicon atmosphere.

6. The process includes a processing step of removing a portion of the underlying substrate to form a pattern including an inferior angle, and a crystal growth step of forming a growth layer on the underlying substrate on which the pattern has been formed. The growth layer is a crystal having a c-axis, A method for manufacturing a semiconductor substrate, wherein the pattern includes a 4n-sided polygon, contains a reference figure which is a regular n-sided polygon and includes n vertices included in the vertices of the pattern, includes a first line segment extending from each of the n vertices, and a second line segment which does not extend from any of the n vertices but is adjacent to the first line segment, where n is a natural number greater than 2, the angle between two adjacent first line segments in the pattern is constant, and equal to the angle between two adjacent second line segments in the pattern.

7. The method for manufacturing a semiconductor substrate according to claim 6, wherein the pattern includes the centroid of the reference figure and a third line segment connecting the intersection points of two adjacent second line segments.

8. The method for manufacturing a semiconductor substrate according to any one of claims 2 to 7, wherein the crystal growth step involves performing crystal growth along the c-axis and crystal growth along the a-axis to form the growth layer.

9. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 8, wherein the base substrate and the growth layer are made of different materials.

10. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 9, wherein the pattern includes a regular m-gon, and m is a natural number greater than 2.

11. The process includes a step of removing a portion of the underlying substrate and forming a pattern including an inferior angle before forming a growth layer on the underlying substrate, The growth layer is a crystal having a c-axis, The processing step is a method for suppressing the introduction of dislocations into a growth layer, comprising a through-hole forming step of removing a portion of the underlying substrate to form through-holes, and a strain layer removal step of removing the strain layer introduced by the through-hole forming step.

12. The process includes a step of removing a portion of the underlying substrate and forming a pattern including an inferior angle before forming a growth layer on the underlying substrate, The growth layer is a crystal having a c-axis, The pattern includes a 4n-sided polygon and contains a reference figure which is a regular n-sided polygon and includes n vertices included in the vertices of the pattern, and includes a first line segment extending from each of the n vertices, and a second line segment which does not extend from any of the n vertices but is adjacent to the first line segment, where n is a natural number greater than 2, the angle between two adjacent first line segments in the pattern is constant, and a method for suppressing the introduction of dislocations into a growth layer which is equal to the angle between two adjacent second line segments in the pattern.

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