Display device and method for manufacturing the same

Abstract

According to the present invention, a TFT layer (20a) on a resin substrate (10) has a polysilicon semiconductor layer (12) formed from a polysilicon film. In conductor regions (12b, 12c), first TFTs (9aa) electrically connected to each other via a source line (18f) are provided corresponding to a plurality of sub-pixels (P) that constitute a display region (D). A transparent back gate layer (BGa), which is formed from an oxide semiconductor film and has a conductive portion (BGac) obtained by making at least a portion thereof conductive, is provided in a lower layer of the TFT layer (20a). The conductive portion (BGac) overlaps at least a channel region (12a) in a plane view, and is electrically connected to the source line (18f).

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the same.

Background Art

[0002] In recent years, as a display device replacing a liquid crystal display device, a self-emitting organic EL display device using an organic electroluminescence (hereinafter also referred to as "EL") element has been attracting attention. In an organic EL display device, for example, a flexible organic EL display device including a TFT layer in which a plurality of thin film transistors (hereinafter also referred to as "TFTs") for driving an organic EL element are formed for each sub pixel constituting a display region is proposed on a resin substrate having flexibility as a base substrate. Here, as a semiconductor layer constituting the TFT, for example, a polysilicon semiconductor layer made of polysilicon having high mobility, an oxide semiconductor layer made of an oxide semiconductor such as In-Ga-Zn-O having a small leakage current, etc. are well known.

[0003] Here, in a flexible organic EL display device, a TFT including a polysilicon semiconductor layer (hereinafter also referred to as "polysilicon TFT"), particularly a polysilicon TFT having a top gate structure in which a gate electrode is formed on an upper layer of the polysilicon semiconductor layer, may have unstable threshold (Vth) characteristics due to polarization of the resin substrate. In order to stabilize the threshold of the polysilicon TFT, it is known to form a metal film or the like with an inorganic film interposed therebetween under the polysilicon TFT and use this metal film as a back gate. For example, in the display device described in Patent Document 1, an additional film for suppressing a change in characteristics due to intrusion of light from the back surface of the channel or imparting a back gate effect is disposed below a polysilicon TFT (switching element).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] However, in flexible organic EL display devices, a high panel aperture ratio (transmittance) is required when placing fingerprint sensors, cameras, etc., beneath the panel. However, metal films and additional films with light-shielding properties to suppress changes in characteristics due to light penetration, as described in Patent Document 1, are unsuitable as materials for the back gate because they reduce panel transmittance.

[0006] The present invention has been made in view of the above, and its objective is to achieve both stabilization of the threshold and maintenance of panel transmittance for a TFT comprising a polysilicon semiconductor layer provided on a base substrate, particularly a resin substrate. [Means for solving the problem]

[0007] To achieve the above objective, the present invention provides a display device comprising a base substrate and a thin-film transistor layer provided on the base substrate, wherein the thin-film transistor layer has a polysilicon semiconductor layer formed of a polysilicon film, with defined channel regions and conductor regions, and a plurality of thin-film transistors electrically connected to each other via signal wiring in the conductor region are provided corresponding to a plurality of subpixels constituting a display region, and a transparent back gate layer is provided below the thin-film transistor layer, which has a conductorized portion formed of an oxide semiconductor film, wherein at least a portion of the oxide semiconductor film is made conductor, and the conductorized portion overlaps with the channel region in a plan view and is electrically connected to the signal wiring.

[0008] A method for manufacturing a display device according to the present invention comprises a base substrate and a thin-film transistor layer provided on the base substrate, wherein the thin-film transistor layer has a polysilicon semiconductor layer formed of a polysilicon film with defined channel regions and conductor regions, and a plurality of thin-film transistors electrically connected to each other via signal wiring in the conductor region are provided corresponding to a plurality of subpixels constituting a display region, and a transparent back gate layer is provided below the thin-film transistor layer, which is formed of an oxide semiconductor film and has a conductor portion in which at least a part of the oxide semiconductor film is made conductor, and the thin-film transistor layer formation step for forming the thin-film transistor layer comprises a first base coat film formation step for forming a first base coat film on the base substrate, a back gate layer formation step for forming the oxide semiconductor film on the substrate surface on which the first base coat film is formed, and then patterning the oxide semiconductor film to form the back gate layer, a second base coat film formation step for forming a second base coat film on the substrate surface on which the back gate layer is formed, and the second base coat film A polysilicon semiconductor layer formation step involves forming the polysilicon film on the substrate surface, then patterning the polysilicon film to form the polysilicon semiconductor layer; a gate insulating film formation step involves forming a gate insulating film on the substrate surface on which the polysilicon semiconductor layer is formed so as to cover the polysilicon semiconductor layer; a gate electrode formation step involves forming a lower metal film on the substrate surface on which the gate insulating film is formed, then patterning the lower metal film to form a plurality of gate electrodes; a doping step involves doping each of the gate electrodes as a mask to form the channel region and the conductor region of the polysilicon semiconductor layer; an interlayer insulating film formation step involves forming at least one interlayer insulating film on the substrate surface on which the plurality of gate electrodes are formed; a contact hole formation step involves forming contact holes on the substrate surface on which the at least one interlayer insulating film is formed, exposing at least a portion of the conductor region in the polysilicon semiconductor layer and the conductor portion in the back gate layer; and after forming the upper metal film on the substrate surface on which the contact holes are formed, the upper metal film is patterned.The method comprises a signal wiring formation step of forming the signal wiring that covers the exposed surface of the conductive portion exposed within the contact hole, wherein in the second base coat film formation step, heat treatment after the formation of the second base coat film makes at least the region overlapping with the channel region in a plan view of the back gate layer conductive to form the conductive portion, and in the signal wiring formation step, the conductive portion and the signal wiring are electrically connected. [Effects of the Invention]

[0009] According to the present invention, it is possible to achieve both stabilization of the threshold and maintenance of panel transmittance for a TFT comprising a polysilicon semiconductor layer provided on a base substrate, particularly a resin substrate. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a plan view showing a schematic configuration of an organic EL display device according to the first embodiment of the present invention. [Figure 2] Figure 2 is a plan view of the display area of ​​an organic EL display device according to the first embodiment of the present invention. [Figure 3] Figure 3 is an equivalent circuit diagram showing the pixel circuit of an organic EL display device according to the first embodiment of the present invention. [Figure 4] Figure 4 is a schematic plan view illustrating the arrangement of the pixel circuits of an organic EL display device according to the first embodiment of the present invention. [Figure 5] Figure 5 is an enlarged plan view of the area within the dashed line in Figure 4, showing the first TFT constituting the pixel circuit of an organic EL display device according to the first embodiment of the present invention. [Figure 6] Figure 6 is an enlarged plan view within the dashed-dotted line in Figure 4, showing a modified example of the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention, and corresponds to Figure 5. [Figure 7] Figure 7 is an enlarged plan view within the dashed-dotted line in Figure 4, showing a modified example of the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention, and corresponds to Figure 5. [Figure 8] FIG. 8 is a cross-sectional view of a display area and a frame area of an organic EL display device according to a first embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view of a display area and a frame area of an organic EL display device according to a second embodiment of the present invention, and is a figure corresponding to FIG. 8. [Figure 11] FIG. 11 is a cross-sectional view of a display area and a frame area of an organic EL display device according to a third embodiment of the present invention, and is a figure corresponding to FIG. 8. [Figure 12] FIG. 12 is a schematic plan view schematically showing an arrangement of pixel circuits of an organic EL display device according to a fourth embodiment of the present invention, and is a figure corresponding to FIG. 4. [Figure 13] FIG. 13 is an enlarged plan view within a two-dot chain line in FIG. 12, showing a first TFT constituting a pixel circuit of an organic EL display device according to a fourth embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view of a display area of an organic EL display device according to a fourth embodiment of the present invention taken along line XIV-XIV in FIG. 13. [Figure 15] FIG. 15 is an enlarged plan view within a two-dot chain line in FIG. 12, showing a first TFT constituting a pixel circuit of an organic EL display device according to a fifth embodiment of the present invention. [Figure 16] FIG. 16 is a cross-sectional view of a display area of an organic EL display device according to a fifth embodiment of the present invention taken along line XVI-XVI in FIG. 15.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. Note that the present invention is not limited to the following embodiments.

[0012] 《First Embodiment》 Figures 1 to 9 show a first embodiment of a display device according to the present invention. In each of the following embodiments, an organic EL display device including an organic EL element is exemplified as a display device including a light-emitting element. Here, FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a of the present embodiment. FIG. 2 is a plan view of a display area D of the organic EL display device 50a. FIG. 3 is an equivalent circuit diagram showing a pixel circuit C of the organic EL display device 50a. FIG. 4 is a schematic plan view schematically showing an arrangement of pixel circuits C of the organic EL display device 50a. FIG. 5 is an enlarged plan view within a two-dot chain line in FIG. 4 showing a first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a. FIG. 6 is an enlarged plan view within a two-dot chain line in FIG. 4 showing a modified example of the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a, and is a figure corresponding to FIG. 5. FIG. 7 is an enlarged plan view within a two-dot chain line in FIG. 4 showing a modified example of the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a, and is a figure corresponding to FIG. 5. FIG. 8 is a cross-sectional view of the display area D and a frame area F of the organic EL display device 50a. FIG. 9 is a cross-sectional view showing an organic EL layer 23 constituting the organic EL display device 50a. In FIGS. 5 to 7, the upper layer of the gate electrode 14a is omitted.

[0013] As shown in FIG. 1, the organic EL display device 50a includes, for example, a display area D for performing image display provided in a rectangular shape, and a frame area F provided in a frame shape around the display area D. In the present embodiment, a rectangular display area D is exemplified, but this rectangular shape includes, for example, a substantially rectangular shape such as a shape with an arc-shaped side, a shape with an arc-shaped corner, or a shape with a notch in a part of the side.

[0014] In the display area D, as shown in Figure 2, multiple subpixels P are arranged in a matrix. Furthermore, in the display area D, as shown in Figure 2, for example, subpixels P having a red light-emitting region Lr for displaying red, subpixels P having a green light-emitting region Lg for displaying green, and subpixels P having a blue light-emitting region Lb for displaying blue are arranged adjacent to each other. In the display area D, for example, one pixel is composed of three adjacent subpixels P having a red light-emitting region Lr, a green light-emitting region Lg, and a blue light-emitting region Lb. The arrangement of the subpixels P is not particularly limited and examples include pentile arrangements and stripe arrangements.

[0015] A terminal section T is provided at one end of the frame area F (the right end in Figure 1) so as to extend in one direction (the vertical direction in Figure 1). Also, as shown in Figure 1, a bendable section B is provided in the frame area F between the terminal section T and the display area D, so as to extend in one direction (the vertical direction in Figure 1) and can be bent, for example, 180° (in a U-shape) with the vertical direction in Figure 1 as the axis of bending.

[0016] As shown in Figure 8, the organic EL display device 50a comprises a flexible resin substrate 10 provided as a base substrate and a TFT layer 20a provided on the resin substrate 10.

[0017] The resin substrate 10 is made of an organic resin material such as polyimide resin. The base substrate is not limited to the resin substrate 10, but may be, for example, a glass substrate.

[0018] In the TFT layer 20a, each sub-pixel P is provided with a pixel circuit C consisting of a first TFT 9aa, a second TFT 9b, and a capacitor 9c, as shown in Figure 3. As shown in Figure 4, the pixel circuits C are arranged in a matrix corresponding to each sub-pixel P. The black circles (●) in Figures 3 and 4 indicate nodes.

[0019] As shown in Figure 8, the TFT layer 20a comprises a first base coat film 11a and a second base coat film 11b provided on the resin substrate 10, a plurality of first TFTs 9aa, a plurality of second TFTs 9b (see Figure 3), and a plurality of capacitors 9c (see Figure 3) provided on the second base coat film 11b for each subpixel P, and a planarization film 19 provided on each first TFT 9aa, each second TFT 9b, and each capacitor 9c. Here, as shown in Figures 2 to 4, the TFT layer 20a is provided with a plurality of gate lines 14 as signal wiring so as to extend parallel to each other in the horizontal direction in the figures. Also, as shown in Figures 2 to 4, the TFT layer 20a is provided with a plurality of source lines 18f as signal wiring so as to extend parallel to each other in the vertical direction in the figures, in a direction that intersects (orthogonal to) the plurality of gate lines 14. Each power line 18g is positioned adjacent to each source line 18f, as shown in Figure 2. Each source line 18f is connected to, for example, the source driver SD, as shown in Figure 4.

[0020] Furthermore, in the TFT layer 20a, as shown in Figure 8, a first base coat film 11a and a second base coat film 11b, a semiconductor film that forms a semiconductor layer, a gate insulating film 13, a first metal film (lower metal film) that forms a first wiring layer such as a gate line 14 (see also Figures 2 to 4), a gate electrode 14a, and a lower conductive layer, a first interlayer insulating film 15, a second metal film that forms a second wiring layer such as an upper conductive layer, a second interlayer insulating film 17, a third metal film (upper metal film) that forms a third wiring layer such as a source line 18f (see also Figures 2 to 4), a source electrode 18a, a drain electrode 18b, and a power line 18g, and a planarization film 19 are sequentially laminated on the resin substrate 10.

[0021] The first base coat film 11a, the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are composed of single-layer or multilayer films of inorganic insulating films such as silicon nitride (SiNx (where x is a positive number)), silicon oxide (SiO2), and silicon oxynitride (SiON). In particular, the first base coat film 11a is preferably composed of a multilayer film such as SiNx (upper layer) / SiO2 (lower layer). The second base coat film 11b is preferably composed of a multilayer film such as SiO2 (upper layer) / SiNx (lower layer).

[0022] The first, second, and third metal films are composed of, for example, single-layer metal films such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and tungsten (W), or multilayer metal films such as Mo (top layer) / Al (middle layer) / Mo (bottom layer), Ti / Al / Ti, Al (top layer) / Ti (bottom layer), Cu / Mo, and Cu / Ti.

[0023] As shown in Figure 3, the first TFT9aa is electrically connected to the corresponding gate line 14 and source line 18f (signal wiring) at each subpixel P. Furthermore, as shown in Figure 8, the first TFT9aa comprises a polysilicon semiconductor layer 12 (first semiconductor layer), a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and a source electrode 18a and a drain electrode 18b, which are sequentially provided on the second base coat film 11b. In other words, the first TFT9aa can be described as a top-gate type polysilicon TFT.

[0024] The polysilicon semiconductor layer 12 is composed of a low-temperature polysilicon film, such as LTPS (low-temperature polysilicon). As shown in Figure 8, the polysilicon semiconductor layer 12 is provided on the second base coat film 11b in an island-like shape in plan view. The polysilicon semiconductor layer 12 is doped with impurity ions and partially made conductive. As a result, the polysilicon semiconductor layer 12 has a source region 12b and a drain region 12c defined to be spaced apart from each other as conductive regions, and a channel region 12a defined between the source region 12b and the drain region 12c. Multiple first TFTs 9aa are electrically connected in the source region 12b and the drain region 12c via corresponding gate lines 14 and source lines 18f (signal lines).

[0025] As shown in Figure 8, the gate insulating film 13 is provided so as to cover the polysilicon semiconductor layer 12.

[0026] As shown in Figure 8, the gate electrode 14a (first wiring layer) is provided on the gate insulating film 13 so as to overlap with the channel region 12a of the polysilicon semiconductor layer 12. The gate electrode 14a is configured to control the conductivity between the source region 12b and the drain region 12c of the polysilicon semiconductor layer 12. The gate electrode 14a is formed of a first metal film.

[0027] As shown in Figure 8, the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in order to cover the gate electrode 14a.

[0028] As shown in Figure 8, the source electrode 18a and the drain electrode 18b (third wiring layer) are provided spaced apart from each other on the second interlayer insulating film 17. Furthermore, as shown in Figure 8, the source electrode 18a and the drain electrode 18b are electrically connected to the source region 12b and the drain region 12c of the polysilicon semiconductor layer 12, respectively, via contact holes Ha and Hb formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. The source electrode 18a and the drain electrode 18b are formed from a third metal film.

[0029] In the organic EL display device 50a, as shown in Figures 4 to 8, a back gate layer BGa is provided below the first TFT 9aa that constitutes the TFT layer 20a. Specifically, the back gate layer BGa is provided between the first base coat film 11a and the second base coat film 11b that constitute the first TFT 9aa. The back gate layer BGa may be provided in the display area D and the bezel area F so as to cover the entire surface of the TFT layer 20a, or it may be provided only in the area necessary for the conductive part BGac, which will be described later. The thickness of the back gate layer BGa is, for example, about 10 to 100 nm.

[0030] The back gate layer BGa is composed of the aforementioned In-Ga-Zn-O oxide semiconductor film and is transparent. Therefore, even when a fingerprint sensor, camera, etc., are placed beneath the panel (display area D) of the organic EL display device 50a, the influence of the back gate layer BGa (and its conductive portion BGac) on the panel transmittance is small, and the panel transmittance is not easily reduced.

[0031] In-Ga-Zn-O oxide semiconductors are ternary oxides of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited. Furthermore, In-Ga-Zn-O semiconductors may be amorphous or crystalline. As for crystalline In-Ga-Zn-O semiconductors, crystalline In-Ga-Zn-O semiconductors in which the c-axis is oriented generally perpendicular to the layer plane are preferred. In addition, other oxide semiconductors may be included instead of In-Ga-Zn-O semiconductors. Other oxide semiconductors may include, for example, In-Sn-Zn-O semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). Here, In-Sn-Zn-O semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, InGaO3(ZnO)5, and magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x It may also contain elements such as ZnO. Furthermore, as the Zn-O semiconductor, amorphous, polycrystalline, microcrystalline, or unimpeded ZnO can be used, with one or more impurity elements from Group 1, Group 13, Group 14, Group 15, and Group 17 added.

[0032] Furthermore, as shown in Figures 4 to 8, the back gate layer BGa has a conductive portion BGac in which the oxide semiconductor film is made conductive. The conductive portion BGac can be called a transparent conductive layer. Note that at least a part of the back gate layer BGa may be the conductive portion BGac, or the entire back gate layer BGa may be the conductive portion BGac.

[0033] As shown in Figure 4, the conductive portion BGac (back gate layer BGa) is provided integrally (in a strip shape) in a plan view, along the direction in which the source line 18f (signal wiring) extends, and spanning multiple sub-pixels P (the pixel circuits C that constitute them).

[0034] In the organic EL display device 50a, the conductive portion BGac overlaps with the channel region 12a of the polysilicon semiconductor layer 12 constituting the first TFT 9aa in a plan view, as shown in Figure 8. Note that the conductive portion BGac only needs to overlap with the channel region 12a of the polysilicon semiconductor layer 12 in a plan view. For example, as shown in Figures 5 and 6, in a plan view, the back gate layer BGa and its conductive portion BGac (dot portion in the figure) may be arranged in a mesh pattern corresponding to the pattern shape of the polysilicon semiconductor layer 12. In this case, the conductive portion BGac may be formed on at least a part of the mesh pattern of the back gate layer BGa (see Figure 5), or on the entire pattern (see Figure 6). On the other hand, as shown in Figure 7, in a plan view, the back gate layer BGa and its conductive portion BGac may be arranged to cover the entire sub-pixel P (the pixel circuit C that constitutes it). In this case as well, the conductive portion BGac may be formed on at least a part of the pattern of the back gate layer BGa, or it may be formed on the entire pattern (see Figure 7).

[0035] The first TFT 9aa configured as described above may include, for example, p-channel type TFTs such as a writing TFT, a driving TFT, a power supply TFT, and a light emission control TFT. The writing TFT is configured to apply the voltage of the source line 18f to one terminal electrode of the driving TFT (hereinafter referred to as the "first terminal electrode") according to the selection of the gate line 14. The driving TFT is configured to apply a driving current to one terminal electrode of the light emission control TFT according to the voltage applied between its gate electrode and the first terminal electrode. Here, the driving TFT is configured to control the current of the organic EL element 25, which will be described later. The power supply TFT is configured to apply the voltage of the power line 18g to the first terminal electrode of the driving TFT. The light emission control TFT is configured to apply the above driving current to the organic EL element 25. Among these, it is preferable that the first TFT 9aa is a driving TFT. In other words, since the driving TFT affects the brightness of the organic EL element 25, it is preferable that the driving TFT be composed of a first TFT 9aa equipped with a back gate layer BGa having a conductive portion BGac. Note that the writing TFT, power supply TFT, and light emission control TFT other than the driving TFT are switching TFTs, and therefore may or may not be equipped with a back gate layer BGa.

[0036] As shown in Figure 3, the second TFT9b is electrically connected to the corresponding first TFT9aa and power line 18g at each subpixel P. The second TFT9b also comprises a second semiconductor layer, a gate insulating film 13, a gate electrode, a first interlayer insulating film 15, a second interlayer insulating film 17, and source and drain electrodes, and has the same structure as the first TFT9aa described above. The second semiconductor layer is formed from, for example, a low-temperature polysilicon film or an In-Ga-Zn-O based oxide semiconductor film. The In-Ga-Zn-O based oxide semiconductor used is the same as the In-Ga-Zn-O based oxide semiconductor described above.

[0037] The second TFT 9b configured as described above may include, for example, n-channel type TFTs such as an initialization TFT, a compensation TFT, and an anode discharge TFT. The initialization TFT is configured to initialize the voltage applied to the gate electrode of the driving TFT. The compensation TFT is configured to compensate the threshold voltage of the driving TFT by putting it into a diode connection state according to the selection of the gate line 14. The anode discharge TFT is configured to reset the charge accumulated on the first electrode 21 of the organic EL element 25, which will be described later, according to the selection of the gate line 14. The initialization TFT, compensation TFT, and anode discharge TFT are switching TFTs, and may or may not have a back gate layer BGa.

[0038] In this embodiment, top-gate type first TFT9aa and second TFT9b are exemplified, but the first TFT9aa and second TFT9b may be bottom-gate type TFTs. The first TFT9aa is preferably a top-gate type TFT.

[0039] As shown in Figure 3, the capacitor 9c is electrically connected to the corresponding first TFT 9aa and power line 18g in each sub-pixel P. Here, the capacitor 9c comprises, for example, a lower conductive layer (first wiring layer) formed of a first metal film, a first interlayer insulating film 15 provided to cover the lower conductive layer, and an upper conductive layer (second wiring layer) formed of a second metal film provided on the first interlayer insulating film 15 so as to overlap with the lower conductive layer. The upper conductive layer 16 is electrically connected to the power line 18g, for example, through a contact hole formed in the second interlayer insulating film 17.

[0040] In the organic EL display device 50a, as shown in Figure 8, the back gate layer BGa and its conductive portion BGac are arranged not only in the area where multiple subpixels P are arranged in the display area D (hereinafter also referred to as the "active area"), but also in the frame area F.

[0041] In the organic EL display device 50a, the conductive portion BGac is electrically connected to the source line 18f (signal wiring) in the area of ​​the frame region F where subpixels P are not located (hereinafter also referred to as the "inactive region"), as shown in Figures 4 and 8. Specifically, as shown in Figure 8, the conductive portion BGac and the source line 18f are electrically connected via contact holes Hf formed in the laminated film of the second base coat film 11b, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17, which is provided between the conductive portion BGac and the source line 18f as at least one layer of inorganic insulating film. As a result, the conductive portion BGac is fixed at the potential of the source line 18f.

[0042] Incidentally, in a flexible organic EL display device equipped with a back gate separated by an inorganic insulating film (base coat film) beneath a top-gate type polysilicon TFT, conventional display devices in which the back gate and potential-fixing wiring (signal wiring) are electrically connected via contact holes formed in the inorganic insulating film within the pixel circuit C (active region) have the disadvantage that the threshold characteristics of the TFT are unstable due to impurities from the resin substrate directly beneath the back gate. This is thought to be because, due to the presence of contact holes near the TFT, hydrogen atoms generated from the base coat film due to the opening of the contact holes adhere to the channel portion of the TFT.

[0043] In contrast, in the organic EL display device 50a, the conductive portion BGac in the back gate layer BGa and the source line 18f are electrically connected via the contact hole Hf outside the pixel circuit C (inactive region), making the above-mentioned problems less likely to occur.

[0044] The planarized film 19 has a flat surface in the display area D and is composed of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0045] As shown in Figure 8, the organic EL display device 50a includes an organic EL element layer 31 provided as a light-emitting layer constituting the display area D, as an upper layer of the TFT layer 20a, and a sealing film 35 provided on the organic EL element layer 31.

[0046] As shown in Figure 8, the organic EL element layer 31 comprises multiple organic EL elements 25, which are multiple light-emitting elements arranged in a matrix corresponding to multiple subpixels P.

[0047] As shown in Figure 8, the organic EL element 25 comprises a plurality of first electrodes 21 arranged sequentially on the planarization film 19, a plurality of organic EL layers 23 provided on each subpixel P on the first electrodes 21, and a second electrode 24 provided on the organic EL layer 23 in common to the plurality of subpixels P. Furthermore, as shown in Figure 8, the organic EL element 25 is covered with a sealing film 35.

[0048] As shown in Figure 8, the first electrode 21 is arranged in a matrix on the planarization film 19 to correspond to a plurality of subpixels P. Furthermore, as shown in Figure 8, each first electrode 21 is electrically connected to the drain electrode 18d (or source electrode 18c) of each second TFT 9b via a contact hole formed in the planarization film 19. The first electrode 21 also has the function of injecting holes into the organic EL layer 23. In order to improve the hole injection efficiency into the organic EL layer 23, it is more preferable to form the first electrode 21 from a material with a high work function. Here, examples of materials that constitute the first electrode 21 include metallic materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Furthermore, the material that constitutes the first electrode 21 may be an alloy such as astatine (At) / astatine oxide (AtO2). In addition, the material that constitutes the first electrode 21 may be a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Furthermore, the first electrode 21 may be formed by stacking multiple layers made of the above material. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0049] The peripheral edge of the first electrode 21 is covered by an edge cover 22 that is provided in a grid pattern common to multiple subpixels P. Examples of materials that make up the edge cover 22 include positive-type photosensitive resin materials such as polyimide resin, acrylic resin, polysiloxane resin, and novolac resin, or polysiloxane-based SOG materials. A portion of the surface of the edge cover 22 protrudes upward in the figure and forms island-like pixel photospacers, as shown in Figure 8.

[0050] As shown in Figure 8, the organic EL layer 23 is arranged on each first electrode 21 and is provided in a matrix shape to correspond to multiple subpixels P. Here, as shown in Figure 9, each organic EL layer 23 comprises a hole injection layer 1, a hole transport layer 2, an emissive layer 3, an electron transport layer 4, and an electron injection layer 5, which are provided in order on the first electrode 21.

[0051] The hole injection layer 1, also called the anode buffer layer, has the function of bringing the energy levels of the first electrode 21 and the organic EL layer 23 closer together, thereby improving the hole injection efficiency from the first electrode 21 to the organic EL layer 23. Examples of materials that constitute the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0052] The hole transport layer 2 has the function of improving the efficiency of hole transport from the first electrode 21 to the organic EL layer 23. Examples of materials that constitute the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, zinc selenide, and the like.

[0053] The light-emitting layer 3 is a region in which holes and electrons are injected from the first electrode 21 and the second electrode 24, respectively, when a voltage is applied by the first electrode 21 and the second electrode 24, and where holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminescence efficiency. Examples of materials constituting the light-emitting layer 3 include metal oxynoide compounds [8-hydroxyquinoline metal complex], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzthiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0054] The electron transport layer 4 has the function of efficiently transporting electrons to the light-emitting layer 3. Examples of materials that make up the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxynoide compounds.

[0055] The electron injection layer 5 has the function of bringing the energy levels of the second electrode 24 and the organic EL layer 23 closer together, thereby improving the efficiency of electron injection from the second electrode 24 to the organic EL layer 23. This function allows the driving voltage of the organic EL element 25 to be lowered. The electron injection layer 5 is also called the cathode buffer layer. Examples of materials that make up the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), as well as aluminum oxide (Al2O3) and strontium oxide (SrO).

[0056] As shown in Figure 8, the second electrode 24 is provided so as to cover each organic EL layer 23 and edge cover 22. The second electrode 24 also has the function of injecting electrons into the organic EL layer 23. Furthermore, in order to improve the electron injection efficiency into the organic EL layer 23, it is more preferable that the second electrode 24 be made of a material with a small work function. Examples of materials that make up the second electrode 24 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), lithium fluoride (LiF), etc. Furthermore, the second electrode 24 may be formed from an alloy such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Alternatively, the second electrode 24 may be formed from a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Furthermore, the second electrode 24 may be formed by stacking multiple layers made of the above materials. Examples of materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0057] As shown in FIG. 8, the sealing film 35 includes a first sealing inorganic insulating film 32 provided to cover the second electrode 24, a sealing organic film 33 provided on the first sealing inorganic insulating film 32, and a second sealing inorganic insulating film 34 provided to cover the sealing organic film 33, and has a function of protecting the organic EL layer 23 from moisture, oxygen, etc. Here, the first sealing inorganic insulating film 32 and the second sealing inorganic insulating film 34 are made of inorganic materials such as silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (SiNx (x is a positive number)) such as trisilicon tetranitride (Si3N4), silicon carbonitride (SiCN), etc. The sealing organic film 33 is made of an organic material such as an acrylic resin, a polyurea resin, a parylene resin, a polyimide resin, a polyamide resin, etc.

[0058] In the above-described organic EL display device 50a, in each sub-pixel P, by inputting a gate signal to the first TFT 9aa via the gate line 14, the first TFT 9aa is turned on, and a data signal is written to the gate electrode of the second TFT 9b and the capacitor 9c via the source line 18f. When a current from the power supply line 18g corresponding to the gate voltage of the second TFT 9b is supplied to the organic EL layer 23, the light-emitting layer 3 of the organic EL layer 23 emits light to perform image display. In the organic EL display device 50a, even when the first TFT 9aa is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that the light emission by the light-emitting layer 3 is maintained until the gate signal of the next frame is input.

[0059] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. The method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer formation step.

[0060] <TFT Layer Formation Step> The TFT layer formation process is a process for forming a TFT layer 20a and comprises a first base coat film formation process, a back gate layer formation process, a second base coat film formation process, a polysilicon semiconductor layer formation process, a gate insulating film formation process, a gate electrode formation process, a doping process, an interlayer insulating film formation process, a contact hole formation process, and a signal wiring formation process.

[0061] (First base coat film formation process) First, a first base coat film 11a is formed on a resin substrate 10 formed on a glass substrate by sequentially depositing a silicon oxide film (approximately 250 nm thick) and a silicon nitride film (approximately 50 nm thick) on the resin substrate 10, for example, by plasma CVD (Chemical Vapor Deposition), thereby forming a laminated film such as SiNx (upper layer) / SiO2 (lower layer).

[0062] (Back gate layer formation process) On the substrate surface on which the first base coat film 11a is formed, an oxide semiconductor film made of an oxide semiconductor such as an InGaZnO4 film (approximately 30 nm thick) is deposited, for example, by sputtering, and then the oxide semiconductor film is patterned. This forms a strip-shaped back gate layer BGa that extends parallel to the direction in which the source line 18f, formed in a subsequent process, extends.

[0063] (Second base coat film formation process) On the substrate surface on which a back gate layer BGa is formed, a silicon nitride film (approximately 50 nm thick) and a silicon oxide film (approximately 250 nm thick) are sequentially deposited, for example, by plasma CVD, to form a second base coat film 11b composed of a laminated film such as SiO2 (upper layer) / SiNx (lower layer).

[0064] In the manufacturing method of the organic EL display device 50a, a portion of the back gate layer BGa is made conductive by heat treatment after the formation of the second base coat film 11b, thereby forming a conductive portion BGac. Specifically, in the back gate layer BGa, the conductive portion BGac is formed in a region of the polysilicon semiconductor layer 12 formed in a subsequent process that overlaps with the channel region 12a in a plan view.

[0065] (Polysilicon semiconductor layer formation process) An amorphous silicon film (approximately 50 nm thick) is deposited on the substrate surface on which the second base coat film 11b is formed, for example by plasma CVD. The amorphous silicon film is then crystallized by laser annealing or the like to form a polysilicon film made of polysilicon, and then the polysilicon film is patterned to form a polysilicon semiconductor layer 12.

[0066] (Gate insulating film formation process) A silicon oxide film (approximately 100 nm thick) is deposited on the substrate surface on which the polysilicon semiconductor layer 12 is formed, for example by plasma CVD. Then, the silicon oxide film is patterned to cover the polysilicon semiconductor layer, thereby forming the gate insulating film 13.

[0067] (Gate Socket Formation Process) On the substrate surface on which the gate insulating film 13 is formed, a first metal film (lower metal film), such as a molybdenum film (about 200 nm thick), is deposited, for example, by sputtering. Then, the first metal film is patterned to form a first wiring layer, such as a gate electrode 14a and a gate wire 14.

[0068] (Doping process) By using the gate electrode 14a as a mask and doping the polysilicon semiconductor layer 12 with impurity ions, a portion of the polysilicon semiconductor layer 12 is made conductive, thereby forming a source region 12b, a drain region 12c, and a channel region 12a in the polysilicon semiconductor layer 12.

[0069] (Interlayer insulating film formation process) At least one interlayer insulating film is formed on the substrate surface on which the gate electrode 14a is formed (the substrate surface on which a portion of the polysilicon semiconductor layer 12 is made conductive). A first interlayer insulating film 15 is formed on the substrate surface by sequentially depositing a silicon nitride film (approximately 150 nm thick) and a silicon oxide film (approximately 100 nm thick) by, for example, plasma CVD. Subsequently, a second interlayer insulating film 17 is formed on the substrate surface on which the first interlayer insulating film 15 is formed by depositing a silicon oxide film (approximately 100 nm thick) by, for example, plasma CVD.

[0070] (Contact hole formation process) In the display area D (active area) of the substrate surface on which the second interlayer insulating film 17 is formed, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are appropriately patterned, for example by dry etching, to form contact holes Ha and Hb that expose at least a portion of the surface of the source area 12b and drain area 12c of the polysilicon semiconductor layer 12. Furthermore, in the frame area F (inactive area) of the substrate surface, the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are appropriately patterned, for example by dry etching, to form contact holes Hf that expose at least a portion of the surface of the conductive portion BGac of the back gate layer BGa.

[0071] (Signal wiring formation process) On the substrate surface where the above-mentioned contact holes Ha, Hb, and Hf are formed, a third metal film (upper metal film) is formed by sequentially depositing, for example, a titanium film (approximately 50 nm thick), an aluminum film (approximately 400 nm thick), and a titanium film (approximately 200 nm thick) by sputtering. Then, the third metal film is patterned to form a third wiring layer, such as a source wire 18f, a source electrode 18a, a drain electrode 18b, and a power line 18g.

[0072] Thus, in the manufacturing method of the organic EL display device 50a, the conductive part BGac and the source line 18f are electrically connected in the signal wiring formation step.

[0073] <Other processes in the TFT layer formation process> The TFT layer formation process may optionally include a second wiring layer formation process, a planarization film formation process, etc.

[0074] (Second wiring layer formation process) On the surface of the substrate on which the first interlayer insulating film 15 is formed in the interlayer insulating film formation process, for example, by sputtering, a second metal film such as a molybdenum film (about 200 nm thick) is formed, and then the second metal film is patterned to form a second wiring layer such as an upper conductive layer.

[0075] (Planarization film formation process) On the surface of the substrate on which the source line 18f etc. are formed, for example, by spin coating or slit coating, an acrylic photosensitive resin film (about 2 μm thick) is applied, and then pre-baking, exposure, development, and post-baking are performed on the applied film to form a planarization film 19.

[0076] Also, the manufacturing method of the organic EL display device 50a includes an organic EL element layer formation process and a sealing film formation process.

[0077] <Organic EL element layer formation process> On the planarization film 19 of the TFT layer 20a formed in the TFT layer formation process, using a well-known method, a first electrode 21, an edge cover 22, an organic EL layer 23 (hole injection layer 1, hole transport layer 2, light-emitting layer 3, electron transport layer 4, electron injection layer 5), and a second electrode 24 are formed to form an organic EL element 25 and form an organic EL element layer 31.

[0078] <Sealing film formation process> First, on the substrate surface on which the organic EL element layer 31 formed in the organic EL element layer formation process is formed, an inorganic insulating film such as a silicon nitride film, silicon oxide film, or silicon oxynitride film is deposited by plasma CVD using a CMM as a deposition mask to cover each organic EL element 25, thereby forming a first sealing inorganic insulating film 32. Next, an organic resin material such as acrylic resin is deposited on the first sealing inorganic insulating film 32 by, for example, an inkjet method to form a sealing organic film 33. Then, an inorganic insulating film such as a silicon nitride film, silicon oxide film, or silicon oxynitride film is deposited by plasma CVD using a CMM as a deposition mask to cover the sealing organic film 33, thereby forming a second sealing inorganic insulating film 34 and thus forming a sealing film 35. Through the above steps, a sealing film 35 can be formed in which the first sealing inorganic insulating film 32, the sealing organic film 33, and the second sealing inorganic insulating film 34 are sequentially stacked in the display area D.

[0079] Finally, after attaching a protective sheet (not shown) to the substrate surface, the glass substrate is peeled off the bottom surface of the resin substrate 10 by irradiating the resin substrate 10 with laser light from the glass substrate side, and a protective sheet (not shown) is attached to the bottom surface of the resin substrate 10 from which the glass substrate has been peeled off. In this manner, the organic EL display device 50a can be manufactured.

[0080] <Effects> As described above, the following effects can be obtained with the organic EL display device 50a of this embodiment. In the organic EL display device 50a, a back gate layer BGa having a conductive portion BGac is provided between the resin substrate 10 and a TFT layer 20a on which a top gate type first TFT 9aa (polysilicon TFT) comprising a polysilicon semiconductor layer 12 is provided corresponding to a plurality of sub-pixels P, separated by a second base coat film 11b. The conductive portion BGac is integrally provided so as to span a plurality of sub-pixels P (the pixel circuits C constituting them) along the direction in which the source line 18f (signal wiring) extends in a plan view, and has at least a channel regionBecause it overlaps with 12a in a plan view and is electrically connected to the source line 18f, the threshold (Vth) shift caused by the polarization of the resin substrate 10 is suppressed for the first TFT 9aa, and the threshold characteristics are stabilized. Furthermore, in the organic EL display device 50a, the back gate layer BGa is composed of a transparent oxide semiconductor film, and the conductive portion BGac is composed of an oxide semiconductor layer in which at least a part is made conductive, thus ensuring panel transmittance. Thus, the organic EL display device 50a makes it possible to achieve both stabilization of the threshold of the TFT (especially the top-gate type polysilicon TFT) and maintenance of panel transmittance. In addition, in the organic EL display device 50a, the conductive part BGac and the source line 18f are electrically connected via the contact hole Hf outside the pixel circuit C (inactive region), so hydrogen atoms generated from the first base coat film 11a form channels region Adhesion to 12a is suppressed, and the threshold characteristics of the first TFT 9aa become even more stable.

[0081] 《Second Embodiment》 Next, a second embodiment of the present invention will be described using Figure 10. Figure 10 is a cross-sectional view of the display area D and the frame area F of the organic EL display device 50b of this embodiment, and corresponds to Figure 8. The overall configuration of the organic EL display device 50b is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20b, so a detailed explanation will be omitted here. Also, the same reference numerals are used for components that are the same as those in the first embodiment, and their descriptions will be omitted.

[0082] In the organic EL display device 50b, as shown in Figure 10, an island-shaped metal layer M is provided in a plan view between the lower end of the contact hole Hf and the conductive portion BGac in the frame region F (inactive region). The metal layer M is positioned between the back gate layer BGa and the second base coat film 11b. As a result, the conductive portion BGac and the source line 18f are electrically connected via the metal layer M.

[0083] The metal layer M, like the first metal film, second metal film, third metal film, etc., is composed of a single metal film such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), or a multilayer metal film such as Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, Cu / Ti.

[0084] The organic EL display device 50b can be constructed by adding the following metal layer formation step to the TFT layer formation step of the organic EL display device 50a described above, after the back gate layer formation step and before the second base coat film formation step.

[0085] (Metal layer formation process) After forming the above-mentioned metal film on the substrate surface on which the back gate layer BGa is formed, for example by sputtering, the metal film is patterned to form a metal layer M.

[0086] <Effects> According to the organic EL display device 50b described above, in addition to the effects of the organic EL display device 50a mentioned above, the following effects can be obtained. In the organic EL display device 50b, a metal layer M is provided between the conductive portion BGac and the second base coat film 11b in the frame region F (inactive region), specifically the region that overlaps in a plan view with the contact hole Hf that electrically connects the conductive portion BGac and the source line 18f. This metal layer M prevents the conductive portion BGac from penetrating when forming the contact hole Hf.

[0087] 《Third Embodiment》 Next, a third embodiment of the present invention will be described using Figure 11. Figure 11 is a cross-sectional view of the display area D and the frame area F of the organic EL display device 50c of this embodiment, and corresponds to Figure 8. The overall configuration of the organic EL display device 50c is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20c, so a detailed explanation will be omitted here. Also, the same reference numerals are used for components that are the same as those in the first embodiment, and their descriptions will be omitted.

[0088] In the organic EL display device 50c, as shown in Figure 11, in the display area D (active area), the back gate layer BGc has a non-conductive portion BGcn in which the oxide semiconductor film is not made conductive.

[0089] The non-conducting portion BGcn is provided between multiple adjacent sub-pixels P in the direction in which the source line 18f extends as a signal trace (see Figure 4). In other words, as shown in Figure 11, in the display area D (active area), the conductive portion BGcc in the back gate layer BGc is provided separately for each sub-pixel P. The conductive portion BGcc overlaps with the entire first TFT 9ac (the entire surface of the polysilicon semiconductor layer 12 that constitutes it) in a plan view. Thus, in the organic EL display device 50c, the conductive portion BGcc and the non-conducting portion BGcn are arranged alternately along the direction in which the source line 18f extends.

[0090] The organic EL display device 50c may also be configured to include a metal layer M, similar to the organic EL display device 50b described above.

[0091] The organic EL display device 50c can be constructed by modifying the second base coat film formation step in the TFT layer formation step of the organic EL display device 50a described above as follows. For example, heat treatment is performed after the formation of the second base coat film 11b so that the back gate layer BGc in the region between a plurality of adjacent subpixels P (first TFT 9ac) in the direction in which the source line 18f extends is not affected by heat or its effects are reduced.

[0092] <Effects> According to the organic EL display device 50c described above, in addition to the effects of the organic EL display device 50a mentioned above, the following effects can be obtained. In the organic EL display device 50c, non-conducting sections BGcn are provided between multiple adjacent sub-pixels P (first TFT9ac) in the back gate layer BGc of the display area D (active area) in the direction in which the source line 18f extends. Because the conductive section BGcn separates the conductive section BGcc for each sub-pixel P, it becomes difficult for a potential difference to occur between the conductive section BGcc and the polysilicon semiconductor layer 12. As a result, the stabilization of the threshold characteristics of the first TFT9ac can be improved.

[0093] 《Fourth Embodiment》 Next, a fourth embodiment of the present invention will be described using Figures 12 to 14. Figure 12 is a schematic plan view illustrating the arrangement of the pixel circuit C of the organic EL display device 50d of this embodiment, and corresponds to Figure 4. Figure 13 is an enlarged plan view of the area within the dashed line in Figure 12, showing the first TFT 9ad constituting the pixel circuit C of the organic EL display device 50d. Figure 14 is a cross-sectional view of the display area D of the organic EL display device 50d along the line XIV-XIV in Figure 13. Note that the upper layer of the gate electrode 14a is omitted in Figure 13. The overall configuration of the organic EL display device 50d is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20d, so a detailed explanation is omitted here. Also, the same reference numerals are used for components similar to those in the first embodiment, and their explanations are omitted.

[0094] In the organic EL display device 50d, as shown in Figures 12 to 14, the conductive portion BGdc (back gate layer BGd) is provided in an island-like manner in a plan view, covering the entire subpixel P for each subpixel P. Specifically, as shown in Figures 13 and 14, the island-like conductive portion BGdc overlaps the entire first TFT 9ad (the entire surface of the polysilicon semiconductor layer 12 that constitutes it) in a plan view.

[0095] In the organic EL display device 50d, as shown in Figure 14, the conductive portion BGdc is electrically connected to the source line 18f via the contact hole Hf in the display area D (active area).

[0096] The organic EL display device 50d may also be configured to include a metal layer M, similar to the organic EL display device 50b described above.

[0097] The organic EL display device 50d can be constructed by modifying the TFT layer formation process of the organic EL display device 50a described above, specifically by changing the back gate layer formation process and the contact hole formation process as follows. For example, in the back gate layer formation process, by changing the pattern shape of the oxide semiconductor film, an island-shaped back gate layer BGd is formed that overlaps in a plan view with the entire surface of the polysilicon semiconductor layer 12 (the entire first TFT 9ad) formed in a subsequent process. In the contact hole formation process, in the display area D (active area), contact holes Hf are formed in the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17, exposing at least a portion of the surface of the conductive portion BGdc.

[0098] <Effects> The organic EL display device 50d described above can achieve the same effects as the organic EL display device 50a described above.

[0099] 《Fifth Embodiment》 Next, a fifth embodiment of the present invention will be described using Figures 15 and 16. Figure 15 is an enlarged plan view within the dashed line in Figure 12, showing the first TFT 9ae constituting the pixel circuit C of the organic EL display device 50e of this embodiment. Figure 16 is a cross-sectional view of the display area D of the organic EL display device 50e along the line XVI-XVI in Figure 15. Note that the upper layer of the gate electrode 14a is omitted in Figure 15. The overall configuration of the organic EL display device 50e is the same as in the fourth embodiment described above, except for the configuration of the TFT layer 20e, so a detailed explanation is omitted here. Also, the same reference numerals are used for components similar to those in the fourth embodiment, and their descriptions are omitted.

[0100] In the organic EL display device 50e, similar to the organic EL display device 50d described above, as shown in Figures 15 to 16, the conductive portion BGec (back gate layer BGe) is provided in an island-like manner so as to cover the entire subpixel P for each subpixel P in a plan view. Specifically, the conductive portion BGec overlaps the entire surface of the polysilicon semiconductor layer 12 (the entire first TFT 9ae) in a plan view.

[0101] In this organic EL display device 50e, similar to the organic EL display device 50c described above, the back gate layer BGe in the display area D (active area) has a non-conductive portion BGen in which the oxide semiconductor film is not made conductive.

[0102] In a plan view, the non-conducting portion BGen is provided in a frame shape around the island-shaped conductive portion BGec. Due to the frame-shaped non-conducting portion BGen, in the display area D (active area), the conductive portion BGec in the back gate layer BGe is provided in an isolated pattern separated for each sub-pixel P.

[0103] The organic EL display device 50e may also be configured to include a metal layer M, similar to the organic EL display device 50b described above.

[0104] The organic EL display device 50e can be constructed by modifying the second base coat film formation step in the TFT layer formation step of the organic EL display device 50d described above as follows. For example, heat treatment is performed after the formation of the second base coat film 11b so that the back gate layer BGe around each subpixel P (first TFT 9ae) is not affected by heat or its effects are reduced.

[0105] <Effects> According to the organic EL display device 50e described above, in addition to the effects of the organic EL display device 50a mentioned above, the following effects can be obtained. In the organic EL display device 50e, a frame-shaped non-conducting portion BGen is provided around the sub-pixel P (first TFT9ae) in the back gate layer BGe. Because the conductive portion BGec is separated for each sub-pixel P by the frame-shaped non-conducting portion BGen, a potential difference is less likely to occur between the conductive portion BGec and the polysilicon semiconductor layer 12. As a result, the stabilization of the threshold characteristics of the first TFT9ae can be improved.

[0106] Other embodiments In each of the above embodiments, the conductor portion is integrally provided so as to span multiple subpixels along the direction in which the source line extends as a signal wire, but is not limited thereto. The conductor portion may also be integrally provided so as to span multiple subpixels along the direction in which the gate line extends as a signal wire. In this case, the conductor portion may be electrically connected to the gate line.

[0107] In the embodiments described above, an organic EL layer with a five-layer stacked structure consisting of a hole injection layer, a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer was exemplified. However, the organic EL layer may also have a three-layer stacked structure consisting of, for example, a hole injection layer / hole transport layer, an emissive layer, and an electron transport layer / electron injection layer.

[0108] Furthermore, while the above embodiments illustrate organic EL display devices in which the first electrode is the anode and the second electrode is the cathode, the present invention can also be applied to organic EL display devices in which the laminated structure of the organic EL layer is reversed, with the first electrode being the cathode and the second electrode being the anode.

[0109] In the embodiments described above, an organic EL display device was shown in which the electrode of the TFT connected to the first electrode is used as the drain electrode. However, the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called the source electrode.

[0110] In the embodiments described above, an organic EL display device was used as the display device, but the present invention can also be applied to display devices such as active matrix driven liquid crystal displays.

[0111] In the embodiments described above, an organic EL display device was used as an example of a display device. However, the present invention is not limited to organic EL display devices and can be applied to any flexible display device. For example, it can be applied to a flexible display device equipped with a QLED (Quantum-dot light emitting diode), which is a light-emitting element using a quantum dot-containing layer. [Industrial applicability]

[0112] As described above, the present invention is useful for flexible display devices. [Explanation of Symbols]

[0113] BGa, BGc, BGd, BGe backgate layer BGac,BGcc,BGdc,BGec Conductor part BGcn, BGen non-conducting part D Display area D F Frame area M Metal Layer P subpixel 9aa,9ac,9ad,9ae First TFT 10. Resin substrate (base substrate) 11a First base coat film 11b Second base coat film 12 Polysilicon semiconductor layer 12a Channel region 12b Source region (conductor region) 12c Drain region (conductor region) 18f Source line (signal wiring) 20a, 20b, 20c, 20d, 20e TFT (Thin Film Transistor) Layers 25 Organic EL elements (organic electroluminescent elements, light-emitting elements) 31 Organic EL element layer (light-emitting element layer) 35 Encapsulation film 50a, 50b, 50c, 50d, 50e organic EL display device

Claims

1. The device comprises a base substrate and a thin-film transistor layer provided on the base substrate. The thin-film transistor layer has a polysilicon semiconductor layer formed from a polysilicon film, with defined channel and conductor regions, and multiple thin-film transistors electrically connected to each other via signal wiring in the conductor region are provided corresponding to multiple subpixels constituting the display area. A display device is provided in which a transparent back gate layer is formed of an oxide semiconductor film and has a conductive portion in which at least a part of the oxide semiconductor film is made conductive, below the thin-film transistor layer, The above-mentioned conductive portion overlaps with the above-mentioned channel region in a plan view and is electrically connected to the above-mentioned signal wiring, characterized in that the display device.

2. In the display device described in claim 1, The display device is characterized in that the conductive portion is integrally provided so as to span the plurality of subpixels in the direction in which the signal wiring extends when viewed from above.

3. In the display device described in claim 2, A frame area is provided around the above display area. The above-mentioned conductor portion is arranged in the above-mentioned frame region. A display device characterized in that, in the area within the frame region where the plurality of subpixels are not arranged, the conductive portion is electrically connected to the signal wiring.

4. In the display device described in claim 2, The back gate layer in the above display area has a non-conductive portion in which the oxide semiconductor film is not conductive. The display device is characterized in that the non-conducting portion is provided between a plurality of adjacent subpixels.

5. In the display device described in claim 1, The above-mentioned conductive portion is characterized in that, in a plan view, it is provided in an island-like manner for each of the above-mentioned subpixels.

6. In the display device described in claim 5, The back gate layer in the above display area has a non-conductive portion in which the oxide semiconductor film is not conductive. The display device is characterized in that the non-conducting portion is provided in a frame shape along the periphery of the island-shaped conductive portion in a plan view.

7. In the display device described in claim 5, A display device characterized in that, in the above-mentioned display area, the island-shaped conductive portion is electrically connected to the signal wiring.

8. In a display device according to any one of claims 1 to 7, A display device characterized in that the conductive portion and the signal wiring are connected via a contact hole formed in at least one layer of inorganic insulating film provided between the conductive portion and the signal wiring.

9. In the display device described in claim 8, A display device characterized in that an island-shaped metal layer is provided between the lower end of the contact hole and the conductive portion, as viewed from above.

10. In a display device according to any one of claims 1 to 7, The display device is characterized in that the conductive portion in the above-mentioned display area is arranged in a mesh-like pattern in a plan view so as to correspond to the shape of the polysilicon semiconductor layer.

11. In a display device according to any one of claims 1 to 7, The display device is characterized in that the conductive portion in the above-mentioned display area is provided so as to cover the entirety of each subpixel in a plan view.

12. In a display device according to any one of claims 1 to 7, The display device is characterized in that the back gate layer is provided over the entire surface of the thin-film transistor layer.

13. In a display device according to any one of claims 1 to 7, The above-mentioned signal wiring is characterized in that it is either source wiring or gate wiring.

14. In a display device according to any one of claims 1 to 7, The thin-film transistor layer described above comprises a first base coat film and a second base coat film sequentially stacked on the base substrate described above. The display device is characterized in that the back gate layer is provided between the first base coat film and the second base coat film.

15. In the display device described in claim 14, The thin-film transistor layer described above is The polysilicon semiconductor layer provided on the second base coat film, A gate insulating film is provided so as to cover the above polysilicon semiconductor layer, A display device characterized by comprising a plurality of gate electrodes provided on the gate insulating film.

16. In a display device according to any one of claims 1 to 7, A light-emitting layer is provided on the thin-film transistor layer, and a plurality of light-emitting elements are arranged corresponding to the plurality of subpixels, A display device characterized by comprising a sealing film provided so as to cover the above-mentioned light-emitting layer.

17. In the display device described in claim 16, The above-mentioned light-emitting elements are characterized in that they are organic electroluminescent elements.

18. In the display device described in claim 16, The display device is characterized in that the plurality of thin-film transistors described above are driving thin-film transistors configured to control the current of each of the light-emitting elements.

19. In a display device according to any one of claims 1 to 7, The above-mentioned base substrate is a resin substrate, characterized in that it is a display device.

20. The device comprises a base substrate and a thin-film transistor layer provided on the base substrate. The thin-film transistor layer has a polysilicon semiconductor layer formed from a polysilicon film, with defined channel and conductor regions, and multiple thin-film transistors electrically connected to each other via signal wiring in the conductor region are provided corresponding to multiple subpixels constituting the display area. A method for manufacturing a display device, wherein a transparent back gate layer is provided below the thin-film transistor layer, the back gate layer being formed of an oxide semiconductor film and having a conductive portion in which at least a part of the oxide semiconductor film is made conductive, The thin-film transistor layer formation step for forming the thin-film transistor layer described above is: A first base coat film formation step in which a first base coat film is formed on the above base substrate, A back gate layer formation step is performed by forming the oxide semiconductor film on the substrate surface on which the first base coat film is formed, followed by patterning the oxide semiconductor film to form the back gate layer. A second base coat film formation step in which a second base coat film is formed on the substrate surface on which the above back gate layer is formed, A polysilicon semiconductor layer formation step involves forming the polysilicon film on the substrate surface on which the second base coat film described above is formed, followed by patterning the polysilicon film to form the polysilicon semiconductor layer, and A gate insulating film formation step involves forming a gate insulating film on the substrate surface on which the polysilicon semiconductor layer is formed so as to cover the polysilicon semiconductor layer, A gate electrode formation step involves forming a lower metal film on the substrate surface on which the gate insulating film is formed, and then patterning the lower metal film to form a plurality of gate electrodes. A doping step in which each of the above gate electrodes is used as a mask to perform doping and form the above channel region and the above conductor region of the polysilicon semiconductor layer, An interlayer insulating film formation step is to form at least one interlayer insulating film on the substrate surface on which the above-mentioned plurality of gate electrodes are formed, A contact hole formation step is to form a contact hole on the substrate surface on which the above-mentioned at least one interlayer insulating film is formed, exposing at least a portion of the conductive region in the polysilicon semiconductor layer and the conductive portion in the back gate layer. The process includes a signal wiring formation step of forming an upper metal film on the substrate surface in which the above-mentioned contact holes are formed, and then patterning the upper metal film to form the signal wiring that covers the exposed surface of the conductive portion exposed within the contact holes. In the second base coat film formation step described above, by heat treatment after the formation of the second base coat film, at least the region of the back gate layer that overlaps with the channel region in a plan view is made conductive to form the conductive portion. A method for manufacturing a display device, characterized in that, in the signal wiring formation step described above, the conductive portion and the signal wiring are electrically connected.

21. In the method for manufacturing a display device according to claim 20, The above thin-film transistor layer formation step includes a metal layer formation step, which occurs after the back gate layer formation step and before the second base coat film formation step. The above metal layer formation step is characterized by forming a metal film on the substrate surface on which the back gate layer is formed, and then patterning the metal film to form an island-shaped metal layer in plan view between the lower end of the contact hole and the conductive portion.

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