SAG nanowire growth by ion implantation

Abstract

The present disclosure relates to a nanowire structure comprising a substrate having a substrate body and an ion-implanted region, a patterned mask having an opening in an upper portion of the substrate, and a nanowire. The substrate body is formed of a conductive material, and the ion-implanted region extends from an upper surface of the substrate body into the substrate body and is electrically isolated. A surface portion of the substrate body is exposed through the opening in the patterned mask, while the ion-implanted region is completely covered by the patterned mask. The nanowire is formed directly on the exposed surface portion of the substrate body and is not in contact with the ion-implanted region. Furthermore, the nanowire is confined within the ion-implanted region, which is configured to provide a conductive barrier for the nanowire in the substrate.

Description

Technical Field

[0001] The present disclosure relates to a selective area growth (SAG) nanowire structure and a method of manufacturing the same, and more particularly to an SAG nanowire structure having an ion-implanted substrate and a method of manufacturing an SAG nanowire structure by ion implantation.

Background Art

[0002] Nanowires are extremely promising for applications in quantum computing. Unfortunately, it is difficult to produce high-quality nanowires. Conventional processes for manufacturing nanowires have selective area growth (SAG) in which nanowires are selectively grown on a substrate. For proper functioning, the nanowires need to be made of a conductive semiconductor material, but the substrate on which the nanowires grow is often an insulating material. Also, nanowires grown on the same substrate can be separated from each other. However, there is often a large difference between the crystal lattice constant of the substrate and the nanowires grown via SAG. This lattice mismatch causes crystal defects such as dislocations and stacking faults in the growing nanowires. Crystal defects can penetrate the nanowires and further degrade the properties of the resulting nanowires.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Therefore, there is a need for a nanowire structure with reduced crystal defects and a method of manufacturing the same.

Means for Solving the Problems

[0004] This disclosure relates to a nanowire structure and a method for manufacturing the same. The nanowire structure of the disclosure comprises a substrate having a substrate body and an ion implantation region, a patterned mask having an opening at the top of the substrate, and nanowires. Here, the substrate body is formed of a conductive material, and the ion implantation region extending from the upper surface of the substrate body into the substrate body is electrically insulated. The surface portion of the upper surface of the substrate body is exposed through the opening of the patterned mask, and the ion implantation region is completely covered by the patterned mask. The nanowires are formed directly on the exposed surface portion of the substrate body through the opening of the patterned mask and do not come into contact with the ion implantation region. Furthermore, the nanowires are confined within the ion implantation region, which is configured to provide a conductive barrier for the nanowires in the substrate.

[0005] In one embodiment of the nanowire structure, the ion implantation region has a closed-loop shape.

[0006] In one embodiment of the nanowire structure, the substrate body has a thickness between 50 μm and 1000 μm, and the ion implantation region has a depth between 2 nm and 50 μm.

[0007] In one embodiment of the nanowire structure, the substrate is formed from indium phosphide, gallium antimony, or gallium arsenide, and the nanowires are formed from indium arsenide, indium antimony, or indium arsenide antimony.

[0008] In another embodiment, the nanowire structure further comprises a superconducting layer formed on top of the nanowire.

[0009] In another embodiment, another nanowire structure comprises a substrate having a substrate body and at least one ion implantation region, a patterning mask having a first opening and a second opening on the upper part of the substrate, a first nanowire, and a second nanowire. Here, the substrate body is formed of a conductive material, while at least one ion implantation region extends from the upper surface of the substrate body into the substrate body and is electrically insulating. A first surface portion of the upper surface of the substrate body is exposed through a first opening of the patterning mask, a second surface portion of the upper surface of the substrate body is exposed through a second opening of the patterning mask, and at least one ion implantation region is completely covered by the patterning mask. The first nanowire is formed directly above the exposed first surface portion of the substrate body through the first opening of the patterning mask. The second nanowire is formed directly above the exposed second surface portion of the substrate body through the second opening of the patterning mask. The first and second nanowires do not come into contact with the at least one ion implantation region. At least one portion of the ion implantation region lies between the first and second nanowires, blocking the conductive path within the substrate between the first and second nanowires.

[0010] In one embodiment of another nanowire structure, at least one ion implantation region comprises a first ion implantation region and a second ion implantation region. Here, the first nanowire is confined within the first ion implantation region, and the first ion implantation region is configured to provide a conductive barrier for the first nanowire. The second nanowire is confined within the second ion implantation region, and the second ion implantation region is configured to provide a conductive barrier for the second nanowire. A portion of the first ion implantation region and a portion of the second ion implantation region are located between the first and second nanowires.

[0011] In one embodiment of another nanowire structure, the first ion implantation region has a closed-loop shape, and the second ion implantation region has a closed-loop shape.

[0012] In one embodiment of another nanowire structure, the first ion implantation region and the second ion implantation region have different shapes.

[0013] In one embodiment of another nanowire structure, the depths of the first ion implantation region and the depths of the second ion implantation region are different.

[0014] In another embodiment, the nanowire structure further comprises a first superconductor layer formed on top of the first nanowire and a second superconductor layer formed on top of the second nanowire, where the first and second superconductor layers are not connected.

[0015] In another embodiment of the nanowire structure, the substrate body has a thickness between 50 μm and 1000 μm. The first ion implantation region has a depth between 2 nm and 50 μm, and the second ion implantation region has a depth between 2 nm and 50 μm.

[0016] In another embodiment of the nanowire structure, the substrate body has a thickness between 50 μm and 1000 μm, and at least one ion implantation region has a depth between 2 nm and 50 μm.

[0017] In one embodiment of another nanowire structure, the substrate is formed of indium phosphide, gallium antimony, or gallium arsenide, and at least one nanowire is formed of indium arsenide, indium antimony, or indium arsenide antimony.

[0018] In one example method for manufacturing a nanowire structure, first, a substrate body formed of a conductive material is provided. Next, an implantation mask having an implantation opening is provided on top of the substrate body. Through the implantation opening of the implantation mask, a treated surface portion of the upper surface of the substrate body is exposed. Next, ion implantation is applied to the substrate body through the implantation opening, and a portion of the substrate body extending from the exposed treated surface portion into the substrate body is converted into an ion implantation region. The ion implantation region is electrically insulated. After the ion implantation region is formed, the implantation mask is removed. A patterning mask having a nanowire opening is provided on top of the substrate body and the ion implantation region. Through the nanowire opening of the patterning mask, a nanowire surface portion of the upper surface of the substrate body is exposed, and the ion implantation region is completely covered by the patterning mask. Finally, nanowires are formed on top of the exposed nanowire surface portion of the substrate body through the nanowire opening of the patterning mask. Here, the nanowires do not come into contact with the ion implantation region. The nanowires are confined within the ion implantation region, which is configured to provide a conductive barrier for the nanowires in the substrate.

[0019] In one embodiment of the example method, ion implantation is performed by implanting oxygen ions into the substrate body through an implantation opening.

[0020] In one embodiment of the example method, the substrate is formed from one of indium phosphide, gallium antimony, and gallium arsenide, and the nanowires are formed from one of indium arsenide, indium antimony, and indium arsenide antimony.

[0021] In one embodiment of the example method, the substrate body has a thickness between 50 μm and 1000 μm, and the ion implantation region has a depth between 2 nm and 50 μm.

[0022] In another embodiment, the example method further includes the step of providing a superconducting layer on a nanowire.

[0023] In another embodiment, an example method further has a step of planarizing the upper surface of the substrate body after removing the injection mask and before providing the patterning mask.

[0024] After reading the following detailed description of the preferred embodiments with reference to the accompanying drawings, those skilled in the art will clearly understand the scope of the present disclosure and can understand additional aspects of the present disclosure.

[0025] The accompanying drawings incorporated herein and constituting a part of this specification show some aspects of the present disclosure and, together with the present disclosure, serve to explain the principles of the present disclosure.

Brief Description of the Drawings

[0026] [Figure 1A] It is a diagram showing an example of a nanowire structure according to an embodiment of the present disclosure. [Figure 1B] It is a diagram showing an example of a nanowire structure according to an embodiment of the present disclosure. [Figure 2] It is a flowchart showing an example of a method for manufacturing a nanowire structure according to an embodiment of the present disclosure. [Figure 3] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. [Figure 4] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. [Figure 5] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. [Figure 6] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. [Figure 7] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. [Figure 8] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. [Figure 9] It is a diagram showing the steps related to the manufacturing process provided in FIG. 2. It is understood that for clarity, FIGS. 1 to 9 do not show a scale. [Modes for carrying out the invention]

[0027] The embodiments described below are intended to enable those skilled in the art to carry out the embodiments and to provide the information necessary to demonstrate the best mode of carrying out the embodiments. By reading the following description in reference to the accompanying drawings, those skilled in the art will be able to understand the concepts of this disclosure and recognize the applications of these concepts that are not specifically addressed in this application. It will be understood that these concepts and applications are within the scope of this disclosure and the accompanying claims.

[0028] In this application, various elements are described using terms such as "first," "second," etc. These elements are not limited by these terms. These terms are used simply to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The terms "and / or" as used in this application include any and all combinations of one or more of the relevant enumerated items.

[0029] When an element such as a layer, region, or substrate is described as being "on top of" or "extending above" another element, it is understood that this may mean it is directly on top of the other element, extends directly onto the other element, or has further intervening elements. On the other hand, when an element is described as being "directly on top of" or "extending directly above" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is described as being "on top of" or "extending on top of" another element, it is understood that this may mean it is directly on top of the other element, extends directly onto the other element, or has further intervening elements. On the other hand, when an element is described as being "directly on top of" or "extending directly above" another element, there are no intervening elements. Also, when an element is described as being "connected" or "coupled" to another element, it is understood that this may mean it is directly connected to or coupled to the other element, or has further intervening elements. In contrast, when one element is said to be "directly connected" or "directly coupled" to another element, there is no intervening element.

[0030] Relative terms used in this application, such as “down,” “up,” “above,” “downward,” “horizontal,” or “vertical,” may be used to describe the relationship between one element, layer, or region and another, as shown in the drawings. It is understood that these terms, and the terms mentioned above, are intended to encompass different orientations of the apparatus in addition to the orientation shown in the drawings.

[0031] The terms used in this application are for the sole purpose of describing specific embodiments and are not intended to limit the disclosure. Furthermore, the singular forms “a,” “an,” and “the” used in this application are intended to include the plural form unless the context explicitly indicates otherwise. In addition, as used in this application, the terms “comprises,” “comprising,” “includes,” and / or “including” identify the presence of described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise specified, all terms used in this Application (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which this Disclosure pertains. Furthermore, terms used in this Application should be understood to have a meaning consistent with their meanings in the context of this Specified and related art, and should not be understood in an idealized or formal sense unless explicitly defined.

[0033] This disclosure relates to a selective region growth (SAG) nanowire structure having an ion implantation substrate and a method for manufacturing the same. Figures 1A and 1B provide an example of a nanowire structure 10 according to one embodiment of the present disclosure. Figure 1A shows a top view of the nanowire structure 10, and Figure 1B shows a cross-sectional view of the nanowire structure 10 along the dashed line A-A'. For illustrative purposes of this figure, the nanowire structure 10 has a substrate 12 which has a first ion implantation region 14, a second ion implantation region 16, a first nanowire 18, and a second nanowire 20. The first nanowire 18 and the second nanowire 20 may be confined within the first ion implantation region 14 and the second ion implantation region 16, respectively. In different applications, the nanowire structure 10 may contain more nanowires, and correspondingly, the substrate 12 may contain more ion implantation regions.

[0034] In detail, the substrate 12 has a substrate body 22, a first ion implantation region 14, and a second ion implantation region 16. Here, the substrate body 22 is made of indium arsenide (InAs), indium antimony (InSb), gallium antimony (GaSb), and indium gallium arsenide (InGa 0.8 As 0.2 The substrate may be formed of a conductive material such as ). The first ion implantation region 14 and the second ion implantation region 16 are electrically insulated and extend from the upper surface of the substrate body 22 into the substrate body 22, preventing electron transmission through the substrate body 22 (details will be described later). The substrate body 22 may have a thickness of 50 μm to 1000 μm. Each of the first ion implantation region 14 and the second ion implantation region 16 may have a depth (Z direction) of 2 nm to 50 μm extending from the upper surface of the substrate body 22 into the substrate body 22.

[0035] A patterning mask 24 having a first nanowire opening 26 and a second nanowire opening 28 is present on the upper part of the substrate 12 (shown in Figure 1B, not Figure 1A). Thus, the first nanowire surface portion 22-1N and the second nanowire surface portion 22-2N of the upper surface of the substrate body 22 are exposed through the first nanowire opening 26 and the second nanowire opening 28 of the patterning mask 24, respectively. It should be noted that the patterning mask 24 completely covers the first ion implantation region 14 and the second ion implantation region 16, and therefore the first ion implantation region 14 and the second ion implantation region 16 are not exposed through the first nanowire opening 26 or the second nanowire opening 28 of the patterning mask 24. The patterning mask 24 may be formed of a dielectric material such as silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), or diamond. The patterned mask 24 may have a thickness of 2 nm to 1000 nm.

[0036] Each of the first nanowire 18 and the second nanowire 20 is an elongated component with a nanoscale width (W N), and having a length-to-width ratio of at least 10 or 20, they are selectively grown on the substrate body 22 via a patterning mask 24. Non-limiting examples of nanowires 18 / 20 have an average width (W) in the range of 10 to 1000 nm, 50 to 100 nm if required, or 75 to 125 nm. NA ) has. The length (L) of the nanowire 18 / 20. N The thickness (T) of the nanowire 18 / 20 is on the order of micrometers, and may be, for example, at least 1 μm or at least 10 μm. N The nanowires may be between 20 nm and 300 nm. The first nanowire 18 and the second nanowire 20 may be formed from a conductive semiconductor such as indium arsenide (InAs), indium antimony (InSb), or indium arsenide-antimony (InAsSb).

[0037] The first nanowire 18 is located directly above the first nanowire surface portion 22-1N of the substrate body 22 via the first nanowire opening 26 of the patterning mask 24. Since both the first nanowire 18 and the substrate body 22 are formed from conductive materials, the lattice constants of the substrate body 22 and the first nanowire 18 can be made relatively close. Therefore, defects such as mismatched dislocations, slip planes, and stacking faults caused by lattice constant mismatches are extremely rare. Similarly, the second nanowire 20 is located directly above the second nanowire surface portion 22-2N of the substrate body 22 via the second nanowire opening 28 of the patterning mask 24. Since both the second nanowire 20 and the substrate body 22 are formed from conductive materials, the lattice constants of the substrate body 22 and the second nanowire 20 can be made relatively close. This makes misfitted dislocations, slip planes, and stacking faults acceptable. If the substrate body 22 is formed of an insulating material, a high lattice constant mismatch may occur between the nanowires 18 / 20 and the substrate body 22. As a result, the first nanowire 18 and / or the second nanowire 20 may not function properly.

[0038] In quantum computing, quantum states arising from electrons within a structure are hosted and transmitted using nanowires. It is desirable that this movement be consistent and uniform. Therefore, it is desirable that each surface of the nanowire be smooth. Since the first nanowire 18 is formed directly on the first nanowire surface portion 22-1N of the substrate body 22, and the second nanowire 20 is formed directly on the second nanowire surface portion 22-2N of the substrate body 22, it is desirable that the first nanowire surface portion 22-1N and the second nanowire surface portion 22-2N of the substrate body 22 be planarized to have a vertical roughness of less than 10 Å.

[0039] It should be noted that the first nanowire 18 and the second nanowire 20 only come into contact with the surface portion 22-1N of the first nanowire and the surface portion 22-2N of the second nanowire, respectively, and do not come into contact with the first ion implantation region 14 or the second ion implantation region 16 (the first ion implantation region 14 and the second ion implantation region 16 are completely covered by the patterned mask 24). Therefore, although the lattice constants of the first ion implantation region 14 or the second ion implantation region 16 may differ significantly from the lattice constants of the nanowires 18 / 20, this does not result in defects during the growth of the nanowires 18 / 20.

[0040] Each of the first ion implantation region 14 and the second ion implantation region 16 may form a closed loop in the XY plane (where the X, Y, and Z directions are mutually orthogonal). The first nanowire 18 is confined within the first ion implantation region 14, and the second nanowire 20 is confined within the second ion implantation region 16. Thus, the first ion implantation region 14 and the second ion implantation region 16 block the conductive path in the substrate 12 between the first nanowire 18 and the second nanowire 20. The first nanowire 18 and the second nanowire 20 are electrically insulated from each other. If the first ion implantation region 14 and the second ion implantation region 16 are not present, a conductive path exists between the first nanowire 18 and the second nanowire 20 through the substrate body 12 (formed of a conductive material). As a result, the first nanowire 18 and / or the second nanowire 20 may not function properly. If the first nanowire 26 and the second nanowire 28 have different shapes and / or lengths, the first ion implantation region 14 and the second ion implantation region 16 may have different shapes. Also, the first ion implantation region 14 and the second ion implantation region 16 may have different depths.

[0041] The nanowire structure 10 may also further have a first superconductor 30 and a second superconductor 32. The first superconductor 30 is located on top of the first nanowire 18 and, if necessary, above a portion of the patterning mask 24. The second superconductor 32 is located on top of the second nanowire 20 and, if necessary, above another portion of the patterning mask 24. The first superconductor 30 and the second superconductor 32 do not have to be connected. Each of the first superconductor 30 and the second superconductor 32 may be made of aluminum (Al), lead (Pb), niobindium (NbIn), tin (Sn), or vanadium (V) and may have a thickness between 3 nm and 30 nm.

[0042] Figure 2 provides a flowchart illustrating a method for manufacturing a nanowire structure 10 according to one embodiment of the present disclosure. Figures 3 to 9 show steps in the manufacturing method provided in Figure 2. The exemplary steps are shown in series, but the exemplary steps are not necessarily in any particular order. Some steps may be performed in a different order than those presented. Furthermore, methods within the scope of the present disclosure may have fewer or more steps than those shown in Figures 3 to 9.

[0043] First, as shown in Figure 3, the substrate body 22 is provided (step 100). The substrate 22 is made of InAs, InSb, GaSb, and InGa 0.8 As 0.2 The substrate body 22 may be formed of a conductive material such as the above. The substrate body 22 may have a thickness of 50 μm to 1000 μm. As shown in Figure 4, an injection mask 34 having a first injection opening 36 and a second injection opening 38 is provided on the substrate body 22 (step 102). Each of the first injection opening 36 and the second injection opening 38 may have a closed loop shape in the XY plane (not shown). The injection mask 34 may be formed of a polymer such as photoresist or polymethyl methacrylate (PMMA) with a thickness between 100 nm and 5 μm. The step of providing the injection mask 34 on the substrate body 22 may include the steps of providing an injection mask layer over the entire upper surface of the substrate body 22, and then patterning the injection mask layer by any preferred process to provide the injection mask 34 with the first injection opening 36 and the second injection opening 38.

[0044] Here, the first injection opening 36 and the second injection opening 38 are designed for the following ion implantation process. The first treated surface portion 22-1P of the substrate body 22 is exposed through the first injection opening 36, and the second treated surface portion 22-2P of the substrate body 22 is exposed through the second injection opening 38. Each of the exposed first treated surface portion 22-1P and the exposed second treated surface portion 22-2P of the substrate body 22 may have a closed loop shape in the XY plane (not shown).

[0045] Next, as shown in Figure 5, ion implantation is applied to the substrate body 22, providing the substrate 12 with a first ion implantation region 14 and a second ion implantation region 16 (step 104). In a non-limiting example, the ion implantation process may be carried out by implanting oxygen ions into the substrate body 22. Oxygen implantation into the conductive substrate body 22 forms electron traps, which reduce local conductivity. Due to the implantation mask 34, the ion implantation process is applied to the substrate body 22 only through the first implantation opening 36 and the second implantation opening 38. Thus, a portion of the substrate body 22 extending into the substrate body 22 from the exposed first treated surface portion 22-1P is converted into the first ion implantation region 14 as a conductive barrier. Another portion of the substrate body 22 extending into the substrate body 22 from the exposed second treated surface portion 22-2P is converted into the second ion implantation region 16 as a conductive barrier. Each of the first ion implantation region 14 and the second ion implantation region 16 may have a closed-loop shape in the XY plane (not shown). The depth of each ion implantation region 14 / 16 (Z direction) can be controlled, for example, between 2 nm and 50 μm, by different implantation parameters such as energy, different ion currents, and / or different heat treatment parameters.

[0046] As shown in Figure 6, the implantation mask 34 is then removed (step 106). Optionally, a polishing process may follow to clean the substrate 12 and / or planarize the upper surface of the substrate 12 (including the upper surface of the substrate body 22 and the upper surfaces of the ion implantation regions 14 and 16). As shown in Figure 7, a patterning mask 24 having a first nanowire opening 26 and a second nanowire opening 28 is provided on the substrate 12 (step 108). The patterning mask 24 may be formed from a dielectric material such as SiO2, SiN, Al2O3, diamond, or any material that inhibits suitable epitaxial growth and maintains selectivity. The patterning mask 24 may have a thickness between 2 nm and 1000 nm. The step of providing a patterned mask 24 on a substrate 12 may include the steps of providing a mask layer over the entire upper surface of the substrate 12, and then patterning the mask layer by any preferred process (such as lithography) to provide a first nanowire opening 26 and a second nanowire opening 28 in the patterned mask 24.

[0047] Here, the patterning mask 24 is designed for subsequent nanowire growth. The first ion implantation region 14 and the second ion implantation region 16 are not desirable bases for nanowire growth because their lattice constants may have a relatively large mismatch with the lattice constants of the nanowires 18 and 20 that are formed later. Therefore, the patterning mask 24 is designed to completely cover the first ion implantation region 14 and the second ion implantation region 16. As a result, subsequent nanowire growth does not occur directly over the first ion implantation region 14 or the second ion implantation region 16. The first nanowire surface portion 22-1N and the second nanowire surface portion 22-2N of the substrate body 22 are exposed through the first nanowire opening 26 and the second nanowire opening 28 of the patterning mask 24, respectively. The first nanowire opening 26 is designed to be confined within the first ion implantation region 14, and as a result, the nanowire grown on the first nanowire surface portion 22-1N through the first nanowire opening 26 is confined within the first ion implantation region 14. The second nanowire opening 28 is designed to be confined within the second ion implantation region 16, and as a result, the nanowire grown on the second nanowire surface portion 22-2N through the second nanowire opening 28 is confined within the second ion implantation region 16.

[0048] As shown in Figure 8, after the patterned mask 24 is formed, the first nanowire 18 and the second nanowire 20 are formed (step 110). The first nanowire 18 is grown on the first nanowire surface portion 22-1N of the substrate body 22 through the first nanowire opening 26, and the second nanowire 20 is grown on the second nanowire surface portion 22-2N of the substrate body 22 through the second nanowire opening 28. Since the first nanowire 18, the second nanowire 20, and the substrate body 22 are formed from a conductive material, the lattice constant mismatch between the substrate body 22 and the first nanowire 18, and between the substrate body 22 and the second nanowire 20, is relatively small. Therefore, defects such as misfit dislocations, slip planes, and stacking faults caused by lattice constant mismatch are considerably reduced.

[0049] Furthermore, since the first nanowire opening 26 is confined within the first ion implantation region 14, the first nanowire 18 grown through the first nanowire opening 26 is also confined within the first ion implantation region 14. Similarly, the second nanowire 20 is confined within the second ion implantation region 16. It is clear that a portion of the first ion implantation region 14 and a portion of the second ion implantation region 16 are positioned between the first nanowire 18 and the second nanowire 20, thus blocking the conductive path between the first nanowire 18 and the second nanowire 20 through the substrate body 22. Therefore, the first nanowire 18 and the second nanowire 20 are electrically insulated from each other. Finally, as shown in Figure 9, a first superconducting conductor 30 and a second superconductor 32 are provided to complete the nanowire structure 10 (step 112). The first superconductor 30 is formed on top of the first nanowire 18 and, if necessary, on a portion of the patterning mask 24. The first superconductor 30 does not have to cover the entire first nanowire 18. The second superconductor 32 is formed on top of the second nanowire 20 and, if necessary, on another portion of the patterning mask 24. The second superconductor 32 does not have to cover the entire second nanowire 20. The first superconductor 30 and the second superconductor 32 do not have to be connected. In some applications, the first superconductor 30 and the second superconductor 32 may be formed continuously as a continuous film layer covering the entire patterning mask 24, the first nanowire 18, and the second nanowire 20 (not shown). If necessary, the continuous film layer may be patterned to separate the first nanowire 18 and the second nanowire 20 (not shown).

[0050] Those skilled in the art will understand the improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are deemed to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. It is a nanowire structure, A substrate including the substrate body and the ion implantation region, The aforementioned substrate body is formed of a semiconductor material, The ion implantation region is electrically insulated and extends from the upper surface of the substrate body to the substrate body. circuit board and A patterning mask provided on the upper part of the substrate, The substrate body has an opening that exposes the surface portion of the upper surface, The ion implantation region is completely covered, Patterned masks and A nanowire formed directly on the exposed surface portion of the substrate body through the opening of the patterned mask, The nanowire does not come into contact with the ion implantation region. The nanowire is confined within the ion implantation region, and the ion implantation region is configured to provide a conductive barrier for the nanowire in the substrate. Nanowires and It has, The substrate body is formed from one of the following: indium arsenide (InAs), indium antimony (InSb), gallium antimony (GaSb), and indium gallium arsenide (InGa 0.8 As 0.2). The nanowire structure is formed from one of the following: indium arsenide, indium antimony, or indium arsenide-antimony.

2. The nanowire structure according to claim 1, wherein the ion implantation region has a closed loop shape.

3. The substrate body has a thickness of 50 μm to 1000 μm. The nanowire structure according to claim 1, wherein the ion implantation region has a depth between 2 nm and 50 μm.

4. Furthermore, the nanowire structure according to claim 1, further comprising a superconducting layer formed on the upper part of the nanowire.

5. It is a nanowire structure, A substrate having a substrate body and at least one ion implantation region, The aforementioned substrate body is formed of a semiconductor material, The at least one ion implantation region is electrically insulated and extends from the upper surface of the substrate body to the substrate body. circuit board and A patterning mask having a first opening and a second opening provided on the upper part of the substrate, The first surface portion of the upper surface of the substrate body is exposed through the first opening of the patterning mask, The second surface portion of the upper surface of the substrate body is exposed through the second opening of the patterning mask. The patterned mask completely covers the at least one ion implantation region. Patterned masks and Through the first opening of the patterned mask, a first nanowire is formed directly on the exposed first surface portion of the substrate body, Through the second opening of the patterned mask, a second nanowire is formed directly on the exposed second surface portion of the substrate body, It has, The first nanowire and the second nanowire are not in contact with the at least one ion implantation region. A portion of at least one ion implantation region lies between the first nanowire and the second nanowire, and the conductive path in the substrate between the first nanowire and the second nanowire becomes blocked. The substrate body is formed from one of the following: indium arsenide (InAs), indium antimony (InSb), gallium antimony (GaSb), and indium gallium arsenide (InGa 0.8 As 0.2). The first nanowire is formed from indium arsenide, indium antimony, and indium arsenide-antimony. The second nanowire is a nanowire structure formed from indium arsenide, indium antimony, or indium arsenide-antimony.

6. The at least one ion implantation region comprises a first ion implantation region and a second ion implantation region. The first nanowire is confined within the first ion implantation region, and the first ion implantation region is configured to provide a conductive barrier for the first nanowire. The second nanowire is confined within the second ion implantation region, and the second ion implantation region is configured to provide a conductive barrier for the second nanowire. The nanowire structure according to claim 5, wherein a portion of the first ion implantation region and a portion of the second ion implantation region are arranged between the first nanowire and the second nanowire.

7. The nanowire structure according to claim 6, wherein the first ion implantation region has a closed loop shape, and the second ion implantation region has a closed loop shape.

8. The nanowire structure according to claim 6, wherein the first ion implantation region and the second ion implantation region have different shapes.

9. The nanowire structure according to claim 6, wherein the depths of the first ion implantation region and the second ion implantation region are different.

10. moreover, The present invention comprises a first superconductor layer formed on the upper part of the first nanowire, and a second superconductor layer formed on the upper part of the second nanowire. The nanowire structure according to claim 6, wherein the first superconductor layer and the second superconductor layer are not connected.

11. The substrate body has a thickness between 50 μm and 1000 μm. The first ion implantation region has a depth between 2 nm and 50 μm. The nanowire structure according to claim 6, wherein the second ion implantation region has a depth between 2 nm and 50 μm.

12. A method for manufacturing nanowire structures, The steps include providing a substrate body formed from a semiconductor material, A step of providing an injection mask having an injection opening at the top of the substrate body, wherein the treated surface portion of the upper surface of the substrate body is exposed through the injection opening of the injection mask, A step of applying ion implantation to the substrate body through the implantation opening, wherein a portion of the substrate body extending from the exposed processing surface portion into the substrate body is converted into an ion implantation region. The ion implantation region is electrically insulated, step and The step of removing the injection mask, A step of providing a patterned mask having nanowire openings on the substrate body and the upper part of the ion implantation region, wherein the patterned mask completely covers the ion implantation region, and the nanowire surface portion of the upper surface of the substrate body is exposed through the nanowire openings of the patterned mask. A step of forming nanowires on the exposed nanowire surface portion of the substrate body through the nanowire opening of the patterned mask, wherein the nanowires do not come into contact with the ion implantation region, the nanowires are confined within the ion implantation region, and the ion implantation region is configured to provide a conductive barrier for the nanowires in the substrate; It has, The substrate body is formed from one of the following: indium arsenide (InAs), indium antimony (InSb), gallium antimony (GaSb), and indium gallium arsenide (InGa 0.8 As 0.2). A method wherein the nanowire is formed from one of indium arsenide, indium antimony, and indium arsenide-antimony.

13. The method according to claim 12, wherein the ion implantation is performed by implanting oxygen ions into the substrate body through the implantation opening.

14. The substrate body has a thickness between 50 μm and 1000 μm. The method according to claim 12, wherein the ion implantation region has a depth between 2 nm and 50 μm.

15. The method according to claim 12, further comprising the step of flattening the upper surface of the substrate body after removing the injection mask and before providing the patterned mask.

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