Signal generation method and signal generator
The FPGA-based signal generator with multiple buffer memories addresses data continuity issues in high-speed AWGs by storing and repeating waveform data across buffers, enabling continuous signal output for arbitrary-length patterns.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- ANRITSU CORP
- Filing Date
- 2023-03-24
- Publication Date
- 2026-06-02
AI Technical Summary
Existing arbitrary waveform generators (AWGs) face challenges in maintaining data continuity when generating high-speed signals due to data bandwidth limitations, particularly at speeds around 10-100 GHz, as common external RAMs like DDR struggle to provide sufficient bandwidth, leading to data loss or discontinuity when user patterns are not integer multiples of memory read width.
A signal generation method and generator using an FPGA-based configuration with multiple buffer memories (first, second, and third buffer memories) to store and manage waveform data, ensuring data continuity by storing previous clock cycle data and repeating patterns across these buffers to maintain continuous output.
The method enables loop output of arbitrary-length user patterns with maintained data continuity, overcoming bandwidth limitations and ensuring seamless signal generation even at high frequencies.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a signal generation method and a signal generator.
Background Art
[0002] Patent Document 1 describes a digital function generator. The digital function generator includes a waveform memory in which waveform data is stored, and reads out the waveform data from the waveform memory according to waveform conditions set from the outside, and generates an arbitrary signal waveform in a signal generator that generates an arbitrary signal waveform up to the high frequency range.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] With the increasing speed of communication standards such as Ethernet (registered trademark) and PCIe (registered trademark), an arbitrary waveform can be generated analogously, and a high-speed arbitrary signal generator (Arbitrary Waveform Generator, hereinafter sometimes referred to as AWG) is required. As signals to be output by the AWG, there are an arbitrarily set waveform pattern and a waveform pattern in which the user sets the waveform data itself. Hereinafter, these waveform patterns are expressed as user patterns. By reading the user pattern in a loop, it is possible to output a long-period pattern that exceeds the memory size built into the AWG.
[0005] When an AWG with an output speed of about several GHz outputs a user pattern, sufficient data bandwidth can be ensured even when using a general external RAM such as DDR as the pattern memory.
[0006] However, for the high speeds currently required in AWG (around 10-100 GHz), using common external RAM such as DDR is difficult due to data bandwidth limitations. For example, DDR4 2400 with a data width of 16 bits has a data bandwidth of approximately 34 Gb / s.
[0007] Therefore, in order to secure the necessary data bandwidth, a method is employed in which data is read from the internal memory of the FPGA (or ASIC, etc.) at a speed corresponding to the output data bandwidth of the AWG, and the read value is output as is. The required bandwidth is, for example, 1 Tb / s for an AWG with 8-bit resolution and 128 GHz. The above method basically does not require or requires little buffer memory and the circuit is simple, so when implemented with an FPGA, it has advantages in terms of circuit resources within the FPGA. On the other hand, when attempting to output a user pattern in a loop, the data size can only be set to data that is an integer multiple of the memory read width. This is because the width of data that can be read at one time is fixed for almost all semiconductor memory, and it is basically impossible to change this value. For example, if the memory read width is 4096 bits and the output data resolution of the AWG is 8 bits, then only data that is an integer multiple of 512 Symbols can be set.
[0008] If a user pattern is set to a value other than an integer multiple of the memory read width and output as is, naturally, data that does not fit within the memory read width will be skipped or require processing to fill in the gaps, resulting in a loss of data continuity.
[0009] Thus, when data continuity is lost, communication devices can avoid problems by sending the discontinuous data separately and then combining them. However, in AWG, discontinuity in the generated signals is completely unacceptable, making it crucial to maintain continuity.
[0010] The present invention has been made in view of the above circumstances, and provides a signal generation method and a signal generator that can generate a loop output while maintaining data continuity for a user pattern of any length. [Means for solving the problem]
[0011] To achieve the aforementioned objectives, the signal generation method and signal generator according to the present invention are characterized by the following [1] to [4]. [1] A method for generating a signal using a signal generator (100), The signal generator includes a user pattern memory (12) for storing arbitrarily set waveform patterns, a first buffer memory (141), a second buffer memory (142), and a third buffer memory (143). The sizes of the first buffer memory, the second buffer memory, and the third buffer memory are, respectively, the same size as the memory read width of the user pattern memory. A first storage step involves storing the read data of the waveform pattern in the first buffer memory, A second storage step involves storing the read data of the waveform pattern from one clock cycle prior in the second buffer memory, A third storage step involves storing the first data from the read data of the waveform pattern in the third buffer memory, A signal output step includes outputting repeating data, which is a repetition of the waveform pattern, based on the data stored in the first buffer memory, the second buffer memory, and the third buffer memory. Signal generation method. [2] The aforementioned signal generator is configured with an FPGA. The signal generation method described in [1]. [3] It comprises a user pattern memory (12) for storing arbitrarily set waveform patterns, a first buffer memory (141), a second buffer memory (142), and a third buffer memory (143), The sizes of the first buffer memory, the second buffer memory, and the third buffer memory are each the same as the memory read width of the user pattern memory. The first buffer memory stores the read data of the waveform pattern. The second buffer memory stores the read data of the waveform pattern at one clock before. The third buffer memory stores the head data of the read data of the waveform pattern. Based on the data stored in the first buffer memory, the second buffer memory, and the third buffer memory, continuous repetitive data that is the repetition of the waveform pattern is output. Signal generator (100). [4] It is composed of an FPGA. The signal generator according to [3].
Advantages of the Invention
[0012] According to the present invention, in a signal generator, for an arbitrary-length user pattern, loop output while maintaining data continuity can be performed.
[0013] The present invention has been briefly described above. Further, the details of the present invention will be further clarified by reading through the embodiments (hereinafter referred to as "embodiments") for carrying out the invention described below with reference to the accompanying drawings.
Brief Description of the Drawings
[0014] [Figure 1] It is a conceptual diagram showing a configuration example of a signal generator according to an embodiment of the present disclosure. [Figure 2] It is a conceptual diagram showing a configuration example of a signal generator according to an embodiment of the present invention. [Figure 3] It is an operation explanatory diagram according to an embodiment of the present disclosure. [Figure 4] It is a flowchart exemplifying data sequence adjustment processing according to an embodiment of the present disclosure. [Figure 5] It is a diagram showing the content of variables used in the flow of FIG. 4.
Embodiments for Carrying Out the Invention
[0015] Specific embodiments of the present invention will be described below with reference to the respective drawings.
[0016] FIG. 1 is a conceptual diagram showing a configuration example of a signal generator according to an embodiment of the present disclosure.
[0017] The signal generator 100 includes a control unit 11, a user pattern memory 12, a transceiver 13, and a data sequence adjustment unit 14. The data sequence adjustment unit 14 includes a first buffer memory 141, a second buffer memory 142, and a third buffer memory 143.
[0018] The signal generator 100 is composed of an FPGA, an ASIC, or the like. Hereinafter, it will be described assuming that the signal generator 100 is composed of an FPGA.
[0019] The control unit 11 controls the input and output of data between the memories in the signal generator 100. The control unit 11 controls the input and output of data with an external device via the transceiver 13. The control unit 11 controls various data processes in the signal generator 100 other than these.
[0020] The user pattern memory 12, the first buffer memory 141, the second buffer memory 142, and the third buffer memory 143 are configured using RAMs or registers inside the FPGA. The sizes of the first buffer memory 141, the second buffer memory 142, and the third buffer memory 143 are the same as the memory read width of the user pattern memory 12, respectively. Note that these multiple memories may be physically separate memories, or may be integrated into one or more memories.
[0021] The user pattern memory 12 stores arbitrarily set waveform patterns. The transceiver 13 is typically a gigabit transceiver.
[0022] Figure 2 is a conceptual diagram showing an example of the configuration of a signal generator according to one embodiment of the present invention.
[0023] The control unit 11 acquires waveform data. If the user specifies a user pattern, the source of the waveform data may be a waveform data file input by the user. Alternatively, waveform data may be pre-stored in a storage device 20 such as the computer's hard disk, and the control unit 11 may acquire the stored waveform data. The control unit 11 acquires information indicating the read start address and information indicating the read length.
[0024] The control unit 11 writes the acquired waveform data file to the user pattern memory 12. Based on the acquired information indicating the read start address and information indicating the read length, the control unit 11 controls the data processing in the user pattern memory 12 and the data sequence adjustment unit 14.
[0025] The signal generator 100 according to one embodiment of the present invention is independent of bit width and output frequency. However, for the sake of simplicity, an example of bit width and output frequency is shown in Figure 2. That is, the data sequence adjustment unit 14 reads data from the user pattern memory 12 at 4096 bits and 250 MHz. When reading, the data sequence adjustment unit 14 specifies the address to be read.
[0026] The transceiver 13 acquires the 4096-bit, 250MHz data output from the data sequence adjustment unit 14 and transmits it externally at 64 bits, 32 GHz. The MUX and DAC acquire the signal output from the transceiver 13 and output this signal as an analog waveform at 128 GHz, 8-bit resolution.
[0027] Figure 3 is an explanatory diagram of operation according to one embodiment of the present disclosure. Figure 3 shows a first buffer memory 141, a second buffer memory 142, a third buffer memory 143, and the output from the data sequence adjustment unit 14.
[0028] The first buffer memory 141, the second buffer memory 142, and the third buffer memory 143 each have, for example, a width of 4096 bits, and transitions to the next row by a 250 MHz clock.
[0029] The numbers in Figure 3, labeled as the first buffer memory 141, second buffer memory 142, third buffer memory 143, and output, indicate the addresses on the user pattern memory 12 corresponding to the data. 'x' means that no valid data has yet been entered into that buffer memory.
[0030] The first buffer memory 141 stores waveform pattern read data from the user pattern memory 12. The second buffer memory 142 stores waveform pattern read data from one clock cycle prior. The third buffer memory 143 stores the first data from the waveform pattern read data.
[0031] Figure 3 shows the operation of the signal generator 100 when repeatedly reading and outputting data from address 1 to address 5.25. The numbers 1 to 5 indicating addresses are for convenience only; actual addresses could be, for example, 0x1000 to 0x53FF. Since the reading unit is one address, in conventional AWGs, as described above, the 0.25 minutes of data in this example, which is less than the memory read width, would have to be skipped or compensated for, resulting in a loss of data continuity. The signal generator 100 according to this embodiment processes and outputs the data as shown below, for example, enabling loop output while maintaining data continuity for user patterns of arbitrary length.
[0032] In this example, the data sequence adjustment unit 14 reads the data four times in units of the memory access width, and uses only 1 / 4 of the data read on the fifth attempt.
[0033] [Assigning values to the buffer] Based on the control by the control unit 11, the data column adjustment unit 14 performs the value assignment process to the buffer as follows: The data in the first buffer memory 141 is assigned to the second buffer memory 142. If the data in the first buffer memory 141 is the first item, the data from the first buffer memory 141 is also substituted into the third buffer memory 143. Data is read from the user pattern memory 12 and assigned to the first buffer memory 141.
[0034] [Formation of output data and continuous output] Based on control by the control unit 11, the data sequence adjustment unit 14 outputs data by combining the data stored in the first to third buffer memories. The signal generator 100 according to one embodiment of the present invention continuously outputs repeating data, which is a repetition of a waveform pattern, based on the data stored in the first to third buffer memories.
[0035] Figure 4 is a flowchart illustrating a data column adjustment process according to one embodiment of this disclosure. Figure 5 shows the contents of the variables used in the flowchart of Figure 4. An example of the data column adjustment process will be explained with reference to both Figure 4 and Figure 5.
[0036] First, let's explain the contents of the variables shown in Figure 5. The variable Lm is the memory read access width. The variable Lp is the pattern length of the user pattern. This pattern length may not be an integer multiple of the memory read access width. The variable Af is the starting address for reading. The variable Al is the end-of-read address. The end-of-read address is the value obtained by adding an address equivalent to the length of Lp to Af. The variable Le is the remainder when Lp is divided by Lm. Expressed mathematically, this is Le = Lp mod Lm. The variable Ls is a data adjustment variable.
[0037] The variable Ac is an address counter. The variable R1 is the first buffer, i.e., the first buffer memory 141. The variable R2 is the second buffer, i.e., the second buffer memory 142. The variable R3 is the third buffer, i.e., the third buffer memory 143.
[0038] The variable Di is data read from memory (user pattern memory 12). The variable `Do` is the data to be output.
[0039] Next, an example of data column adjustment processing will be explained based on Figure 4.
[0040] The control unit 11 sets the values of the variables Lm, Lp, Af, Al, and Le respectively (St401). The control unit 11 sets the value of the address counter Ac to the value of the read start address Af. It also sets the value of the data adjustment variable Lc to 0 (St402).
[0041] The control unit 11 determines whether the termination flag is set (St403). If the termination flag is set (St403: YES), processing ends. If the termination flag is not set (St403: NO), processing proceeds to step St404. The termination flag is set when all data of the user pattern has been processed.
[0042] In step St404, the control unit 11 assigns Di to R1. That is, it writes the data read from the user pattern memory 12 to the first buffer memory 141.
[0043] The control unit 11 determines whether Ac and Af are equivalent (St405). If they are equivalent (St405: YES), the process proceeds to step St406. If they are not equivalent (St405: NO), the process proceeds to step St407.
[0044] In step St406, the control unit 11 assigns Di to R3. That is, the control unit 11 writes the data read from the user pattern memory 12 (the same data as the data in the first buffer memory 141) to the third buffer memory 143.
[0045] In step St407, the control unit 11 determines whether Ac and the value obtained by adding 1 to Af are equivalent. If they are equivalent (St407: YES), the process proceeds to step St408. If they are not equivalent (St407: NO), the process proceeds to step St409.
[0046] In step St408, the control unit 11 assigns the value obtained by right-shifting R3 to Do. The amount of this shift is Lm-Ls.
[0047] In step St409, the control unit 11 assigns the value obtained by right-shifting R2 to Do. The amount of this shift is Lm-Ls.
[0048] In step St410, the control unit 11 determines whether Ac and Al are equivalent. If they are equivalent (St410: YES), the process proceeds to step St411. If they are not equivalent (St410: NO), the process proceeds to step St419.
[0049] In step St411, the control unit 11 adds the value obtained by left-shifting R3 to Do. The amount of this shift is Ls + Le.
[0050] The control unit 11 extracts data equivalent to the number of lower Le bits from R1, and adds the left-shifted value of this data to Do (St412). The amount of the shift is Ls. If the value of Ls is 0, no left shift is performed.
[0051] The control unit 11 adds Le to Ls (St413).
[0052] The control unit 11 determines whether Ls is greater than or equal to Lm (St414). If Ls is greater than or equal to Lm (St414: YES), the process proceeds to step St415. If Ls is not greater than or equal to Lm (St414: NO), the process proceeds to step St418.
[0053] In step St415, the control unit 11 substitutes Af for Ac.
[0054] The control unit 11 substitutes the value obtained by subtracting Lm from Ls into Ls (St416).
[0055] The control unit 11 substitutes R1 for R2 (St417). That is, the control unit 11 writes the data from the first buffer memory 141 to the second buffer memory 142. Then the process returns to step St403.
[0056] In step St418, the control unit 11 substitutes Af+1 for Ac.
[0057] In step St419, the control unit 11 adds the value obtained by left-shifting R1 to Do. The amount of the shift at this time is Ls. The control unit 11 adds 1 to Ac (St420).
[0058] Once the above processing is complete (St403:YES), the data sequence adjustment unit 14 of the signal generator 100 outputs the data for which the data sequence adjustment has been completed, i.e., the data stored in Do.
[0059] By processing as described above, the signal generator 100 according to this embodiment can provide loop output that maintains data continuity for user patterns of any length.
[0060] Although various embodiments have been described above with reference to the drawings, it goes without saying that this disclosure is not limited to such examples. It is clear to those skilled in the art that various modifications or alterations can be conceived within the scope of the claims, and these will naturally also fall within the technical scope of this disclosure. For example, the steps in the methods of this disclosure can be performed in any order as long as they do not cause any inconsistencies. Furthermore, the components of the embodiments described above may be combined in any way without departing from the spirit of the disclosure. [Explanation of symbols]
[0061] 100 signal generators 11 Control Unit 12 User Pattern Memory 13 Transceivers 14. Data Column Adjustment Section 141 First Buffer Memory 142 Second Buffer Memory 143 Third Buffer Memory 20 Storage device
Claims
1. A method for generating a signal using a signal generator (100), The signal generator includes a user pattern memory (12) for storing arbitrarily set waveform patterns, a first buffer memory (141), a second buffer memory (142), and a third buffer memory (143). The sizes of the first buffer memory, the second buffer memory, and the third buffer memory are, respectively, the same size as the memory read width of the user pattern memory. A first storage step involves storing the read data of the waveform pattern in the first buffer memory, A second storage step involves storing the waveform pattern read data from one clock cycle prior, which was stored in the first buffer memory by the first storage step, in the second buffer memory. A third storage step involves storing the first data from the waveform pattern read data in the third buffer memory, The system includes a signal output step which outputs repeating data, which is a repetition of the waveform pattern, based on a combination of data stored in the first buffer memory, the second buffer memory, and the third buffer memory. Signal generation method.
2. The aforementioned signal generator is configured with an FPGA. The signal generation method according to claim 1.
3. It comprises a user pattern memory (12) for storing arbitrarily set waveform patterns, a first buffer memory (141), a second buffer memory (142), and a third buffer memory (143), The sizes of the first buffer memory, the second buffer memory, and the third buffer memory are, respectively, the same size as the memory read width of the user pattern memory. The first buffer memory stores the read data of the waveform pattern, The second buffer memory stores the waveform pattern read data from one clock cycle prior, which is stored in the first buffer memory. The third buffer memory stores the first data from the waveform pattern read data, Based on the combination of data stored in the first buffer memory, the second buffer memory, and the third buffer memory, repeating data, which is a repetition of the waveform pattern, is output continuously. Signal generator (100).
4. It is made up of FPGAs. The signal generator according to claim 3.