Display panels and display devices

Abstract

A display panel and a display device are provided, the display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller, and a plurality of line shift prevention circuits, the timing controller is configured to provide a first clock signal, the plurality of line shift prevention circuits are connected to the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal and output the second clock signal to the plurality of clock signal lines, the fall time of the falling edge of the second clock signal is smaller than the fall time of the falling edge of the first clock signal, the gate driving circuit includes a plurality of cascaded shift register units respectively connected to the plurality of clock signal lines, and is configured to output the second clock signal as an output signal, row by row, and each of the plurality of line shift prevention circuits includes at least one resistor and at least one inductor. The display panel can prevent line shift display.

Description

Technical Field

[0001] This disclosure claims the priority of Chinese Patent Application No. 202110594338.4 filed on May 28, 2021, and all the contents disclosed in the above Chinese patent application are incorporated herein by reference.

[0002] Embodiments of this disclosure relate to a display panel and a display device.

Background Art

[0003] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes a plurality of rows of gate scanning signal lines and a plurality of columns of data lines intersecting with the gate scanning signal lines. The driving of the gate scanning signal lines can be performed by an integrated driving circuit to which they are bound. In recent years, with the continuous development of the manufacturing processes of amorphous silicon thin film transistors or oxide thin film transistors, it has also become possible to directly integrate a gate scanning signal line driving circuit on a thin film transistor array substrate to form a GOA (Gate driver On Array) and drive the gate scanning signal lines. For example, an on-off state voltage signal (scanning signal) is supplied using a plurality of rows of gate scanning signal lines including a GOA of a plurality of cascaded shift register units as a pixel array, for example, a plurality of rows of gate scanning signal lines are controlled to be sequentially turned on, and a data signal is supplied to the pixel units of the corresponding row of the pixel array via the data lines, thereby forming the gray voltage required for each pixel unit to display each gray scale of an image and displaying an image of one frame.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of this disclosure is a display panel including a gate driving circuit, a plurality of clock signal lines, a timing controller, and a plurality of line shift prevention circuits, The timing controller is configured to supply a first clock signal, and the plurality of track misalignment prevention circuits are connected to the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal supplied by the timing controller to a second clock signal and to output the second clock signal to the plurality of clock signal lines, wherein the falling edge time of the second clock signal is smaller than the falling edge time of the first clock signal. The gate drive circuit includes a plurality of cascaded shift register units, each connected to one of the plurality of clock signal lines, and is configured to output the second clock signal as an output signal one line at a time, thereby shortening the falling edge time of the output signal. Each of the aforementioned multiple alignment prevention circuits provides a display panel including at least one resistor and at least one inductor.

[0005] For example, in a display panel according to at least one embodiment of the present disclosure, the at least one resistor and the at least one inductor are connected in series or in parallel.

[0006] For example, in a display panel according to at least one embodiment of the present disclosure, the first terminal of the at least one resistor is connected to the timing controller, and the second terminal of the at least one resistor is connected to the at least one inductor.

[0007] For example, in a display panel according to at least one embodiment of the present disclosure, the total resistance of the equivalent resistors of the alignment prevention circuit is 1 ohm to 1000 ohms, and the total inductance of the equivalent inductors of the alignment prevention circuit is 1 μH to 1000 μH.

[0008] For example, in a display panel according to at least one embodiment of the present disclosure, the at least one resistor includes a first resistor and a second resistor, the at least one inductor includes a first inductor and a second inductor, the first resistor and the first inductor are connected in parallel to form a first element, the second resistor and the second inductor are connected in parallel to form a second element, and the first element and the second element are connected in series.

[0009] For example, in a display panel according to at least one embodiment of the present disclosure, the total resistance of the equivalent resistor of the first element and the equivalent resistor of the second element is 1 ohm to 1000 ohms, or the total inductance of the equivalent inductor of the first element and the equivalent inductor of the second element is 1 μH to 1000 μH.

[0010] For example, in a display panel according to at least one embodiment of the present disclosure, the first clock signal includes a first level and a second level arranged sequentially in the time domain, the second clock signal includes a third level and a fourth level arranged sequentially in the time domain, the first level being higher than the second level, the third level being higher than the fourth level, and the fourth level including a first sublevel and a second sublevel, the second sublevel being between the third level and the first sublevel and lower than the first sublevel in the time domain.

[0011] For example, in a display panel according to at least one embodiment of the present disclosure, the first level and the third level are equal, and the first sub-level and the second level are equal.

[0012] For example, in a display panel according to at least one embodiment of the present disclosure, the third level includes a third sublevel and a fourth sublevel, wherein in the time domain, the fourth sublevel is between the third sublevel and the second sublevel, and the third sublevel is higher than the fourth sublevel.

[0013] For example, in a display panel according to at least one embodiment of the present disclosure, the fourth sublevel and the first level are equal.

[0014] For example, in a display panel according to at least one embodiment of the present disclosure, the first clock signal includes a first level and a second level arranged sequentially in the time domain, and the second clock signal includes a third level and a fourth level arranged sequentially in the time domain, wherein the first level is higher than the second level, the third level is higher than the fourth level, and the second level is higher than the fourth level.

[0015] For example, in a display panel according to at least one embodiment of the present disclosure, the third level is higher than the first level.

[0016] For example, a display panel according to at least one embodiment of the present disclosure further includes a level conversion circuit configured to convert the first clock signal into the second clock signal.

[0017] For example, in a display panel according to at least one embodiment of the present disclosure, the shift register unit includes an input circuit, an output circuit, and a first node control circuit, wherein the input circuit is connected to a first node and configured to charge the first node in response to an input signal; the output circuit is connected to the first node and configured to output an output signal at an output terminal under the control of a level signal of the first node; and the first node control circuit is connected to a second node and a third node, respectively, and configured to control the levels of the second node and the third node in response to the input signals.

[0018] For example, in a display panel according to at least one embodiment of the present disclosure, the shift register unit further includes a master reset circuit, which is connected to the first node and the master reset terminal and is configured to receive the master reset signal from the master reset terminal and to control the level of the first node in response to the master reset signal.

[0019] For example, in a display panel according to at least one embodiment of the present disclosure, the shift register unit further includes a first node reset circuit, which is connected to the first node and configured to reset the first node in response to a reset signal.

[0020] For example, in a display panel according to at least one embodiment of the present disclosure, the shift register unit further includes a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit, wherein the second node control circuit is connected to the first node, the second node, and the third node, respectively, and configured to control the levels of the second node and the third node under the control of the level signal of the first node; the first node noise reduction circuit is connected to the first node, the second node, and the third node, and configured to reduce noise in the first node under the control of the level signals of the second node and the third node; and the output noise reduction circuit is connected to the second node, the third node, and the output terminal, and configured to reduce noise in the output terminal under the control of the level signals of the second node and the third node.

[0021] For example, in a display panel according to at least one embodiment of the present disclosure, the output terminals include a shift output terminal and at least one scan signal output terminal.

[0022] For example, in a display panel according to at least one embodiment of the present disclosure, the at least one scanning signal output terminal includes one scanning signal output terminal, and the output circuit includes a second transistor, a third transistor, and a storage capacitor. The gate of the second transistor is connected to the first node, the first pole of the second transistor is connected to the clock signal terminal to receive the second clock signal, the second pole of the second transistor is connected to the shift output terminal, the gate of the third transistor is connected to the first node, the first pole of the third transistor is connected to the clock signal terminal to receive the second clock signal, the second pole of the third transistor is connected to the scanning signal output terminal, the first pole of the storage capacitor is connected to the first node, the second pole of the second capacitor is connected to the scanning signal output terminal, and the second clock signal is transmitted to the output terminal as the output signal.

[0023] For example, a display panel according to at least one embodiment of the present disclosure further includes a display area, a peripheral area that captures the display area, and a circuit board. The display area further includes a plurality of pixels arranged in an array, and is configured to receive and display the output signal of the gate driving circuit. The gate driving circuit and the plurality of clock signal lines are located in the peripheral area. The peripheral area includes a corner portion, and the corner portion includes a part of the shift register unit in the gate driving circuit and the plurality of clock signal lines. The timing controller and the line shift prevention circuit are located on the circuit board.

[0024] At least one embodiment of the present disclosure also provides a display device including a display panel according to any embodiment of the present disclosure.

Brief Description of the Drawings

[0025] To more clearly explain the technical solution of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present invention and do not limit the present invention. [Figure 1A]It is a schematic diagram of pixel charging timing. [Figure 1B] It is a schematic diagram of the display screen of the H-1Line in an ideal state. [Figure 1C] It is a schematic diagram of the line shift of the display screen of the H-1Line in the actual state. [Figure 2] It is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. [Figure 3] It is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. [Figure 4A] It is a schematic diagram of the first clock signal and the second clock signal according to at least one embodiment of the present disclosure. [Figure 4B] It is a schematic diagram of the output signals output by the gate drive circuit before and after adding the line shift prevention circuit according to at least one embodiment of the present disclosure. [Figure 4C] It is a schematic diagram of the parasitic capacitor of the clock signal line according to at least one embodiment of the present disclosure. [Figure 4D] It is a schematic diagram of the circuit load model according to at least one embodiment of the present disclosure. [Figure 4E] It is a schematic plan view of a display panel according to at least one embodiment of the present disclosure. [Figure 5] It is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. [Figure 6] It is a schematic diagram of the waveforms of the first clock signal and the second clock signal according to at least one embodiment of the present disclosure. [Figure 7] It is a schematic diagram of the waveforms of the second clock signal and the output signal according to at least one embodiment of the present disclosure. [Figure 8] It is an enlarged schematic diagram of the output signal according to at least one embodiment of the present disclosure. [Figure 9] It is a schematic diagram of another second clock signal according to at least one embodiment of the present disclosure. [Figure 10] It is a schematic diagram of a shift register unit according to an embodiment of the present disclosure. [Figure 11]Figure 10 is a circuit diagram of a specific example of a shift register unit. [Figure 12] This is a drive timing diagram of a shift register unit according to at least one embodiment of the present disclosure. [Figure 13] This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0026] To further clarify the object, technical solution, and advantages of the embodiments of the present invention, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments. Clearly, the embodiments described are only a part of the embodiments of the present invention, not all of them. All other embodiments that a person skilled in the art could obtain without requiring any creative effort based on the embodiments of the present invention described are within the scope of the present invention.

[0027] Unless otherwise specified, technical or scientific terms used in this disclosure have the ordinary meanings understood by those skilled in the art. Terms such as “first,” “second,” and similar terms used in this disclosure do not indicate order, quantity, or importance, but rather distinguish different components. Similarly, terms such as “one,” “one,” or “the” do not limit the number, but indicate the presence of at least one. Terms such as “includes” or “incorporates” mean that the element or article listed before the term covers the element or article and its equivalents listed after the term, but do not exclude other elements or articles. Terms such as “bonded” or “connected” include electrical coupling, whether direct or indirect, but are not limited to physical or mechanical coupling. Terms such as “up,” “down,” “left,” and “right” merely describe relative positions, and such relative positions change as the absolute position of the subject changes.

[0028] The present disclosure will be described below with reference to several specific embodiments. In order to make the following description of embodiments of the present invention clear and unambiguous, detailed descriptions of known functions and known components may be omitted. If any component of an embodiment of the present invention appears in one or more drawings, that component will be represented by the same reference numeral in each drawing.

[0029] Currently, to meet market needs and improve user experience, display products are becoming higher resolution and refresh rates. For example, the resolution and refresh rate of display screens have reached 8K and 120Hz, 4K and 240Hz, and panel manufacturers are developing more products such as 8K and 60Hz display screens with dual gates and bezel-less display screens to reduce costs. A common feature of these products is a short 1H time (1H time is the time required for, for example, one row of pixels in an LCD display panel to turn on or charge). Table 1 shows the 1H times corresponding to various display products, and the shorter the 1H time, the more difficult it is to charge the pixels in that row.

[0030] [Table 1]

[0031] For example, when charging pixels, in order to ensure that the data is displayed correctly, after the pixel charging is complete, the transmission of the effective level (e.g., high level) of the gate scan signal in the gate line must be stopped in a timely manner before charging the next row of pixels. Otherwise, a row misalignment will occur, meaning that data from the previous row will be displayed in the next row, or data from the next row will be displayed in the previous row.

[0032] Figure 1A is a schematic diagram of the pixel charging timing. For example, as shown in Figure 1A, when the gate scan signal is high level, the data signal D1 corresponding to the pixels of the first row is written to the pixels of the first row (i.e., the pixels of the first row are charged), and charging is terminated only when the gate scan signal is low level. However, because the falling edge time Tf of the gate scan signal is long, the data signal D2 corresponding to the pixels of the second row is output before the gate scan signal has completely gone low level, thus causing a row shift time t. During the row shift time t, a portion of the data signal D2 corresponding to the pixels of the second row is written to the pixels of the first row, causing distortion in the data written to the pixels of the first row, that is, in addition to the data signal D1 that should be displayed, the data signal D2 corresponding to the pixels of the second row is also included. The longer the row shift time t, the more severe the distortion.

[0033] Furthermore, when examining actual samples of display products with resolutions of 8K and refresh rates of 120Hz, serious line misalignment problems have been discovered. In particular, when the display panel displays an H-1 line screen (Pattern), the presence of line misalignment means that the screen displayed on the display product is not the ideal H-1 line display screen shown in Figure 1B (for example, as shown in Figure 1B, where black lines are displayed only as black and white lines are displayed only as white), but rather a screen where both the black of the black lines and the white of the white lines are insufficient, as shown in Figure 1C. As a result, line misalignment occurs in the H-1 line screen, meaning the display screen is completely distorted. In cases where the line misalignment is severe, all lines of the H-1 line screen are lit.

[0034] Therefore, to solve the row misalignment problem in heavily loaded H-1 line screens of display products with resolution and refresh rate of 8K and 120Hz, for example, it is necessary to reduce the load on the gate lines (resistors and capacitors). However, since the gate lines of display products with a resolution of 8K are all copper wires, and the copper thickness is the maximum possible through the process, there are limits to optimization if the load on the gate lines is reduced solely through the process, and therefore other solutions are needed.

[0035] At least one embodiment of the present disclosure provides a display panel comprising a gate drive circuit, a plurality of clock signal lines, a timing controller, and a plurality of row-shift prevention circuits, wherein the timing controller is configured to supply a first clock signal, the plurality of row-shift prevention circuits are connected to the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal supplied by the timing controller to a second clock signal and to output the second clock signal to the plurality of clock signal lines such that the falling edge time of the second clock signal is shorter than the falling edge time of the first clock signal, the gate drive circuit comprises a plurality of cascaded shift register units, each connected to the plurality of clock signal lines, the gate drive circuit is configured to output the second clock signal as an output signal one row at a time, thereby shortening the falling edge time of the output signal, and each of the plurality of row-shift prevention circuits comprises at least one resistor and at least one inductor.

[0036] In the display panel of the embodiment of this disclosure, an inductor is connected in series between the timing controller and the gate drive circuit to form an inductive load, which cancels out the capacitive load on the clock signal line. As a result, only a resistive load exists on the clock signal line, preventing the fall time of the falling edge of the clock signal from being prolonged due to parasitic capacitors on the clock signal line, and thus avoiding misaligned display. In addition, by connecting a resistor in series between the timing controller and the gate drive circuit, the current on the clock signal line is reduced, the heat generated on the clock signal line is reduced, and the performance of the display panel is improved.

[0037] The embodiments and some examples of the present disclosure will be described in detail below with reference to the drawings.

[0038] Figure 2 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. For example, the display panel may have a resolution of 8K and a refresh rate of 120Hz, but may have other resolutions or refresh rates, and the embodiments of the present disclosure are not limited thereto. For example, as shown in Figure 2, in some examples the display panel 1 includes a gate drive circuit 10. For example, as shown in Figure 2, in some other examples the display panel 1 further includes a display area 40, the display area 40 includes a pixel array connected to the gate drive circuit 10, and the pixel array includes multi-row multi-column sub-pixels 410. For example, in some other examples the display panel 1 further includes a data drive circuit 30 and a plurality of data lines DL. The plurality of data lines D are electrically connected to the plurality of columns of sub-pixels 410 and are configured to transmit data signals supplied by the data drive circuit 30 to the plurality of columns of sub-pixels 410.

[0039] For example, the data drive circuit 30 supplies data signals to the pixel array, and the gate drive circuit 10 supplies gate scanning signals to the pixel array. The data drive circuit 30 is electrically connected to the sub-pixel 410 via the data line DL, and the gate drive circuit 10 is electrically connected to the sub-pixel 410 via the gate scanning signal line GL.

[0040] For example, the gate drive circuit drives a display panel, such as a liquid crystal display panel or an organic light-emitting diode display panel, and sequentially supplies gate scanning signals to multiple gate scanning signal lines of the display panel, enabling progressive scanning, interlaced scanning, etc., while the display panel displays one frame of the screen.

[0041] Figure 3 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. For example, as shown in Figure 3, based on the example shown in Figure 2, this display panel 1 further includes a plurality of clock signal lines CLK1 to CLKm (where m is an even number greater than 0), a timing controller 300, and a plurality of lag prevention circuits. For clarity and brevity, Figure 3 shows the display area 40 and the data driving circuit 30, details of which can be found in the description of Figure 2 and will not be described in detail here.

[0042] For example, m may be 2, 4, 6, 12, 16, etc., meaning that the number of clock signal lines may be 2, 4, 6, 12, 16, etc., meaning that the number of clock signal lines is an integer multiple of 2, and the embodiments of this disclosure are not limited thereto. For example, the spacing between the multiple clock signal lines may be between 4 μm and 100 μm, for example, 4 to 20 μm, and the embodiments of this disclosure are not limited thereto.

[0043] For example, the timing controller 300 is configured to supply a first clock signal.

[0044] For example, multiple alignment prevention circuits 400 are connected to a timing controller 300 and multiple clock signal lines CLK1 to CLKm, and are configured to adjust the first clock signal supplied by the timing controller 300 into a second clock signal, and to output the second clock signal to multiple clock signal lines CLK1 to CLKm.

[0045] For example, in some cases, multiple alignment prevention circuits 400 are connected in a one-to-one correspondence with multiple clock signal lines CLK1, that is, one clock signal line is connected to one alignment prevention circuit 400, and the embodiments of this disclosure are not limited thereto.

[0046] For example, in some other examples, the alignment prevention circuit 400 may be provided between the timing controller 300 and other power lines, such as power lines supplying the first to fourth voltages to the first to fourth voltage terminals shown in Figure 10, in order to reduce peak currents, and the embodiments of this disclosure are not limited thereto.

[0047] For example, as shown in Figure 3, the gate drive circuit 10 includes multiple cascaded shift register units GOA, each connected to multiple clock signal lines CLK1 to CLKm, and the gate drive circuit 10 is configured to output the second clock signal as an output signal one line at a time, thereby shortening the falling edge time of the output signal.

[0048] For example, when m=12, as shown in Figure 3, the multiple clock signal lines include the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5, the sixth clock signal line CLK6, the seventh clock signal line CLK7, the eighth clock signal line CLK8, the ninth clock signal line CLK9, the tenth clock signal line CLK10, the eleventh clock signal line CLK11, and the twelfth clock signal line CLK12.

[0049] For example, as shown in Figure 3, the first clock signal line CLK1 is connected to the clock signal terminal of the 12n-11th stage shift register, the second clock signal line CLK2 is connected to the clock signal terminal of the 12n-10th stage shift register, the third clock signal line CLK3 is connected to the clock signal terminal of the 12n-9th stage shift register, the fourth clock signal line CLK4 is connected to the clock signal terminal of the 12n-8th stage shift register, the fifth clock signal line CLK5 is connected to the clock signal terminal of the 12n-7th stage shift register, and the sixth clock signal line CLK6 is connected to the clock signal terminal of the 12n-6th stage shift register. The 7th clock signal line CLK7 is connected to the clock signal terminal of the 12n-5th stage shift register, the 8th clock signal line CLK8 is connected to the clock signal terminal of the 12n-4th stage shift register, the 9th clock signal line CLK9 is connected to the clock signal terminal of the 12n-3rd stage shift register, the 10th clock signal line CLK10 is connected to the clock signal terminal of the 12n-2nd stage shift register, the 11th clock signal line CLK11 is connected to the clock signal terminal of the 12n-1st stage shift register, and the 12th clock signal line CLK12 is connected to the clock signal terminal of the 12nth stage shift register, where n is an integer greater than or equal to 1.

[0050] Note that the connection method to the shift register unit for other numbers of clock signal lines is similar to that for 12 clock signal lines, so it will not be explained in detail here. Of course, other connection methods may be used, and the embodiments of this disclosure are not limited thereto.

[0051] Figure 4A is a schematic diagram of the first and second clock signals according to at least one embodiment of the present disclosure, and Figure 4B is a schematic diagram of the output signals output by the gate drive circuit before and after the addition of the alignment prevention circuit 400 according to at least one embodiment of the present disclosure. For example, as shown in Figure 4A, the upper and lower waveform diagrams are a comparison diagram of the first and second clock signals at the proximal end of the timing controller 300 and a comparison diagram of the first and second clock signals at the distal end of the timing controller 300, respectively.

[0052] For example, as shown in Figure 4A, the falling edge time t1 of the second clock signal (the waveform shown by the solid line in Figure 4A) is shorter than the falling edge time t2 of the first clock signal (the waveform shown by the dotted line in Figure 4A).

[0053] For example, as shown in Figure 4B, the solid line represents the second clock signal output by the gate drive circuit as the output signal, and the dotted line represents the first clock signal output by the gate drive circuit as the output signal. As shown in Figure 4B, when the gate drive circuit 10 outputs the second clock signal as the output signal one row at a time, the falling edge time of the output signal is shortened from t2 to t1, thereby preventing row misalignment.

[0054] Figure 4C is a schematic diagram of a parasitic capacitor in a clock signal line according to at least one embodiment of the present disclosure.

[0055] For example, as shown in Figure 4C, the capacitive load on the clock signal line CLK1 originates from a parasitic capacitor C11 that occurs at the overlap point between the adapter electrode E1 of the clock signal line CLK1 and the clock signal lines CLK2 to CLKm connected to different shift register units, and a parasitic capacitor C21 that occurs at the overlap point between the gate of the output transistor of the shift register unit (third transistor T3 shown in Figure 12) and the adapter electrode E1. In some embodiments of this disclosure, by introducing an inductive load by connecting an inductor in series with the clock signal line, the capacitive load on the clock signal line (e.g., parasitic capacitors C11 and C21) can be canceled out, the impedance of the clock signal can be reduced, the falling edge time of the clock signal can be reduced, and the falling edge time of the output signal can be reduced, thereby avoiding the occurrence of misalignment.

[0056] For clarity and conciseness, the above explanation has only used the clock signal line CLK1 as an example. The remaining clock signal lines CLK2 to CLKm are similar to clock signal line CLK1, so they will not be explained in detail here.

[0057] For example, each of the multiple alignment prevention circuits 400 includes at least one resistor and at least one inductor. For example, at least one resistor and at least one inductor are connected in series or in parallel.

[0058] For example, the total resistance of the equivalent resistors of each row misalignment prevention circuit 400 is between 1 ohm (Ω) and 1000 ohms, and the total inductance of the equivalent inductors of each row misalignment prevention circuit is between 1 μH and 1000 μH. For example, in some cases, the total resistance of the equivalent resistors of each row misalignment prevention circuit 400 is 150 Ω, and the total inductance of each equivalent inductor is 100 μH. Of course, other values ​​may be used and may be determined according to the actual situation, but the embodiments of this disclosure are not limited thereto.

[0059] For example, the first terminal of at least one resistor is connected to the timing controller 300, and the second terminal of at least one resistor is connected to at least one inductor.

[0060] For example, as shown in Figure 3, the alignment prevention circuit 400 connected to the clock signal line CLK1 includes a resistor R1 and an inductor L1. For example, the alignment prevention circuit 400 connected to the clock signal line CLK2 includes a resistor R2 and an inductor L2, the alignment prevention circuit 400 connected to the clock signal line CLK3 includes a resistor R3 and an inductor L3, the alignment prevention circuit 400 connected to the clock signal line CLKm-1 includes a resistor Rm-1 and an inductor Lm-1, and the alignment prevention circuit 400 connected to the clock signal line CLKm includes a resistor Rm and an inductor Lm.

[0061] For example, the first terminals of resistors R1 to Rm are connected to the timing controller 300, the second terminals of resistors R1 to Rm are connected to the first terminals of inductors L1 to Lm, and the second terminals of inductors L1 to Lm are connected one-to-one to multiple clock signal lines CLK1 to CLKm.

[0062] For example, the resistance values ​​of each of the resistors mentioned above may be equal, for instance, the resistance value of resistor R1 = the resistance value of resistor R2 = the resistance value of resistor R3 = the resistance value of resistor Rm-1 = the resistance value of resistor Rm, for example, = 150Ω. Of course, the resistance values ​​of each of the resistors mentioned above do not have to be equal, for example, they may be determined according to the distance from the timing controller 300 to the clock signal line, and the larger the distance from the timing controller 300 to the clock signal line, the smaller the resistance value, for example, the resistance value of resistor R1 < the resistance value of resistor R2 < the value of resistor Rm. Specifically, they may be determined according to the actual situation, and the embodiments of this disclosure are not limited thereto.

[0063] For example, the inductances of each of the above inductors may be equal, for example, the inductance of inductor L1 = the inductance of inductor L2 = the inductance of inductor L3 = the inductance of inductor L3m-1 = the inductance of inductor Lm, for example, = 100 μH. Of course, the inductances of each of the above inductors do not have to be equal, for example, they may be determined according to the distance from the timing controller 300 to the clock signal line, and the larger the distance from the timing controller 300 to the clock signal line, the smaller the inductance, for example, the inductance of inductor L1 < the inductance of inductor L2 < the inductance of inductor Lm. Specifically, they may be determined according to the actual situation, and the embodiments of this disclosure are not limited thereto.

[0064] For clarity and brevity, Figure 3 only shows cases where at least one resistor includes one resistor and at least one inductor includes one inductor, and the resistors and inductors are connected in series. However, embodiments of this disclosure are not limited to this and may include multiple resistors and inductors.

[0065] Figure 4E is a schematic plan view of a display panel according to at least one embodiment of the present disclosure, which, as shown in Figure 4E, includes a display area 11 and a peripheral area 12 that incorporates the display area 11. For example, if the peripheral area 12 is curved, the peripheral area 12 includes a corner portion 13. For example, the display area 11 includes a plurality of pixels arranged in an array that receive output signals from a gate drive circuit and display them as gate scan signals. The peripheral area 12 includes structures such as a gate drive circuit 10 that drives a plurality of subpixels in the display area 11 for display, and a plurality of clock signal lines.

[0066] For example, as shown in Figure 4E, the display panel further includes a circuit board 600, and for example, a timing controller 300 and a misalignment prevention circuit 400 may be provided on the circuit board 600. The specific configuration can be found in the configurations of this field, so it will not be described in detail here.

[0067] In some cases, by connecting a resistor R1 in series to the clock signal line between the timing controller 300 and inductor L1, the temperature of the corners of the display panel can be reduced, avoiding problems such as the display panel overheating and blackening, as well as the risk of fire. In display products with a resolution of 8K and a refresh rate of 120Hz, the signal transmission frequency of the clock signal line is high, the driving capability of the shift register unit GOA is high, and the current of the clock signal line is large. In the corners of the display panel, the wiring of the clock signal line is bent and dense, and considering the bezel, the temperature is generally high. Tests with verification data have shown that when an 8K resolution, 120Hz refresh rate display panel is in operation, the temperature of the corners reaches over 70°C. By connecting a resistor in series, the temperature of the corners of the display panel can be reduced to 50°C. Therefore, by connecting a resistor in series to the clock signal line, the temperature of the corners of the display panel can be reduced, improving the user experience and extending the lifespan of the display panel.

[0068] All passive devices are equivalent to a resistor and an inductor connected in series, or a resistor and a capacitor connected in parallel and then in series. Therefore, the series connections of resistors and inductors shown in Figure 3 are all examples with the fewest devices, and in several other examples, for example, connecting an inductor in parallel next to a resistor, or connecting a resistor in parallel next to an inductor, also fall within the scope of the patent of this disclosure, and the embodiments of this disclosure are not limited thereto.

[0069] Figure 5 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. For example, as shown in Figure 5, in this example, at least one resistor comprises a first resistor R1 and a second resistor R1', and at least one inductor comprises a first inductor L1' and a second inductor L1, the first resistor R1 and the first inductor L1' are connected in parallel to form a first element 410, and the second resistor R1' and the second inductor L1 are connected in parallel to form a second element 420. For example, as shown in Figure 5, the first element 410 and the second element 420 are connected in series.

[0070] For example, in this example, the first element 410 and the second element 420 may be equivalent to inductors, and the total inductance of the equivalent inductor of the first element 410 and the equivalent inductor of the second element 420 may be 1 μH to 1000 μH. Alternatively, in some other examples, if the first element and the second element are equivalent to resistors, the total resistance of the equivalent resistor of the first element and the equivalent resistor of the second element is 1 ohm to 1000 ohms.

[0071] For example, in some other examples, the first element 410 or the second element 420 may include multiple resistors connected in series or in parallel. For example, if the anti-slip circuit 400 includes only one resistor, the resistance of that resistor may be between 1 ohm and 1000 ohms, and if it includes two resistors connected in parallel, the resistance of each resistor may be 2000 ohms, so that the parallel resistance is 1000 ohms, satisfying the requirement that the equivalent resistance of the first element 410 or the second element 420 (i.e., the total resistance of the equivalent resistors of the anti-slip circuit 400) is between 1 ohm and 1000 ohms, and the embodiments of this disclosure are not limited thereto.

[0072] For example, in some other examples, the first element 410 or the second element 420 may include multiple inductors connected in series or in parallel. For example, if the track alignment prevention circuit 400 includes only one inductor, the inductance of that inductor is 1 μH to 1000 μH, and if it includes multiple inductors connected in series or in parallel, the resistance of each inductor may be adjusted according to the actual situation, as long as the total inductance of the equivalent inductor of the first element 410 or the equivalent inductor of the second element 420 (i.e., the total inductance of the equivalent inductor of the track alignment prevention circuit 400) is 1 μH to 1000 μH, and the embodiments of this disclosure are not limited thereto.

[0073] Figure 4D is a schematic diagram of a circuit load model according to at least one embodiment of the present disclosure. For example, as shown in Figure 4D, for one circuit network, all loads may be abstracted as an RLC network, and the network impedance is as follows:

number

[0074] Here, the real part R is resistance, and the imaginary part

[0075]

number

[0076] w = 2πf is the reactance, w = 2πf is the angular frequency, f is the signal frequency, and j is the imaginary unit.

[0077] For example, the impedance amplitude is a mode of Z. As can be seen from the above equation, when C in the circuit is constant, increasing the inductor L can decrease the circuit impedance Z.

[0078]

number

[0079] In this case, the circuit impedance is at its minimum, and the resistance is R. If the inductor is increased again from this point onward, the impedance will begin to increase again.

[0080] In the display panel of the above embodiment of this disclosure, an inductor is connected in series between the timing controller and the gate drive circuit to form an inductive load, which cancels out the capacitive load on the clock signal line. As a result, only a resistive load exists on the clock signal line, preventing the fall time of the falling edge of the clock signal from being prolonged due to parasitic capacitors on the clock signal line. In addition, by connecting a resistor in series between the timing controller and the gate drive circuit, the current on the clock signal line is reduced, the heat generated on the clock signal line is reduced, and the performance of the display panel is improved.

[0081] Figure 6 is a schematic diagram of the waveforms of the first clock signal and the second clock signal according to at least one embodiment of the present disclosure, Figure 7 is a schematic diagram of the waveforms of the second clock signal and the output signal according to at least one embodiment of the present disclosure, and Figure 8 is an enlarged schematic diagram of the output signal according to at least one embodiment of the present disclosure.

[0082] For example, in a gate drive circuit, the waveform of the output signal output from the output terminal depends on the input waveform of the gate drive circuit, that is, it depends on the waveform of the second clock signal supplied by the clock signal line. For example, the waveform of the second clock signal supplied by the clock signal line includes multiple levels, and as a result, the waveform of the output signal output from the output terminal of the gate drive circuit also includes multiple levels, for example, as shown in Figure 7, where multilevel means that one low level includes multiple low levels or one high level includes multiple high levels, and the embodiments of this disclosure are not limited thereto.

[0083] For example, a multi-level second clock signal can optimize the problem of a long falling edge time for the output signal. For instance, the falling edge time can be determined based on the 10% (VGH-VGL1) to 90% (VGH-VGL1) portion of the output signal's falling edge. After the output signal waveform becomes multi-level, the falling edge of the output signal forms an undershoot, reducing the falling edge time of the output signal. For example, VGH is the first level shown in Figure 6, and VGL1 is the first voltage supplied by the first voltage terminal shown in Figure 10. When the low level output from the output terminal of the shift register unit is the conduction of the output noise reduction circuit 180 shown in Figure 10, the first voltage supplied by the first voltage terminal VGL1 is output to the output terminal, so the undershoot height of the falling edge is VGH to VGL1.

[0084] For example, in some cases, the first clock signal includes a first level VGH and a second level LVGL arranged sequentially in the time domain, and the second clock signal includes a third level VGH3 and a fourth level arranged sequentially in the time domain, where the first level VGH is higher than the second level LVGL, the third level VGH3 is higher than the fourth level, and the fourth level includes a first sub-level LVGL1 and a second sub-level LVGL2, where in the time domain, the second sub-level LVGL2 lies between the third level VGH3 and the first sub-level LVGL1. For example, in some cases, the second sub-level LVGL2 is lower than the first sub-level LVGL1, which causes the falling edge of the second clock signal to form an undershoot from the third level VGH3 to the second sub-level LVGL2, thereby shortening the falling edge time.

[0085] For example, in some cases, the first sublevel LVGL1 = -10V (volts) and the second sublevel LVGL2 = -15V, and of course, other values ​​are also possible. For example, the range of values ​​for the first and second sublevels may be -4V to -20V, and may be determined specifically according to the actual situation, and the embodiments of this disclosure are not limited thereto.

[0086] For example, the first sublevel LVG1 may be equal to the first voltage supplied by the first voltage terminal VGL1 shown in Figure 10, for example, both being -10V, and the second voltage supplied by the second voltage terminal VGL2 shown in Figure 10 may be -8V, for example, and may be specifically determined according to the actual circumstances, and the embodiments of this disclosure are not limited thereto.

[0087] For example, in some embodiments of this disclosure, the first level VGH and the third level VGH3 are high levels, and the second level LVGL and the fourth level are low levels, and the same is true in the following embodiments, so they will not be described in detail here.

[0088] For example, as shown in Figure 6, the first level VGH and the third level VGH3 are equal or nearly equal, and the first sublevel LVGL1 and the second level LVGL are equal or nearly equal, but the embodiments of this disclosure are not limited thereto.

[0089] For example, as shown in Figure 8, the gate drive circuit outputs the second clock signal as an output signal. Therefore, the falling edge of the output signal also forms an undershoot from the third level VGH3 to the second sub-level LVGL2, which shortens the falling time of the output signal's falling edge. The falling time of the output signal's falling edge can be reduced from the first time (i.e., the falling time is the horizontal distance from A1 to A3) to the second time (i.e., the falling time is the horizontal distance from A1 to A2).

[0090] Figure 9 is a schematic diagram of another second clock signal according to at least one embodiment of the present disclosure.

[0091] For example, as shown in Figure 9, in some other examples, the third level VGH3 includes the third sublevel VGH5 and the fourth sublevel VGH4, and in the time domain, the fourth sublevel VGH4 lies between the third sublevel VGH5 and the second sublevel LVGL2, i.e., in the time domain, third sublevel VGH5 > fourth sublevel VGH4 > second sublevel LVGL2 > first sublevel LVGL1.

[0092] For example, the third sublevel VGH5 is higher than the fourth sublevel VGH4. This means that when the third sublevel VGH5 of the second clock signal is output, according to the charge conservation law of capacitance, the voltage at the gate of the third transistor T3 (i.e., node N1 shown in Figure 12) can be increased, allowing the third transistor T3 to be turned on more completely. A detailed explanation of this can be found in the following description of Figures 10 to 12, so it will not be explained in detail here.

[0093] For example, in some cases, the fourth sublevel VGH4 and the first level VGH are equal or nearly equal, i.e., the fourth sublevel VGH4 and the third level VGH3 are equal or nearly equal, and the embodiments of this disclosure are not limited thereto.

[0094] For example, as shown in Figures 6 and 9, the width of the second sublevel LVGL2 and the third sublevel VGH5 may be 0.5Hm / 2H, or 0.5H-2H, where 1H is the time required to charge one row of pixels. For example, if 12 clock signal lines are included, i.e., when m=12, the width of the second sublevel LVGL2 and the third sublevel VGH5 may be 6H, i.e., 6 times or less the time required to charge one row of subpixels, and the specific width range may be determined according to the actual circumstances, and the embodiments of this disclosure are not limited thereto.

[0095] For example, in some cases, the waveform of the second clock signal may not employ multilevels, but may directly form an undershoot of VGH5~LVGL2 at the falling edge. For example, in this example, the first clock signal includes a first and second level arranged sequentially in the time domain, and the second clock signal includes a third and fourth level arranged sequentially in the time domain, with the first level being higher than the second level, the third level being higher than the fourth level, and the second level being higher than the fourth level. The third level is higher than the first level.

[0096] For example, the first level is VGH shown in Figure 6, the second level is LVGL shown in Figure 6, the third level is VGH5 shown in Figure 9, and the fourth level is LVGL2 shown in Figure 6 or Figure 9, and the width of all of these is m / 2H.

[0097] In this embodiment, the falling edge of the waveform of the second clock signal forms an undershoot of VGH5 to LVGL2, and since this undershoot is larger than the undershoot VGH-LVGL of the falling edge of the first clock signal, the falling time of the falling edge is shortened.

[0098] For example, the range of values ​​for the first level VGH, the third level VGH3, the third sub-level VGH5 and fourth sub-level VGH4 included in the third level VGH3, the third voltage supplied by the third voltage terminal VGH1 shown in Figure 10, and the fourth voltage supplied by the fourth voltage terminal VGH2 shown in Figure 10 may all be 25V to 40V. For example, in the example shown in Figure 9, the first level VGH is 32V, the third sub-level VGH5 is 36V, and the fourth sub-level VGH4 is 32V. In the example shown in Figure 6, the third level VGH3 is 32V. Specifically, these values ​​may be determined according to the actual circumstances, and the embodiments of this disclosure are not limited thereto.

[0099] For example, in some other examples, the display panel further includes a level conversion circuit (not shown) configured to convert a logic level signal to a first clock signal, or to convert the first clock signal to a second clock signal having the multi-signals shown in Figure 6 or Figure 9.

[0100] For example, in some cases, the level conversion circuit can convert a logic level into a first clock signal having multiple signals, and then output the first clock signal to a track shift prevention circuit 400, which then outputs a second clock signal having multiple signals to multiple clock signal lines. In some other cases, the level conversion circuit can convert the first clock signal into the second clock signal having multiple signals as shown in Figure 6 or Figure 9, and then input it to the track shift prevention circuit. Alternatively, the level conversion circuit may receive the second clock signal from the track shift prevention circuit, then perform multi-level setting on the second clock signal, and then output the multi-level set second clock signal to multiple clock signal lines. The embodiments of this disclosure are not limited to these examples.

[0101] For example, the clock signal employs a multi-level design with one high level and multiple low levels, or multiple high and low levels. This causes the second clock signal to form an undershoot, reducing the delay in the falling edge time and shortening the falling edge time of the output signal. This can enhance the driving capability of the gate drive circuit to some extent, making it useful for driving all kinds of products, such as 4K resolution display products, 8K resolution display products, and chip-on-film (COF) products.

[0102] For example, in some embodiments, only a multi-level configuration of the clock signal may be employed, and in such cases, the driving capability of the shift register unit can be increased to some extent.

[0103] For example, in some other cases, only resistors may be connected in series between the timing controller 300 and multiple signal lines, which effectively reduces the current in the clock signal lines and significantly lowers the temperature at the corners of the display panel. This is suitable for products with a small number of clock signal lines and sufficient charge levels.

[0104] For example, in some other cases, only an inductor may be connected in series between the timing controller 300 and multiple signal lines, with an inductance value of, for example, between 10μH and 500μH. This significantly optimizes the delay of the clock signal line and increases the driving capability of the shift register unit, which is suitable for products that require improved charge rate and have insufficient GOE edges, as well as products with horizontal lines on the screen.

[0105] The embodiments described above can be combined in any way, and the embodiments of this disclosure are not limited thereto.

[0106] For example, the shift register unit may employ circuit structures of the art, such as 4T1C, 10T4C, or 21T1C, and the embodiments of this disclosure are not limited thereto. The specific driving process can be described in the usual descriptions of the art and will not be explained in detail here.

[0107] Figure 10 is a schematic diagram of a shift register unit according to one embodiment of the present disclosure. As shown in Figure 10, the shift register unit 500 includes an input circuit 110, an output circuit 120, a first node N1, and a first node control circuit 130. A gate drive circuit can be obtained by cascading a plurality of the shift register units 500, and the gate drive circuit drives a display panel and sequentially supplies scanning signals to a plurality of gate lines of the display panel, and performs progressive scanning, interlaced scanning, etc., while displaying one frame of the screen on the display panel.

[0108] As shown in Figure 10, the input circuit 110 is connected to a first node N1 (for example, a pull-up node in this case) and configured to charge the first node N1 in response to an input signal. For example, in some examples, the input circuit 110 is connected to an input signal terminal INT and a first node N1 and configured to conduct under the control of an input signal supplied by the input signal terminal INT, thereby connecting the input signal terminal INT to the first node N1, the input signal supplied by the input signal terminal INT is input to the first node N1, and the potential of the first node N1 is charged to an operating potential (e.g., pull-up).

[0109] The output circuit 120 includes an output terminal OUT and is connected to the first node N1. It is configured to output an output signal at the output terminal OUT under the control of the level signal of the first node N1. For example, in some examples, the output circuit 120 is connected to a clock signal terminal CLK, the first node N1, and the output terminal OUT. It conducts under the control of the level signal of the first node N1 and transmits a second clock signal supplied by the clock signal terminal CLK to the output terminal OUT, which is then output as an output signal at the output terminal OUT. Alternatively, in another example, the output circuit 120 is also connected to a voltage terminal and uses a second clock signal supplied by the clock signal terminal CLK as a control signal to control whether or not to connect the voltage terminal to the output terminal OUT, and whether or not to transmit the voltage signal of the voltage terminal to the output terminal OUT and output as an output signal at the output terminal OUT.

[0110] For example, the clock signal terminal CLK is connected to one of the clock signal lines CLK1 to CLKm, receives the second clock signal, and outputs the second clock signal as an output signal to the output terminal OUT.

[0111] For example, the output terminal OUT may include multiple output terminals, such as a shift output terminal and at least one scan signal output terminal, thereby outputting a second clock signal supplied by an output signal, such as a clock signal terminal CLK, to the shift output terminal and the scan signal output terminal, thereby increasing the driving capability of the shift register unit 500. For example, in a shift register unit according to at least one embodiment of the present disclosure, at least one scan signal output terminal includes one scan signal output terminal. For example, the shift output terminal supplies an input signal and a reset signal to the next stage shift register unit 500, and the scan signal output terminal supplies a driving signal to the pixel circuit of a row of pixel units in the display panel. In this way, the influence of loads and signals within the pixel area on cascaded shift register units can be reduced. For example, the shift output terminal and the scan signal output terminal output the same output signal. In other examples, if multiple scan signal output terminals are included, each scan signal output terminal may output a different output signal, and the specific configuration will be determined according to the actual situation, and the embodiments of the present disclosure are not limited thereto.

[0112] The first node control circuit 130 is connected to the second node N2 and the third node N3, respectively, and is configured to control the levels of the second node N2 and the third node N3 in response to an input signal. For example, the first node control circuit 130 may be configured to be connected to the second node N2, the third node N3, a second voltage terminal VGL2 (e.g., supplying a low level) or a separately provided voltage terminal (e.g., a low voltage terminal), and an input terminal INT, thereby electrically connecting the second node N2, the third node N3, and the second voltage terminal VGL2 or the low voltage terminal under the control of an input signal input by the input terminal INT, and ensuring that the levels of the second node N2 and the third node N3 are pulled down to a second voltage during the first node N1 pull-up stage.

[0113] In this embodiment, the "effective output level" of the shift register unit means the level at which the switching transistor in the pixel circuit of the display panel connected to the shift register unit conducts, allowing a data signal to be written to the pixel circuit. In this case, the "ineffective output level" means the level at which the switching transistor in the pixel circuit connected to the shift register unit conducts (i.e., cuts off the switching transistor). Depending on factors such as the type of switching transistor in the pixel circuit (N-type or P-type), the effective output level may be higher or lower than the ineffective output level. Normally, during the operating period of the shift register unit, the output terminal outputs a square wave pulse signal, the effective output level corresponds to the level of the square wave pulse portion of the square wave pulse signal, and the ineffective output level corresponds to the level of the portion other than the square wave pulse.

[0114] In some examples, as shown in Figure 10, the shift register unit further includes a first node reset circuit 150.

[0115] The first node reset circuit 150 is connected to the first node N1 and configured to reset the first node N1 in response to a reset signal. For example, the first node reset circuit 150 may be configured to connect to the first node N1, a second voltage terminal VGL2 (e.g., supplying a low level) or another voltage terminal (e.g., a low voltage terminal) and a reset terminal RST, thereby electrically connecting the first node N1 to the second voltage terminal VGL2 or the low voltage terminal, and pulling down and resetting the first node N1 under the control of a reset signal input by the reset terminal RST.

[0116] As shown in Figure 10, in some examples, the shift register unit 500 may further include a second node control circuit 160, a first node noise reduction circuit 170, and an output noise reduction circuit 180.

[0117] The second node control circuit 160 is connected to the first node N1, the second node N2, and the third node N3, and is configured to control the levels of the second node N2 and the third node N3 under the control of the level signal of the first node N1. For example, in one example, the second node control circuit 160 is connected to the first node N1, the second node N2, the third node N3, the second voltage terminal VGL2, the third voltage terminal VGH1, and the fourth voltage terminal VGH2 or an otherwise provided voltage terminal (e.g., a high voltage terminal), and is configured to pull down the second node N2 and the third node N3 to a low level, and when the first node N1 is at a low level, it connects the second node N2 and the third node N3 to one of the third voltage terminal VGH1 or the fourth voltage terminal VGH2, and when the first node N1 is at a high level, for example, it connects the second node N2 and the third node N3 to the second voltage terminal VGL2 or an otherwise provided voltage terminal (e.g., a low voltage terminal), and is configured to pull down the second node N2 and the third node N3 to a low level.

[0118] For example, in another example, the level of the second node N2 is controlled by the level of the first node N1 and the third voltage from the third voltage terminal VGH1, and the level of the third node N3 is controlled by the level of the first node N1 and the fourth voltage from the fourth voltage terminal VGH2. The specific connection method will be explained in detail below.

[0119] For example, in one example, the third voltage terminal VGH1 and the fourth voltage terminal VGH2 may be configured to alternately receive high levels, that is, when the third voltage terminal VGH1 receives a high level, the fourth voltage terminal VGH2 receives a low level, and conversely, when the third voltage terminal VGH1 receives a low level, the fourth voltage terminal VGH2 receives a high level, thereby causing the second node N2 and the third node N3 to operate alternately, the transistors connected to them to operate alternately, and the lifespan of these transistors to be extended. For example, in another example, the third voltage terminal VGH1 and the fourth voltage terminal VGH2 may be replaced with clock signal terminals that alternately supply high levels (or DC low levels if the implemented transistors are P-type), and the embodiments of this disclosure are not limited thereto.

[0120] The first node noise reduction circuit 170 is connected to the first node N1, the second node N2, and the third node N3, and is configured to reduce the noise of the first node N1 under the control of the levels of the second node N2 and the third node N3. For example, the first node noise reduction circuit 170 is connected to the first node N1, the second node N2, the third node N3, and the second voltage terminal VGL2, and is configured to conduct when the second node N2 and the third node N3 are, for example, at a high level, thereby connecting the first node N1 to the second voltage terminal VGL2 or another voltage terminal (e.g., a low voltage terminal), and reducing the noise of the first node N1 by pulling down the potential of the first node N1 to a non-operating potential.

[0121] The output noise reduction circuit 180 is connected to the second node N2, the third node N3, and the output terminal OUT, and is configured to reduce noise at the output terminal OUT under the control of the levels of the second node N2 and the third node N3. For example, the output noise reduction circuit 180 is connected to the second node N2, the third node N3, the second voltage terminal VGL2, and the output terminal OUT, and is configured to conduct when the second node N2 is, for example, at a high level, thereby reducing noise at the output terminal OUT by connecting it to the second voltage terminal VGL2 or another voltage terminal (for example, a low voltage terminal).

[0122] As shown in Figure 10, in some other examples, the shift register unit 500 further includes a master reset circuit 190.

[0123] For example, the master reset circuit 190 is connected to the first node N1 and configured to reset the first node N1 in response to a master reset signal. For example, the master reset circuit 190 may be configured to connect to the first node N1, a second voltage terminal VGL2 (e.g., supplying a low level) or another voltage terminal (e.g., a low voltage terminal) and a master reset terminal TRST, so that under the control of a master reset signal input by the master reset terminal TRST, the first node N1 can be electrically connected to the second voltage terminal VGL2 or the low voltage terminal, thereby pulling down and resetting the first node N1.

[0124] For example, the first voltage terminal VGL1 is configured to supply a DC low-level signal (e.g., below the low-level portion of a clock signal) and, for example, to be grounded. Here, this DC low-level signal is referred to as the first voltage, and the same applies to each of the following embodiments, so it will not be explained in detail here.

[0125] For example, the second voltage terminal VGL2 is configured to supply a DC low-level signal (e.g., below the low-level portion of a clock signal) and, for example, to ground. Here, the DC low-level signal is referred to as the second voltage, and for example, the second voltage may be less than or equal to the first voltage. The same applies to each of the following embodiments, so they will not be explained in detail here.

[0126] For example, the third voltage terminal VGH1 is configured to supply a DC high-level signal, and the signal supplied by the third voltage terminal VGH1 is called the third voltage. Similarly, the fourth voltage terminal VGH2 is configured to supply a DC high-level signal, and the signal supplied by the fourth voltage terminal VGH2 is called the fourth voltage. For example, the third and fourth voltages may be the same voltage, and both may be greater than the first and second voltages. The same applies to each of the following embodiments, so they will not be explained in detail here.

[0127] Figure 11 is a circuit diagram of a specific example of the shift register unit shown in Figure 10. As shown in Figure 11, the shift register unit 500 further includes the second to 29th transistors T2 to T29 and the storage capacitor C. In the following description, the case in which each transistor is an N-type transistor will be used as an example, but this is not limited to the embodiments of this disclosure.

[0128] The input circuit 110 may be implemented as a fourth transistor T4. The fourth transistor T4 is configured such that its gate and first pole are electrically connected to each other and both are connected to the input terminal INT to receive the input signal, and its second pole is connected to the first node N1, so that when the fourth transistor T4 receives a conduction signal (e.g., a high-level signal) from the input terminal INT and becomes conductive, it uses the conduction signal to charge the first node N1 and raise it to a high level. For example, the gate and first pole of the fourth transistor T4 may be connected to the input terminal INT or other high-voltage terminals (e.g., a third voltage terminal VGH1 or a fourth voltage terminal VGH2), and the embodiments of this disclosure are not limited thereto.

[0129] The output circuit 120 may be implemented to include a comprehensive second transistor T2, a third transistor T3, and a storage capacitor C. The gate of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the clock signal terminal CLK to receive the second clock signal, and the second pole of the second transistor T2 is connected to the shift output terminal CR. The gate of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the clock signal terminal CLK to receive the second clock signal, and the second pole of the third transistor T3 is connected to the scan signal output terminal OUT1 (i.e., the output terminal Gout shown in Figure 3). The first pole of the storage capacitor C is connected to the first node N1, and the second pole of the storage capacitor C is connected to the scan signal output terminal OUT1. However, the shift register unit may further include more output signals and scan signal output terminals corresponding to these output signals.

[0130] For example, the clock signal terminal CLK is connected to the clock signal lines CLK1 to CLKm shown in Figure 3, and receives the second clock signal in the above embodiment.

[0131] The first node control circuit 130 may be implemented as the 14th transistor T14 and the 24th transistor T24. The gate of the 14th transistor T14 is connected to the input terminal INT to receive the input signal, the first pole of the 14th transistor T14 is connected to the first pole and the second node N2, and the second pole of the 14th transistor T14 is connected to the second voltage terminal VGL2. The gate of the 24th transistor T24 is connected to the input terminal INT to receive the input signal, the first pole of the 24th transistor T24 is connected to the first pole and the third node N3, and the second pole of the 24th transistor T24 is connected to the second voltage terminal VGL2.

[0132] The first node reset circuit 150 may be implemented as a fifth transistor T5. The fifth transistor T5 is configured such that its gate is connected to a reset terminal RST to receive a reset signal, its first pole is connected to the first node N1, and its second pole is connected to a second voltage terminal VGL2 to receive a second voltage. When the fifth transistor T5 conducts in response to a reset signal, the first node N1 can be reset by electrically connecting the first node N1 and the second voltage terminal VGL2. For example, the reset terminal RST may be connected to the output terminal of a shift register cascaded to the reset terminal RST, thereby resetting the first node N1 of the shift register unit in this stage in real time at the shift output of the gate scan signal and avoiding erroneous output from the output terminal.

[0133] The master reset circuit 190 may be implemented as a sixth transistor T6. The sixth transistor T6 has its gate connected to the master reset terminal TRST to receive the master reset signal, its first pole connected to the first node N1, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. When the sixth transistor T6 conducts in response to the master reset signal, the first node N1 can be reset by electrically connecting the first node N1 and the second voltage terminal VGL2. For example, the master reset circuit 190 is configured to globally reset all cascaded shift register units at the start or end of the display stage of one frame of an image. For example, the timing of the master reset signal is faster than the trigger signal (described in detail below) that controls the start of the display stage of one frame of an image, thereby resetting the first node N1 of all shift register units at the start of the display stage of one frame of an image and avoiding display screen abnormalities.

[0134] For example, in one example, the second node control circuit 160 may be implemented as the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10. The seventh transistor T7 has its gate connected to the first control node CN1, its first pole connected to the third voltage terminal VGH1 to receive the third voltage, and its second pole connected to the second node N2. The eighth transistor T8 has its gate connected to the first node N1, its first pole connected to the second node N2, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. The ninth transistor T9 has its gate and its own first pole electrically connected to each other, both configured to receive the third voltage by connecting to the third voltage terminal VGH1, and its second pole connected to the first control node CN1. The tenth transistor T10 has its gate connected to the first node N1, its first pole connected to the first control node CN1, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage.

[0135] For example, in another example, the second node control circuit 160 further includes the 27th transistor T27, the 28th transistor T28, the 29th transistor T29, and the 20th transistor T20. The 27th transistor T27 has its gate connected to the second control node CN2, its first pole connected to the fourth voltage terminal VGH2 to receive the fourth voltage, and its second pole connected to the third node N3. The 28th transistor T28 has its gate connected to the first node N1, its first pole connected to the third node N3, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. The 29th transistor T29 has its gate and its first pole electrically connected to each other, both connected to the 4th voltage terminal VGH2 to receive the 4th voltage, and its second pole connected to the 2nd control node CN2. The 20th transistor T20 has its gate connected to the 1st node N1, its first pole connected to the 2nd control node CN2, and its second pole connected to the 2nd voltage terminal VGL2 to receive the 2nd voltage.

[0136] The first node noise reduction circuit 170 may be implemented as the 11th transistor T11 and the 21st transistor T21. The 11th transistor T11 has its gate connected to the second node N2, its first pole connected to the first node N1, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. The 11th transistor T11 conducts when the second node N2 is at a high potential, and by connecting the first node N1 to the second voltage terminal VGL2, it can pull down the first node N1 and achieve noise reduction. The 21st transistor T21 has its gate connected to the third node N3, its first pole connected to the first node N1, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. The 21st transistor T21 conducts when the third node N3 is at a high potential, and by connecting the first node N1 to the second voltage terminal VGL2, it can pull down the first node N1 and achieve noise reduction. For example, the 11th transistor T11 and the 21st transistor T21 operate alternately under the control of the levels of the 2nd node N2 and the 3rd node N3, respectively, which extends the service life of these transistors.

[0137] For example, in one example, the output terminal OUT includes a shift output terminal CR and one scan signal output terminal OUT1 (i.e., the output terminal Gout of the gate drive circuit), and the output noise reduction circuit 180 may be implemented as a 12th transistor T12, a 22nd transistor T22, a 13th transistor T13, and a 23rd transistor T23. The 12th transistor T12 and the 22nd transistor T22 are for noise reduction of the shift output terminal CR, and the 13th transistor T13 and the 23rd transistor T23 are for noise reduction of the scan signal output terminal OUT1. If there are more scan signal output terminals, the output noise reduction circuit 180 may include more transistors to achieve noise reduction of the scan signal output terminals.

[0138] The 12th transistor T12 has its gate connected to the second node N2, its first pole connected to the shift output terminal CR, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. The 12th transistor T12 conducts when the second node N2 is at a high potential, and by connecting the shift output terminal CR to the second voltage terminal VGL2, noise reduction can be achieved at the shift output terminal CR. The 22nd transistor T22 has its gate connected to the third node N3, its first pole connected to the shift output terminal CR, and its second pole connected to the second voltage terminal VGL2 to receive the second voltage. The 22nd transistor T22 conducts when the third node N3 is at a high potential, and by connecting the shift output terminal CR to the second voltage terminal VGL2, noise reduction can be achieved at the shift output terminal CR. For example, the lifespan of the 12th transistor T12 and the 22nd transistor T22 is extended by operating them alternately under the control of the levels of the second node N2 and the third node N3, respectively.

[0139] The 13th transistor T13 has its gate connected to the second node N2, its first pole connected to the scan signal output terminal OUT1, and its second pole connected to the first voltage terminal VGL1 to receive the first voltage. The 13th transistor T13 conducts when the second node N2 is at a high potential, reducing noise at the scan signal output terminal OUT1 by connecting it to the first voltage terminal VGL1. The 23rd transistor T23 has its gate connected to the third node N3, its first pole connected to the scan signal output terminal OUT1, and its second pole connected to the first voltage terminal VGL1 to receive the first voltage. The 23rd transistor T23 conducts when the third node N3 is at a high potential, reducing noise at the scan signal output terminal OUT1 by connecting it to the first voltage terminal VGL1. For example, the lifespan of the 13th transistor T13 and the 23rd transistor T23 is extended by operating alternately under the control of the levels of the second node N2 and the third node N3, respectively.

[0140] In embodiments of the present disclosure, for example, when each circuit is implemented as an N-type transistor, the terms “pull-up” mean charging one node or one electrode of one transistor to raise the absolute value of the level of the node or electrode and to enable the operation of the corresponding transistor (e.g., conduction), and “pull-down” means discharging one node or one electrode of one transistor to lower the absolute value of the level of the node or electrode and to enable the operation of the corresponding transistor (e.g., cutoff).

[0141] Furthermore, for example, if each circuit is implemented as a P-type transistor, the term "pull-up" means discharging one node or one electrode of one transistor to lower the absolute value of the level of that node or electrode and enable the operation of the corresponding transistor (e.g., conduction), while "pull-down" means charging one node or one electrode of one transistor to raise the absolute value of the level of that node or electrode and enable the operation of the corresponding transistor (e.g., cutoff).

[0142] In the description of each embodiment of this disclosure, the first node N1, the second node N2, the third node N3, the first control node CN1, and the second control node CN2 are not actual existing components, but rather related junctions that are electrically connected in the circuit diagram.

[0143] In addition, all transistors used in the embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics, but in the embodiments of this disclosure, thin-film transistors will be used as an example. The source and drain of the transistors used here may be structurally symmetrical, and therefore, the source and drain are structurally the same. In the embodiments of this disclosure, in order to distinguish between the two poles other than the gate of the transistor, one pole will be described as the first pole and the other pole as the second pole.

[0144] Furthermore, in the embodiments of this disclosure, all transistors are described using N-type transistors as examples, in which case the first pole of the transistor is the drain and the second pole is the source. However, this disclosure includes, but is not limited to, N-type transistors. For example, one or more transistors in the shift register unit 500 according to embodiments of this disclosure may be P-type transistors, in which case the first pole of the transistor is the source and the second pole is the drain, and each pole of the type of transistor used may be connected with reference to the corresponding poles of the transistors in embodiments of this disclosure, and the corresponding high or low voltage may be supplied by the corresponding voltage terminals. When N-type transistors are used, indium gallium zinc oxide (IGZO) may be used as the active layer of the thin-film transistor, and when low-temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) is used as the active layer of the thin-film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0145] Figure 12 is a drive timing diagram of a shift register unit according to at least one embodiment of the present disclosure. The potential heights in the signal timing diagram shown in Figure 12 are illustrative only and do not represent actual potential values ​​or relative ratios. In the example above, the high-level signals correspond to the ON signals of the N-type transistors, and the low-level signals correspond to the cutoff signals of the N-type transistors.

[0146] For example, the operating principle of the Nth stage shift register unit 500 of the gate drive circuit 10 shown in Figure 11 will be explained below with reference to the signal timing diagram shown in Figure 12. The operating principle of the shift register unit 500 is as follows.

[0147] In the first stage 1, the input terminal INT is supplied with a high level, and the clock signal terminal CLK is supplied with a low level of the second clock signal. As a result, the fourth transistor T4 conducts, the first node N1 is charged to a first high level, the 14th transistor T14 and the 24th transistor T24 conduct, and the second node N2 and the third node N3 are pulled down to a low level. At this stage, the second transistor T2 and the third transistor T3 conduct in response to the first high level of the first node N1, and output the low level of the second clock signal supplied by the clock signal terminal CLK to the shift output terminal CR and the scan signal output terminal OUT1.

[0148] In the second stage 2, the input terminal INT receives a low level input, the clock signal terminal CLK receives a high level of the second clock signal, the second pole of the storage capacitor C changes from a low level to a high level, and due to the characteristic that the voltage across the capacitor does not change abruptly, the voltage at the first pole of the storage capacitor C (i.e., the first node N1) is bootstrapped. As a result, in this stage, the first node N1 is charged to the second high level, the second transistor T2 and the third transistor T3 conduct in response to the second high level of the first node N1, and in this stage, the shift output terminal CR and the scan signal output terminal OUT1 of the shift register unit output high levels.

[0149] For example, at this stage, if the second clock signal adopts the waveform shown in Figure 9, the voltage at the first pole of the storage capacitor C (i.e., the first node N1) is bootstrapped due to the characteristic that the voltage across the capacitor does not change abruptly. As a result, at this stage, the first node N1 is charged to the third sub-level VGH5, and the voltage at the first node N1 is bootstrapped higher. This leads to more complete conduction of the second transistor T2 and the third transistor T3, which is advantageous for the output of the second clock signal.

[0150] In the third stage 3, the clock signal terminal CLK supplies a low level of the second clock signal, the second pole of the storage capacitor C changes from a high level to a low level, and due to the characteristic that the voltage across the capacitor does not change abruptly, the voltage at the first pole of the storage capacitor C (i.e., the first node N1) changes to a first high level. Therefore, at this stage, the second transistor T2 and the third transistor T3 conduct in response to the first high level at the first node N1, and the shift output terminal CR and the scan signal output terminal OUT1 of the shift register unit output a low level of the second clock signal.

[0151] In the fourth stage, 4, the reset terminal RST supplies a high level reset signal, causing the fifth transistor T5 to conduct, the first node N1 to connect to the second voltage terminal VGL2, the voltage at the first node N1 to change to a low level, and the second node N2 and third node N3 to change to high levels. Therefore, in this stage, the second transistor T2 and third transistor T3 are cut off in response to the low level at the first node N1, the twelfth transistor T12, the twenty-second transistor T22, the thirteenth transistor T13, and the twenty-third transistor T23 to conduct, and the shift output terminal CR and the scan signal output terminal OUT1 of the shift register unit output low levels.

[0152] Before the first stage 1 begins, the master reset terminal TRST supplies a high level of the master reset signal, causing the sixth transistor T6 to conduct, which in turn resets the first node N1 of all shift register units in the gate drive circuit.

[0153] At least one embodiment of the present disclosure also provides a display device. Figure 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. For example, as shown in Figure 13, the display device 100 includes a display panel 1 according to any embodiment of the present disclosure.

[0154] In this embodiment, the display device 100 may be any product or component having a display function, such as a liquid crystal panel, liquid crystal television, display, OLED panel, OLED television, electronic paper display device, mobile phone, tablet, laptop, digital frame, or navigator. The display device 100 may also include other common components such as display panels, and the embodiments of this disclosure are not limited thereto.

[0155] The technical effects of the display device 100 according to the embodiments of this disclosure should be explained in detail here, as they can be found in the corresponding descriptions of the display panels in the embodiments described above.

[0156] For clarity and brevity, not all structures of the display device 100 are shown. Those skilled in the art may install other structures not shown, depending on the specific application, to realize the essential functions of the display device, and the embodiments of this disclosure are not limiting such installations.

[0157] Furthermore, the following should be explained. (1) The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures may refer to conventional designs. (2) Insofar as there is no contradiction, new embodiments can be obtained by combining the embodiments and features of the embodiments of this disclosure with each other.

[0158] The foregoing are exemplary embodiments of the present disclosure and do not limit the scope of the present disclosure, which is defined by the appended claims. [Explanation of Symbols]

[0159] 1 Display Panel 10 Gate drive circuit 11 Display area 12 Peripheral area 13 Corner section 30 Data-driven circuits 40 display area 410 subpixels, 1st element 420 Second element 500 Shift Register Unit

Claims

1. A display panel including a gate drive circuit, multiple clock signal lines, a timing controller, and multiple row misalignment prevention circuits, The timing controller is configured to supply a first clock signal. The plurality of alignment prevention circuits are connected to the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal supplied by the timing controller to a second clock signal, and to output the second clock signal to the plurality of clock signal lines, wherein the falling edge time of the second clock signal is smaller than the falling edge time of the first clock signal. The gate drive circuit includes a plurality of cascaded shift register units, each connected to one of the plurality of clock signal lines, and is configured to output the second clock signal as an output signal, one line at a time. Each of the aforementioned plurality of alignment prevention circuits includes at least one resistor and at least one inductor. The at least one resistor includes a first resistor and a second resistor, and the at least one inductor includes a first inductor and a second inductor. The first resistor and the first inductor are connected in parallel to form a first element, and the second resistor and the second inductor are connected in parallel to form a second element. The first element and the second element are connected in series in a display panel.

2. The display panel according to claim 1, wherein the at least one resistor and the at least one inductor are connected in series or in parallel.

3. The display panel according to claim 1 or 2, wherein the first terminal of the at least one resistor is connected to the timing controller, and the second terminal of the at least one resistor is connected to the at least one inductor.

4. The total resistance value of the equivalent resistors of each of the aforementioned multiple alignment prevention circuits is between 1 ohm and 1000 ohms. The display panel according to any one of claims 1 to 3, wherein the total inductance of each equivalent inductor of the plurality of alignment prevention circuits is 1 μH to 1000 μH.

5. The total resistance value of the equivalent resistors of the first element and the second element is 1 ohm to 1000 ohms, or The display panel according to claim 4, wherein the total inductance of the equivalent inductor of the first element and the equivalent inductor of the second element is 1 μH to 1000 μH.

6. The first clock signal includes a first level and a second level arranged sequentially in the time domain, and the second clock signal includes a third level and a fourth level arranged sequentially in the time domain. The first level is higher than the second level, and the third level is higher than the fourth level. The aforementioned fourth level includes a first sublevel and a second sublevel, In the aforementioned time domain, the second sublevel lies between the third level and the first sublevel. The display panel according to any one of claims 1 to 5, wherein the second sublevel is lower than the first sublevel.

7. The display panel according to claim 6, wherein the first level and the third level are equal, and the first sub-level and the second level are equal.

8. The aforementioned third level includes a third sublevel and a fourth sublevel, In the aforementioned time domain, the fourth sublevel lies between the third sublevel and the second sublevel. The display panel according to claim 6 or 7, wherein the third sublevel is higher than the fourth sublevel.

9. The display panel according to claim 8, wherein the fourth sublevel and the first level are equal.

10. The first clock signal includes a first level and a second level arranged sequentially in the time domain, and the second clock signal includes a third level and a fourth level arranged sequentially in the time domain, wherein the first level is higher than the second level, and the third level is higher than the fourth level. The display panel according to any one of claims 1 to 5, wherein the second level is higher than the fourth level.

11. The display panel according to claim 10, wherein the third level is higher than the first level.

12. The display panel according to any one of claims 6 to 11, further comprising a level conversion circuit configured to convert the first clock signal into a second clock signal.

13. Each of the aforementioned multiple shift register units includes an input circuit, an output circuit, and a first node control circuit. The input circuit is connected to the first node and configured to charge the first node in response to an input signal. The output circuit is connected to the first node and configured to output an output signal at the output terminal under the control of the level of the first node. The display panel according to any one of claims 1 to 12, wherein the first node control circuit is connected to the second node and the third node, respectively, and is configured to control the levels of the second node and the third node in response to the input signal.

14. Each of the aforementioned shift register units further includes a master reset circuit, The display panel according to claim 13, wherein the master reset circuit is connected to the first node and the master reset terminal, and is configured to receive a master reset signal from the master reset terminal and to control the level of the first node in response to the master reset signal.

15. Each of the aforementioned shift register units further includes a first node reset circuit, The display panel according to claim 13 or 14, wherein the first node reset circuit is connected to the first node and configured to reset the first node in response to a reset signal.

16. Each of the aforementioned multiple shift register units further includes a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit. The second node control circuit is connected to the first node, the second node, and the third node, respectively, and is configured to control the levels of the second node and the third node under the control of the level of the first node. The first node noise reduction circuit is connected to the first node, the second node, and the third node, and is configured to reduce noise in the first node under the control of the levels of the second node and the third node. The display panel according to any one of claims 13 to 15, wherein the output noise reduction circuit is connected to the second node, the third node and the output terminal and is configured to reduce noise at the output terminal under the control of the levels of the second node and the third node.

17. The display panel according to any one of claims 13 to 16, wherein the output terminals include a shift output terminal and at least one scan signal output terminal.

18. The at least one scan signal output terminal includes one scan signal output terminal, and the output circuit includes a second transistor, a third transistor, and a storage capacitor. The gate of the second transistor is connected to the first node, the first pole of the second transistor is connected to the clock signal terminal to receive the second clock signal, and the second pole of the second transistor is connected to the shift output terminal. The gate of the third transistor is connected to the first node, the first pole of the third transistor is connected to the clock signal terminal to receive the second clock signal, and the second pole of the third transistor is connected to the scan signal output terminal. The first pole of the storage capacitor is connected to the first node, and the second pole of the storage capacitor is connected to the scan signal output terminal. The display panel according to claim 17, wherein the second clock signal is transmitted to the output terminal as the output signal.

19. The system further includes a display area, a peripheral area that captures the display area, and a circuit board. The display area further includes a plurality of pixels arranged in an array, and is configured to receive and display the output signal of the gate drive circuit. The gate drive circuit and the plurality of clock signal lines are located in the peripheral region, the peripheral region includes a corner portion, and the corner portion includes a part of the shift register unit in the gate drive circuit and the plurality of clock signal lines. The display panel according to any one of claims 1 to 18, wherein the timing controller and the alignment prevention circuit are located on the circuit board.

20. A display device including a display panel according to any one of claims 1 to 19.

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