Semiconductor equipment

Abstract

It suppresses transistor degradation. [Solution] The method comprises a first period and a second period. In the first period, the first transit The zista and the second transistor repeatedly switch on and off alternately, and the third transistor and The fourth transistor is turned off. During the second period, the first transistor and the second The transistor turns off, and the third and fourth transistors turn on alternately. It repeatedly switches between being on and off. In this way, the time the transistor is on can be shortened. Therefore, it suppresses the degradation of transistor characteristics.

Description

Technical Field

[0001] Relates to a semiconductor device, a display device, a liquid crystal display device, a driving method thereof, or a method for producing them. In particular, it relates to a semiconductor device, a display device, a liquid crystal display device having a driving circuit formed on the same substrate as the pixel portion, or a driving method thereof. Or, it relates to an electronic device having the semiconductor device, the display device, or the liquid crystal display device.

Background Art

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal TVs. In particular, the technology of forming a driving circuit such as a gate driver on the same substrate as the pixel portion using a transistor composed of a non-single crystal semiconductor greatly contributes to cost reduction and reliability improvement, and thus is actively developed. A transistor composed of a non-single crystal semiconductor causes deterioration such as an increase in threshold voltage or a decrease in mobility. As this transistor deterioration progresses, there are problems such as the driving circuit becoming difficult to operate and the inability to display an image. Therefore, Patent Document 1, Patent Document 2, and Non-Patent Document 1 disclose a shift register capable of suppressing transistor deterioration. In these documents, two transistors are used to suppress the characteristic deterioration of the transistor. These two transistors are connected between the output terminal of the flip-flop and the wiring to which VSS (hereinafter, negative power supply) is supplied. Then, one transistor and the other transistor are alternately turned on. By doing so, the time for the transistor to be turned on becomes short, so that the characteristic deterioration of the transistor can be suppressed.

[0003] ​ [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2005-50502 [Patent Document 2] Japanese Patent Publication No. 2006-24350 [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, p.333-336 [Overview of the project] [Problems that the invention aims to solve]

[0006] In conventional technology, the time a transistor is on is about half the duration of one frame. Alternatively, to ensure that the shift register operates even if the transistor's characteristics degrade, The channel width of the transistor needs to be increased. Or, the channel width of the transistor needs to be increased. This makes it easier for the transistor's gate to short-circuit with its source or drain. Yes. Or, as the channel width of the transistor increases, each component of the shift register Parasitic capacitance in transistors increases. Or, the transistors that make up the shift register... When the parasitic capacitance in the zista increases, the circuit that supplies signals or voltages to the shift register and Therefore, it is necessary to use a circuit with a large current capacity.

[0007] In view of the above issues, one aspect of the present invention aims to shorten the time that the transistor is turned on. The title is as follows: Alternatively, one aspect of the present invention aims to suppress the degradation of transistor characteristics. Alternatively, one aspect of the present invention aims to reduce the channel width of a transistor. Alternatively, one aspect of the present invention aims to reduce the layout area. One aspect of the present invention aims to narrow the bezel of a display device. One embodiment of the present invention aims to improve the resolution of the display device. Alternatively, one embodiment of the present invention aims to improve the yield The objective is to increase the height of the ball. Alternatively, one aspect of the present invention aims to reduce costs. The problem is to reduce signal distortion or delay. Alternatively, one aspect of the present invention aims to reduce signal distortion or delay. To do so. Alternatively, one aspect of the present invention aims to reduce power consumption. Alternatively, this invention One aspect of the present invention aims to reduce the current capacity of the external circuit. Alternatively, one aspect of the present invention aims to reduce the current capacity of the external circuit. The embodiment reduces the size of the external circuit, or the size of the display device having said external circuit. The following are the issues to be addressed. Note that the description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of the above-mentioned problems. [Means for solving the problem]

[0008] One aspect of the present invention is a first switch electrically connected between a first wire and a second wire. , a second switch electrically connected between the first wiring and the second wiring, the first wiring and the A third switch electrically connected between the two wires, and between the first wire and the second wire. A drive circuit including a fourth switch electrically connected between them, and a pixel including a liquid crystal element, A driving method for a liquid crystal display device, wherein a first switch and a second switch are non-conductive a first period in which the state is set, and a second period in which a third switch and a fourth switch are non-conductive This is a driving method for a liquid crystal display device having the above.

[0009] In one aspect of the present invention, the first period and the second period may be repeatedly arranged in this order if necessary.

[0010] In one aspect of the present invention, the first period and the second period may be approximately equal in length if necessary.

[0011] One aspect of the present invention is a driving method for a liquid crystal display device including a driving circuit including a first switch electrically connected between a first wiring and a second wiring, a second switch electrically connected between the first wiring and the second wiring, a third switch electrically connected between the first wiring and the second wiring, and a fourth switch electrically connected between the first wiring and the second wiring, and a pixel including a liquid crystal element, wherein a first sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a second sub-period in which the first switch is in a conductive state and the second switch, the third switch, and the fourth switch are in a non-conductive state, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A second switch, a third switch, and a fourth switch are electrically connected between the first wiring and the second wiring, a third switch electrically connected between the first wiring and the second wiring, and a fourth switch electrically connected between the first wiring and the second wiring, and a driving circuit including the above, and a pixel including a liquid crystal element, and a driving method for a liquid crystal display device including the above, wherein a first sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a second sub-period in which the first switch is in a conductive state and the second switch, the third switch, and the fourth switch are in a non-conductive state, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A second wiring, a third switch electrically connected between the first wiring and the second wiring, and a fourth switch electrically connected between the first wiring and the second wiring, and a driving circuit including the above, and a pixel including a liquid crystal element, and a driving method for a liquid crystal display device including the above, wherein a first sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a second sub-period in which the first switch is in a conductive state and the second switch, the third switch, and the fourth switch are in a non-conductive state, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A second wiring, and a fourth switch electrically connected between the first wiring and the second wiring, and a driving circuit including the above, and a pixel including a liquid crystal element, and a driving method for a liquid crystal display device including the above, wherein a first sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a second sub-period in which the first switch is in a conductive state and the second switch, the third switch, and the fourth switch are in a non-conductive state, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A driving method for a liquid crystal display device including a driving circuit including a first switch, a second switch, a third switch, and a fourth switch electrically connected between a first wiring and a second wiring, and a pixel including a liquid crystal element, wherein a first sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a second sub-period in which the first switch is in a conductive state and the second switch, the third switch, and the fourth switch are in a non-conductive state, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A sub-period, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A second switch, a third switch, and a fourth switch are in a non-conductive state, a second sub-period having the above, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A second switch, a third switch, and a fourth switch are in a non-conductive state, a second sub-period having the above, and a third sub-period in which the second switch is in a conductive state and the first switch, the third switch, and the fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first And a fourth switch are in a non-conductive state, a first period having the above, a fourth sub-period in which the first switch, the second switch, the third switch, and the fourth switch are in a non-conductive state, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A switch, a second switch, a third switch, and a fourth switch are in a non-conductive state, a fourth sub-period having the above, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A switch, a second switch, and a fourth switch are in a non-conductive state, a fourth sub-period having the above, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A switch, a second switch, and a fourth switch are in a non-conductive state, a fourth sub-period having the above, a fifth sub-period in which the third switch is in a conductive state and the first switch, the second switch, and the fourth switch are in a non-conductive state, and a fourth switch is in a conductive state and the first A sixth sub-period in which the first switch, the second switch, and the third switch are in a non-conductive state, A driving method for a liquid crystal display device having a second period having .

[0012] In one aspect of the present invention, the first period and the second period are repeated in sequence. That's fine.

[0013] In one embodiment of the present invention, the first period and the second period are of approximately equal length. That's good too.

[0014] In one embodiment of the present invention, the first sub-period and the second sub-period are repeated in order, Subperiod 4 and subperiod 5 may be repeated in sequence.

[0015] In one embodiment of the present invention, a first sub-period, a second sub-period, a third sub-period, and The 4th sub-period, the 5th sub-period, and the 6th sub-period are of roughly equal length. That's good too.

[0016] Note that various types of switches can be used. For example, electrical switches These include switches and mechanical switches. In other words, anything that can control the flow of electric current will work. It is not limited to specific things. For example, a transistor (e.g., bipod) can be used as a switch. (e.g., transistors, MOS transistors), diodes (e.g., PN diodes), PIN diode, Schottky diode, MIM (Metal Insulator) Metal diode, MIS (Metal Insulator Semiconductor) It is possible to use ductors (diodes, diode-connected transistors, etc.) It comes. Alternatively, a logic circuit combining these can be used as a switch.

[0017] Examples of mechanical switches include digital micromirror devices (DMDs). Switches using MEMS (Micro-Electro-Mechanical Systems) technology are available. The switch has electrodes that can be moved mechanically, and the movement of these electrodes It operates by controlling the transitions between conductivity and non-conductivity.

[0018] Furthermore, using both N-channel and P-channel transistors, CMO An S-type switch may also be used as the switch.

[0019] Furthermore, when explicitly stating that A and B are connected, it means that A and B are electrically connected. When they are connected, when A and B are functionally connected, and when A and B are directly connected This includes cases where the object is present. Here, A and B are the object (for example, a device, an element, a rotation). (Let it be a path, wiring, electrode, terminal, conductive film, layer, etc.) Therefore, a predetermined connection relationship For example, not limited to the connection relationships shown in the diagram or text, but the connections shown in the diagram or text This includes things other than relationships.

[0020] For example, if A and B are electrically connected, the electrical connection between A and B is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more ions (such as ions) may be connected between A and B. Alternatively, A and B and As an example of a functionally connected system, a circuit that enables a functional connection between A and B (for example) For example, logic circuits (inverters, NAND gates, NOR gates, etc.) and signal conversion circuits (DA conversion). Circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits) (Step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources Switching circuits, amplification circuits (circuits that can increase signal amplitude or current, etc., operational amplifiers) (Differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, One or more control circuits (such as) may be connected between A and B. For example, between A and B Even if another circuit is in between, if the signal output from A is transmitted to B, then A and B and They are assumed to be functionally connected.

[0021] Furthermore, if it is explicitly stated that A and B are electrically connected, then A and B are electrically connected. When connected electrically (that is, when another element or circuit is placed between A and B) (when they are separated) and when A and B are functionally connected (that is, when there is no separate connection between A and B) (When they are functionally connected with a circuit in between) and when A and B are directly connected ( In other words, this includes cases where A and B are connected without any other element or circuit in between. In other words, if you explicitly state that they are electrically connected, then simply state that they are connected. This is equivalent to the case where it is explicitly stated only that it is included.

[0022] Furthermore, a display element, a display device having a display element, a light-emitting element, and a device having a light-emitting element A light-emitting device can take on various forms and contain various elements. For example For example, as a display element, display device, light-emitting element, or light-emitting device, EL (electroluminescent) EL elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent) Transistors that emit light, electron-emitting elements, liquid crystal elements, electronic inks, electrophoretic elements, etc. Rating Light Bulb (GLV), Plasma Display (PDP), Digital Microwave Chromiller devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, Displays where contrast, brightness, reflectance, transmittance, etc., change due to electromagnetic effects. It can have a medium. An EL display is an example of a display device using an EL element. As for display devices using electron emission elements, field emission displays (FEDs) are examples. ) and SED type flat-panel displays (SED: Surface-conduction Display devices using liquid crystal elements, such as electron-emitter displays. Liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays) LCDs, direct-view LCDs, projection LCDs, electronic inks and Electronic paper is an example of a display device that uses electrophoretic elements.

[0023] Liquid crystal elements control the transmission or non-transmission of light through the optical modulation effect of liquid crystals. It is an element composed of a pair of electrodes and liquid crystal. The optical modulation effect of the liquid crystal is as follows: Controlled by the electric field applied to the liquid crystal (including the electric field in the horizontal direction, the electric field in the vertical direction, or the electric field in the diagonal direction) It is controlled. Furthermore, liquid crystal elements include nematic liquid crystals, cholesteric liquid crystals, and smectic liquid crystals. Liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal Polymer liquid crystals, polymer dispersed liquid crystals (PDLCs), ferroelectric liquid crystals, antiferroelectric liquid crystals, main-chain liquid crystals Examples include side-chain polymer liquid crystals, plasma-addressable liquid crystals (PALC), and banana-shaped liquid crystals. This is possible. Furthermore, the LCD driving method is TN (Twisted Nematic) Code, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching) mode, FFS (Fringe Field Switching) tching) mode, MVA (Multi-domain Vertical Ali gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) Mode, ECB (Electrically Controlled Birefringence ngence) mode, FLC (Ferroelectric Liquid Crystal tal) mode, AFLC(AntiFerroelectric Liquid Cr (ystal) mode, PDLC (Polymer Dispersed Liquid) Crystal mode, guest host mode, Blue Phase mode The following can be used: However, this is not limited to liquid crystal elements and their driving methods. This allows you to use various things.

[0024] Furthermore, various types of transistors can be used as transistors. There are no restrictions on the type of transistor used. For example, amorphous silicon, polycrystalline silicon, Microcrystalline silicon (also called nanocrystal or semi-amorphous silicon) This involves using thin-film transistors (TFTs) that have non-single-crystal semiconductor films, such as those shown above. It is possible.

[0025] Furthermore, when manufacturing polycrystalline silicon, by using a catalyst (such as nickel), Further improvement in crystallinity makes it possible to manufacture transistors with superior electrical properties. Oh, when manufacturing microcrystalline silicon, by using a catalyst (such as nickel), crystals This will further improve performance and make it possible to manufacture transistors with better electrical characteristics. The ability to manufacture polycrystalline silicon and microcrystalline silicon without using catalysts (such as nickel) is It is possible.

[0026] Furthermore, improving the crystallinity of silicon to polycrystalline or microcrystalline forms is possible for the entire panel. It is preferable to perform this with the body, but it is not limited to that. The crystallinity of the ricon may be improved.

[0027] Alternatively, transistors can be formed using semiconductor substrates or SOI substrates.

[0028] Alternatively, ZnO, α-InGaZnO, SiGe, GaAs, IZO, ITO, SnO , possessing compound semiconductors or oxide semiconductors such as TiO and AlZnSnO(AZTO) Transistors, and furthermore, thin films made by thinning these compound semiconductors or oxide semiconductors. Lampistors and the like can be used. Note that these are compound semiconductors or oxide semiconductors. It can be used not only in the channel portion of transistors, but also in other applications. For example, these compound semiconductors or oxide semiconductors are used in resistive elements, pixel electrodes, and light-transmitting elements. They can be used as electrodes having the following properties. Furthermore, they can be used to form films simultaneously with the transistor. Since it can be formed, costs can be reduced.

[0029] Alternatively, transistors formed using inkjet or printing methods can be used. come.

[0030] Alternatively, transistors containing organic semiconductors or carbon nanotubes can be used. This allows transistors to be formed on a flexible substrate. Semiconductor devices using such substrates can be made more resistant to impact.

[0031] Furthermore, transistors of various structures can be used. For example, MOS type transistors By using transistors such as junction transistors and bipolar transistors as transistors... It is possible.

[0032] Furthermore, MOS transistors, bipolar transistors, etc., are mixed together on a single substrate. It may be formed.

[0033] In addition, various other transistors can be used.

[0034] Furthermore, transistors can be formed using various substrates. The types of substrates are particularly... It is not limited to a specific type. For example, the substrate could be a single crystal substrate (e.g., silicon Concrete substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates. Stainless steel substrates, substrates with stainless steel foil, tungsten substrates, tan A substrate with Gusten foil, a flexible substrate, etc., can be used. Examples include barium borosilicate glass and aluminobosilicate glass. Flexible Examples of substrates include polyethylene terephthalate (PET) and polyethylene naphthalate. Plastics such as PEN and polyethersulfone (PES), or acrylics Examples include flexible synthetic resins such as lyl. Other examples include laminated films (polypropylene). Includes fibrous materials (such as polyester, vinyl, polyvinyl fluoride, and polyvinyl chloride). Paper, base film (polyester, polyamide, polyimide, inorganic vapor-deposited film, paper products) Examples include: forming a transistor using one substrate, and then transferring it to another substrate. The transistor may be transposed and placed on a different substrate. The substrates that can be placed on them include single crystal substrates, SOI substrates, glass substrates, quartz substrates, and plastic substrates. Circuit boards, paper circuit boards, cellophane circuit boards, stone circuit boards, wood circuit boards, cloth circuit boards (natural fibers (silk, cotton, hemp)) , synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, Includes cupro, rayon, recycled polyester, etc., leather substrate, rubber substrate, stainless steel A stainless steel substrate, a substrate having stainless steel foil, etc., can be used. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of an animal such as a human may be used as a substrate. Alternatively, a transistor may be formed using a substrate, and then the substrate may be polished to make it thinner. The substrates to be polished include single crystal substrates, SOI substrates, glass substrates, quartz substrates, and plastic substrates. Using substrates such as stainless steel substrates, stainless steel substrates, and substrates with stainless steel foil. This allows for the formation of transistors with good characteristics and improved performance. Formation of low-power transistors, manufacturing of durable devices, heat resistance, weight reduction, and This allows for a thinner design.

[0035] Furthermore, transistor configurations can take various forms and are not limited to a specific configuration. For example, a multi-gate structure with two or more gate electrodes can be applied.

[0036] As another example, a structure can be applied in which gate electrodes are positioned above and below the channel. Furthermore, by arranging gate electrodes above and below the channel, multiple traps can be connected. The configuration will be like having transistors connected in parallel.

[0037] Structures where the gate electrode is positioned above the channel region, and structures where the gate electrode is positioned below the channel region. Structures in which elements are arranged, positive staggered structure, inverse staggered structure, and channel regions divided into multiple regions A structure in which channel regions are connected in parallel, or a configuration in which channel regions are connected in series. This can also be applied. Furthermore, source electrodes and drain electrodes can be placed in the channel region (or a part thereof). This can also be applied to structures where the elements overlap.

[0038] Furthermore, various types of transistors can be used, and they can be formed using various substrates. Therefore, all the circuits necessary to realize a given function can be the same. It is also possible to form it on a single substrate. For example, the number of times required to achieve a predetermined function All of the substrates are various types, such as glass substrates, plastic substrates, single crystal substrates, or SOI substrates. It is also possible to form it using a substrate. Alternatively, it may be necessary to achieve a predetermined function. A portion of the essential circuitry is formed on a certain substrate, and the other circuits necessary to achieve a predetermined function are also formed on a substrate. It is also possible that a part of it is formed on a separate substrate. In other words, to achieve a predetermined function It is not necessary for all the circuits required to be formed on the same circuit board. For example, Some of the circuits necessary to realize this function are formed on a glass substrate by transistors. Furthermore, another part of the circuit necessary to realize the predetermined function is formed on a single crystal substrate. An IC chip composed of transistors formed using a single-crystal substrate is called a COG (Chip). The IC chip is connected to a glass substrate (On Glass) and then placed on the glass substrate. It is also possible to use TAB (Tape Automate) for the IC chip. It is also possible to connect to the glass substrate using bonding or a printed circuit board.

[0039] A transistor is defined as having at least three terminals, including a gate, a drain, and a source. It is an element having a drain region and a channel region between the drain region and the source region, Current can be passed through the rain region, channel region, and source region. Here, The terms "sow" and "drain" vary depending on the transistor's structure and operating conditions, so which one is the drain? It is difficult to determine whether it is a source or a drain. Therefore, source and drain The area that functions as a source or drain is sometimes not called a source or drain. In that case, for example... In some cases, these are referred to as the first terminal and the second terminal, respectively. Alternatively, they can be referred to as They are sometimes referred to as the first electrode and the second electrode. Alternatively, they may be referred to as the first region and the second region. There is a match.

[0040] Furthermore, a transistor has at least three terminals, including the base, emitter, and collector. It may also be an element having a first terminal, and the collector may be the first terminal, and the second terminal, respectively. It may sometimes be written as "2 terminals," etc.

[0041] Furthermore, if B is formed on top of A, or if B is formed on top of A, When describing this, it is not limited to the case that B is formed in direct contact with A. This also includes cases where this does not occur, i.e., when another object is intervening between A and B. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers). (etc.)

[0042] Therefore, for example, explicitly stating that layer B is formed on top of layer A (or on top of layer A) If described, this applies to cases where layer B is formed in direct contact with layer A, and where layer A is formed on top of layer B. Another layer (such as layer C or layer D) is formed in direct contact with it, and layer B is formed in direct contact with it on top of that. This includes cases where a layer is formed. Note that other layers (e.g., layer C or layer D) are: It can be single-layered or multi-layered.

[0043] Furthermore, the same applies when it is explicitly stated that B is formed above A. It is not limited to B being in direct contact with A, but rather there may be another object between A and B. This includes cases where intervening layers are present. For example, if layer B is formed above layer A, In this case, there are two possibilities: when layer B is formed in direct contact with layer A, and when layer B is formed in direct contact with layer A. Then another layer (for example, layer C or layer D) is formed, and layer B is formed directly in contact with it. This includes cases where it is a single layer. Note that other layers (for example, layer C or layer D) may also be single layers. That's fine, and multiple layers are also acceptable.

[0044] Furthermore, B is formed on top of A, B is formed on top of A, or B is formed above A. When explicitly stating that something has been done, this includes cases where B is formed diagonally upwards. .

[0045] The same applies when B is below A, or when B is below A.

[0046] Furthermore, it is preferable that any terms explicitly stated as singular remain singular. However, this is not the only option; there can be multiple instances. Similarly, explicitly specifying the number of instances is also possible. For items that are listed as such, it is preferable that there be multiple items. However, this is not limited to these items. It can also be singular.

[0047] Note that in the diagram, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0048] Note that the figure is a schematic representation of an ideal example and is not limited to the shapes or values ​​shown in the figure. It cannot be fixed. For example, variations in shape due to manufacturing technology, variations in shape due to errors, noise Variations in signals, voltages, or currents, or signals, voltages, due to timing differences. Alternatively, it may include variations in current, etc.

[0049] Note that technical terms may be used to describe specific embodiments or examples. Many, but not limited to, this applies.

[0050] Furthermore, terms that are not defined (including scientific and technical terms such as specialized or academic terms) are generally... It can be used with the same meaning as the general meaning understood by those who are normally skilled in the art. (Dictionaries, etc.) The terminology defined therein should be interpreted in a way that is consistent with the context of the related technology. It is preferable.

[0051] Note that terms such as "1st," "2nd," and "3rd" refer to various elements, components, areas, layers, and regions that are separate from each other. It is used to distinguish and describe things. Therefore, terms such as "first," "second," and "third" refer to elements and parts. It does not limit the number of materials, areas, layers, zones, etc. Furthermore, for example, "the first" It can be replaced with "second" or "third," etc.

[0052] Also, "upwards," "upwards," "downwards," "sideways," "to the right," "to the left," Words indicating spatial arrangement, such as "diagonally," "further back," or "in front," can refer to a certain element or It is sometimes used to briefly illustrate, using diagrams, the relationship between a feature and other elements or features. There are many. However, this is not limited to these; the terms indicating these spatial arrangements are added in the direction they are depicted in the diagram. Furthermore, it is possible to include other directions. For example, when it is explicitly indicated as A on B. This is not limited to B being on top of A. The devices in the diagram may be inverted or rotated 180°. Since it is possible to do so, it is possible to include the case where B is below A. In this way, "above The phrase "ni" can include both the direction "upwards" and the direction "downwards." Furthermore, it is not limited to this, as the devices in the diagram can be rotated in various directions, The phrase "upwards" can mean not only "upwards" and "downwards," but also "sideways," "to the right," and "left." It is possible to include other directions such as "towards," "diagonally," "towards the back," or "towards the front." .

[0053] In one aspect of the present invention, a first terminal is connected to a first wire, and a second terminal is connected to a second wire. The gate of the first transistor is connected to the third wiring, and the first terminal is connected to the first wiring. The second terminal is connected to the second wiring, and the gate is connected to the fourth wiring. The transistor has a first terminal connected to the first wire and a second terminal connected to the second wire. The gate of the third transistor is connected to the fifth wiring, and the first terminal is connected to the first wiring. The fourth terminal is connected to the second wire, and the gate is connected to the sixth wire. It has a transistor and

[0054] In one aspect of the present invention, a first terminal is connected to a first wire, and a second terminal is connected to a second wire. The gate of the first transistor is connected to the third wiring, and the first terminal is connected to the first wiring. The second terminal is connected to the second wiring, and the gate is connected to the fourth wiring. The transistor has a first terminal connected to the first wire and a second terminal connected to the second wire. The gate of the third transistor is connected to the fifth wiring, and the first terminal is connected to the first wiring. The fourth terminal is connected to the second wire, and the gate is connected to the sixth wire. The transistor has its first terminal connected to the seventh wire and its second terminal connected to the second wire. It has a fifth transistor whose gate is connected to an eighth wire.

[0055] One aspect of the present invention is that a first transistor and a second transistor alternately turn on and off. Repeatedly, and a first period during which the third and fourth transistors are turned off, The first transistor and the second transistor are turned off, and the third transistor and the The circuit has a second period in which the four transistors alternately switch on and off.

[0056] One aspect of the present invention is a first wiring and a second wiring that are electrically connected via a first path. The period of time, and the second period of time during which the first wiring and the second wiring are electrically connected via the second path. , a third period in which the first wiring and the second wiring become conductive via the third path, and the first The method includes a fourth period during which the wiring and the second wiring become conductive via the fourth path. [Effects of the Invention]

[0057] One aspect of the present invention makes it possible to shorten the on-time of the transistor. Alternatively, this One aspect of the invention can suppress the degradation of transistor characteristics. Or, one aspect of the invention One embodiment allows for a reduction in the channel width of the transistor. Alternatively, one embodiment of the present invention This allows for a reduction in the layout area. Alternatively, one aspect of the present invention relates to a display device. The frame can be made narrower. Alternatively, one aspect of the present invention is to make the display device high-resolution. This can be done. Alternatively, one aspect of the present invention can increase the yield. Alternatively, this invention One aspect of the present invention can reduce costs. Alternatively, one aspect of the present invention can reduce the raw signal This can reduce or reduce delays. Alternatively, one aspect of the present invention can reduce power consumption. This is possible. Alternatively, in one aspect of the present invention, the current capacity of the external circuit can be reduced. Alternatively, one aspect of the present invention relates to the size of an external circuit, or a display device having said external circuit. The size can be reduced. [Brief explanation of the drawing]

[0058] [Figure 1] This is a circuit diagram of a semiconductor device and a timing chart to explain its operation. [Figure 2] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 3] This is a schematic diagram illustrating the operation of a semiconductor device, along with a circuit diagram of the semiconductor device. [Figure 4] This is a circuit diagram of a semiconductor device. [Figure 5] This is a circuit diagram of a semiconductor device. [Figure 6] This is a circuit diagram of a semiconductor device. [Figure 7] This is a circuit diagram of a semiconductor device. [Figure 8] This is a circuit diagram of a semiconductor device and a timing chart to explain its operation. [Figure 9] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 10] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 11] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 12] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 13] This is a schematic diagram illustrating the operation of a semiconductor device. [Figure 14] This is a timing chart used to explain the operation of a semiconductor device. [Figure 15] This is a timing chart used to explain the operation of a semiconductor device. [Figure 16] This is a circuit diagram of a semiconductor device. [Figure 17] This is a circuit diagram of a semiconductor device. [Figure 18] This is a circuit diagram of a semiconductor device. [Figure 19] This is a circuit diagram of a semiconductor device and a timing chart to explain its operation. [Figure 20] This is a circuit diagram of a semiconductor device. [Figure 21] This is a circuit diagram of a semiconductor device. [Figure 22] This is a circuit diagram of a semiconductor device. [Figure 23] This is a circuit diagram of a semiconductor device. [Figure 24] This is a circuit diagram of a semiconductor device. [Figure 25] This is a circuit diagram of a semiconductor device. [Figure 26] This is a circuit diagram of a shift register. [Figure 27] This is a timing chart to explain the operation of a shift register. [Figure 28] This is a timing chart to explain the operation of a shift register. [Figure 29] This is a schematic diagram illustrating the operation of a shift register. [Figure 30] This is a block diagram of a display device. [Figure 31] This is a block diagram of a display device. [Figure 32] This is a circuit diagram of a semiconductor device and a timing chart to explain its operation. [Figure 33] This is a circuit diagram of a pixel and a timing chart to explain its operation. [Figure 34] This is a circuit diagram of a pixel. [Figure 35] This is a top view and a cross-sectional view of the display device. [Figure 36] This is a cross-sectional view of a transistor. [Figure 37] This is a layout diagram of a shift register. [Figure 38] This is a layout diagram of a shift register. [Figure 39] This is a diagram illustrating electronic devices. [Figure 40] This is a diagram illustrating electronic devices. [Figure 41] This is a circuit diagram of a semiconductor device and a schematic diagram to explain its operation. [Figure 42] This is a timing chart used to explain the operation of a semiconductor device. [Figure 43] This is a circuit diagram of a semiconductor device. [Figure 44] This is a timing chart used to explain the operation of a semiconductor device. [Figure 45] This is a timing chart used to explain the operation of a semiconductor device. [Figure 46] This is a cross-sectional view illustrating the transistor manufacturing process. [Modes for carrying out the invention]

[0059] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments are numerous. It can be implemented in several different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be changed in various ways. The interpretation is not limited to the description of the form of implementation. Similarly, symbols indicating the same thing are shown using common symbols across different drawings, and the same part or the same Detailed explanations of the parts with similar functions will be omitted.

[0060] Furthermore, the content described in one embodiment (even a part of it) may vary depending on the form of its implementation. Other content (even partial content) described in the tone, and / or one or more other implementations To apply, combine, or replace the content described in the form (even if only a part of it is acceptable), It is possible to do things like this.

[0061] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content stated, or the content stated using the text described in the specification.

[0062] Furthermore, a diagram (even a partial one) described in one embodiment may refer to another part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more figures. In another embodiment, the diagram (or even just a part of it) described above can be combined by This allows for the creation of even more diagrams.

[0063] (Embodiment 1) This embodiment describes an example of a semiconductor device. The semiconductor device of this embodiment is For example, it can be used in shift registers, gate drivers, source drivers, or display devices. It is possible to do so. Furthermore, the semiconductor device of this embodiment can be referred to as a drive circuit. be.

[0064] First, regarding the basic circuit that can be used in the semiconductor device of this embodiment, see Figure 41(A). This will be explained by referring to Figure 41(A). The circuit in Figure 41(A) consists of multiple circuits, including circuit 101 and circuit 102. It has a circuit. And the circuit 101 has switches 11_1 and 11_2 Circuit 102 has multiple switches, and switches 12_1 and 12_2 It has multiple switches. Switch 11_1, switch 11_2, switch 12_1, and Switch 12_2 is connected between wiring 111 and wiring 112. Note that Figure 41(A The circuit shown can be described as a semiconductor device or a drive circuit.

[0065] Switches 11_1, 11_2, 12_1, and 12_2 are distributed It has the function of controlling the conductivity state between wire 111 and wiring 112. Therefore, as shown in Figure 41(B) As such, between wiring 111 and wiring 112, there are paths 121_1, 121_2, and There are multiple paths, such as 122_1 and path 122_2. However, this is not limited to these. If N (natural number) switches are connected between wiring 111 and wiring 112, then wiring 11 There can be N possible paths between point 1 and wiring 112.

[0066] Note that this refers to the path between wiring A (e.g., wiring 111) and wiring B (e.g., wiring 112). In this case, wiring A can be connected to wiring B via a switch. However, Not limited to this, there can be various elements (for example, switches) between wiring A and wiring B. (such as transistors, diodes, resistors, or capacitive elements), or various circuits (e.g., battery It is possible to connect circuits such as inverter circuits, shift register circuits, etc. Therefore, for example, a resistor or transistor can be connected in series or parallel with switch 11_1. It is possible to connect elements such as transistors.

[0067] As an example, let's assume that signal OUT is output from wiring 111. Signal OUT is H Often, it is a digital signal with a level and an L level, and functions as an output signal. This is possible. Therefore, wiring 111 can function as a signal line. In particular The wiring 111 can be extended and arranged in the pixel area. , it is possible to connect to the pixel. Alternatively, wiring 111 can be connected to the transistors that the pixel has It is connected to the gate of a transistor (for example, a selection transistor or a switching transistor). This is possible. Therefore, the signal OUT is a selection signal, a transfer signal, a start signal, a reset signal. It can function as a gate signal, a signal, or a scanning signal. And wiring 11 1 can function as a gate line, scan line, or output signal line. Wiring 112 As an example, voltage V1 is supplied. Voltage V1 is a low-level signal. They are often roughly equal in value, and include ground voltage, power supply voltage, earth, reference voltage, or negative voltage. It can function as a power supply voltage, etc. Therefore, wiring 112 can function as a power line. It is possible to do so. However, it is not limited to this, and a signal is input to wiring 112. Wiring 112 can function as a signal line.

[0068] Note that "approximately" refers to errors due to noise, errors due to process variations, and manufacturing errors of the element. This includes errors due to variations in degree and / or various other errors such as measurement errors.

[0069] As an example, let V1 be the potential of a low-level signal and V2 be the potential of a high-level signal. And, let V2 > V1. Therefore, when we write voltage V2, voltage V2 is the signal It is assumed to be approximately equal to the H level. However, it is not limited to this, and the L level The signal potential can be lower than V1, or higher than V1. Alternatively, the potential of the H-level signal can be lower than V2, or higher than V2. It is possible.

[0070] Voltage refers to the potential difference between a given potential and a reference potential (for example, ground potential). In many cases, voltage, potential, and potential difference are rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0071] Next, the operation of the circuit in Figure 41(A) will be explained with reference to the timing chart in Figure 42. The timing chart in Figure 42 has multiple periods, and each period has multiple sub-periods. It has. For example, the timing chart in Figure 42 shows multiple periods, such as period A and period B. (Hereafter, the period will also be called the frame period.) Period A has Period A0, Period A1 , and multiple sub-periods such as period A2 (hereinafter, sub-periods are also referred to as 1-gate selection periods) Period B has (u). Period B has multiple sub-periods called Period B0, Period B1, and Period B2. do.

[0072] In the example timing chart shown in Figure 42, periods A and B are arranged in order. However, this is not limited to this, and periods A and B can be arranged in various orders. Alternatively, the timing chart may have periods other than period A and period B. It is possible. Alternatively, it is possible to omit either period A or period B.

[0073] Furthermore, within period A, period A1 and period A2 are repeatedly arranged, followed by period A0. Then, period A1 and period A2 are repeatedly arranged within period A. Furthermore, periods A0, A1, and A2 can be arranged in various orders. It is possible to do so. Alternatively, period A may include period B0, period B1, period B2, and / or Other periods can be placed. Or, period A0, period A1, and period Either of the A2 options can be omitted. Alternatively, period A0 can be placed after period A1. It is possible to do so, and it is possible to place it after period A2, and at the beginning of period A It is possible to place it, and it is also possible to place it after other periods.

[0074] Furthermore, in period B, period B1 and period B2 are arranged repeatedly, followed by period B0. Then, period B1 and period B2 are repeated within period B. Furthermore, periods B0, B1, and B2 can be arranged in various orders. It is possible to do so. Alternatively, period B may include period A0, period A1, period A2, and / or Other periods can be placed. Or, period B0, period B1, and period It is possible to omit any of the B2s. Alternatively, period B0 can be placed after period B1. It is possible to do so, and it is possible to place it after period B2, and at the beginning of period B It is possible to place it, and it is also possible to place it after other periods.

[0075] First, let's explain the operation during period A. During period A, switch 11_1 and switch 12 _1 repeatedly switches on and off at sub-period intervals, and switches 11_2 and 12_2 It turns off. The on and off states of switches 11_1 and 12_1 are inverse of each other. In many cases, they are present. However, this is not limited to this, and switches 11_1 and 12_1 are also present. It can be turned off, and it can be turned on. Or, switch 11_ 2. And / or, switch 12_2 can be turned on.

[0076] During period A1 of period A, switch 11_1 is turned ON, as shown in Figure 41(C). Switches 11_2, 12_1, and 12_2 are turned off. Therefore, As shown in Figure 41(D), path 121_1 becomes conductive, and path 121_2 and path 1 22_1 and path 122_2 become non-conductive. Then wiring 111 and wiring 112 and Since it becomes conductive via switch 11_1, the voltage supplied to wiring 112 (for example) The voltage V1) or signal is supplied to the wiring 111 via switch 11_1. Then, wiring 111 and wiring 112 become conductive via path 121_1, The voltage (e.g., voltage V1) or signal supplied to 112 is routed through path 121_1 to wiring 1 It will be supplied to 11.

[0077] During period A2 of period A, switch 12_1 is turned on, and switch 11_1, switch Switch 11_2 and switch 12_2 are turned off. Therefore, as shown in Figure 41(E), Path 122_1 becomes conductive, and paths 121_1, 121_2, and 122_2 This becomes a non-conductive state. Then, wire 111 and wire 112 are connected via switch 12_1. Since it becomes conductive, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is switched It is supplied to wiring 111 via switch 12_1. In other words, wiring 111 and wiring 112 This means that conduction occurs via path 122_1, so the voltage supplied to wiring 112 (for example) The voltage V1) or signal is supplied to the wiring 111 via path 122_1.

[0078] During period A0 of period A, switch 11_1, switch 11_2, switch 12_1, And switch 12_2 is turned off. Therefore, as shown in Figure 41(H), path 121_ 1. Paths 121_2, 122_1, and 122_2 become non-conductive. Since wiring 111 and wiring 112 become non-conductive, the voltage supplied to wiring 112 ( For example, voltage V1) or a signal will no longer be supplied to wiring 111.

[0079] Next, we will explain the operation during period B. During period B, switch 11_1 and switch 12 Switch 1 is turned off, and switches 11_2 and 12_2 switch on and off every sub-period. This is often repeated. However, it is not limited to this, and switches 11_2 and 12 _2 can be turned off and on. Or, a switch. Switch 11_1 and / or switch 12_1 can be turned on.

[0080] During period B1 of period B, switch 11_2 is turned on, and switch 11_1, switch Switch 12_1 and switch 12_2 are turned off. Therefore, as shown in Figure 41(F), Path 121_2 becomes conductive, and paths 121_1, 122_1, and 122_ 2 becomes non-conductive. Then, wire 111 and wire 112 are connected via switch 11_2. As it becomes conductive, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is It is supplied to wiring 111 via switch 11_2. In other words, wiring 111 and wiring 11 2 is because it becomes conductive via path 121_2, so the voltage supplied to wiring 112 (e.g.) For example, voltage V1) or a signal is supplied to wiring 111 via path 121_2.

[0081] During period B2 of period B, switch 12_2 is turned on, and switch 11_1, switch Switch 11_2 and switch 12_1 are turned off. Therefore, as shown in Figure 41(G), Path 122_2 becomes conductive, and paths 121_1, 121_2, and 122_ 1 becomes non-conductive. Then, wire 111 and wire 112 are connected via switch 12_2 As it becomes conductive, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is It is supplied to wiring 111 via switch 12_2. In other words, wiring 111 and wiring 11 2 means that conduction occurs via path 122_2, so the voltage supplied to wiring 112 (e.g.) For example, voltage V1) or a signal is supplied to wiring 111 via path 122_2.

[0082] During period B0 of period B, switch 11_1, switch 11_2, switch 12_1, And switch 12_2 is turned off. Therefore, as shown in Figure 41(H), path 121_ 1. Paths 121_2, 122_1, and 122_2 become non-conductive. Since wiring 111 and wiring 112 become non-conductive, the voltage supplied to wiring 112 ( For example, voltage V1) or a signal will no longer be supplied to wiring 111.

[0083] As described above, by switching the duration for which each switch is on, the switch can be turned on. The time required to become [that state] can be shortened. Therefore, the element or circuit used as a switch This can suppress deterioration such as the above.

[0084] During periods A0 and B0, the wiring 111 receives a signal of voltage V2 or H level. Often, a high-level clock signal (for example) is input. However, it is not limited to this. Furthermore, wiring 111 can be in a floating state without any voltage or signal input. ru.

[0085] Note that the time at which period A0 begins in period A (or the time from the start of period A to the start of period A0) The time until the start time is the time when period B0 starts in period B (or the start of period B). It is often roughly equal to the time from the time to the start time of period B0. However, if this is the case Not limited.

[0086] Note that the term "period" can be replaced with "step" or "action." For example, the first period, the second When it says "period 2," it can be replaced with "step 1" and "step 2." be.

[0087] Furthermore, if it is possible to operate as shown in Figures 41(B) to (H), the switch configuration is as shown in Figure Not limited to 41(A).

[0088] Note that two or more of switches 11_1~11_2 and switches 12_1~12_2 must be selected. It is possible for (for example, two, three, or four) switches to be turned on simultaneously. For example, It is possible for switch 11_1 and switch 12_1 to be turned on simultaneously.

[0089] Furthermore, circuit 101 and / or circuit 102 may have three or more switches. Yes, for example, as shown in Figure 43(A), the circuit 101 has switches 11_1~11_m Circuit 102 has multiple switches (where m is a natural number), and switches 12_1~12_ It is possible to have multiple switches called m. Switches 11_1 to 11_m are each Each corresponds to either switch 11_1 or switch 11_2 and has the same function. Switch 1 2_1 to 12_m correspond to switch 12_1 or switch 12_2, respectively, and are similar devices. It has the ability. Switches 11_1~11_m and switches 12_1~12_m are connected to wiring 1 It is connected between 11 and wiring 112. Therefore, as shown in Figure 43(B), wiring 111 Between and wiring 112, there are multiple paths called paths 121_1~121_m and path 122 There are multiple paths, _1~121_m. However, it is not limited to these, circuit 101 , and / or, each of the circuits 102 may have one switch. The number of switches in circuit 101 and the number of switches in circuit 102 are different. This is possible.

[0090] Figure 44 shows an example of a timing chart that can be used in the circuit shown in Figure 43(A). The timing chart for 44 is an example where m=3. Therefore, circuit 101 is It is possible to have multiple switches, namely switches 11_1 to 11_3, and circuit 10 2 can have multiple switches, namely switches 12_1 to 12_3. Figure 4 The timing chart in 4 has multiple periods: Period A, Period B, and Period C. Period C, like Period A or Period B, has multiple subperiods called Period C0, Period C1, and Period C2. It has a period. And in the example timing chart in Figure 44, period A, period B, and Periods A, B, and C are arranged in order. However, this is not limited to this arrangement; periods A, B, and C may also be arranged in order. These can be arranged in various orders. Alternatively, the timing chart is for period A. In addition to periods B and C, there can be various other periods, as well as periods A and B It is possible to omit either period C1 or period C. And period C includes period C1 and Period C2 is placed repeatedly, followed by period C0. Then, again, period C Period C1 and period C2 are arranged repeatedly within this. However, this is not limited to the period C0, period C1, and period C2 can be arranged in various orders. Or, Period C includes periods A0, A1, A2, B0, B1, B2, and / or Other periods can be set. Or, period C0, period C1, and period It is possible to omit either of the periods C2. Alternatively, period C0 may be placed after period C1. It is possible to place it, and it is possible to place it after period C2, and other periods It can be placed next to it.

[0091] During periods A and B, switches 11_3 and 12_3 will be turned off. As a result, paths 121_3 and 122_3 become non-conductive. However, this is not limited to this. Switch 11_3 and / or switch 12_3 can be turned on. ru.

[0092] During period C, switches 11_3 and 12_3 are switched on and off in sub-periods. Repeat, switch 11_1, switch 11_2, switch 12_1, and switch 12 Switch _2 will be turned off. The on and off states of switches 11_3 and 12_3 are mutual. In many cases, it is reversed. However, this is not limited to this, and also applies to switch 11_3 and switch 12_3 can be turned on and can be turned off. Or, Switch 11_1, Switch 11_2, Switch 12_1, and / or Switch 12_2 It can be turned on.

[0093] During period C1 of period C, switch 11_3 is turned on, and switch 11_1 and switch 1 Switches 1_2, 12_1, 12_2, and 12_3 will be turned off. Then, path 121_3 becomes conductive, and paths 121_1, 121_2, and 122 _1, path 122_2, and path 122_3 become non-conductive. Then wiring 111 and Wiring 112 becomes conductive via switch 11_3, and therefore supplies power to wiring 112. The voltage (e.g., voltage V1) or signal is supplied to the wiring 111 via switch 11_3. In other words, wiring 111 and wiring 112 become electrically connected via path 121_3. Therefore, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is routed through path 121_3. It is supplied to wiring 111 via this.

[0094] During period C2 of period C, switch 12_3 is turned on, and switch 11_1 and switch 1 Switches 1_2, 11_3, 12_1, and 12_2 will be turned off. Then, path 122_3 becomes conductive, and paths 121_1, 121_2, and 121 _3, path 122_1, and path 122_2 become non-conductive. Then wiring 111 and Wiring 112 becomes conductive via switch 12_3, so power is supplied to wiring 112. The voltage (e.g., voltage V1) or signal is supplied to the wiring 111 via switch 12_3. In other words, wiring 111 and wiring 112 become electrically connected via path 122_3. Therefore, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is routed through path 122_3. It is supplied to wiring 111 via this.

[0095] During period C0 of period C, switches 11_1, 11_2, 11_3, and Switch 12_1, switch 12_2, and switch 12_3 are turned off. Therefore, path 1 21_1, Route 121_2, Route 121_3, Route 122_1, Route 122_2, Route 1 22_3 becomes non-conductive. Consequently, wires 111 and 112 become non-conductive. Therefore, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is supplied to wiring 111. You won't be able to anymore.

[0096] In Figure 43(A), a larger value of m results in a shorter time during which the switch remains on. This makes it possible to suppress the deterioration of elements or circuits used as switches. This is possible. However, if m is too large, the circuit size becomes too large. Therefore It is preferable that m ≤ 6. More preferably, it is preferable that m ≤ 4. Preferably, m=2 or m=3.

[0097] Note that the circuit in Fig. 41(A) has a plurality of circuits corresponding to circuit 101 or circuit 102. This is possible. Fig. 43(C) shows an example of a case where the circuit has a plurality of circuits, namely circuit 101, circuit 102, and circuit 10 3. Circuit 103 has a plurality of switches, namely switch 13_1 and switch 13_2. Circuit 103 corresponds to circuit 101 or circuit 102, switch 13_1 corresponds to switch 11_1 or switch 12_1, and switch 13_2 corresponds to switch 11_2 or switch 12_2. Switch 13_ 1 and switch 13_2 are connected between wiring 111 and wiring 112. Therefore, as shown in Fig. 4 3(D), between wiring 111 and wiring 112, in addition to path 121_1, path 12 1_2, path 122_1, and path 122_2, there are also a plurality of paths, namely path 123_1 and path 123 _2. However, it is not limited to this. The circuit can have one circuit corresponding to circuit 101 or circuit 102, or four or more circuits corresponding to circuit 101 or circuit 102.

[0098] Fig. 45 shows an example of a timing chart that can be used for the circuit in Fig. 43(C). In the timing chart of Fig. 45, period A has a plurality of sub-periods, namely period A0 to A3, and period B has a plurality of sub-periods, namely period B0 to B3. In period A, after period A1 to A3 are repeatedly arranged, period A0 is arranged. Then, again, in period A, period A1 to A3 are repeatedly arranged. Similarly, in period B, after period B1 to B3 are repeatedly arranged, period B0 is arranged. Then, again, in period B, period B1 to B3 are repeatedly arranged. However, it is not limited to this. In period A, period A0 to A3 repeatedly arranged.​​​​ They can be arranged in various orders. Alternatively, in period B, periods B0 to B3 are They can be arranged in various orders. Alternatively, in period A, any of periods B0 to B3 It is possible to include either or other periods. Alternatively, in period B, period A0 It is possible to place any of the periods ~A3 or other periods. Alternatively, in period A In this case, it is possible to omit any of the periods A0 to A3. Alternatively, in period B... Therefore, it is possible to omit any of the periods B0 to B3. Alternatively, in period A, Period A0 can be placed after any of periods A1 to A3, and other periods It is possible to place it next to the interval. Alternatively, in period B, period B0 is period B1~ It can be placed after any of the B3 periods, and after any other period. It is possible.

[0099] During period A, switches 11_1, 12_1, and 13_1 are turned on in sequence. As a result, switches 11_2, 12_2, and 13_2 turn off. Furthermore, this is not limited to switches 11_1, 12_1, and 13_1. These can be turned on in various orders. Alternatively, switch 11_1, switch 1 2_1 and switch 13_1 can be turned off and on. It is possible. Or, switch 11_2, switch 12_2, and / or switch 13_ Option 2 can be turned on.

[0100] During periods A0, A1, and A2 of period A, switch 13_1 and switch 13 _2 will be turned off. Therefore, paths 123_1 and 123_2 will become non-conductive. However, this is not limited to the case where switch 13_1 and / or switch 13_2 are ON. It is possible to become that.

[0101] During period A3 of period A, switch 13_1 is turned on, and switch 11_1 and switch 1 Switches 1_2, 12_1, 12_2, and 13_2 will be turned off. Then, path 123_1 becomes conductive, and paths 121_1, 121_2, and 122 _1, path 122_2, and path 123_2 become non-conductive. Then wiring 111 and Wiring 112 becomes conductive via switch 13_1, and therefore supplies power to wiring 112. The voltage (e.g., voltage V1) or signal is supplied to the wiring 111 via switch 13_1. In other words, wiring 111 and wiring 112 become electrically connected via path 123_1. Therefore, the voltage (e.g., voltage V1) or signal supplied to wiring 112 is routed through path 123_1. It is supplied to wiring 111 via this.

[0102] During period B, switches 11_2, 12_2, and 13_2 are turned on in sequence. As a result, switches 11_1, 12_1, and 13_1 turn off. Furthermore, it is not limited to this, but also includes switches 11_2, 12_2, and 13_2. These can be turned on in various orders. Alternatively, switch 11_2, switch 1 Switch 2_2 and switch 13_2 can be turned off and on. It is possible. Or, switch 11_1, switch 12_1, and / or switch 13_ 1 can be turned on.

[0103] During period B0, period B1, and period B2 of period B, switch 13_1 and switch 13 _2 turn off. Thus, path 123_1 and path 123_2 become non-conductive . However, it is not limited to this, and switch 13_1 and / or switch 13_2 can turn on .

[0104] During period B3 of period B, switch 13_2 turns on, and switch 11_1, switch 1 1_2, switch 12_1, switch 12_2, and switch 13_1 turn off. Thus , path 123_2 becomes conductive, and path 121_1, path 121_2, path 122 _1, path 122_2, and path 123_1 become non-conductive. Then, wiring 111 and wiring 112 become conductive via switch 13_2, so the voltage (e.g., voltage V1) or signal supplied to wiring 112 is supplied to wiring 111 via switch 13_2 . In other words, wiring 111 and wiring 112 become conductive via path 123_2 , so the voltage (e.g., voltage V1) or signal supplied to wiring 112 is supplied to wiring 111 via path 123_2 .

[0105] In addition, in FIG. 43(C), due to the large number of circuits corresponding to circuit 101 or circuit 102 , the time for the switch to turn on can be shortened. Thus, deterioration of the element or circuit used as the switch, etc., can be suppressed. However, if the number of circuits corresponding to circuit 101 or circuit 102 is too large, the number of switches increases, so the circuit scale becomes too large . Therefore, the number of circuits corresponding to circuit 101 or circuit 102 is preferably 6 or less. More preferably, it is preferably 4 or less. Further​​ Preferably, there are 3 or 2. However, it is not limited to this, circuit 1 The number of circuits corresponding to 01 or circuit 102 can be 1 or 6 or more. It is possible.

[0106] Note that in Figure 43(C), as in Figure 43(A), it corresponds to either circuit 101 or circuit 102. Each of the multiple circuits has three or more switches connected between wire 111 and wire 112. It is possible to have a chi.

[0107] Furthermore, it is possible to divide the wiring into multiple wires. And these multiple wires are... It is possible to input the same signal or voltage, or to input separate signals or voltages. It is possible that the multiple wires are connected to the same wire or element. This is possible, and these multiple wires can be connected to separate wires or components, etc. Yes, there is. In one example shown in Figure 43(E), wiring 112 is connected to multiple wirings called wiring 112A to 112D. The configuration when divided into parts is shown. Between wiring 112A~112D and wiring 111, Switch 11_1, Switch 11_2, Switch 12_1, and Switch 12_2 are connected. Wiring 112A~112D corresponds to wiring 112. Therefore, wiring 112A~11 Voltage V1 can be supplied to 2D, and wiring 112A~112D is a power line and It is possible to function in this way. However, it is not limited to this, and wiring 112A~112D It is possible to input separate voltages or separate signals. Alternatively, wiring 112A~ It is possible to share either wiring 112D, or wiring 112A to 112D. Each of these can be shared with other wiring.

[0108] Furthermore, similar to Figure 43(E), in Figures 43(A) and 43(C), wiring 112 It is possible to divide it into multiple wires. And the wire 111 and the multiple wires It is possible to connect switches in between each of them.

[0109] Next, let's look at an example of using a transistor as a switch, referring to Figure 1(A). Let me explain. Figure 1(A) shows the switches 11_1 and 11_2 of Figure 41(A), and Switch 12_1 and Switch 12_2 are defined as transistors 101_1 and 12_2, respectively. Transistor 101_2, transistor 102_1, and transistor 102_2 are used. The configuration of the case is shown. However, it is not limited to this, and the contents described in Figures 41-45, or these In a configuration combining these elements, it is possible to use a transistor as a switch. For example, in Figures 43(A), 43(C), and 43(E), a switch is used. It is possible to use a generator.

[0110] Furthermore, transistors 101_1, 101_2, 102_1, and The transistor 102_2 is assumed to be an N-channel type. The st is defined as the potential difference (Vgs) between the gate and source exceeding the threshold voltage (Vth). It shall be turned on. However, it shall not be limited to this, transistor 101_1, transistor Transistor 101_2, transistor 102_1, and / or transistor 102_2 are P It is possible for it to be a channel type. A P-channel transistor has a gate and source. The device will turn on when the potential difference (Vgs) between them falls below the threshold voltage (Vth). For this purpose, a CMOS switch can be used as the switch.

[0111] The connection relationships of the semiconductor device in Figure 1(A) will be explained. Transistor 101_1, Transistor Transistor 101_2, transistor 102_1, and the first terminal of transistor 102_2 It is connected to wiring 112. Transistor 101_1, Transistor 101_2, Transistor The second terminals of transistor 102_1 and transistor 102_2 are connected to wiring 111. And then, transistor 101_1, transistor 101_2, transistor 102 The gates of _1 and transistor 102_2 are connected to wiring 113_1 and wiring 113_2, respectively. It is connected to wiring 114_1 and wiring 114_2. However, it is not limited to this, and there are other possibilities. Various connection configurations are possible.

[0112] Wiring 113_1 and wiring 113_2 are, for example, connected to signals S1_1 and S1 Assume that _2 is input. Signals S1_1 and S1_2 are digital signals. In many cases, it can function as a clock signal. Wiring 114_1, and wiring For example, in 114_2, signals S2_1 and S2_2 are input, respectively. Signal S2_1 is the inverted signal of signal S1_1, or a signal with a phase difference of 180° from signal S1_1. Often, these are shifted signals, and can function as inverted clock signals. Therefore, signal S2_2 is the inverted signal of signal S1_2, or has a phase difference of 180° from signal S1_2. Often, the signal is out of sync and can function as an inverted clock signal. And, not limited to this, wiring 111, wiring 112, wiring 113_1, wiring 113_2, Line 114_1 and wiring 114_2 also carry various signals, various currents, or various electrical signals. It is possible to input pressure.

[0113] Signals S1_1 and S1_2 are transmitted at regular intervals (e.g., every frame or every operation period). In many cases, it alternates between active and inactive states. And signal S1 In the case where the active state and inactive state are reversed between _1 and signal S1_2 Many. Similarly, signals S2_1 and S2_2 are given every certain period (for example, every frame). In many cases, it alternates between an active state and an inactive state (or every operating period). Then, the active state and inactive state are reversed between signal S2_1 and signal S2_2. In many cases, this is the case. For example, in the k (k is a natural number)th frame, the signal S1_1 and If signal S2_1 is in the active state, then signals S1_2 and S2_2 are not It becomes active. Then, in the k+1 frame, signal S1_1 and signal S If 2_1 becomes inactive, then signals S1_2 and S2_2 become active. The state becomes B. However, it is not limited to this, and both signal S1_1 and signal S1_2 are the same It is possible to be in the same state (active or inactive). Similarly, signals Both S2_1 and signal S2_2 are in the same state (active or inactive). It is possible to become: or signal S1_1, signal S1_2, signal S2_1, and signal S2_2 is generated every multiple frames, each time power is supplied to the semiconductor device, or randomly. It is possible to repeatedly switch between an active state and an inactive state.

[0114] Note that when a signal is in an active state, it means that the signal can be at either a high (H) or low (L) level. This refers to a state where a signal is inactive. On the other hand, a signal being inactive means that the signal is at a certain value (e.g., For example, it means the signal becomes H level or L level. Here, as an example, the signal becomes inactive. When describing a "tive" state, the signal should be assumed to be at a low level. However, this is not limited to the above. It is not fixed. For example, even when a signal becomes active, the signal does not necessarily have a constant value. This is possible.

[0115] Note that wiring 113_1, wiring 113_2, wiring 114_1, and wiring 114_2 are signals It can function as a line or a clock signal line. However, it is not limited to this. Voltage is supplied to wiring 113_1, wiring 113_2, wiring 114_1, and wiring 114_2. In such cases, these wires can function as power lines.

[0116] Furthermore, it is possible to input multiphase clock signals to semiconductor devices. For example, n(n is It is possible to input a clock signal with a natural number of phases (n-phase) into a semiconductor device. A "phase" refers to n clock signals, each with a different phase. For example, an n-phase clock signal. For example, consider n clock signals, each with a period shifted by 1 / n periods. However, this is not the only example.

[0117] Note that signals S1_1, S2_1, S1_2, and S2_2 are in the active state. In this case, to simplify the circuit that generates the signal, the time to reach L level and the H level It is preferable that the time to become L is approximately equal to this. However, it is not limited to this, and the L level The time it takes to reach level H can be longer than the time it takes to reach level L. The time required can be shorter than the time it takes to reach the H level.

[0118] Equilibrium refers to a duty cycle of approximately 50%, that is, the time between the H level and the L level. This means that the time is approximately equal to the time of the first level. Non-equilibrium means that it is not in equilibrium, that is, H level. This refers to a situation where the time at the L level is different from the time at the L level.

[0119] Next, refer to the timing chart in Figure 1(B) for the operation of the semiconductor device in Figure 1(A). Let me explain. The timing chart in Figure 1(B) corresponds to the timing chart in Figure 42. Yes. Note that the explanation of the parts that are common to the operation in Figure 41(A) will be omitted.

[0120] First, let's explain the operation of period A. During period A, signals S1_1 and S2_1 are It becomes active, and signals S1_2 and S2_2 become inactive. The signals S1_1 and S2_1 alternate between high and low levels in sub-periods. And signals S1_2 and S2_2 become L level. In case 1, the H level and L level are often inverted relative to each other. However, this is not the only case. Furthermore, signals S1_1 and S2_1 can be at L level and H level. It is possible for it to become H. Alternatively, signal S1_2 and / or signal S2_2 are H. It is possible to become a bell.

[0121] During period A1 of period A, signal S1_1 becomes high level, and signals S1_2 and S2_ 1, and signal S2_2 becomes L level. Therefore, as shown in Figure 2(A), the transistor Transistor 101_1 turns on, and transistors 101_2, 102_1, and Transistor 102_2 turns off. Then, wires 111 and 112 connect to the transistor. Since conduction occurs via 101_1, voltage V1 is transmitted from wire 112 to wire 111. It is supplied via ZISTA 101_1.

[0122] During period A2 of period A, signal S2_1 becomes high level, and signal S1_1, signal S1_ 2. And signal S2_2 becomes L level. Therefore, as shown in Figure 2(B), the transistor Transistor 102_1 turns on, and transistors 101_1, 101_2, and Transistor 102_2 turns off. Then, wires 111 and 112 connect to the transistor. Since conduction occurs via 102_1, voltage V1 is transmitted from wire 112 to wire 111. It is supplied via ZISTA 102_1.

[0123] During period A0 of period A, signals S1_1, S1_2, S2_1, and S2 _2 becomes L level. Therefore, as shown in Figure 2(C), transistor 101_1, Transistor 101_2, transistor 102_1, and transistor 102_2 are turned off. Yes. Then, wire 111 and wire 112 become non-conductive.

[0124] Next, we will explain the operation of period B. During period B, signals S1_2 and S2_2 It becomes active, and signals S1_1 and S2_1 become inactive. The signals S1_2 and S2_2 alternate between high and low levels in sub-periods. And signals S1_1 and S2_1 become L level. Signals S1_2 and S2_ In case 2, the H level and L level are often inverted relative to each other. However, this is not the only case. Furthermore, signals S1_2 and S2_2 can be at L level and H level. It is possible for it to become H. Alternatively, signal S1_1 and / or signal S2_1 are H. It is possible to become a bell.

[0125] During period B1 of period B, signal S1_2 becomes H level, and signals S1_1 and S2_ 1. And signal S2_2 becomes L level. Therefore, as shown in Figure 3(A), the transistor Transistor 101_2 turns on, and transistors 101_1, 102_1, and Transistor 102_2 turns off. Then, wires 111 and 112 connect to the transistor. Since conduction occurs via 101_2, voltage V1 is transmitted from wire 112 to wire 111. It is supplied via ZISTA 101_2.

[0126] During period B2 of period B, signal S2_2 becomes H level, and signal S1_1, signal S1_ 2. And signal S2_1 becomes L level. Therefore, as shown in Figure 3(B), the transistor Transistor 102_2 turns on, and transistors 101_1, 101_2, and Transistor 102_1 turns off. Then, wires 111 and 112 connect to the transistor. Since conduction occurs via 102_2, voltage V1 is transmitted from wire 112 to wire 111. It is supplied via ZISTA 102_2.

[0127] During period B0 of period B, signals S1_1, S1_2, S2_1, and S2 _2 becomes L level. Therefore, as shown in Figure 2(C), transistor 101_1, Transistor 101_2, transistor 102_1, and transistor 102_2 are turned off. Yes. Then, wire 111 and wire 112 become non-conductive.

[0128] As described above, the semiconductor device of this embodiment shortens the time the transistor is on. This is possible. Therefore, the degradation of transistor characteristics can be suppressed. Thus, A shift register, gate driver, or display device, etc., are included in the semiconductor device of this embodiment. By doing so, their lifespan can be extended.

[0129] Alternatively, in the semiconductor device of this embodiment, the polarity of all transistors is set to N-channel type or It is possible to make it a P-channel type. Therefore, compared to CMOS circuits, the number of steps It is possible to reduce costs, improve yield, enhance reliability, or lower overall costs. In particular, If all transistors, including the elemental parts, are N-channel type, then the semiconductor layer of the transistor Examples include non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors. It becomes possible to use such semiconductors. However, transistors using these semiconductors will degrade. It is often easy. However, the semiconductor device of this embodiment suppresses transistor degradation. It is possible.

[0130] Alternatively, to ensure that the semiconductor device operates even if the characteristics of the transistor deteriorate, There is no need to increase the channel width of the transistor. Therefore, the channel width of the transistor can be reduced. This is possible because, in the semiconductor device of this embodiment, transistor degradation is suppressed. Because it can be controlled.

[0131] Furthermore, the L level of signals S1_1, S1_2, S2_1, and / or S2_2 It is possible to lower the potential of the signal to V1. In this case, when the signal reaches the L level, A reverse bias is applied to the transistor. Therefore, the degradation of the transistor can be mitigated. Yes, it is possible. However, it is not limited to this, and also applies to signals S1_1, S1_2, S2_1, and Alternatively, the potential of the low level of signal S2_2 can be higher than V1.

[0132] Note that the H level of signals S1_1, S1_2, S2_1, and / or S2_2 It is possible to lower the potential of the terminal below V2. In this case, the signal becomes high level. When a transistor is turned on, the Vgs of the transistor decreases. Therefore, This can suppress the degradation of the zista. However, it is not limited to this, and the signal S1_1, signal The high-level potentials of signals S1_2, S2_1, and / or S2_2 are higher than V2. It is possible.

[0133] Furthermore, the channel width of transistor 101_1 and the channel width of transistor 101_2 are It is preferable that these are approximately equal. Similarly, the channel width of transistor 102_1 and It is preferable that the channel width of transistor 102_2 is approximately equal to that of transistor 102_2. By making the size of the transistors roughly equal, the current capacity is made roughly equal. It is possible to do so. Therefore, even when switching between multiple transistors, the signal waveform can be controlled. These can be made roughly equal. Or, the degree of transistor characteristic degradation can be made roughly It can be made equal. However, it is not limited to this, the channel of transistor 101_1 The channel width and the channel width of transistor 101_2 can be different. The channel width of transistor 102_1 and the channel width of transistor 102_2 are different. It is possible to make it work.

[0134] Note that when referring to the channel width of a transistor, this is referred to as the W / L of the transistor (W: channel width). This can be rephrased as the ratio of channel width (L: channel length).

[0135] Furthermore, as shown in Figure 4(A), similar to Figure 43(E), wiring 112 is connected to wiring 112A~1 It is possible to divide it into multiple wires called 12D. Transistor 101_1, Transistor Transistor 101_2, transistor 102_1, and the first terminal of transistor 102_2 These are connected to wiring 112A, wiring 112B, wiring 112C, and wiring 112D, respectively.

[0136] Furthermore, as shown in Figure 3(C), transistor 101_1 and transistor 101_2 The first terminals can be connected to wires 113_2 and 113_1, respectively. Alternatively, as shown in Figure 4(B), transistor 101_1, transistor 101_2 The first terminals of transistor 102_1 and transistor 102_2 are connected to wiring 1, respectively. It is possible to connect 13_2, wiring 113_1, wiring 114_2, and wiring 114_1. Yes. In this case, during the period when the transistor is turned off by an inactive signal, An active signal is input to the first terminal of the transistor. Therefore, during this period During this time, an L-level signal is input to the gate of the transistor, and an H-level signal is input to the gate. This will include the period during which the signal is input to the first terminal of the transistor. Then, the reverse bias will be applied to the transistor. Since it is applied to the transistor, it can suppress the degradation of the transistor. However, this Not limited to transistors 101_1, 101_2, 102 _1, and the first terminal of transistor 102_2 are connected to wire 114_2 and wire 114, respectively. The same effect can be obtained even when connected as follows: _1, wiring 113_2, wiring 113_1. Alternatively, as shown in Figure 4(C), transistor 101_1, transistor 101 The first terminals of transistors 102_1 and 102_2 are, respectively, It can be connected to wire 114_1, wiring 114_2, wiring 113_1, and wiring 113_2. It is Noh.

[0137] Note that Figure 5(A) shows the configuration when a transistor is used as the switch in Figure 43(C). This shows that, as switch 13_1 and switch 13_2, transistor 103_ 1. Transistor 103_2 is used. Transistor 103_1 is transistor 1 01_1 corresponds to transistor 102_1, and transistor 103_2 is a transistor This corresponds to transistor 101_2 or transistor 102_2. Transistor 103_1 and The first terminal of transistor 103_2 is connected to wiring 112, and transistor 103_1 and The second terminal of transistor 103_2 is connected to wiring 111. The gate of transistor 103_1 is connected to wiring 115_1, and the gate of transistor 103_2 The wire is connected to wiring 115_2. Wiring 115_1 and wiring 115_2 each have, Signals S3_1 and S3_2 are input. Signals S3_1 and S3_2 are Often being a digital signal, it can function as a clock signal.

[0138] Furthermore, the content described in Figure 43(C) can be applied to Figure 5(A).

[0139] Furthermore, similar to Figure 5(A), in Figures 3(C) and 4(A)-(C), the semiconductor device is It is possible to have multiple circuits corresponding to circuit 101 or circuit 102.

[0140] Figure 5(B) shows the configuration when a transistor is used as the switch in Figure 43(A). This shows that the switch 11_1~11_m is a transistor 101_1~101_m. Used as switches 12_1~12_m, transistors 102_1~102_m It is used. The first terminal of transistors 101_1~101_m is connected to wiring 112. The second terminals of transistors 101_1 to 101_m are connected to wiring 111. The gates of transistors 101_1 to 101_m are connected to wiring 113_1 to 113_m, respectively. The first terminals of transistors 102_1 to 102_m are connected to wiring 112. The second terminals of transistors 102_1 to 102_m are connected to wiring 111. The gates of transistors 102_1 to 102_m are connected to wiring 114_1 to 114_m, respectively. Signals S1_1 to S1_m are input to wiring 113_1 to 113_m, respectively. Signals S2_1 to S2_m are input to wires 114_1 to 114_m, respectively. 1_1 to S1_m become active sequentially at regular intervals (for example, every frame). Similarly, signals S2_1 to S2_m are activated sequentially at regular intervals (e.g., every frame). It enters a "b" state. This shortens the period during which the signal is active. Furthermore, the on-time of the transistor can be shortened, thus reducing transistor degradation. It can be suppressed.

[0141] Furthermore, the content described in Figure 43(A) can be applied to Figure 5(B).

[0142] Furthermore, similar to Figure 5(B), in Figures 3(C) and 4(A)~(C), circuit 101, And each of the circuits 102 can have multiple transistors. Or, see Figure 5. In (A) as well, the circuit corresponding to circuit 101 or circuit 102 each has multiple transistors It is possible to have a sta.

[0143] As shown in Figure 6(A), transistor 101_1 is connected to one terminal (hereinafter referred to as the positive terminal). One terminal (hereinafter also called the negative terminal) is connected to wiring 111, and the other terminal (hereinafter also called the negative terminal) is connected to wiring 113_1. It is possible to replace the connected diode 101a_1. Alternatively, the transistor One terminal of terminal 101_2 is connected to wiring 111, and the other terminal is connected to wiring 113_2. It is possible to replace the diode 101a_2 with the transistor 1. One terminal of 02_1 is connected to wiring 111, and the other terminal is connected to wiring 114_1. It is possible to replace it with diode 102a_1. Alternatively, transistor 102 One terminal of _2 is connected to wiring 111, and the other terminal is connected to wiring 114_2. It can be replaced with iod 102a_2.

[0144] Furthermore, as shown in Figure 6(B), transistor 101_1, transistor 101_2, It is possible to connect transistor 102_1 and transistor 102_2 in a diode configuration. In this case, transistor 101_1, transistor 101_2, transistor 1 02_1 and the first terminal of transistor 102_2 are connected to wire 113_1 and wire 1, respectively. 13_2 is connected to wiring 114_1 and wiring 114_2. Transistor 101_1, Transistor 101_2, transistor 102_1, and the second of transistor 102_2 The terminals and gates are connected to wiring 111. However, this is not limited to transistors. 101_1, transistor 101_2, transistor 102_1, and transistor 10 The gates of 2_2 are wires 113_1, 113_2, 114_1, and 11 It is possible to connect to 4_2.

[0145] Furthermore, similar to Figures 6(A) and 6(B), Figures 3(C), 4(A) and 4(C), and 5(A) ~(B) also includes transistors (for example, transistor 101_1, transistor 1 Place transistors 01_2, 102_1, and 102_2) on the diode. It is possible to replace them. Or, the gate of the transistor and the first terminal or the second terminal and By connecting this, it is possible to convert the transistor into a diode connection.

[0146] Furthermore, as shown in Figure 6(C), a P-channel transistor is used as the transistor. It is possible to do so. Transistor 101p_1, Transistor 101p_2, Transistor Transistor 102p_1 and transistor 102p_2 are, respectively, transistor 101_1, This corresponds to transistors 101_2, 102_1, and 102_2. It is a P-channel type. And, if the polarity of the transistor is P-channel type, then wiring 112 Voltage V2 is supplied, and signals S1_1, S1_2, S2_1, and S2_2 are In many cases, the timing chart is reversed compared to Figure 1(B).

[0147] Furthermore, similar to Figure 6(C), Figures 3(C), 4(A)-(C), 5(A)-(B), and Figure In 6(A) and (B), a P-channel transistor is used as the transistor. It is possible.

[0148] (Embodiment 2) This embodiment describes an example of a semiconductor device. The semiconductor device of this embodiment is It is possible to have the semiconductor device of Embodiment 1. The semiconductor device of this embodiment is Lip-flops, shift registers, gate drivers, source drivers, or display devices, etc. It can be used for the following. The semiconductor device of this embodiment is a flip-flop, or This can be indicated as a drive circuit.

[0149] First, an example of the semiconductor device of this embodiment will be described with reference to Figure 7(A). Figure 7 The semiconductor device (A) has circuit 101, circuit 102, and transistor 201. The path 101 is connected to multiple transistors, namely transistor 101_1 and transistor 101_2. Circuit 102 has transistor 102_1 and transistor 102_2 It has multiple transistors.

[0150] Note that transistor 201 is a transistor of transistor 101_1, transistor 101_2, and It is preferable that the polarity is the same as that of transistor 102_1 and transistor 102_2, N It is often a channel type. However, it is not limited to this, and transistor 201 is a P channel. It is possible for it to be a channel type.

[0151] Next, the connection relationships of the semiconductor device in Figure 7(A) will be explained. Transistor 201's first The terminal of the transistor 201 is connected to wiring 211, and the second terminal of the transistor 201 is connected to wiring 111. The first terminal of transistor 101_1 is connected to wiring 112, and the transistor The second terminal of transistor 101_1 is connected to wiring 111. The first terminal of transistor 101_2 The terminal of is connected to wiring 112, and the second terminal of transistor 101_2 is connected to wiring 111 The first terminal of transistor 102_1 is connected to wiring 112, and the transistor The second terminal of transistor 102_1 is connected to wiring 111, and the gate of transistor 102_1 The terminal is connected to wiring 114_1. The first terminal of transistor 102_2 is connected to wiring 1 The second terminal of transistor 102_2 is connected to wire 111, and the transistor The gate of inverter 102_2 is connected to wiring 114_2. However, it is not limited to this. Furthermore, various other connection configurations are possible.

[0152] Note that the gate of transistor 201 is denoted as node A. The gate of transistor 101_1 This is denoted as node B1. The gate of transistor 101_2 is denoted as node B2. Node A, Node B1, and Node B2 can be referred to as wiring.

[0153] Next, an example of an input or output signal or voltage for each wire will be described. Wiring 111 It is assumed that a signal OUT is output from there. A signal CK is input to wiring 211. Let's assume that signal CK corresponds to signal S1 and can function as a clock signal. The voltage V1 is assumed to be input to wiring 112. However, this is not limited to this, These wires can also be used to input various other signals, voltages, or currents. That is the case.

[0154] Furthermore, wiring 211 can function as a signal line or a clock signal line. Furthermore, this is not the only possible use; wiring 211 can function as various other types of wiring. be.

[0155] Next, we will explain the function of transistor 201. Transistor 201 is no The timing of supplying the H-level signal CK to wiring 111 is controlled according to the potential of A. This provides a function to control the timing at which the signal OUT becomes high level, and pull up It can function as a transistor or a bootstrap transistor. For example, transistor 201 turns on during period A0 as described in Embodiment 1. Then, an H-level signal CK is supplied to wiring 111. However, this is not limited to the transistor. The Zista 201 can also have a variety of other functions.

[0156] As shown in Figure 7(B), the semiconductor device may have a circuit 200. Various configurations can be used for circuit 200, and circuit 200 can be one or multiple It shall have a number of transistors. The polarity of these transistors is such that transistor 1 01_1, Transistor 101_2, Transistor 102_1, Transistor 102_2 , and transistor 201 shall have the same polarity. However, this is not limited to this. For example, circuit 200 has an N-channel transistor and a P-channel transistor. It is possible that circuit 200 is a CMOS circuit. Circuit 200 has multiple terminals, namely terminals 200a to 200k. Terminal 200a, Terminal 2 00b, terminal 200c, terminal 200d, terminal 200e, terminal 200f, terminal 200g, end Terminals 200h, 200i, 200j, and 200k are each connected to wiring 211_1 Wiring 211_2, Wiring 114_1, Wiring 114_2, Wiring 212, Wiring 213, Wiring 1 12, Node A, wiring 111, Node B1, Node B2 are connected. However, this is not limited to this. It is not specified, and circuit 200 can have various other terminals, such as terminal 200a It is possible to omit any of the ~200k values. Alternatively, each terminal of circuit 200 can be... It can also be connected to various wiring or nodes.

[0157] Furthermore, wiring 211_1 and wiring 211_2 are connected to signals CK_1 and CK_2, respectively. The signals CK_1 and CK_2 are assumed to be inputs. Signals S1_1 and S1 It corresponds to _2 and can function as a clock signal. Wiring 114_1, Wiring 1 It is assumed that signals CKB_1 and CKB_2 are input to 14_2, respectively. Signal C KB_1 and signal CKB_2 correspond to signals S2_1 and S2_2 respectively, and are inverted crossovers. It can function as a signal. The wiring 212 is to which the signal SP is input. The signal SP is often a digital signal and can function as a start signal. It is possible. Alternatively, signal SP may be a transfer signal, output signal, or from another stage (e.g., the previous stage). It can function as a selection signal, etc. Signal RE is input to wiring 213. The signal RE is often a digital signal and functions as a reset signal. This is possible. Alternatively, signal RE can be the transfer signal or output signal of another stage (e.g., the next stage). It can function as a selection signal or the like. However, it is not limited to this, These wires can also be used to input various other signals, voltages, or currents. be.

[0158] Note that wiring 211_1 and wiring 211_2 function as signal lines or clock signal lines. It is possible to do so. Alternatively, wiring 212 and wiring 213 can be signal lines, gate lines, or These can function as scan lines, etc. However, they are not limited to this, and these arrangements The wire can also function as various other types of wiring.

[0159] Note that circuit 200 has signals CK_1, CK_2, CKB_1, and CKB_2. Signal SP, signal RE, voltage V1, potential of node A, signal OUT, potential of node B1, and / or, depending on the potential of node B2, the potential of node A, signal OUT, the potential of node B1, And / or, it has the function of controlling the potential of node B2 and can function as a control circuit. It is capable of this. However, it is not limited to this, and circuit 200 can have various other functions. It is possible.

[0160] As shown in Figure 8(A), the semiconductor device has circuits 300 and 400. This is possible. Various configurations can be used for circuits 300 and 400. For example, circuit 400 controls the gate potential of transistor 101_1. It has a logic circuit and a logic circuit for controlling the gate potential of transistor 101_2. It is possible to do so. An example of these logic circuits is shown in Figure 20(A) as follows: A logic circuit combining AND and NOT gates at the input, or a two-input circuit as shown in Figure 20(B). There are NOR gates, etc. However, it is not limited to these, and there are various other types of circuits 400. It is possible to use roads.

[0161] Circuits 300 and 400 shall each have one or more transistors. The polarity of these transistors is as follows: transistor 101_1, transistor 101_2, Transistors 102_1, 102_2, and 201 have the same polarity. It shall be assumed that... However, it is not limited to this. For example, circuit 300, and / or... The circuit 400 may have an N-channel transistor and a P-channel transistor. It is possible. In other words, circuit 300 and / or circuit 400 are CMOS circuits. It is possible.

[0162] Circuit 300 has multiple terminals, 300a to 300i. Circuit 400 is It has multiple terminals, terminals 400a to 400f. Terminal 300a, terminal 300b, terminal Child 300c, terminal 300d, terminal 300e, terminal 300f, terminal 300g, terminal 300h , and terminal 300i are wires 211_1, 211_2, 114_1, and 300i respectively. 114_2, Wiring 212, Wiring 213, Wiring 112, Gate of Transistor 201, Wiring Connects to 111. Terminals 400a, 400b, 400c, 400d, terminal Terminals 400e and 400f correspond to wiring 211_1, wiring 211_2, and transistor, respectively. Gate 201, wiring 112, gate of transistor 101_1, transistor 101_ It is connected to gate 2, but is not limited to circuit 300, and / or circuit 4. 00 can also have various other terminals, and terminals 300a to 300i Either or any of terminals 400a to 400f can be omitted. Or, the circuit Each terminal of circuit 300 and / or 400 is connected to various other wires or nodes. It is possible.

[0163] Note that circuit 300 has signals CK_1, CK_2, CKB_1, and CKB_2. Depending on the signal SP, signal RE, voltage V1, the potential of node A, and / or signal OUT, Code A and / or has the function of controlling the potential of wiring 111 and functions as a control circuit. This is possible. Circuit 400 has signals CK_1, CK_2, potential at node A, and voltage. V1, depending on the potential of node B1 and / or node B2, node B1 and / Alternatively, it may have the function of controlling the potential of node B2 and function as a control circuit. However, it is not limited to this, and circuits 300 and 400 also have various other functions. It is possible to do so.

[0164] Next, the operation of the semiconductor device of this embodiment will be described. Here, as an example, Figure 8 Regarding the operation of the semiconductor device (A), see Figures 8(B), 9(A), 9(B), and 10(A) ), Figure 10(B), Figure 11(A), Figure 11(B), Figure 12(A), Figure 12(B), Figure 13 (A) and Figure 13(B) will be explained with reference. Figure 8(B) shows the signal CK, signal CK_ 1. Signal CK_2, Signal CKB_1, Signal CKB_2, Signal SP, Signal RE, Node A Potential (Va), potential at node B1 (Vb1), potential at node B2 (Vb2), and signal O This shows the UT. The duration of one operation (or one frame) in the timing chart in Figure 8(B) is The period has periods T1, T2, T3, T4, and T5. Figure 9(A), Figure 1 Figures 0(A), 11(A), 12(A), and 13(A) each show the k-th frame. Schematic diagram of the operation of the semiconductor device during periods T1, T2, T3, T4, and T5. This is shown in Figures 9(B), 10(B), 11(B), 12(B), and 13(B). These are periods T1, T2, T3, T4, and T5 of the k+1th frame, respectively. A schematic diagram of the operation of the semiconductor device is shown. Note that this is the same as the operation of the semiconductor device in Figure 1(A). However, the explanation will be omitted. Note that the operation of the semiconductor device in Figure 8(A) is explained in Figure 7( This can be applied to the operation of semiconductor devices A) and B).

[0165] First, during period T1 of the k-th frame, signal CKB_1 becomes high, and signal CKB Since _2 becomes low level, transistor 102_1 turns on, and transistor 102 _2 turns off. At the same time, signals CK_1 and CK_2 become low, so the circuit Circuit 400 reduces the potential of nodes B1 and B2. For example, circuit 400 reduces the potential of L The bell signal or voltage V1 is supplied to nodes B1 and B2. Alternatively, circuit 400 Capacitive coupling reduces the potentials of nodes B1 and B2. Therefore, the transient Tube 101_1 and transistor 101_2 are turned off. As a result, the same as in Figure 2(B) As such, wiring 112 and wiring 111 become conductive via transistor 102_1. Voltage V1 is supplied from wiring 112 to wiring 111 via transistor 102_1. At this point, the signal SP becomes high, so circuit 300 raises the potential of node A. For example, circuit 300 supplies a high-level signal or voltage V2 to node A. Then, The potential of node A is the low-level potential (V1) of signal CK, and the threshold voltage of transistor 201. When the sum of (V1 + Vth201) and (Vth201) rises to (V1 + Vth201), transistor 201 It turns on. Therefore, wire 211 and wire 111 become conductive via transistor 201. Therefore, the L-level signal CK is transmitted from wiring 211 through transistor 201 to wiring 11 It is supplied to 1. After that, the potential of node A continues to rise further. And then a certain potential (small At least when it reaches V1 + Vth201 or higher, circuit 300 sends a signal to node A. It stops supplying voltage, etc. Therefore, node A maintains its potential at this time, floating It enters a idle state. As a result, the signal OUT becomes low level.

[0166] Furthermore, during the period T1 of the k-frame, circuit 300 receives an L-level signal or voltage V1. It is possible to supply the following to wiring 111. However, it is not limited to this, and circuit 300 It is possible not to supply signals or voltages to wiring 111.

[0167] On the other hand, during period T1 of the k+1 frame, signal CKB_1 becomes L level, and signal CK Since B_2 becomes high, transistor 102_1 turns off, and transistor 10 The point where 2_2 is turned on is different from the behavior during period T1 of the k-th frame.

[0168] Next, during period T2 of the k-th frame, signal CKB_1 becomes L level, and signal CKB Since _2 remains at the L level, transistor 102_1 turns off, 102_2 remains off. At the same time, signal CK_1 becomes high level, and signal CK_2 The voltage remains at an L level, but the potential at node A remains high, so circuit 400 is no Maintain the potentials of node B1 and node B2 at a low value. For example, circuit 400 is L level signal The signal or voltage V1 continues to be supplied to nodes B1 and B2. Alternatively, circuit 400 is signal Without supplying power or voltage to nodes B1 and B2, nodes B1 and B2 This puts them into a floating state. Therefore, transistors 101_1 and 101_2 are turned off. This remains the case. As a result, as in Figure 2(C), wiring 112 and wiring 111 remain in a non-conductive state. This is what happens when circuit 300 is not supplying signals or voltages to node A. There are many. In other words, node A remains in a floating state, so the potential (V1+V) in period T1 is high. The state (th201 or higher) remains maintained. Therefore, transistor 201 remains on. Therefore, wiring 211 and wiring 111 remain in a conductive state. At this time, signal CK is L As the voltage rises from the bell to the H level, the potential of wiring 111 begins to rise. Then, node A Since it remains in a floating state, the potential of node A is between the gate and the second terminal of transistor 201. It increases due to the parasitic capacity between them. This is the so-called bootstrap behavior. Thus, The potential at node A rises to V2 + Vth201 + α (where α is a positive number). Then, wiring 1 The potential of 11 rises to the potential (V2) of the H-level signal CK. In this way, the signal OUT will be at the H level.

[0169] On the other hand, during the period T2 of the k+1th frame, the signal CK_1 remains at the L level, and the signal The point where CK_2 reaches the H level differs from the behavior during period T2 of the k-th frame. However, Even in this case, since the potential of node A remains high, circuit 400 will not be able to connect nodes B1 and Node A. Maintain the potential of line B2 at a low value.

[0170] Next, during period T3 of the k-th frame, signal CKB_1 becomes high, and signal CKB Since _2 remains at the L level, transistor 102_1 turns on, 102_2 remains off. At the same time, signal CK_1 goes to low level, and signal CK_2 Since it remains at an L level, circuit 400 lowers the potential of nodes B1 and B2 to a low value. Maintain this state. For example, circuit 400 sends an L-level signal or voltage V1 to node B1 and node B1. Continue supplying to node B2. Alternatively, circuit 400 supplies signals or voltages etc. to node B1 and node B1. Without supplying power to node B2, nodes B1 and B2 are left in a floating state. Therefore, the transition Transistors 102_1 and 102_2 remain off. As a result, Figure 2(B) Similarly, wiring 112 and wiring 111 become conductive via transistor 102_1. Therefore, voltage V1 is supplied from wiring 112 to wiring 111 via transistor 102_1. At this time, the signal RE becomes high, so circuit 400 reduces the potential of node A. For example, circuit 400 supplies a low-level signal or voltage V1 to node A. As a result, transistor 201 turns off, and wires 211 and 111 become non-conductive. Therefore, the signal OUT becomes low.

[0171] Furthermore, during the period T3 of the k-frame, circuit 300 receives an L-level signal or voltage V1. It is possible to supply these to wiring 111.

[0172] On the other hand, during period T3 of the k+1 frame, the signal CKB_1 remains at the L level, Since CKB_2 goes to a high level, transistor 102_1 remains off, The point at which `njista102_2` turns on differs from the operation during period T3 in frame k.

[0173] Next, during period T4 of the k-th frame, signal CKB_1 becomes L level, and signal CKB Since _2 remains at the L level, transistor 102_1 turns off, 102_2 remains off. At the same time, signal CK_1 becomes high level, and signal CK_2 Since it remains at an L level, circuit 400 raises the potential of node B1. For example, circuit 4 00 supplies a high-level signal or voltage V2 to node B1. Alternatively, circuit 400, Capacitive coupling increases the potential of node B1. Furthermore, circuit 400 increases the potential of node B2. Maintain a low potential. For example, circuit 400 receives an L-level signal or voltage V1 at the node. To supply to B2. Alternatively, circuit 400 may supply signals or voltages etc. to node B2 without supplying them. Node B2 is put into a floating state. Therefore, transistor 101_1 turns on, and the transistor Sta 101_2 remains off. As a result, wiring 112 and wiring remain off, similar to Figure 2(A). Since 111 and 112 become conductive via transistor 101_1, the voltage V1 is transmitted to wire 112 It is supplied from there to wiring 111 via transistor 101_1. At this time, circuit 300 , maintain the potential of node A at V1. For example, circuit 300 receives an L-level signal or voltage V 1 is supplied to node A. Alternatively, circuit 300 supplies a signal or voltage etc. to node A. By not having it, node A is left in a floating state. Therefore, transistor 201 is turned off. As a result, wiring 211 and wiring 111 remain in a non-conductive state. Thus, The OUT indicator will remain at the L level.

[0174] Furthermore, during the k-frame period T4, circuit 300 receives an L-level signal or voltage V1. It is possible to supply power to wiring 111. However, it is not limited to this, and circuit 300 can also supply power. It is possible not to supply voltage or other signals to wiring 111.

[0175] On the other hand, during period T4 of the k+1 frame, the signal CK_1 remains at a low level, and the signal The point where CK_2 reaches the H level is different from the behavior during period T4 of the k-th frame. Circuit 400 maintains node B1 at a low potential and raises the potential of node B2, so The point where transistor 101_1 remains off and transistor 101_2 turns on The operation during period T4 in the k-th frame is different.

[0176] Next, during period T5 of the k-th frame, signal CKB_1 becomes high level, and signal CKB Since _2 remains at the L level, transistor 102_1 turns on, and transistor 10 2_2 remains off. At the same time, signal CK_1 goes to low level, and signal CK_2 goes low. Since the level remains the same, circuit 400 reduces the potential of node B1. For example, circuit 400 supplies a low-level signal or voltage V1 to node B1. Alternatively, circuit 400 Furthermore, through capacitive coupling, the potential at node B1 is reduced. In addition, circuit 400 is at node B Maintain the potential of 2 at a low value. For example, circuit 400 receives an L-level signal or voltage V1. It supplies power to node B2. Alternatively, circuit 400 does not supply signals or voltages to node B2. Next, node B2 is put into a floating state. Therefore, transistor 101_1 is turned off, and the transistor The inverter 101_2 remains off. As a result, as in Figure 2(B), wiring 111 and Since wiring 112 and transistor 102_1 become conductive, the voltage V1 is connected to wiring 1 Power is supplied from 12 to wiring 111 via transistor 102_1. At this time, circuit 30 0 maintains the potential of node A at V1. For example, circuit 300 receives an L-level signal or electric current. Voltage V1 is supplied to node A. Alternatively, circuit 300 supplies signals or voltages to node A. By not supplying power, node A is left in a floating state. Therefore, transistor 201 Since it remains off, wire 211 and wire 111 remain non-conductive. The signal OUT remains at a low level.

[0177] Furthermore, during the k-frame period T5, circuit 300 receives an L-level signal or voltage V1. It is possible to supply power to wiring 111. However, it is not limited to this, and circuit 300 can also supply power. It is possible not to supply voltage or other signals to wiring 111.

[0178] On the other hand, during period T5 of the k+1 frame, the signal CKB_1 remains at the L level, Since CKB_2 goes to a high level, transistor 102_1 turns off, and the transistor The point where Ta102_2 is turned on differs from the operation of period T5 in the k-th frame.

[0179] As described above, the semiconductor device of this embodiment operates in the k-th frame and the k+1 frame. By repeating the operation in the first position, the time the transistor is on is shortened. This is possible. Therefore, the degradation of transistor characteristics can be suppressed. Thus, A shift register, gate driver, or display device, etc., are included in the semiconductor device of this embodiment. By doing so, their lifespan can be extended.

[0180] Alternatively, the semiconductor device of this embodiment may have all transistors configured to be N-channel or P-channel. It is possible to use a channel type. Therefore, compared to CMOS circuits, the number of manufacturing steps can be reduced. This can lead to a reduction in the number of pixels, improved yield, increased reliability, or cost reduction. If all transistors, including the parts, are N-channel type, then the semiconductor layer of the transistor and And, non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors It becomes possible to use these. However, transistors using these semiconductors degrade. It is often easy. However, the semiconductor device of this embodiment suppresses transistor degradation. It is possible.

[0181] Alternatively, to ensure that the semiconductor device operates even if the characteristics of the transistor deteriorate, There is no need to increase the channel width of the transistor. Therefore, the channel width of the transistor can be reduced. This is possible because, in the semiconductor device of this embodiment, transistor degradation is suppressed. Because it can be controlled.

[0182] In Figure 8(B), period T2 is indicated as the selected period, and the other periods (period T1, period Periods T3, T4, and T5 can be designated as non-selective periods. T1, period T2, period T3, period T4, and period T5 are set as set period, output period, respectively. These can be referred to as the reset period, the first non-selection period, and the second non-selection period.

[0183] As shown in Figure 14(A), the signals CK, CK_1, CK_2, and CKB are as follows: In _1 and signal CKB_2, the time it takes to reach a high level is shorter than the time it takes to reach a low level. This makes it possible to do so. By doing so, during period T2, the signal CK will reach an L level. At that time, the potential of node A remains high, so transistor 201 remains on. Therefore, wiring 211 and wiring 111 remain in a conductive state via transistor 201. Therefore, the low-level signal CK is transmitted from wire 211 to wire 111 via transistor 201. It is supplied. The channel width of transistor 201 is often large, so the potential of wiring 111 It quickly decreases to V1. Therefore, the falling edge time of signal OUT can be shortened. It can be done. However, it is not limited to this, and includes signals CK, CK_1, CK_2, and CKB. In _1 and signal CKB_2, the time spent at the H level is longer than the time spent at the L level. It is possible.

[0184] Furthermore, as shown in Figure 14(B), during the period T2, a voltage V1 or L-level signal is applied. By supplying power to node A and wiring 111, the signal OUT can be set to a low level. This is possible. By doing so, the drive frequency can be slowed down, thus reducing power consumption. It is possible to reduce the risk.

[0185] Furthermore, as shown in Figure 5(A), the semiconductor device duplicates the circuit corresponding to circuit 101 or circuit 102. In the case of multiple devices, it is possible to input multiphase clock signals to the semiconductor device. Figure 15( A) shows an example of a timing chart when a three-phase clock signal is input to a semiconductor device. This indicates, however, that it is not limited to this.

[0186] Furthermore, as shown in Figure 5(B), if circuit 101 or circuit 102 has multiple transistors... This is possible. Figure 15(B) shows that circuit 101 or circuit 102 has three transistors An example of a timing chart in the case of having this is shown. However, it is not limited to this.

[0187] Note that the channel width of transistor 201 is the same as that of transistor 101_1 and transistor 10 Larger than the channel width of transistors 1_2, 102_1, and 102_2 This is preferable. By doing so, the on-resistance of transistor 201 becomes smaller. Therefore, the rise time or fall time of the signal OUT can be shortened. Furthermore, and not limited to this, the channel width of transistor 201 is, transistor 101_1, Transistor 101_2, transistor 102_1, and / or transistor 102_ It is possible to have a channel width smaller than 2.

[0188] Furthermore, in transistor 201, the parasitic capacitance between the gate and the second terminal is the gate and It is preferable that the capacitance between the first terminal and the parasitic capacitance is greater than the parasitic capacitance between the terminals. This is because, during period T2, This is because the potential of node A tends to increase due to the bootstrap operation. Therefore, a conductive layer that functions as a gate and a conductive layer that functions as a source or drain are The overlapping area is preferably larger on the second terminal side than on the first terminal side. This is not limited to this.

[0189] Furthermore, as described in Embodiment 1, it is possible to divide the wiring into multiple wires. Therefore, it is possible to input the same signal or voltage to these multiple wires, or to input them separately. It is possible to input signals or voltages, etc. Alternatively, the multiple wires may be connected to the same wire. Alternatively, they can be connected to elements, and these multiple wires can be connected to separate wires or elements. It can be connected to the following. Figure 16(A) shows, as an example, wiring 112. This shows the configuration when the wiring is divided into multiple lines, 112A to 112D.

[0190] Furthermore, similar to Figure 16(A), Figures 7(B) and 8(A) also show multiple wiring configurations. It is possible to divide it into lines. Note that this applies not only to wiring 112, but also to wiring 114_1 and wiring 1 14_2, wiring 211, wiring 211_1, wiring 211_2, wiring 212, and / or, wiring It is possible to divide wire 213 into multiple wires.

[0191] Furthermore, as shown in Figure 16(B), the first terminal of transistor 101_1 and the transistor The first terminal of station 101_2 is connected to wires 211_1 and 211_2, respectively. This is possible. The first terminal of transistor 102_1 and the first terminal of transistor 102_2 The first terminal can be connected to wiring 114_2 and wiring 114_1, respectively. By doing so, as in Figure 4(B), transistors 101_1 to 101_2, and Since a reverse bias can be applied to transistors 102_1~102_2, This can suppress the degradation of transistors. However, it is not limited to this, The first terminal of transistor 101_1, the first terminal of transistor 101_2, transistor 10 The first terminal of 2_1 and the first terminal of transistor 102_2 are connected to various wires or It can be connected to various nodes. For example, the first terminal of transistor 101_1 The child and the first terminal of transistor 101_2 are connected to node B2 and node B1, respectively. It is possible to do so.

[0192] Furthermore, similar to Figure 16(B), in Figures 7(B) and 8(A), transistor 1 The first terminal of 01_1 and the first terminal of transistor 101_2 are connected to wiring 211, respectively. _1, can be connected to wiring 211_2. The first of transistor 102_1 The terminals and the first terminal of transistor 102_2 are connected to wire 114_1 and wire 114, respectively. It is possible to connect it to _2.

[0193] Furthermore, as shown in Figure 17(A), between the gate and the second terminal of transistor 201, It is possible to connect a new capacitive element 202. In this way, the boot during period T2 During strap operation, the potential of node A can be increased. Therefore, transistor 2 Since the Vgs of 01 will increase, the falling or rising time of the signal OUT will be increased. It can be shortened. However, it is not limited to this, and the capacitive element 202 can be a transient It is possible to use the st as a MOS capacitance. In this case, the st used as a MOS capacitance To increase the capacitance of the transistor, the gate of the transistor is connected to node A. Therefore, it is preferable that the first or second terminal of the transistor be connected to the wiring 111. It seems so.

[0194] Furthermore, similar to Figure 17(A), Figures 7(B), 8(A), and 16(A)-(B) are also shown. Even if a capacitive element 202 is newly connected between the gate and the second terminal of transistor 201 It is possible to continue.

[0195] Furthermore, it is possible to split the output signal into two. For example, one output signal can be used in another stage. It can function as a signal for transfer to a flip-flop (for example, the next stage). The other output signal can function as a signal output to a pixel. For example. As shown in Figure 17(B), transistor 203 can be newly added. Transistor 203 has the same function as transistor 201 and is an N-channel type. In many cases, the first terminal of transistor 203 is connected to wiring 211, and the transistor The second terminal of transistor 203 is connected to wiring 212, and the gate of transistor 203 is connected to the transistor It connects to the gate of Zista 201.

[0196] However, it is not limited to this, and transistor 203 can also be a P-channel type. Alternatively, the first terminal of transistor 203 and the first terminal of transistor 201 are It is possible to connect them with separate wiring. Alternatively, the gate and transistor 203 can be connected. The gate of the ENGISTA 201 can be connected to separate wiring.

[0197] Furthermore, as shown in Figure 18, not only transistor 203, but also circuit 231 and circuit 23 It is possible to add a second circuit. Circuit 231 has the same function as circuit 101. Circuit 232 has the same function as circuit 102. Circuit 231 has transistor 231_ Circuit 232 has multiple transistors, namely transistor 1 and transistor 231_2, and the circuit 232 is a transistor It has multiple transistors, namely transistor 232_1 and transistor 232_2. Transistor 231_1, Transistor 231_2, Transistor 232_1, and Transistor Transistor 232_2 consists of transistors 101_1, 101_2, and 232_2 respectively. It is assumed that the transistors correspond to 102_1 and 102_2, and are of the N-channel type. Transistors 231_1, 231_2, 232_1, and The first terminal of transistor 232_2 is connected to wiring 112. Transistor 231_ 1. Transistors 231_2, 232_1, and 232_2 The second terminal is connected to wiring 212. Transistor 231_1, Transistor 231 The gates of transistors 232_1 and 232_2 are, respectively, nodes. It is connected to B2, node B3, wiring 114_1, and wiring 114_2. However, it is not limited to this. Transistor 231_1, Transistor 231_2, Transistor 232_1, And / or, transistor 232_2 can be a P-channel type. , transistor 231_1, transistor 231_2, transistor 232_1, and / Alternatively, the first or second terminal of transistor 232_2 may be connected to separate wires. It is possible to do so.

[0198] In Figures 17(B) and 18, the output signal from wiring 111 is supplied to the pixel. If the signal is such that the output signal from wiring 212 is a signal for transfer, then transistor 20 The channel width of 3 is preferably smaller than the channel width of transistor 201. Why? Therefore, since wiring 111 is connected to a gate line or pixel, the load on wiring 111 is This is because it is often greater than the load on line 212. However, this is not limited to this, and wiring 1 The signal output from 11 is the transmission signal, and the signal output from wiring 212 is the signal to the pixel. If it is an output signal, the channel width of transistor 203 is the same as that of transistor 201. It is possible to have a value larger than the channel width.

[0199] In Figures 17(B) and 18, the output signal from wiring 111 is supplied to the pixel. If the signal is such that the output signal from wiring 212 is a signal for transfer, then transistor 23 1_1, transistor 231_2, transistor 232_1, and transistor 232_ The channel width of 2 is: transistor 101_1, transistor 101_2, transistor 1 It is preferable that 02_1 is smaller than the channel width of transistor 102_2. Since wiring 111 is connected to a gate line or pixel, the load on wiring 111 is on wiring 2 This is because the load is often greater than 12. However, this is not limited to this, and the transit Transistor 231_1, Transistor 231_2, Transistor 232_1, and Transistor 2 The channel width of 32_2 is, transistor 101_1, transistor 101_2, transistor It is possible to have a channel width greater than that of transistor 102_1 and transistor 102_2.

[0200] Note that in Figures 17(B) and 18, the gate and the second terminal of transistor 203 are It is possible to connect a capacitive element in between.

[0201] Note that, similar to Figures 17(B) and 18, Figures 7(B), 8(A), 16(A)~( B), and also in Figure 17(A), transistor 203, circuit 231, and / or rotation It is possible to add a new route, Route 232.

[0202] As shown in Figure 19(A), a P-channel transistor is used as the transistor. It is possible to have: Transistor 101p_1, Transistor 101p_2, Transistor Transistor 102p_1, transistor 102p_2, and transistor 201p are, respectively, Transistor 101_1, Transistor 101_2, Transistor 102_1, Transistor It corresponds to transistor 102_2 and transistor 201, and is a P-channel type. When the polarity of the sta is P-channel type, as shown in Figure 19(B), the voltage V is applied to wiring 112. 2 is supplied, signal CK, signal CK_1, signal CK_2, signal CKB_1, signal CKB_ 2. Potentials Va, Vb1, Vb2, and signal OUT are timed as shown in Figure 8(B). Compared to charts, they are often inverted.

[0203] Furthermore, similar to Figure 19(A), Figures 7(B), 8(A), 16(A)-(B), and 17 (A)~(B), and also in Figure 18, the transistor is a P-channel type transistor. It is possible to use "ta".

[0204] (Embodiment 3) In this embodiment, a specific example of the circuit 300 described in Embodiment 2 will be explained. Circuit 300 can be described as a semiconductor device, a drive circuit, or a gate driver. The contents described in Embodiments 1 and 2 will not be explained further. The contents described in Embodiments 1 and 2 can be freely combined with the contents described in this embodiment. It is possible.

[0205] First, an example of circuit 300 will be explained with reference to Figure 21(A). Circuit 300 is... Transistor 301, Transistor 302, Transistor 303, Transistor 304_1 , transistor 304_2, transistor 305_1, and transistor 305_2 However, it is not limited to this, and circuit 300 can have various other features. Alternatively, circuit 300 may omit any of these transistors. That is the case.

[0206] Note that transistors 301, 302, 303, and 3 04_1, transistor 304_2, transistor 305_1, and transistor 305 _2 is preferably of the same polarity as transistor 201 and is of the N-channel type. This shall apply. However, it shall not be limited to transistor 301, transistor 302, and transistor 301. ZISTA 303, Transistor 304_1, Transistor 304_2, Transistor 305 Transistor _1 and transistor 305_2 can be P-channel type.

[0207] Next, an example of the connection relationship of circuit 300 will be described. The first terminal of transistor 301 It is connected to wiring 212, and the second terminal of transistor 301 is connected to node A. The gate of transistor 301 is connected to wiring 212. The first of transistor 302 The terminal is connected to wiring 112, and the second terminal of transistor 302 is connected to node A. The gate of transistor 302 is connected to wiring 213. Terminal 1 is connected to wire 112, and the second terminal of transistor 303 is connected to wire 111. The gate of transistor 303 is connected to wiring 213. Transistor 30 Terminals 4_1 and the first terminal of transistor 304_2 are connected to wiring 212. The second terminals of transistor 304_1 and transistor 304_2 are connected to node A. The gates of transistors 304_1 and 304_2 are connected to wiring 114, respectively. _1, connected to wiring 114_2. Transistor 305_1 and transistor 305 The first terminal of _2 is connected to node A. Transistor 305_1, and transistor The second terminal of transistor 305_2 is connected to wiring 111. Transistor 305_1, and The gates of transistor 305_2 are connected to wires 211_1 and 211_2, respectively. However, this is not the only possible connection configuration; various other connection configurations are also possible.

[0208] Next, we will explain an example of the function of each transistor. Transistor 301 is a signal Depending on the SP number, the continuity state between wiring 212 and node A is controlled, thereby achieving an H level. It has the function of controlling the timing of supplying the signal to node A, and functions as a diode. It is possible to do so. Transistor 302, in response to signal RE, connects to wiring 112 and node A By controlling the conduction state, the timing at which voltage V1 is supplied to node A can be controlled. It has the function of controlling and can function as a switch. Transistor 303 is By controlling the conduction state between wiring 112 and wiring 111 in response to signal RE, the voltage V1 has the function of controlling the timing at which it is supplied to wiring 111, and functions as a switch. It is possible to do so. Transistor 304_1, in response to signal CKB_1, wire 212 By controlling the conduction state between node A and node A, the signal SP is supplied to node A. It has the function of controlling the ming and can function as a switch. (Transistor) 304_2 controls the conduction state between wiring 212 and node A in response to signal CKB_2. This has the function of controlling the timing at which signal SP is supplied to node A, It can function as a switch. Transistor 305_1 responds to the signal CK_1. It has the function of controlling the conductivity between node A and wiring 111, and functions as a switch. This is possible. Transistor 305_2 is wired to node A in response to signal CK_2. It has a function to control the conductivity state with 111 and can function as a switch. However, these transistors are not limited to this and can have a variety of other functions. It is Noh.

[0209] Next, regarding the operation of the semiconductor device in Figure 21(A), refer to the timing chart in Figure 8(B). I will explain by referring to it.

[0210] First, during the k-frame period T1, the signal SP becomes high, so the transistor 301 turns on. At the same time, signal CKB_1 becomes high level and signal CKB_2 becomes low level. As the bell is activated, transistor 304_1 turns on and transistor 304_2 turns off. Therefore, since wiring 212 and node A become conductive, signal SP is connected to wiring 212. It is supplied from to node A. Then the potential of node A begins to rise. At this time, signal C Since K_1 and signal CK_2 become low, transistor 305_1 and the transistor Station 305_2 turns off. Therefore, node A and wiring 111 become non-conductive. Since the signal RE is at a low level, transistors 302 and 303 are turned off. Therefore, wiring 112 and node A become non-conductive, and wiring 112 and wiring 111 The two become non-conductive. After that, the potential of node A is equal to the potential of the H-level signal SP (V2) Then, subtract the threshold voltage of transistor 301 (Vth301) and (V2-Vth301) and At that point, transistor 301 turns off. Similarly, the potential of node A reaches the high level. The threshold voltage (Vth304) of transistor 304_1 is obtained from the potential (V2) of the signal CKB_1. When the value obtained by subtracting _1) is (V2 - Vth304_1), transistor 304_ 1 turns off. Here, when the potential of node A becomes V2-Vth301, Assume that transistors 301 and 304_1 are turned off. Therefore, wiring 212 and node Node A becomes non-conductive. As a result, node A becomes floating, and the potential changes from V2 to Vt. Maintain h301.

[0211] On the other hand, during period T1 of the k+1 frame, signal CKB_1 becomes L level, and signal CK Since B_2 becomes high, transistor 304_1 turns off, and transistor 30 The point where 4_2 is turned on is different from the behavior during period T1 of the k-th frame.

[0212] Next, during the k-frame period T2, the signal SP becomes L level, so the transistor 301 remains off. Then, signal CKB_1 goes to L level, and signal CKB_2 Since it remains at the L level, transistors 304_1 and 304_2 are turned off. This remains the case. Therefore, wiring 212 and node A remain in a non-conductive state. At this time, Signal CK_1 becomes high, while signal CK_2 remains low. However, node A The potential is V2 + Vth201 + β (where β is a positive number), so transistor 305_1 and Transistor 305_2 remains off. Therefore, node A and wiring 111 are not connected. The circuit remains in a conductive state. And since the signal RE remains at a low level, transistor 302 , and transistor 303 remains off. Therefore, wiring 112 and node A are decoupled. The circuit remains in a conductive state, and wiring 112 and wiring 111 remain in a non-conductive state.

[0213] On the other hand, during period T2 of the k+1 frame, the signal CKB_1 remains at a low level, The point where CKB_2 reaches the H level differs from the operation during period T2 of the k-th frame. And even in this case, the potential of node A becomes V2 + Vth201 + β, so the transistor Transistors 305_1 and 305_2 remain off.

[0214] Next, in period T3 of frame k, the signal SP remains at an L level, so the transient The TA301 remains off. Then, the signal CKB_1 becomes high level, and the signal CKB_ Since 2 remains at the L level, transistor 304_1 turns on, and transistor 3 04_2 remains off. Therefore, wiring 212 and node A become conductive, A low-level signal SP is supplied to node A from wiring 212. At this time, signal CK_1 The signal CK_2 remains at a low level, so transistor 305_1 and Transistor 305_2 remains off. Therefore, node A and wiring 111 are not connected. The conduction state remains. And, since the signal RE becomes high level, transistor 302 and Transistor 303 turns on. Therefore, wiring 112 and node A become conductive. Then, wiring 112 and wiring 111 become electrically connected. Then, voltage V1 is transmitted from wiring 112. Power is supplied to wire A, and voltage V1 is supplied from wire 112 to wire 111.

[0215] On the other hand, during period T3 of the k+1 frame, signal CKB_1 becomes L level, and signal CK Since B_2 becomes high, transistor 304_1 turns off, and transistor 30 The point where 4_2 is turned on is different from the operation of period T3 in the k-th frame.

[0216] Next, in period T4 of frame k, the signal SP remains at an L level, so the transient The TA301 remains off. Then, the signal CKB_1 goes to L level, and the signal CKB_ Since 2 remains at the L level, transistor 304_1 turns off, and transistor 3 04_2 remains off. Therefore, wiring 212 and node A remain non-conductive. At this time, signal CK_1 becomes high level, while signal CK_2 remains low level. As a result, transistor 305_1 turns on, while transistor 305_2 remains off. Therefore, node A and wiring 111 become conductive. And signal RE becomes low. Therefore, transistors 302 and 303 turn off. Thus, wiring 11 Node 2 and node A become non-conductive, and wiring 112 and wiring 111 become non-conductive.

[0217] On the other hand, during period T4 of the k+1 frame, the signal CK_1 remains at a low level, and the signal Since CK_2 becomes high level, transistor 305_1 remains off, and the transistor The point where STA305_2 is turned on differs from the operation of period T4 in the k-th frame.

[0218] Next, in period T5 of frame k, the signal SP remains at an L level, so the transient The TA301 remains off. Then, the signal CKB_1 becomes high level, and the signal CKB_ Since 2 remains at the L level, transistor 304_1 turns on, and transistor 3 04_2 remains off. Therefore, wiring 212 and node A become conductive, A low-level signal SP is supplied to node A. At this time, signal CK_1 becomes low. Since the signal CK_2 remains at a low level, transistor 305_1 turns off, The transistor 305_2 remains off. Therefore, there is no conductivity between node A and wiring 111. This is the state. And since the signal RE remains at the L level, transistor 302 and the transistor... Zistor 303 remains off. Therefore, wiring 112 and node A become non-conductive. Wiring 112 and wiring 111 remain in a non-conductive state.

[0219] On the other hand, during period T5 of the k+1 frame, the signal CKB_1 remains at the L level, Since CKB_2 goes to a high level, transistor 305_1 remains off, The point at which the 'njista305_2' is turned on differs from the operation during period T5 in frame k.

[0220] As described above, the semiconductor device of this embodiment operates in the k-th frame and the k+1 frame. By repeating the operation in the first position, the time the transistor is on is shortened. This is possible. Therefore, the degradation of transistor characteristics can be suppressed. Thus, A shift register, gate driver, or display device, etc., are included in the semiconductor device of this embodiment. By doing so, their lifespan can be extended.

[0221] In particular, transistor 304_1, transistor 304_2, transistor 305_1, and Transistor 305_2 has a period of being off and a period of repeatedly switching between on and off. It has. Therefore, the on time of the transistor is shortened, so the transistor It is possible to suppress the degradation of characteristics.

[0222] Alternatively, the semiconductor device of this embodiment may have all transistors configured to be N-channel or P-channel. It is possible to use a channel type. Therefore, compared to CMOS circuits, the number of manufacturing steps can be reduced. This can lead to a reduction in the number of pixels, improved yield, increased reliability, or cost reduction. If all transistors, including the parts, are N-channel type, then the semiconductor layer of the transistor and And, non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors It becomes possible to use these. However, transistors using these semiconductors degrade. It is often easy. However, the semiconductor device of this embodiment suppresses transistor degradation. It is possible.

[0223] Alternatively, to ensure that the semiconductor device operates even if the characteristics of the transistor deteriorate, There is no need to increase the channel width of the transistor. Therefore, the channel width of the transistor can be reduced. This is possible because, in the semiconductor device of this embodiment, transistor degradation is suppressed. Because it can be controlled.

[0224] Furthermore, the channel width of transistor 304_1 and the channel width of transistor 304_2 are It is preferable that they are roughly equal. Alternatively, the channel width of transistor 305_1 and It is preferable that the channel width is approximately equal to that of the Rangista 305_2. This is because the traction Transistor 304_1 and transistor 304_2 have similar functions, and transistor 30 This is because transistors 5_1 and 305_2 have similar functions. However, this is not limited to... The channel width of transistor 304_1 is not determined, and the channel width of transistor 304_2 is not determined. It can be larger than the width, or smaller. Or, transistor 3 The channel width of transistor 05_1 can be larger than the channel width of transistor 305_2. And it is possible to do it on a small scale.

[0225] Furthermore, the channel width of transistor 303 is larger than the channel width of transistor 302. This is preferable because the load on wiring 111 may be greater than the load on node A. Because there are many. However, this is not the only reason; the channel width of transistor 303 is also It is possible to have a channel width smaller than that of the 302.

[0226] Furthermore, it is possible to omit some of the transistors in circuit 300. For example, It is possible to omit either transistor 305_1 or transistor 305_2. In this case, the other gate of transistor 305_1 and transistor 305_2 receives a signal. It is possible to input CK. In Figure 21(B), transistor 305_2 is omitted. The configuration in this case is shown. However, it is not limited to this, and various other transistors can be omitted. This is possible. For example, both transistor 305_1 and transistor 305_2 It is possible to omit them. Alternatively, transistors 304_1 and 304_2 It is possible to omit one of them. In this case, transistor 304_1 and transistor The other gate, TA304_2, can be input with the signal CKB. Alternatively, It is possible to omit both transistor 304_1 and transistor 304_2. Alternatively, transistor 302 can be omitted. The number 3 can be omitted.

[0227] Furthermore, as shown in Figure 5(B) of Embodiment 1, circuits 101 and 102 have m transistors If a transistor is present, as shown in Figure 22(A), the circuit 300 has transistor 304_1 Multiple transistors named ~304_m and transistors 305_1~305_m It is possible to have multiple transistors. Transistors 304_1~304_m This corresponds to transistor 304_1 or transistor 304_2, and transistor 305 _1~305_m corresponds to transistor 305_1 or transistor 305_2.

[0228] Note that, similar to Figure 22(A), in Figure 21(B), circuit 300 also has transistor 3 Multiple transistors, namely 04_1~304_m, and transistors 305_1~305_ It is possible to have multiple transistors, namely m.

[0229] Furthermore, as shown in Figure 22(B), transistor 305_1 and transistor 305_ The first terminal of 2 is connected to wiring 112, transistor 305_1, and transistor The gates of 305_2 can be connected to nodes B1 and B2, respectively. However, this is not limited to the following, the first of transistors 305_1 and 305_2 Terminal 1 can be connected to wires 114_2 and 114_1, respectively. Alternatively, the first terminals of transistor 305_1 and transistor 305_2 are, respectively, It is possible to connect wire 211_2 and wiring 211_1. Alternatively, transistor 3 The first terminals of transistor 05_1 and transistor 305_2 are node B2 and node B1, respectively. It is possible to connect to it.

[0230] Furthermore, similar to Figure 22(B), in Figures 21(B) and 22(A), the transitions The first terminals of transistors 305_1 and 305_2 are connected to wiring 112, The gates of transistor 305_1 and transistor 305_2 are, respectively, node B1 and node B1. It can be connected to the B2.

[0231] As shown in Figure 23(A), the first terminal of transistor 301 is connected to wiring 214. It is possible to continue. Voltage V2 is supplied to wiring 214, and wiring 214 is power supply It can function as a line. However, it is not limited to this, and wiring 214 can function as a line for a period of time. It is possible to input a signal that becomes high level at T1.

[0232] Furthermore, similar to Figure 23(A), in Figures 21(B) and 22(A)~(B), The first terminal of the transistor 301 can be connected to the wiring 214.

[0233] As shown in Figure 23(B), a P-channel transistor is used as the transistor. It is possible to have: transistor 301p, transistor 302p, transistor 3 03p, Transistor 304_1p, Transistor 304_2p, Transistor 305_ 1p and transistor 305_2p are transistors 301 and 30 2, Transistor 303, Transistor 304_1, Transistor 304_2, Transistor It corresponds to transistor 305_1 and transistor 305_2, and is a P-channel type. When the transistor polarity is P-channel type, as shown in Figure 19(B), wiring 112 has Voltage V2 is supplied, and signals CK, CK_1, CK_2, CKB_1, and signal Compare CKB_2, potential Va, and signal OUT with the timing chart in Figure 8(B). Often, it's reversed.

[0234] Furthermore, similar to Figure 23(B), Figures 21(B), 22(A)-(B), and 23(A) In this case, a P-channel transistor can be used as the transistor. .

[0235] (Embodiment 4) In this embodiment, a specific example of the circuit 400 described in Embodiment 2 will be explained. Circuit 400 can be described as a semiconductor device, a drive circuit, or a gate driver. The contents described in Embodiments 1 and 2 will not be explained further. The contents described in Embodiments 1 to 3 can be freely combined with the contents described in this embodiment. It is possible.

[0236] First, an example of circuit 400 will be explained with reference to Figure 24(A). Circuit 400 is... Transistor 401_1, Transistor 401_2, Transistor 402_1, Transistor It has a 402_2 capacitor, a 403_1 capacitor, and a 403_2 capacitor. However, it has Without limitation, circuit 400 can have a variety of other things. Or, circuit The 400 can omit either of these transistors or capacitive elements.

[0237] Furthermore, transistors 401_1, 401_2, 402_1, and It is preferable that transistor 402_2 has the same polarity as transistor 201, N It is assumed to be a channel type. However, it is not limited to this, transistor 401_1, Transistor 401_2, transistor 402_1, and transistor 402_2 are P-type It is possible for it to be a channel type.

[0238] Next, an example of the connection relationship of circuit 400 will be explained. Transistor 401_1's first The terminal is connected to wiring 112, and the second terminal of transistor 401_1 is connected to node B1. The gate of transistor 401_1 is connected to node A. Transistor 4 The first terminal of 01_2 is connected to wiring 112, and the second terminal of transistor 401_2 It is connected to node B2, and the gate of transistor 401_2 is connected to node A. The first terminal of transistor 402_1 is connected to wiring 112, and transistor 402 The second terminal of _1 is connected to node B1, and the gate of transistor 402_1 is wired It is connected to 211_2. The first terminal of transistor 402_2 is connected to wiring 112. The second terminal of transistor 402_2 is connected to node B2, and transistor 40 The gate of 2_2 is connected to wiring 211_1. One electrode of the capacitive element 403_1 is The other electrode of the capacitive element 403_1 is connected to node B1, and the wiring 211_1 is connected to node B1. One electrode of the capacitive element 403_2 is connected to the wiring 211_2, and the capacitive element 403_ The other electrode of 2 is connected to node B2. However, this is not the only option, and various other connections are possible. It is possible to configure it as a connected system.

[0239] Next, we will describe some examples of the functions of each transistor and each capacitive element. Station 401_1 controls the conductivity between wiring 112 and node B1 according to the potential of node A. By controlling this, it has the function of controlling the timing at which voltage V1 is supplied to node B1. And it can function as a switch. Transistor 401_2 is at node A By controlling the conduction state between wiring 112 and node B2 according to the potential, the voltage V1 It has the function of controlling the timing of when it is supplied to node B2 and functions as a switch. This is possible. Transistor 402_1, in response to the signal CK_2, is connected to wiring 112 and no By controlling the conductivity state with node B1, the timing at which voltage V1 is supplied to node B1 is controlled. It has the function of controlling the ng and can function as a switch. Transistor 4 02_2 controls the conduction state between wiring 112 and node B2 in accordance with signal CK_1. This has the function of controlling the timing at which voltage V1 is supplied to node B2, and It can function as a switch. Capacitive element 403_1 responds to signal CK_1, It has the function of controlling the potential of node B1. Capacitive element 403_2 responds to the signal CK_2. It has the function of controlling the potential of node B2. However, it is not limited to these Rangitators and capacitive elements can also have a variety of other functions.

[0240] Next, regarding the operation of the semiconductor device in Figure 24(A), refer to the timing chart in Figure 7(B). I will explain by referring to it.

[0241] First, in the k-th frame period T1, the potential of node A is high (for example, (V2-Vt This results in h301), so transistors 401_1 and 401_2 turn on. At this time, signal CK_1 becomes L level and signal CK_2 becomes L level, Transistor 402_1 and transistor 402_2 are turned off. Therefore, wiring 112 and Node B1 becomes conductive, and wiring 112 becomes conductive to node B2. Then, Voltage V1 is supplied from wiring 112 to node B1, and voltage V1 is supplied from wiring 112 to node B2 It is supplied to.

[0242] Next, in the k-th frame period T2, the potential of node A is high (for example, (V2+Vt Since it remains h201+α), transistors 401_1 and 401_2 are O It remains as is. At this time, signal CK_1 becomes high level and signal CK_2 becomes low level As a result, transistor 402_1 remains off, and transistor 402_2 This is turned on. Therefore, wiring 112 and node B1 remain in a conductive state, and wiring 112 The circuit remains in a conductive state with node B2. Then, voltage V1 is transmitted from wiring 112 to node B1. The voltage V1 is supplied to node B2 from wiring 112.

[0243] On the other hand, during the period T2 of the k+1th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes high level, transistor 402_1 turns on, and transistor 4 The point where 02_2 turns off is different from the operation during period T2 in the k-th frame.

[0244] Next, in period T3 of frame k, the potential of node A becomes V1, so the transient Transistors 401_1 and 401_2 are turned off. At this time, signal CK_1 is at a low level. As a result, the signal CK_2 remains at a low level, so transistor 402_1 turns off. As a result, transistor 402_2 turns off. Therefore, wiring 112 and node B1 The circuit becomes non-conductive, and the wiring 112 and node B2 become non-conductive. Here, the capacitive element 403_1 has an L-level signal CK_1 (potential of wiring 211_1) and V1 (node ​​B The potential difference with (potential 1) is maintained. Then, the capacitive element 403_2 receives an L-level signal. The potential difference between CK_2 (potential of wiring 211_2) and V1 (potential of node B2) is maintained. ru.

[0245] Next, in period T4 of frame k, the potential of node A remains V1, so the transition Transistors 401_1 and 401_2 remain off. At this time, the signal CK_1 As the signal CK_2 becomes high and remains low, transistor 402_1 The circuit remains off, and transistor 402_2 turns on. Therefore, the wiring 112 and the circuit are connected. Node B1 becomes non-conductive, and wiring 112 and node B2 become conductive. Then, the electricity Pressure V1 is supplied from wiring 112 to node B2. As a result, node B1 becomes floating. Therefore, when the signal CK_1 changes from a low level to a high level, the capacitance of the capacitive element 403_1 changes. The binding causes the potential at node B1 to rise.

[0246] On the other hand, during period T4 of the k+1 frame, the signal CK_1 remains at a low level, and the signal Since CK_2 becomes high level, transistor 402_1 turns on, and transistor 4 The fact that 02_2 remains off is different from the period T4 in the k-th frame. Therefore, the wiring 112 and node B1 become conductive, and wiring 112 and node B2 become non-conductive. Then, voltage V1 is supplied from wiring 112 to node B1. As a result, node B2 It enters a floating state. Therefore, when the signal CK_2 changes from a low level to a high level, the capacitive element 40 The capacitive coupling of 3_2 causes the potential at node B2 to rise.

[0247] Next, in period T5 of frame k, the potential of node A remains V1, so the transition Transistors 401_1 and 401_2 remain off. At this time, the signal CK_1 As the signal CK_2 becomes L level, transistor 402_1 The circuit remains off, and transistor 402_2 turns off. Therefore, wiring 112 and the circuit remain off. Node B1 becomes non-conductive, and wiring 112 and node B2 become non-conductive. As a result Nodes B1 and B2 become floating. Therefore, signal CK_1 changes from high level to low level. At this level, the potential of node B1 decreases due to the capacitive coupling of the capacitive element 403_1. However, since signal CK_1 remains at a low level, the potential of node B1 remains at V1. .

[0248] On the other hand, during period T5 of the k+1 frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes L level, the potential of node B2 is due to capacitive coupling of capacitive element 403_2 The point where it decreases is different from period T5 in frame k. And the potential of node B1 is The fact that it remains V1 is different from the period T5 of the k-th frame.

[0249] As described above, the semiconductor device of this embodiment operates in the k-th frame and the k+1 frame. By repeating the operation in the first position, the time the transistor is on is shortened. This is possible. Therefore, the degradation of transistor characteristics can be suppressed. Thus, A shift register, gate driver, or display device, etc., are included in the semiconductor device of this embodiment. By doing so, their lifespan can be extended.

[0250] Alternatively, the semiconductor device of this embodiment may have all transistors configured to be N-channel or P-channel. It is possible to use a channel type. Therefore, compared to CMOS circuits, the number of manufacturing steps can be reduced. This can lead to a reduction in the number of pixels, improved yield, increased reliability, or cost reduction. If all transistors, including the parts, are N-channel type, then the semiconductor layer of the transistor and And, non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors It becomes possible to use these. However, transistors using these semiconductors degrade. It is often easy. However, the semiconductor device of this embodiment suppresses transistor degradation. It is possible.

[0251] Alternatively, to ensure that the semiconductor device operates even if the characteristics of the transistor deteriorate, There is no need to increase the channel width of the transistor. Therefore, the channel width of the transistor can be reduced. This is possible because, in the semiconductor device of this embodiment, transistor degradation is suppressed. Because it can be controlled.

[0252] Furthermore, the channel width of transistor 401_1 and the channel width of transistor 401_2 are These are preferably approximately equal. Alternatively, the channel width of transistor 402_1 and The channel width of transistor 402_2 is preferably approximately equal to the capacity. The capacitance value of the capacitance element 403_1, or the area where one electrode and the other electrode overlap, and capacitance element 4 The capacitance value of 03_2, or the area where one electrode and the other electrode overlap, is approximately equal to the capacitance value of 03_2. This is preferable because transistors 401_1 and 401_2 are similar. Transistors 402_1 and 402_2 have similar functions, This is because capacitive elements 403_1 and 403_2 have similar functions.

[0253] Note that the channel width of transistor 401_1 is different from the channel width of transistor 402_1. It is preferable that it is also large. Alternatively, the channel width of transistor 401_2 is It is preferable that it be larger than the channel width of ST402_2. However, it is not limited to this. The channel width of transistor 401_1 is smaller than the channel width of transistor 402_1. It is possible to do so. Alternatively, the channel width of transistor 401_2 is the transistor It is possible to have a channel width smaller than that of 402_2.

[0254] As shown in Figure 24(B), wiring 112 is divided into multiple wirings 112G to 112J. It is possible to divide it into lines. Transistor 401_1, Transistor 401_2, The first terminals of transistor 402_1 and transistor 402_2 are connected to wiring 112G, respectively. Wirings 112H, 112I, and 112J are connected. Wirings 112G to 112J are connected. This corresponds to wiring 112. Therefore, voltage V1 can be supplied to wiring 112G~112J. It is possible, and wiring 112G~112J can function as a power line. However Furthermore, it is not limited to this; signals can be input to wiring 112G~112J. In this case, wiring 112G~112J can function as signal lines. It is possible to supply separate signals or separate voltages to wiring 112G~112J. be.

[0255] Furthermore, as shown in Figure 24(C), transistor 401_1 and transistor 402_ The first terminal of 1 is connected to wiring 211_2, transistor 401_2, and transistor The first terminal of terminal 402_2 can be connected to wiring 211_1. If the transistor is turned off by this, then the first terminal of the transistor A clock signal is input to it. Therefore, applying a reverse bias to the transistor is possible. Therefore, the degradation of the transistor's characteristics can be suppressed. However, this is not limited to this. The first terminals of transistors 401_1 and 402_1 are connected to wiring 1. Connected to 14_2, and the first terminals of transistors 401_2 and 402_2 The child can be connected to wiring 114_1. Even in this case, the reverse bias will be a problem. Since it is applied to the transistor, it can suppress the degradation of the transistor's characteristics. Or, The first terminals of transistors 401_1 and 401_2 are connected to wiring 112. It is possible to continue.

[0256] Furthermore, as shown in Figure 25(A), transistor 402_1 and transistor 402_ The number 2 can be omitted.

[0257] Furthermore, similar to Figure 25(A), in Figures 24(B)~(C), transistor 402_ 1. Transistor 402_2 can be omitted.

[0258] Furthermore, as shown in Figure 25(B), it is possible to use MOS capacitors as the capacitive elements. Transistors 403a_1 and 403a_2 are N-channel type. In many cases, it functions as a MOS capacitance. The first terminal of transistor 403a_1 and Terminal 2 is connected to node B1, and the gate of transistor 403a_1 is connected to wiring 211. It is connected to _1. The first and second terminals of transistor 403a_2 are connected to node B Connected to 2, the gate of transistor 403a_2 is connected to wiring 211_2. By doing so, transistors 403a_1 and 403a_2 are connected. This makes it easier to create a Nell region, allowing for a larger capacity.

[0259] Furthermore, similar to Figure 25(B), the same applies to Figures 24(B)-(C) and Figure 25(A). It is possible to use MOS capacitance as the quantitative element.

[0260] Furthermore, as shown in Figure 5(B) of Embodiment 1, circuits 101 and 102 have m transistors If a transistor is present, as shown in Figure 25(C), the semiconductor device has transistor 401_1 Multiple transistors named ~401_m, and multiple transistors named 402_1~402_m It has a number of transistors and multiple capacitive elements, namely 403_1 to 403_m. This is possible. However, it is not limited to this, and transistors 402_1 to 402_m can be used. It can be omitted.

[0261] Furthermore, similar to Figure 25(C), Figures 24(B)-(C) and 25(A)-(B) show odors. However, the semiconductor device has multiple transistors called transistors 401_1 to 401_m, Multiple transistors, namely transistors 402_1 to 402_m, and capacitive element 403_ It is possible to have multiple capacitance elements ranging from 1 to 403m.

[0262] As shown in Figure 25(D), a P-channel transistor is used as the transistor. It is possible to have: Transistor 401_1p, Transistor 401_2p, Transistor Transistor 402_1p and transistor 402_2p are, respectively, transistor 401_1 , for transistors 401_2, 402_1, and 402_2 In response, it is a P-channel type. And when the polarity of the transistor is P-channel type, Figure 19 As shown in (B), voltage V2 is supplied to wiring 112, signal CK, signal CK_1, Signals CK_2, CKB_1, CKB_2, potential Va, and signal OUT are shown in Figure 8. In many cases, the chart shows a reversal compared to the timing chart in B).

[0263] Furthermore, similar to Figure 25(D), Figures 24(B) to (C), and Figures 25(A) to (C) show odors. However, it is possible to use a P-channel transistor as the transistor.

[0264] (Embodiment 5) This embodiment describes an example of a shift register. The shift register of this embodiment The stator can have semiconductor devices according to Embodiments 1 to 3. The boot register can be described as a semiconductor device or a gate driver. The contents described in Embodiments 1 to 4 will not be explained further. The contents described in Embodiment 4 can be freely combined with the contents described in this embodiment. ru.

[0265] First, an example of a shift register will be explained with reference to Figure 26. A shift register is, Multiple flip-flops called 501_1 to 501_N (where N is a natural number) It holds.

[0266] Note that the flip-flops 501_1 to 501_N correspond to Embodiments 1 to 4, respectively. This corresponds to the semiconductor device described below. An example in Figure 26 is the flip-flops 501_1~50 Let's consider the case where the semiconductor device shown in Figure 7(A) is used as 1_N. However, this is not applicable. Without limitation, other examples of flip-flops 501_1 to 501_N include Embodiment 1 to The semiconductor device or circuit described in Embodiment 4, or various other semiconductor devices or circuits It is possible to use roads.

[0267] Next, we will explain the connection of the shift register. The shift register is connected via wiring 511_1 ~511_N, Wiring 512, Wiring 512_1, Wiring 512_2, Wiring 513, Wiring 513 _1, wire 513_2, wire 514, wire 515, wire 516 are connected. And then, In the lip-flop 501_i (where i is one of 1 to N), wires 111 and 21 1. Wiring 211_1, Wiring 211_2, Wiring 114_1, Wiring 114_2, Wiring 112, Wiring 212 and wiring 213 are, respectively, wiring 511_i, wiring 512, wiring 512_1, Wiring 512_2, Wiring 513_1, Wiring 513_2, Wiring 514, Wiring 511_i-1, It is connected to wiring 511_i+1. Here, the odd-numbered flip-flops and the even-numbered flip-flops For the flop, the wiring is 211, 211_1, 211_2, 114_1, The connection destinations for wiring 114_2 are often different. For example, i (where i is one of 1 to N) stages. In the flip-flop, wire 211, wire 211_1, wire 211_2, wire 1 14_1 and wiring 114_2 are, respectively, wiring 512, wiring 512_1, and wiring 512_2 Let's assume that it is connected to wiring 513_1 and wiring 513_2. In this case, the i+1 stage flip In a flip-flop, or an i-1 stage flip-flop, use wiring 211, wiring 211_ 1. Wiring 211_2, wiring 114_1, and wiring 114_2 are, respectively, wire 513, wiring Wiring 513_1, wiring 513_2, wiring 512_1, and wiring 512_2 are connected.

[0268] Note that in the case of flip-flop 501_1, wiring 212 is connected to wiring 515. There are many. And in flip-flop 501_N, wire 213 is connected to wire 516. In many cases

[0269] Next, we will describe an example of a signal or voltage that is input to or output to each wire. Wiring 511_ From 1 to 511_N, for example, signals GOUT_1 to GOUT_N are output respectively. It shall be assumed that signals GOUT_1 to GOUT_N are, respectively, flip-flop 501_1 This is the output signal of ~501_N. And signals GOUT_1~GOUT_N are signals OU Corresponding to T, output signal, selection signal, transfer signal, start signal, reset signal, gate signal , or it can function as a scanning signal. Wiring 512, wiring 512_1, and Line 512_2, for example, has signals GCK, GCK_1, and GCK_2 respectively. The input is to be: Signal GCK corresponds to signal CK or signal CKB, and the clock signal It can function as a signal. Signal GCK_1 is signal CK_1, or signal CKB It corresponds to _1 and can function as a clock signal. Signal GCK_2 is a signal It corresponds to CK_2 or signal CKB_2 and can function as a clock signal. Wiring 513, wiring 513_1, and wiring 513_2 each have, as an example, the signal GC. Assume that KB, signal GCKB_1, and signal GCKB_2 are inputs. Signal GCKB is, It can function as an inverting clock signal, corresponding to either the CK or CKB signal. Signal GCKB_1 corresponds to signal CK_1 or signal CKB_1, and is an inverted clock signal. It can function as follows: Signal GCKB_2 is signal CK_2, or signal CKB It corresponds to _2 and can function as an inverting clock signal. Wiring 514 has For example, let's assume that voltage V1 is supplied. Wiring 515, for example, has a signal GSP The input is assumed to be the signal GSP, which corresponds to the signal SP, and is either a start signal or a vertical signal. It can function as a period signal. For example, the signal GRE is input to wiring 516. It shall be assumed that the signal GRE corresponds to the signal RE and functions as a reset signal. This is possible. However, it is not limited to this, and these wires can also receive various other signals. It is possible to input various voltages or various currents.

[0270] Note that wiring 511_1 to 511_N are signal lines, gate lines, scan lines, or output signal lines. It is possible for it to function. Wiring 512, wiring 512_1, and wiring 512_2 are It can function as a signal line or clock signal line. Wiring 513, Wiring 513_ 1. Wiring 513_2 can function as a signal line or a clock signal line. Wiring 514 can function as a power line or a ground line. Wiring 516 can function as a signal line. This is possible. However, it is not limited to this, and these wires can be connected to various other types of wires. It is possible for it to function in this way.

[0271] Note that wiring 512, wiring 512_1, wiring 512_2, wiring 513, wiring 513_1, Lines 513_2, 514, 515, and 516 receive signals from circuit 520 or It is assumed that voltage or other signals are input. Circuit 520 sends signals or voltages to the shift register. By supplying it, it has the function of controlling the shift register, control circuit, or control It can function as a rapper, etc.

[0272] For example, circuit 520 may include circuits 521 and 522. Circuit 521 generates power supply voltages such as positive power supply voltage, negative power supply voltage, ground voltage, and reference voltage. It has the function of being able to function as a power supply circuit or a regulator. Circuit 52 2 is the clock signal, inverted clock signal, start signal, reset signal, and / or, It has the function of generating various signals, such as audio signals, and functions as a timing generator. It is possible to do so. However, it is not limited to this, and circuit 520 can be used with circuit 521 and circuit 5 In addition to 22, it is possible to have various other circuits or elements. For example, circuit 52 0 is an oscillator, level shift circuit, inverter circuit, buffer circuit, DA conversion circuit, AD conversion circuit, operational amplifier, shift register, lookup table, coil, transistor It may include elements such as capacitors, capacitive elements, resistive elements, and / or frequency dividers.

[0273] Next, regarding the operation of the shift register in Figure 26, please refer to the timing chart in Figure 27. Let me explain. Figure 27 is an example of a timing chart to illustrate the operation of a shift register. Figure 27 shows signals GSP, GRE, GCK, GCK_1, and GC. K_2, signal GCKB, signal GCKB_1, signal GCKB_2, signal GOUT_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal GOUT_N An example is shown. Note that the operation of the semiconductor device in Embodiments 1 to 4 is common to the above. I will omit that explanation.

[0274] Let's explain the operation of the flip-flop 501_i. First, when the signal GOUT_i-1 is high... It reaches a certain level. Then, the flip-flop 501_i begins its operation during period T1. Then, the signal GOUT_i becomes low. Subsequently, the signals GCK and GCKB are inverted. Then, the flip-flop 501_i starts operating during period T2, and the signal GOU T_i becomes high level. The signal GOUT_i is reset to flip-flop 501_i-1. It is input as a start signal and also input as a start signal to flip-flop 501_i+1. Therefore, flip-flop 501_i-1 starts operating during period T3. Then, the flip-flop 501_i+1 begins operation during period T1. Subsequently, the signal The GCK and GCKB signals are inverted again. Then the flip-flop 501_i+1 Operation in period T2 begins, and signal GOUT_i+1 becomes high. Signal GOUT _i+1 is input to the flip-flop 501_i as a reset signal. Therefore Since the flip-flop 501_i starts operating during period T3, the signal GOUT_ i becomes low. After that, until the signal GOUT_i-1 becomes high again, it will remain frozen. The flop 501_i is activated during period T4 whenever the signals GCK and GCKB are inverted. The operation in [location] and the operation in period T5 are repeated.

[0275] Note that flip-flop 501_1 replaces the output signal of the previous flip-flop. The signal GSP is input from circuit 520 via wiring 515. Therefore, the signal GSP is When it reaches the H level, flip-flop 501_1 begins its operation for period T1.

[0276] Note that in flip-flop 501_N, instead of the output signal of the next stage flip-flop... The signal GRE is input from circuit 520 via wiring 516. Therefore, the signal GRE is When it reaches the H level, the flip-flop 501_N begins its operation during period T3.

[0277] The operation of the shift register of this embodiment has been described above. ZISTA uses the semiconductor devices of Embodiments 1 to 4, It is possible to obtain the same benefits as the device.

[0278] Furthermore, it is possible to make the relationship between signals GCK and GCKB unbalanced. For example, see Figure As shown in the timing chart of 28(A), in signals GCK and GCKB, It is possible to make the period of being at H level shorter than the period of being at L level. As a result, even if delays or distortions occur in signals GOUT_1 to GOUT_N, This prevents a period during which these signals are simultaneously at a high level. Therefore, the form of this implementation When a state shift register is used in a display device, it prevents multiple rows from being selected simultaneously. This is possible. However, it is not limited to this, and the signals GCK and / or GCKB In this scenario, the period of being at level H can be longer than the period of being at level L.

[0279] Furthermore, it is possible to input a multiphase clock signal to the shift register. For example, see Figure 2. As shown in the timing chart 8(B), an M-phase (M is a natural number) clock signal is used. It is possible to do this. In this case, in signals GOUT_1 to GOUT_N, at a certain stage The period during which the level reaches H may overlap with the periods during which the level reaches H in the preceding and following sections. Therefore, when this embodiment is used in a display device, multiple rows can be selected simultaneously. This will result in the video signal to the pixels of other rows being used as a precharge voltage. It becomes possible to use it.

[0280] In Figure 28(B), it is preferable that M ≤ 8. More preferably, M ≤ 6. It is preferable that there be a condition. More preferably, it is preferable that M ≤ 4. This is because Shift When a tracer is used in the scan line driving circuit of a display device, if M is too large, multiple pixels will be affected. This is because several types of video signals are written to the pixel. This is because the period during which data is entered becomes longer, which may lead to a decrease in display quality.

[0281] Furthermore, similar to Figure 28(B), the timing chart in Figure 28(A) also shows multiphase It is possible to use a lock signal.

[0282] Note that wiring 516 can be shared with other wiring or omitted. For example, wiring 516 is wire 512, wire 512_1, wire 512_2, wire 513, wire 513_1 It can be shared with wiring 513_2, wiring 514, or wiring 515. In addition, wiring 516 is omitted, and in flip-flop 501_N, wiring 516 is wiring 512, Wiring 512_1, Wiring 512_2, Wiring 513, Wiring 513_1, Wiring 513_ 2. It can be shared with wiring 514 or wiring 515. As another example, wiring 5 16 can be omitted. In this case, in flip-flop 501_N, Transistors 302 and 303 can be omitted.

[0283] Furthermore, it is possible to add new wiring. For example, as a flip-flop, as shown in Figure 2. If a configuration requiring voltage V2 is used, as in 3(A), additional wiring is added. It is possible to do so. And it is possible to supply voltage V2 to the wiring. However Furthermore, this is not limited to this; various new wiring can be added depending on the flip-flop configuration. It is possible to do so, and it is also possible to omit the wiring.

[0284] Furthermore, as shown in Figure 29, it is possible to split the output signal. In one example shown in Figure 29, The semiconductor device shown in Figure 17(B) is used as the flip-flops 501_1 to 501_N, respectively. It can be there. In flip-flop 501_i, wiring 111, wiring 211, wiring 211 _1, wiring 211_2, wiring 114_1, wiring 114_2, wiring 112, wiring 212, wiring Line 213 and wiring 212 are, respectively, wiring 511_i, wiring 512, wiring 512_1, and wiring Wire 512_2, Wiring 513_1, Wiring 513_2, Wiring 514, Wiring 517_i-1, Distribution Line 511_i+1 is connected to wiring 517_i. By doing this, wiring 511_ Even if a load such as a pixel or gate line is connected to 1~511_N, the next stage flip Therefore, the transfer signals used to drive the flops are not affected by any distortion or delay. This can reduce the impact of shift register delays. However, it is not limited to this, and distribution Wire 212 can be connected to wiring 511_i-1. Alternatively, wiring 213 can be connected to It can be connected to wiring 517_i+1.

[0285] (Embodiment 6) This embodiment describes an example of a display device.

[0286] First, with reference to Figure 30(A), an example of a liquid crystal display system block will be described. The liquid crystal display device consists of circuits 5361, 5362, 5363_1, and 5363_ 2. It has a pixel section 5364, a circuit 5365, and an illumination device 5366. In this configuration, multiple wires 5371 extend from circuit 5362 and are arranged, and multiple wires 5372 are arranged It is arranged as an extension from path 5363_1 and circuit 5363_2. And multiple Each of the intersection regions of line 5371 and multiple wirings 5372 contains a display element such as a liquid crystal element. The 5367 pixels are arranged in a matrix.

[0287] Circuit 5361, in response to the video signal 5360, controls circuits 5362, 5363_1, and 5 363_2 and circuit 5365 have the function of supplying signals, voltage, or current, etc. Controllers, control circuits, timing generators, power supply circuits, or regulators, etc. It is possible for it to function. In this embodiment, as an example, circuit 5361 is circuit 5 362, start signal for signal line drive circuit (SSP), clock signal for signal line drive circuit ( SCK), inverting clock signal for signal line drive circuit (SCKB), data for video signal (DA) TA) and a latch signal (LAT) shall be supplied. Alternatively, circuit 5361 is an example and Then, the start signal (G) for the scan line drive circuit is sent to circuits 5363_1 and 5363_2. SP), a clock signal for the scan line drive circuit (GCK), and an inverting clock for the scan line drive circuit. The signal (GCKB) shall be supplied. Alternatively, circuit 5361 shall supply the signal to circuit 5365. It shall supply a light control signal (BLC). However, it shall not be limited to this, circuit 5361 also handles various signals, voltages, or currents, etc., in circuit 5362, It is possible to supply power to path 5363_1, circuit 5363_2, and circuit 5365.

[0288] Circuit 5362 receives signals supplied from circuit 5361 (e.g., SSP, SCK, SCKB). It has the function of outputting video signals to multiple wires 5371 according to DATA and LAT. It can function as a signal line driving circuit. Circuit 5363_1 and Circuit 536 3_2 operates according to the signals (GSP, GCK, GCKB) supplied from circuit 5361. It has the function of outputting scan signals to multiple wires 5372 and functions as a scan line drive circuit. This is possible. Circuit 5365 responds to the signal (BLC) supplied from circuit 5361. By controlling the amount of power or the time supplied to the lighting device 5366, the lighting device It has the function of controlling the brightness (or average brightness) of 5366 and can function as a power supply circuit. It is possible.

[0289] Furthermore, if video signals are input to multiple wires 5371, the multiple wires 5371 will receive the signal. It can function as a wire, video signal wire, or source wire, etc. Multiple wires 53 When a scan signal is input to 72, multiple wires 5372 are signal lines, scan lines, or gate lines. It can function as a line or similar element, but is not limited to this.

[0290] Furthermore, the same signal is input to circuits 5363_1 and 5363_2 from circuit 5361. In this case, the scanning signal that circuit 5363_1 outputs to multiple wires 5372, and circuit 5363 The scanning signals that _2 outputs to multiple wires 5372 will be at roughly the same timing. There are many cases. Therefore, the load driven by circuits 5363_1 and 5363_2 is reduced. It can be made larger. Therefore, the display device can be made larger. Alternatively, the display device can be made larger. High resolution can be achieved. Or, circuits 5363_1 and 5363_2 have Since the channel width of the transistor can be reduced, a narrow-bezel display device can be obtained. This is possible. However, it is not limited to this, and circuit 5361 can be used with circuit 5363_1 and circuit 536 It is possible to supply separate signals to 3_2 and 3_2.

[0291] Note that either circuit 5363_1 or circuit 5363_2 can be omitted.

[0292] Furthermore, new wiring such as capacitance lines, power lines, and scanning lines can be added to the pixel section 5364. It is possible. And circuit 5361 outputs signals or voltages to these wires. This is possible. Alternatively, a new circuit similar to circuit 5363_1 or circuit 5363_2 can be added. In addition, this newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0293] Furthermore, pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in Figure 30(B), the display element can emit light, so circuit 5 365 and the lighting device 5366 can be omitted. And power to the display element To supply power, multiple wires 5373 capable of functioning as power lines are provided in the pixel section 53 It can be arranged in 64. Circuit 5361 distributes a power supply voltage called voltage (ANO). It is possible to supply power to line 5373. This wiring 5373 is connected according to the color element of the pixel. It is possible to connect to all pixels, and it is also possible to connect to all pixels in common.

[0294] Note that in Figure 30(B), as an example, circuit 5361 is connected to circuit 5363_1 and circuit 536 An example of supplying separate signals to 3_2 is shown. Circuit 5361 is for the scan line drive circuit. Start signal (GSP1), clock signal for scan line drive circuit (GCK1), and scan line drive Signals such as the inverting clock signal for the dynamic circuit (GCKB1) are supplied to circuit 5363_1. Circuit 5361 then provides a start signal (GSP2) for the scan line drive circuit, and for the scan line drive circuit Clock signal (GCK2), and inverting clock signal for scan line drive circuit (GCKB2), etc. The signal is supplied to circuit 5363_2. In this case, circuit 5363_1 has multiple wires 53 Scanning only the odd-numbered rows of wiring 72, circuit 5363_2 is a multiple wiring 5372 This makes it possible to scan only the wiring in even-numbered rows. Therefore, circuit 5363_1, and Since the driving frequency of track 5363_2 can be reduced, power consumption can be reduced. Alternatively, increase the area available for laying out one stage of flip-flops. This is possible. Therefore, the display device can be made high-resolution. Alternatively, the display device can be made larger. This is possible. However, it is not limited to this, and, similar to Figure 30(A), circuit 5361 is, It is possible to output the same signal to both circuit 5363_1 and circuit 5363_2.

[0295] Note that, similar to Figure 30(B), in Figure 30(A), circuit 5361 is also circuit 5363 It is possible to supply separate signals to _1 and circuit 5363_2.

[0296] The above describes an example of a system block for a display device.

[0297] Next, an example of the configuration of the display device is shown in Figures 31(A), (B), (C), (D), and ( See E) for further explanation.

[0298] Figure 31(A) shows a circuit that has the function of outputting a signal to the pixel unit 5364 (for example, circuit 5 Circuits 362, 5363_1, and 5363_2, etc., are on the same substrate as the pixel unit 5364. It is formed at 5380. The circuit 5361 is formed on a separate substrate from the pixel section 5364. This reduces the number of external parts, thus lowering costs. Alternatively, Since the number of signals or voltages input to board 5380 decreases, the relationship between board 5380 and external components The number of connections can be reduced. Therefore, it is possible to improve reliability or yield. can.

[0299] Furthermore, if the circuit is formed on a substrate separate from the pixel section 5364, the substrate is TAB(Ta FPC (Flexible Printed Circuit) is a method of Automated Bonding. It can be mounted on a Printed Circuit. Alternatively, the board can be , COG (Chip on Glass) method, the same substrate 538 as the pixel unit 5364 It is possible to implement this in 0.

[0300] Furthermore, if the circuit is formed on a substrate separate from the pixel section 5364, the substrate may contain a single-crystal semiconductor. It is possible to form a transistor using the substrate. Therefore, the substrate is formed The circuit offers advantages such as improved drive frequency, improved drive voltage, and reduced output signal variation. You can obtain [something].

[0301] Furthermore, signals, voltages, or currents are input from external circuits via input terminal 5381. In many cases, this is the case.

[0302] In Figure 31(B), circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) is formed on the same substrate 5380 as the pixel section 5364. And the circuit 5361, Circuit 5362 is formed on a separate substrate from the pixel section 5364. This way, the mobility is small. The transistors make it possible to construct the circuit formed on the substrate 5380. So, as semiconductor layers in transistors, there are non-single-crystal semiconductors, amorphous semiconductors, and microcrystalline semiconductors. It becomes possible to use organic semiconductors or oxide semiconductors. Therefore, the display device This allows for larger size, reduction of the number of processes, cost reduction, and improvement of yield.

[0303] Furthermore, as shown in Figure 31(C), a part of circuit 5362 (circuit 5362a) is the pixel section 53 It is formed on the same substrate 5380 as 64, and the remaining circuit 5362 (circuit 5362b) is the pixel section 5 It is possible to form it on a different substrate than 364. Circuit 5362a has low mobility Circuits that can be constructed using transistors (e.g., shift registers, selectors, etc.) It often has switches, etc. And circuit 5362b has high mobility and characteristic variation A circuit that is preferably constructed using transistors with low shift resistance (for example, a shift resistance transistor) They often have latch circuits, buffer circuits, DA conversion circuits, AD conversion circuits, etc. By doing so, as in Figure 31(B), the semiconductor layer of the transistor is non-single Using crystalline semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors, etc. This makes it possible to further reduce the number of external parts.

[0304] Figure 31(D) shows a circuit that has the function of outputting a signal to the pixel unit 5364 (for example, circuit 5 Circuits 362, 5363_1, and 5363_2, etc., and the control of these circuits The functional circuit (for example, circuit 5361) is formed on a separate substrate from the pixel section 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. This can lead to an improvement in yield.

[0305] Furthermore, similar to Figure 31(D), in Figures 31(A) to (C), circuit 5363_1, and The circuit 5363_2 can be formed on a separate substrate from the pixel section 5364.

[0306] In Figure 31(E), a portion of circuit 5361 (circuit 5361a) is on the same substrate as the pixel unit 5364. 5380 is formed, and the remaining circuit 5361 (circuit 5361b) is separate from the pixel section 5364. It is formed on the substrate. Circuit 5361a is composed of transistors with low mobility. If the circuit has the capability to do so (for example, a switch, selector, level shift circuit, etc.) There are many. And circuit 5361b uses transistors with high mobility and low variability. A circuit that is preferably configured in this way (for example, a shift register, a timing generator, etc.) They often have a syrator, regulator, or analog buffer.

[0307] In addition, in Figures 31(A) to (D), the circuit 5361a is on the same substrate as the pixel unit 5364. It is possible to form the circuit 5361b on a separate substrate from the pixel section 5364.

[0308] Here, circuits 5363_1 and 5363_2 are referred to as Embodiments 1 to 5. It is possible to use the semiconductor device or shift register. In this case, circuit 5363_ 1. The circuit 5363_2 and the pixel section are formed on the same substrate, It is possible to set the polarity of all transistors formed to either N-channel or P-channel type. Therefore, it is possible to reduce the number of processes, improve yield, improve reliability, or reduce costs. This can be achieved. In particular, when the polarity of all transistors is N-channel type, Non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, and organic semiconductors are used as semiconductor layers in transistors. It becomes possible to use conductors or oxide semiconductors. Therefore, the size of the display device can be increased. This can lead to a reduction in strikes or an improvement in yield.

[0309] Alternatively, the semiconductor device or shift register of Embodiments 1 to 5 is a transistor The channel width can be reduced. Therefore, the layout area can be reduced. Therefore, the picture frame can be made smaller. Alternatively, the layout area can be reduced. This allows for higher resolution.

[0310] Alternatively, the semiconductor device or shift register of Embodiments 1 to 5 has parasitic capacitance. It can be made smaller. Therefore, power consumption can be reduced. Or, external circuit The current capacity can be reduced. Alternatively, the size of the external circuit, or the external circuit The size of the display device can be reduced.

[0311] Furthermore, non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors Transistors that use semiconductor layers exhibit characteristics such as increased threshold voltage or decreased mobility. Degradation often occurs. However, semiconductor devices or shifters of Embodiments 1 to 5 The transistor resistor can suppress the degradation of transistor characteristics, thus extending the lifespan of the display device. It can be made longer.

[0312] Furthermore, as part of circuit 5362, the semiconductor device of Embodiments 1 to 5, or the Shift A tracer can be used. For example, circuit 5362a is implemented in Embodiment 1. It is possible to have a semiconductor device of form 4, or a shift register.

[0313] (Embodiment 7) In this embodiment, an example of a signal line driving circuit will be described. Note that the signal line driving circuit will be half It can be described as a conductor device or a signal generating circuit.

[0314] An example of a signal line driving circuit will be explained with reference to Figure 32(A). The signal line driving circuit is: Multiple circuits named Circuit 602_1 to 602_N (where N is a natural number), Circuit 600, and Circuit 6 It has 01. And circuits 602_1 to 602_N each have transistor 603_ It has multiple transistors numbered 1 to 603_k (where k is a natural number). Transistor 603 _1~603_k are assumed to be N-channel type, but are not limited to this. For example, transistors 603_1 to 603_k can be made into P-channel types. Therefore, it is possible to use a CMOS type switch.

[0315] The connection relationships of the signal line drive circuit will be explained using circuit 602_1 as an example. Transistor The first terminals of 603_1 to 603_k are connected to wiring 605_1. Transistor 6 The second terminals of 03_1~603_k are connected to wiring S1~Sk, respectively. Transis The gates of terminals 603_1 to 603_k are connected to wirings 604_1 to 604_k, respectively. For example, the first terminal of transistor 603_1 is connected to wiring 605_1, and The second terminal of transistor 603_1 is connected to wiring S1, and the gateway of transistor 603_1 This is connected to wiring 604_1.

[0316] Circuit 600 transmits signals to circuits 602_1~602_ via wiring 604_1~604_k. It has the function of supplying N and can function as a shift register or decoder, etc. This signal is often a digital signal and can function as a selection signal. It is possible. And wiring 604_1~604_k can function as signal lines. be.

[0317] Circuit 601 has the function of outputting signals to circuits 602_1 to 602_N, and the video signal is generated It can function as a circuit, etc. For example, circuit 601 has wiring 605_1 The signal is supplied to circuit 602_1 via wiring 605_2. At the same time, the signal is supplied to circuit 6 It is supplied to 02_2. This signal is often an analog signal and is used as a video signal. It is possible to do so. And wiring 605_1~605_N functions as a signal line. It is possible to do so.

[0318] Circuits 602_1 to 602_N select which wire to output the output signal of circuit 601 to. It has a selection function and can function as a selector circuit. For example, circuit 602 _1 specifies which of the wirings S1 to Sk outputs the signal that circuit 601 outputs to wiring 605_1. It has a function to select whether to output to a specific location.

[0319] Transistors 603_1 to 603_k are connected to wiring 6, respectively, according to the output signal of circuit 600. It has the function of controlling the conductivity state between 05_1 and wiring S1~Sk, and functions as a switch. ru.

[0320] Next, regarding the operation of the signal line drive circuit in Figure 32(A), see the timing chart in Figure 32(B). Refer to Figure 32(B) for explanation. The signal 614_1 input to wiring 604_1 is shown in Figure 32(B). , Signal 614_2 input to wiring 604_2, Signal 614 input to wiring 604_k _k, signal 615_1 input to wiring 605_1, and signal input to wiring 605_2 An example of item 615_2 is shown.

[0321] Furthermore, one operating period of the signal line drive circuit corresponds to one gate selection period in the display device. The gate selection period is when a pixel belonging to a certain row is selected and a video signal is written to that pixel. This refers to the period during which it is possible to do something.

[0322] The gate selection period is divided into periods T0, T1, and so on, up to Tk. This is the period for simultaneously applying a pre-charge voltage to the pixels belonging to the selected row. It can function as a pre-charge period. Periods T1 to Tk can each be selected. This is the period for writing a video signal to the pixels belonging to the row, and is defined as the writing period. It is possible to do so.

[0323] For convenience, the operation of the signal line drive circuit will be explained using the operation of circuit 602_1 as an example.

[0324] First, during period T0, circuit 600 sends an H-level signal to wiring 604_1~604_k. This outputs the following: Transistors 603_1~603_k turn on, so wire 605 _1 and wiring S1~Sk become conductive. At this time, circuit 601 is connected to wiring 605_1 Since a precharge voltage Vp is supplied to it, the precharge voltage Vp is, Outputs are sent to wiring S1 to Sk via 03_1 to 603_k. Then, the preset The charge voltage Vp is written to the pixels belonging to the selected row, so the pixels belonging to the selected row The pixels are pre-charged.

[0325] Next, during period T1, circuit 600 outputs a high-level signal to wiring 604_1. Then, transistor 603_1 turns on, and wiring 605_1 and wiring S1 become electrically connected. This state occurs. Then, wiring 605_1 and wiring S2~Sk become non-conductive. At this time, If circuit 601 outputs signal Data(S1) to wiring 605_1, then signal D ata(S1) is output to wiring S1 via transistor 603_1. The signal Data(S1) is the pixel belonging to the selected row among the pixels connected to wiring S1. It will be written directly.

[0326] Next, during period T2, circuit 600 outputs a high-level signal to wiring 604_2. Then, transistor 603_2 turns on, and wiring 605_2 and wiring S2 become conductive. This is the state in which the wiring 605_1 and wiring S1 become non-conductive, and the wiring 605_1 and Wiring S3 to Sk remains in a non-conductive state. At this time, circuit 601 receives the signal Data( If S2) is output to wiring 605_1, then the signal Data(S2) is a transistor The signal Data(S1) is output to wiring S2 via TA603_2. The pixels connected to line S1 that belong to the selected row are written to.

[0327] Subsequently, until period Tk, circuit 600 sends a high-level signal to wiring 604_1~604_k. Since the output is generated sequentially, the same applies to periods T1 and T2, and also to periods T3 through Tk, as shown in circuit 6. 00 outputs high-level signals sequentially to wiring 604_3~604_k. Therefore, the transistor Since transistors 603_3 to 603_k are turned on in order, transistors 603_1 to 603_ k is turned on in order. Therefore, the signals output from circuit 601 are in order of wiring S1 to Sk. The output is displayed. In this way, it is possible to sequentially write the signal to the pixels belonging to the selected row. It will become.

[0328] The above describes an example of a signal line drive circuit. The signal line drive circuit of this embodiment is a selector Because it has a circuit that functions as a connector, the number of signals or wires can be reduced. Alternatively, a voltage for pre-charging before writing the video signal to the pixel (period T0) Since it is written to the pixels, the video signal writing time can be shortened. Therefore This allows for larger and higher-resolution display devices. However, it is not limited to this. Furthermore, it is possible to omit the period T0 and not precharge the pixels.

[0329] Furthermore, if k is too large, the writing time to the pixels will be shortened, so the video signal to the pixels The writing process may not complete within the allotted time. Therefore, it is preferable that k ≤ 6. It is more preferable that k ≤ 3. Even more preferable that k = 2. It's nice.

[0330] In particular, when the color elements of a pixel are divided into n (where n is a natural number) parts, it is possible to set k=n. Yes, for example, when the color elements of a pixel are divided into three parts: red (R), green (G), and blue (B). It is possible that k=3. In this case, the 1-gate selection period is period T0, period T1 It is then divided into period T2 and period T3. And in period T1, period T2, and period T3, It is possible to write video signals to the red (R) pixels, green (G) pixels, and blue (B) pixels. However, this is not the only option, and the order of periods T1, T2, and T3 can be set arbitrarily. It is possible to do so.

[0331] In particular, a pixel has n (where n is a natural number) subpixels (hereinafter also called subpixels or secondary pixels). When a pixel is divided into subpixels, it is possible to set k=n. For example, if a pixel is divided into two subpixels If divided, k=2 is possible. In this case, the 1-gate selection period is period T. It is divided into periods 0, T1, and T2. Then, in period T1, one of the two subpixels The video signal is written, and during period T2, the video signal is written to the other of the two subpixels. This is possible.

[0332] Note that the drive frequencies of circuits 600 and 602_1~602_N are often low. Circuits 600 and 602_1 to 602_N are formed on the same substrate as the pixel section. It is possible. In this way, the number of connections between the substrate on which the pixel is formed and the external circuit can be reduced. This allows for improvements in yield or reliability. Furthermore, see Figure 3. As shown in 1(C), the scan line driving circuit is also formed on the same substrate as the pixel section, further This reduces the number of connections to external circuits.

[0333] The circuit 600 is a semiconductor device or shift register of Embodiments 1 to 4. It is possible to use this. In this case, the polarity of all transistors in circuit 600 is It can be an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. This can lead to improved yield or reduced costs.

[0334] Furthermore, this applies not only to circuit 600, but also to all transistors in circuits 602_1 to 602_N. The polarity can also be N-channel or P-channel. Therefore, circuit 6 When circuits 00 and 602_1 to 602_N are formed on the same substrate as the pixel section, the number of steps This can lead to reductions in transients, improved yield, or cost reductions. In particular, all transients By making the polarity of the transistor an N-channel type, the semiconductor layer of the transistor is non-single-connected. By using crystalline semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors, etc. This is possible because the drive frequencies of circuits 600 and 602_1~602_N are Because it is often low.

[0335] (Embodiment 8) In this embodiment, the pixel configuration and pixel operation applicable to the liquid crystal display device are described below. explain.

[0336] Figure 33(A) shows an example of a pixel. Pixel 3020 is composed of a transistor 3021 and a liquid crystal element. It has 3022 and a capacitive element 3023. And the first terminal of transistor 3021 It is connected to wiring 3031, and the second terminal of transistor 3021 is connected to liquid crystal element 3022 One electrode of the transistor 3021 is connected to one electrode of the capacitor element 3023, and the transistor 3021 is connected to one electrode of the capacitor element 3023. The wire is connected to wiring 3032. The other electrode of liquid crystal element 3022 is connected to electrode 3034. The other electrode of the capacitive element 3023 is connected to the wiring 3033.

[0337] For example, a video signal can be input to wiring 3031. For example, a scan signal, selection signal, or gate signal can be input to 2. For example, a constant voltage can be supplied to wiring 3033. Electrode 3 For example, a constant voltage can be supplied to 034. However, this is not limited to this. The video signal is not specified, and a precharge voltage is supplied to wiring 3031. The writing time can be shortened. Alternatively, a signal is input to wiring 3033. This makes it possible to control the voltage applied to the liquid crystal element 3022. By inputting a signal to electrode 3034, frame inversion drive can be achieved. It is Noh.

[0338] Wiring 3031 can function as a signal line, video signal line, or source line. Wiring 3032 can function as a signal line, scan line, or gate line. The wiring 3033 can function as a power line or a capacitance line. Electrode 303 4 can function as a common electrode or a counter electrode. However, it is not limited to this. However, if voltage is supplied to wiring 3031 and wiring 3032, these wirings are power lines. It can function as follows: Alternatively, if a signal is input to wiring 3033, wiring 3033 can function as a signal line.

[0339] Transistor 3021 determines the conductivity between wiring 3031 and one electrode of liquid crystal element 3022. By controlling it, it has the function of controlling the timing of writing the video signal to the pixel. It can function as a switch. Capacitive element 3023 is one of the liquid crystal elements 3022. Maintaining the potential difference between the electrode and the wiring 3033, the voltage applied to the liquid crystal element 3022 It has the function of maintaining a constant value and functions as a holding capacity. However, it is not limited to this.

[0340] Figure 33(B) shows a timing chart to explain the operation of the pixels in Figure 33(A). An example is shown. Figure 33(B) shows the signal 3042_j (where j is a natural number) and the signal 3042_j+1 This shows signal 3041_i (where i is a natural number), signal 3041_i+1, and voltage 3042. Figure 33(B) shows the k-th (where k is a natural number) frame and the k+1 frame. Note that signals 3042_j, ​​3042_j+1, 3041_i, and 3041_i +1 and voltage 3042 are signals input to wiring 3032 in row j, respectively, row j+1 The signal input to wiring 3032, the signal input to wiring 3031 in the i-th column, i+1th column This is an example of the signal input to wiring 3031 and the voltage supplied to wiring 3032.

[0341] The operation of pixel 3020, located at row j and column i, is described below. The signal 3042_j is at the H level. When this happens, transistor 3021 turns on. Therefore, the i-th row wiring 3031 and the liquid crystal element Since one electrode of 3022 becomes conductive, the signal 3041_j is transmitted to transistor 302 It is input to one electrode of the liquid crystal element 3022 via 1. Then, the capacitive element 3023, At this time, maintain the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. Therefore, until the signal 3042_j reaches a high level again, the liquid crystal element 302 The voltage applied to 2 remains constant. Then, the liquid crystal element 3022 responds to the applied voltage. It expresses gradations of tone.

[0342] In Figure 33(B), positive and negative polarity signals are alternately distributed for each row selection period. An example of what happens when input to line 3031 is shown. A positive polarity signal is one in which the potential is equal to the reference value (for example). A signal higher than the potential of electrode 3034 is a negative polarity signal, where the potential is higher than the reference value. This refers to a signal lower than (for example, the potential of electrode 3034). However, it is not limited to this. The signal input to wiring 3031 can have the same polarity for the duration of one frame. ru.

[0343] Note that Figure 33(B) shows the polarity of signal 3041_i and the polarity of signal 3041_i+1. An example of a case where they are different is shown. However, it is not limited to this, and the polarity of signal 3041_i and The polarity of signal 3041_i+1 can be the same.

[0344] Figure 33(B) shows the period during which signal 3042_j is at the H level, and the signal 3042_j This example shows a case where the period when +1 is at the H level does not overlap. However, this is not the only example. Furthermore, as shown in Figure 33(C), the period during which signal 3042_j is at an H level, and signal 30 The period during which 42_j+1 is at an H level can overlap. In this case, wiring 303 It is preferable that the same polarity signal is supplied to 1 for the duration of one frame. The signal 3041_j, which is written to the j-th row pixel, is used to write the j+1-th row pixel. It can be pre-charged. This shortens the time it takes to write the video signal to the pixels. This is possible. Therefore, the display device can be made high-resolution. Or, the display device's display The display area can be enlarged. Alternatively, the same wiring 3031 can be used for one frame period. Since a polarity signal is input, power consumption can be reduced.

[0345] Furthermore, the pixel configuration in Figure 34(A) and the timing chart in Figure 33(C) are combined. This enables dot inversion driving. In the pixel configuration shown in Figure 34(A), Pixel 3020(i, j) is connected to wiring 3031_i. On the other hand, pixel 3020(i, j+1) is connected to wiring 3031_i+1. In other words, the pixels belonging to the i-th column are in row 1. The wires are connected alternately, one at a time, to wire 3031_i and the other to wire 3031_i+1. In this way, the i-th row The pixels belonging to the eye are written with alternating positive and negative polarity signals, one row at a time. This enables dot inversion driving. However, it is not limited to this, and also applies to the i-th column. The pixels are arranged alternately in multiple rows (for example, 2 or 3 rows), with wiring 3031_i and wiring 3031 It is possible to connect it to _i+1.

[0346] Furthermore, a subpixel structure can be used as the pixel configuration. Figure 34(B) Figure 34( Figure B) shows a subpixel structure called 1S+2G, and Figure 34(C) shows 2S+1 It shows a subpixel structure called G. Subpixels 3020A and 3020B are It corresponds to pixel 3020. Transistors 3021A and 3021B are transistors Compatible with the 3021. Liquid crystal elements 3022A and 3022B are liquid crystal elements Corresponds to 3022. Capacitive elements 3023A and 3023B are the same as capacitive element 3023 Corresponds to. Wiring 3031A and Wiring 3031B correspond to Wiring 3031. Wiring 30 Wiring 32A and 3032B correspond to wiring 3032.

[0347] Here, the pixels of this embodiment, the semiconductor devices of Embodiments 1 to 7, and the shift register By combining it with a station, display device, or signal line drive circuit, various advantages can be obtained. It can be obtained. For example, when using a subpixel structure as pixels, the display device can be driven The number of signals required to operate increases. Therefore, the number of gate lines or source lines The number increases. As a result, the number of connections between the substrate on which the pixel is formed and the external circuitry increases significantly. The number may increase. However, even if the number of gate lines increases, as shown in Embodiment 6 Therefore, the scanning line driving circuit can be formed on the same substrate as the pixel section. Without significantly increasing the number of connections between the substrate on which the subpixel structure is formed and the external circuit, the subpixel structure Pixels can be used. Alternatively, even if the number of source lines increases, the signal line drive of Embodiment 6 can be used. By using a dynamic circuit, the number of source lines can be reduced. Therefore, the pixel section Without significantly increasing the number of connections between the substrate on which the subpixel structure is formed and the external circuit, the subpixel structure Pixels can be used.

[0348] Alternatively, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel is formed and the external circuit In some cases, the capacitance can increase significantly. Therefore, the capacitance line is half of the capacitance lines of Embodiments 1 to 5. It is possible to supply signals using a conductor device or a shift register. The semiconductor device or shift register of Embodiments 1 to 5 is formed on the same substrate as the pixel portion. Therefore, it is possible to significantly reduce the number of connections between the substrate on which the pixel portion is formed and the external circuit. The signal can be input to the capacitance line without increasing the capacitance.

[0349] Alternatively, if AC drive is used, the time required to write the video signal to the pixels becomes shorter. As a result, there may be insufficient time to write the video signal to the pixels. Similarly, when using pixels with a subpixel structure, the time required to write the video signal to the pixels is short. This can result in insufficient time to write the video signal to the pixels. Therefore, using the signal line driving circuit of Embodiment 7, it is possible to write a video signal to the pixels. It is possible. In this case, before writing the video signal to the pixel, a pre-charge voltage is applied to the pixel. Because it writes the signal, the video signal can be written to the pixels in a short amount of time. Or, see Figure 28. As shown in (B), the period during which one row is selected and the period during which another row is selected overlap. This makes it possible to use the video signal from another line as the voltage for precharging. .

[0350] (Embodiment 9) In this embodiment, an example of the cross-sectional structure of the display device is shown in Figures 35(A), (B), and ( Refer to C) for further explanation.

[0351] Figure 35(A) is an example of a top view of a display device. A drive circuit 5392 and A pixel section 5393 is formed. An example of a drive circuit 5392 is a scan line drive circuit , or signal line drive circuits, etc.

[0352] Figure 35(B) shows an example of the AB section of Figure 35(A). And in Figure 35(B) , a substrate 5400, a conductive layer 5401 formed on the substrate 5400, and the conductive layer 5401 An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. A semiconductor layer 5403a is formed, and a semiconductor layer 5403b is formed on top of the semiconductor layer 5403a. Furthermore, a conductive layer 5404 is formed on the semiconductor layer 5403b and the insulating layer 5402, and An insulating layer 5405 having an opening is formed on the edge layer 5402 and the conductive layer 5404. , a conductive layer 5406 formed on the insulating layer 5405 and in the openings of the insulating layer 5405, and insulation An insulating layer 5408 is placed on top of layer 5405 and on top of the conductive layer 5406, and insulating layer 5405 A liquid crystal layer 5407 formed on top of the liquid crystal layer 5407 and an insulating layer 5405 formed on top of the liquid crystal layer 5407 The conductive layer 5409 and the substrate 5410 formed on the conductive layer 5409 are shown.

[0353] The conductive layer 5401 can function as a gate electrode. The insulating layer 5402 is a gate electrode. It can function as a conductive insulating film. The conductive layer 5404 is used for wiring and transistors. It can function as an electrode, or an electrode of a capacitive element. The insulating layer 5405 is a layer It can function as an interlayer or planarization layer. The conductive layer 5406 is used for wiring, pixel electricity It can function as a pole or a reflector electrode. The insulating layer 5408 is a sealing material. It is possible for it to function. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0354] In this case, parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409. As a result, the output signal of the drive circuit 5392 or the potential of each node may have a smudge or delay. This can happen. Or, power consumption will increase. However, as shown in Figure 35(B)... Furthermore, an insulating layer 5408 capable of functioning as a sealant is placed on top of the drive circuit 5392. By forming this, the parasitic capacitance that occurs between the drive circuit 5392 and the conductive layer 5409 is eliminated. This can be reduced because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. This is because there are many of them. Therefore, the output signal of the drive circuit 5392 or the raw potential of each node This can reduce the delay or power consumption of the drive circuit 5392. It is possible.

[0355] Furthermore, as shown in Figure 35(C), a portion of the drive circuit 5392 is placed on top of it, functioning as a sealing material. It is possible to form an insulating layer 5408 that allows for this. This makes it possible to reduce the parasitic capacitance that occurs between the drive circuit 5392 and the conductive layer 5409. Therefore, the output signal of the drive circuit 5392 or the potential of each node can be reduced. Yes, it is possible. However, it is not limited to this, and on the drive circuit 5392, a material that functions as a sealant can be used. It is possible that an insulating layer 5408 is not formed.

[0356] Furthermore, the display element is not limited to liquid crystal elements, but can include various other elements such as EL elements or electrophoretic elements. It is possible to use indicative elements.

[0357] In this embodiment, an example of the cross-sectional structure of the display device has been described. This involves combining the semiconductor device or shift register of Embodiments 1 to 5. This is possible. For example, non-single-crystal semiconductors and amorphous semiconductors can be used as semiconductor layers in transistors. When using microcrystalline semiconductors, organic semiconductors, or oxide semiconductors, the transistor's chat The panel width is often large. However, as in this embodiment, the parasitic capacitance of the drive circuit is If it can be made smaller, the channel width of the transistor can be reduced. Therefore, Layer Since the footprint can be reduced, the display device can have a narrow bezel. This allows for high-definition display devices.

[0358] (Embodiment 10) In this embodiment, an example of the transistor structure is shown in Figures 36(A), (B), and (C). (See the references below for further explanation.)

[0359] Figure 36(A) shows an example of the configuration of a top-gate type transistor. Figure 36(B) shows... This is an example of the configuration of a bottom-gate type transistor. Figure 36(C) shows a semiconductor substrate. This is an example of the structure of a transistor that is manufactured using this method.

[0360] Figure 36(A) shows a substrate 5260 and an insulating layer 5261 formed on the substrate 5260, Formed on the insulating layer 5261, region 5262a, region 5262b, region 5262c, A semiconductor layer 5262 having regions 5262d and 5262e, and a covering for the semiconductor layer 5262 An insulating layer 5263 is formed in such a manner, and a semiconductor layer 5262 and an insulating layer 5263 are formed on top of the insulating layer 5263. A conductive layer 5264 and an insulating layer 5263 and a conductive layer 5264 are formed on top of the conductive layer 5264 and have openings. An insulating layer 5265 and conductive material formed on the insulating layer 5265 and in the openings of the insulating layer 5265. A layer 5266 and a conductive layer 5266 and an insulating layer 5265 formed on top of the conductive layer 5266 and having an opening An insulating layer 5267 and a conductive layer formed on the insulating layer 5267 and in the openings of the insulating layer 5267. 5268 and an insulating layer 5267 and a conductive layer 5268 formed on top of the conductive layer 5268, having an opening Edge layer 5269 and light-emitting layer 5 formed on top of the insulating layer 5269 and in the opening of the insulating layer 5269 270 and the conductive layer 5271 formed on the insulating layer 5269 and the light-emitting layer 5270 show.

[0361] Figure 36(B) shows a substrate 5300 and a conductive layer 5301 formed on the substrate 5300. An insulating layer 5302 is formed to cover the conductive layer 5301, and the conductive layer 5301 and the insulating layer 5 A semiconductor layer 5303a formed on 302, and a semiconductor layer formed on semiconductor layer 5303a Conductive layer 5303b and conductive layer formed on semiconductor layer 5303b and insulating layer 5302 A layer 5304 is formed on the insulating layer 5302 and on the conductive layer 5304, and has an opening. An insulating layer 5305 and a conductive layer formed on the insulating layer 5305 and in the openings of the insulating layer 5305. 5306 and the liquid crystal layer 5307 which is placed on the insulating layer 5305 and on the conductive layer 5306 This shows a conductive layer 5308 formed on top of the liquid crystal layer 5307.

[0362] Figure 36(C) shows a semiconductor substrate 5352 having regions 5353 and 5355, and a semiconductor An insulating layer 5356 formed on the substrate 5352, and a semiconductor substrate 5352 formed on the semiconductor substrate 5352 An insulating layer 5354, a conductive layer 5357 formed on the insulating layer 5356, and an insulating layer 535 4. An insulating layer 535 having an opening, formed on the insulating layer 5356 and the conductive layer 5357. 8 and the conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358 This is shown. In this way, transistors are fabricated in region 5350 and region 5351, respectively.

[0363] The insulating layer 5261 can function as an undercoat. The insulating layer 5354 is between elements. It functions as a separation layer (e.g., a field oxide film). Insulating layer 5263, insulating layer 5302, The insulating layer 5356 can function as a gate insulating film. The conductive layer 5264, The electrode layer 5301 and the conductive layer 5357 can function as gate electrodes. Insulating layer 5265, insulating layer 5267, insulating layer 5305, and insulating layer 5358 are interlayer films or flat It can function as a film. Conductive layer 5266, conductive layer 5304, and conductive layer 5 359 can function as wiring, a transistor electrode, or a capacitive element electrode, etc. It is possible. The conductive layer 5268 and the conductive layer 5306 are used as pixel electrodes or reflective electrodes, etc. It is possible for it to function. The insulating layer 5269 can function as a dam. The conductive layer 5271 and the conductive layer 5308 function as counter electrodes or common electrodes, etc. This is possible.

[0364] Examples of substrates 5260 and 5300 include glass substrates, quartz substrates, and silicon substrates. (or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel substrate, ste Substrates having stainless steel foil, tungsten substrates, and tungsten foil Examples include rigid substrates or flexible substrates. An example of a glass substrate is barium borosilicate glass. Examples include glass and aluminoborosilicate glass. An example of a flexible substrate is polyethylene. Reflatate (PET), polyethylene naphthalate (PEN), polyethersulfate Plastics such as PES, or flexible synthetic resins such as acrylic, etc. There are also laminated films (polypropylene, polyester, vinyl, polyf Paper containing fibrous materials (such as polyvinyl chloride, polyvinyl chloride, etc.), base film (polyester, Examples include polyamides, polyimides, inorganic vapor-deposited films, and paper products.

[0365] As an example of the semiconductor substrate 5352, a single crystal Si group having n-type or p-type conductivity A board can be used. However, it is not limited to this, and a board similar to the circuit board 5260 can be used. It can be used. Region 5353 is, for example, a semiconductor substrate 5352 with impurities. This is an added region that functions as a well. For example, if the semiconductor substrate 5352 is p-type If it has an electrical type, region 5353 has an n-type conductivity and functions as an n-well. On the other hand, if the semiconductor substrate 5352 has an n-type conductivity, then region 5353 has a p-type conductivity. It has and functions as a p-well. Region 5355 is, for example, a semiconductor substrate 5 This is a region added to 352 and functions as either a source region or a drain region. It is possible to form an LDD region on the conductive substrate 5352.

[0366] Examples of insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxide. Acids such as silicon dioxide (SiOxNy) (x>y) and silicon nitride (SiNxOy) (x>y) This includes films containing elemental or nitrogen, or laminated structures thereof. The insulating layer 5261 has a two-layer structure. One example of a structure that can be provided is a silicon nitride film as the first insulating layer, and the second layer A silicon oxide film can be provided as an insulating film. The insulating layer 5261 is provided in a three-layer structure. One example of this is when a silicon oxide film is provided as the first insulating layer, and the second insulating layer is It is possible to provide a silicon nitride film and a silicon oxide film as a third insulating layer.

[0367] Examples of semiconductor layers 5262, 5303a, and 5303b include non-single Crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) , single crystal semiconductors, compound semiconductors or oxide semiconductors (ZnO, InGaZnO, SiG e, GaAs, IZO, ITO, SnO, TiO, AlZnSnO(AZTO)), organic Examples include semiconductors and carbon nanotubes.

[0368] For example, region 5262a is an intrinsic region where no impurities are added to the semiconductor layer 5262. This state functions as a channel region. However, if a trace amount of impurity is added to region 5262a... It is possible to add impurities to region 5262a, region 5262b, region Lower than the concentration of impurities added to region 5262c, region 5262d, or region 5262e This is preferable. Regions 5262b and 5262d are areas to which impurities are added at low concentrations. This is a domain, and as an LDD (Lightly Doped Drain) domain, it is a machine It is possible. However, areas 5262b and 5262d can be omitted. Regions 5262c and 5262e are areas where impurities are added to the semiconductor layer 5262 at high concentrations. It is a region that functions as either a source region or a drain region.

[0369] Furthermore, semiconductor layer 5303b is a semiconductor layer to which phosphorus and other impurity elements are added. It has an n-type conductivity.

[0370] Furthermore, when an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0371] Examples of insulating layers 5263, 5302, and 5356 include silicon dioxide (Si Silicon nitride (Ox), silicon nitride (SiNx), silicon oxide nitride (SiOxNy) (x>y), silicon nitride oxide A film containing oxygen or nitrogen, such as (SiNxOy)(x>y), or a laminated structure thereof. There are structures, etc.

[0372] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, Conductive layer 5304, conductive layer 5306, conductive layer 5308, conductive layer 5357, and conductive layer 535 Examples of 9 include single-layer conductive films, or multilayer structures thereof. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. (Mo), Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni) Platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), scandium (Sc), zinc (Zn), phosphorus (P), boron (B), arsenic (As) Gallium (Ga), indium (In), tin (Sn), oxygen (O), zirconium (Z) r) A single element film selected from the group composed of cerium (Ce), or Examples of such compounds include those containing one or more elements selected from the aforementioned group. Therefore, an alloy containing one or more elements selected from the above group (indium tin oxide (I TO), indium zinc oxide (IZO), silicon oxide-containing indium tin oxide (ITS) O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum Odymium (Al-Nd), aluminum tungsten (Al-Ta), aluminum zirconium (Al -Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium Silver (Mg-Ag), Molybdenum niobium (Mo-Nb), Molybdenum tungsten (Mo- W), alloy materials such as molybdenum tantalum (Mo-Ta), one selected from the above group or compounds of multiple elements with nitrogen (such as titanium nitride, tantalum nitride, molybdenum nitride, etc.) Nitride film), or a compound of silicon with one or more elements selected from the group (nitride film) Sten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Examples include silicide films such as butene silicon. Other examples include carbon nanotubes and organic There are nanotube materials such as nanotubes, inorganic nanotubes, or metallic nanotubes. .

[0373] Furthermore, silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron). It is possible to include them. By including impurities in silicon, the conductivity is improved, and / or This allows it to behave like a normal conductor, making it possible to use it in wiring or electrodes. This makes it easier to use, for example.

[0374] Note that silicon can be in the form of single crystals, polycrystalline silicon, or microcrystalline silicon. Silicon, including silicon, which has various crystalline properties, or amorphous silicon. It is possible to use silicon that does not have crystalline properties, such as single-layer silicon. By using crystalline silicon or polycrystalline silicon, wiring, electrodes, conductive layers, conductive films, and terminals can be constructed. The resistance of components such as children can be reduced. As silicon, amorphous silicon or microcrystalline silicon can be used. By using silicon, wiring and other components can be formed through a simple process.

[0375] Furthermore, when using semiconductor materials such as silicon as the conductive layer, the semiconductor material such as silicon It is possible to form the material simultaneously with the semiconductor layer of the transistor.

[0376] Furthermore, aluminum or silver have high conductivity, which can reduce signal delay. Furthermore, aluminum or silver are easy to etch, making them easy to pattern, and fine It can perform fine machining.

[0377] Furthermore, because copper has high conductivity, it can reduce signal delay. If possible, it is preferable to use a laminated structure to improve adhesion.

[0378] Molybdenum or titanium are used in oxide semiconductors (such as ITO and IZO), or silicon. It has advantages such as being less prone to defects even when in contact with other materials, being easy to etch, and having high heat resistance. Therefore, it is desirable. Thus, as a conductive layer in contact with an oxide semiconductor or silicon, It is preferable to use molybdenum or titanium.

[0379] Furthermore, tungsten is preferable because it has advantages such as high heat resistance.

[0380] Furthermore, neodymium is desirable because it has advantages such as high heat resistance. In particular, as a conductive layer By using an alloy material of neodymium and aluminum, aluminum can be used in hillock This makes it less likely to occur. However, it is not limited to this, and also applies to aluminum, tantalum, and zirconia. By using alloy materials with um, titanium, or cerium, aluminum can also be made into a hiro This makes it less likely to cause cracks. In particular, alloy materials of aluminum and cerium are less prone to cracking. It can be significantly reduced.

[0381] Note that ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanochips are also used. Tubes and similar materials are translucent, so these materials can be used as pixel electrodes, counter electrodes, or common electrodes. It can be used in light-transmitting parts such as electrodes. In particular, IZO is used in etching. It is desirable because it is easy to etch and process. When IZO is etched, no residue remains. This is less likely to happen. Therefore, when IZO is used as the pixel electrode, To reduce the occurrence of defects (short circuits, misalignment, etc.) in liquid crystal elements and light-emitting elements. It is possible.

[0382] Furthermore, the conductive layer can be a single-layer structure or a multi-layer structure. By using a single-layer structure, the manufacturing process for wiring, electrodes, conductive layers, conductive films, terminals, etc. is simplified. It can be streamlined, reducing the number of processing days and lowering costs. On the other hand, By creating a layered structure, the advantages of each material are utilized while reducing their disadvantages. This allows for the formation of high-performance wiring, electrodes, etc. For example, low-resistance materials (aluminium) By incorporating materials such as um into a multilayer structure, the resistance of the wiring can be reduced. For example, by creating a laminated structure in which a low heat-resistant material is sandwiched between high heat-resistant materials, a low heat-resistant material can be achieved. By taking advantage of the properties of the material, it is possible to increase the heat resistance of wiring, electrodes, etc. One example of such a layered structure is a layer containing aluminum, molybdenum, titanium, A laminated structure sandwiching the material between layers containing neodymium or similar materials is desirable.

[0383] Furthermore, direct contact between wires, electrodes, etc., can negatively affect each other. For example... Then, one wire or electrode enters the other wire or electrode, changing its properties. This can result in the inability to achieve the original purpose. Another example is the formation of high-resistance areas. Alternatively, problems may arise during manufacturing, making it impossible to manufacture properly. In addition, a material that reacts with other materials and changes its properties is a material that does not react easily with those other materials. It is possible to sandwich or cover with it. For example, ITO and aluminum When connecting, neodymium alloy, titanium, and molybdenum should be placed between the ITO and the aluminum. It is possible to insert things like this. For example, when connecting silicon and aluminum, It is possible to sandwich neodymium alloy, titanium, and molybdenum between silicon and aluminum. These materials are used in wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. It can also be used for this purpose.

[0384] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 Examples of 8 include single-layer insulating films, or multilayer structures thereof. For example, silicon dioxide (SiOx), silicon nitride (SiNx), or silicon oxide nitride ( Oxygen or silicon dioxide (SiNxOy) (x>y), silicon nitride (SiNxOy) (x>y), etc. Nitrogen-containing membranes, carbon-containing membranes such as DLC (diamond-like carbon), or siloxane Sun resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclob Examples include resin or organic materials such as acrylic.

[0385] Examples of the light-emitting layer 5270 include organic EL elements and inorganic EL elements. Examples of elements include a hole injection layer made of a hole injection material and a hole transport layer made of a hole transport material. A layer consisting of a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, and an electron injection material An electron injection layer, or a single-layer structure of a layer made by mixing multiple of these materials, or These include layered structures.

[0386] Examples of liquid crystal layers 5307 include nematic liquid crystals, cholesteric liquid crystals, and smectic liquid crystals. Crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high Molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main-chain liquid crystal, side Examples include chain-type polymer liquid crystals, plasma addressable liquid crystals (PALC), and banana-type liquid crystals. Yes, it is possible. Also, the LCD driving method is TN (Twisted Nematic) mode. STN (Super Twisted Nematic) mode, IPS (In-Pl) FFS (Fringe Field Switching) mode, FFS (Fringe Field Switching) hing) mode, MVA (Multi-domain Vertical Alignment) ment) mode, PVA (Patterned Vertical Alignment) t) mode, ASV (Advanced Super View) mode, ASM (Ax ally Symmetric aligned Micro-cell) mode, O CB (Optically Compensated Birefringence) Electrically Controlled Birefring (ECB) ence) mode, FLC (Ferroelectric Liquid Crystal) l) Mode, AFLC (AntiFerroelectric Liquid Crys) tal) mode, PDLC (Polymer Dispersed Liquid Cr (host) mode, guest host mode, Blue Phase mode There is.

[0387] Furthermore, an insulating layer that functions as an alignment film is placed on top of the insulating layer 5305 and on top of the conductive layer 5306. It is possible to form insulating layers and other structures that function as protrusions.

[0388] Furthermore, on top of the conductive layer 5308, there are color filters, black matrices, or protrusions. It is possible to form insulating layers and the like that which function as conductive layers. Below the conductive layer 5308, there is an alignment film and It is possible to form an insulating layer that functions in this way.

[0389] In the cross-sectional structure shown in Figure 36(A), the insulating layer 5269, the light-emitting layer 5270, and the conductive layer Omitting 5271, the liquid crystal layer 5307 and conductive layer 5308 shown in Figure 36(B) are replaced with the insulating layer 526 It is possible to form it on 7 and on the conductive layer 5268.

[0390] Note that in the cross-sectional structure of Figure 36(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted. The insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 shown in 36(A) are insulated with insulating layer 530 It is possible to form it on 5 and on the conductive layer 5306.

[0391] Furthermore, in the cross-sectional structure of Figure 36(C), on top of the insulating layer 5358 and the conductive layer 5359, Form the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 shown in 36(A). This is possible. Alternatively, the liquid crystal layer 5307 and conductive layer 5308 shown in Figure 36(B) can be used as an insulating layer. It is possible to form it on 5358 and on the conductive layer 5359.

[0392] The transistor of this embodiment can be applied to embodiments 1 to 9. In particular, in Figure 36(B), the semiconductor layer is a non-single crystal semiconductor, an amorphous semiconductor, and a microcrystalline semiconductor. When using crystalline semiconductors, organic semiconductors, or oxide semiconductors, the transistor degrades. This can happen. However, the semiconductor devices and shift registers of Embodiments 1 to 9 In display devices, or in other applications, it is useful because it can suppress transistor degradation.

[0393] (Embodiment 11) In this embodiment, the layout diagram of the shift register (hereinafter also referred to as the top view) will be described. To clarify, in this embodiment, as an example, the shift register layer described in Embodiment 5 The diagram will now be explained. Note that the contents described in this embodiment are described in Embodiment 5. In addition to the shift register described, the semiconductor devices of Embodiments 1 to 10, and the shift registers It can be applied to a zista or display device. (See layout diagram of this embodiment.) This is just one example, and not an exhaustive list.

[0394] The layout diagram of this embodiment will be described with reference to Figures 37 and 38. Figure 37 Figure 38 shows an example of a layout diagram of a shift register, and Figure 38 shows an example of a diagram. The layout diagram of semiconductor device 7(A) is shown.

[0395] The transistors or wiring shown in Figures 37 and 38 consist of a conductive layer 701 and a semiconductor layer 70 2. It is composed of a conductive layer 703, a conductive layer 704, and a contact hole 705. Furthermore, this is not limited to the formation of a new conductive layer, insulating film, or contact hole. It is possible to do so. For example, a contactor for connecting conductive layer 701 and conductive layer 703 It is possible to add new Kutohall.

[0396] The conductive layer 701 may include portions that function as gate electrodes or wiring. The conductive layer 702 may include a portion that functions as a semiconductor layer of the transistor. The conductive layer 703 may include portions that function as wiring, sources, or drains. The conductive layer 704 may include portions that function as transparent electrodes, pixel electrodes, or wiring. It is possible. The contact hole 705 has the function of connecting the conductive layer 701 and the conductive layer 704. Alternatively, it has the function of connecting the conductive layer 703 and the conductive layer 704.

[0397] In the example shown in Figure 37, the wiring has an opening 711. Thus, the wiring has an opening. This can reduce parasitic capacitance. Alternatively, the trauma caused by electrostatic discharge can be reduced. This can suppress the destruction of the inverter. However, it is not limited to this, and the wiring has openings. It is possible that it is not possible.

[0398] In the example shown in Figure 37, openings are provided at the points where the wires intersect and in the surrounding areas. This reduces the crossover capacitance of the wiring. Therefore, noise reduction. Alternatively, it can reduce signal delay or distortion.

[0399] In the example shown in Figure 37, a conductive layer 704 is formed on a portion of the conductive layer 703 of the wiring. The conductive layer 704 then connects with the conductive layer 703 via the contact hole 705. The connection is made. In this way, the wiring resistance can be reduced, thus reducing the voltage drop, or This can reduce signal delay or distortion. However, it is not limited to this, and the conductive Layer 704 and the contact hole 705 can be omitted.

[0400] In the example shown in Figure 37, the wiring width of wiring 512 is the same as the wiring width of wiring 512_1, and wiring 512_ It is preferable that the wiring width is greater than 2. This is because a large current is generated in wiring 512. Therefore. For similar reasons, the wiring width of wiring 513 is the same as the wiring width of wiring 513_1, and It is preferable that the width is greater than the wiring width of wiring 513_2. However, it is not limited to this.

[0401] In the example shown in Figure 38, transistors 101_1, 101_2, and 1 In transistors 02_1, 102_2, and / or 201, the second The area where the conductive layer 701 and conductive layer 703 of the terminal overlap is the area where the conductive layer 701 and conductive layer 703 of the first terminal overlap. It is preferable that the area overlapping with layer 703 is smaller. By doing so, the transition The gate of sta 201 or the noise of wiring 111 can be reduced. Alternatively, the second This can suppress the concentration of the electric field at the terminal, thus preventing transistor degradation or transistor It can suppress the destruction of the sta.

[0402] Furthermore, a semiconductor layer 702 is formed in the portion where the conductive layer 701 and the conductive layer 703 overlap. This is possible. By doing so, the parasitic capacitance between the conductive layer 701 and the conductive layer 703 can be reduced. Because it can be made smaller, noise can be reduced. For the same reason, conductive layer A semiconductor layer 702 or a conductive layer 703 is formed in the portion where 701 and the conductive layer 704 overlap. It is possible.

[0403] Furthermore, a conductive layer 704 is formed on a part of the conductive layer 701, and the conductive layer 701 is contact It is possible to connect to the conductive layer 704 via the tohole 705. This can reduce the wiring resistance. Alternatively, a conductive layer 703 can be placed on top of a portion of the conductive layer 701. , and a conductive layer 704 is formed, and the conductive layer 701 is contacted via the contact hole 705 The conductive layer 703 is connected to the conductive layer 704 via another contact hole 705. It is possible to connect to the conductive layer 704. By doing so, the wiring resistance is reduced. It can be lowered further.

[0404] Furthermore, a conductive layer 704 is formed on a part of the conductive layer 703, and the conductive layer 703 is contact It is possible to connect to the conductive layer 704 via the tohole 705. This can reduce wiring resistance.

[0405] Furthermore, a conductive layer 701 or a conductive layer 703 is formed beneath a portion of the conductive layer 704, and the conductive layer 704, through the contact hole 705, connects to the conductive layer 701 or the conductive layer 703 It is possible to connect them in this way. By doing so, the wiring resistance can be reduced. .

[0406] As already mentioned, there is a parasitic capacitance between the gate and the first terminal of transistor 201. Rather than increasing the parasitic capacitance between the gate and the second terminal of transistor 201, It is possible. As shown in Figure 38, it functions as the first electrode of transistor 201. The width of the conductive layer 703 is shown as width 731, and it is used as the second electrode of the transistor 201. The width of the conductive layer 703 that can perform this function is indicated as width 732. And width 731 is width 732 It is possible to have a value greater than this. By doing so, the gate of transistor 201 and The parasitic capacitance between the gate and the second terminal of transistor 201 is greater than the parasitic capacitance between the first terminal and the second terminal. It is possible to increase the parasitic capacity. However, this is not the only option.

[0407] (Embodiment 12) This embodiment shows an example of the manufacturing process for transistors and capacitive elements. In particular, semiconductors The fabrication process when using an oxide semiconductor as the layer will be described. So, InMO3(ZnO) m It is possible to use layers denoted as (m>0). For M, one or more metallic elements selected from Ga, Fe, Ni, Mn, and Co. These include metallic elements. For example, M can be Ga, or Ga and Ni or G In some cases, metal elements other than Ga, such as α and Fe, may be present in oxide semiconductors. In addition to the metallic elements included as M, Fe, Ni, and other transition metals are included as impurity elements. Some contain elements or oxides of the transition metal. Such thin films are made in In-Ga It can be described as a -Zn-O non-single crystal film. Note that the oxide semiconductor is ZnO. It is possible to use this. Furthermore, the mobile ions in the oxide semiconductor layer, typically sodium, can be used. The concentration is 5 × 10 18 / cm 3 Furthermore, 1 x 10 18 / cm 3 The following is true: This is preferable because it can suppress changes in the electrical characteristics of the inverter. However, this It is not limited to this; various other oxide semiconductor materials can be used as semiconductor layers. Yes. Alternatively, the semiconductor layer can be a single-crystal semiconductor, a polycrystalline semiconductor, or a microcrystalline semiconductor. Stal, or nanocrystal semiconductors, amorphous semiconductors, or various non It is possible to use single-crystal semiconductors, etc.

[0408] Refer to Figures 46(A) to (C) for an example of the manufacturing process for transistors and capacitive elements. Let me explain. Figures 46(A) to (C) show the transistor 5441 and the capacitive element 5442. This is an example of the manufacturing process. Transistor 5441 is an example of an inverse staggered thin-film transistor. Yes, wiring is provided on the oxide semiconductor layer via source or drain electrodes. This is an example of a transistor.

[0409] First, a first conductive layer is formed over the entire surface of the substrate 5420 by sputtering. Next, Using a resist mask formed by a photolithography process using a first photomask Then, the first conductive layer is selectively etched to form conductive layer 5421 and conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 Element 2 can function as one electrode of a capacitive element. However, it is not limited to this. Furthermore, the conductive layer 5421 and the conductive layer 5422 are connected to the electrodes of wiring, gate electrodes, or capacitive elements. It is possible to have a part that functions in this way. After this, the resist mask is removed.

[0410] Next, the insulating layer 5423 is formed over the entire surface using plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421 , and is formed to cover the conductive layer 5422. The thickness of the insulating layer 5423 is 50n It is often in the range of m to 250 nm.

[0411] Furthermore, when a silicon oxide layer is used as the insulating layer 5423, an organic silane gas is used. By the CVD method, it is possible to form a silicon oxide layer. It contains ethyl silicate (TEOS: chemical formula Si(OC2H5)4) and tetramethylsilane (TM). S: Chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMD) S), triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane ( Silicon-containing compounds such as SiH(N(CH3)2)3), or yttrium oxide (Y2 It is possible to use O3).

[0412] Next, a resist mask formed by a photolithography process using a second photomask. Using this method, the insulating layer 5423 is selectively etched to reach the conductive layer 5421. Hole 5424 is formed. After this, the resist mask is removed. However, this is not limited to this. Therefore, it is possible to omit the contact hole 5424. Alternatively, an oxide semiconductor layer After the formation of the first layer, it is possible to form the contact hole 5424. The cross-sectional view corresponds to Figure 46(A).

[0413] Next, an oxide semiconductor layer is formed over the entire surface by sputtering. However, this is not limited to this method. Furthermore, an oxide semiconductor layer is formed by sputtering, and then n + Forming layers It is possible to do so. The thickness of the oxide semiconductor layer is typically between 5 nm and 200 nm. many.

[0414] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced. It is preferable to perform reverse sputtering to generate plasma. Furthermore, the debris adhering to the surface of the insulating layer 5423 and the bottom surface of the contact hole 5424 It can be removed. Reverse sputtering is a process where no voltage is applied to the target side, Under a GON atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma on the substrate surface. This is a method of reforming. However, it is not limited to this, and nitrogen or helical gas can be used instead of an argon atmosphere. It is possible to use elements such as um. Alternatively, oxygen, hydrogen, N2O, etc. in an argon atmosphere. It is possible to perform the procedure in an atmosphere with added [components]. Alternatively, an argon atmosphere with Cl2, CF4, etc. It is possible to perform this in an atmosphere with added [components]. Furthermore, when reverse sputtering is performed, the insulating layer 54 The surface of 23 is preferably shaved down to about 2-10 nm. After such plasma treatment, air By forming an oxide semiconductor layer without exposure to sunlight, the boundary between the gate insulating layer and the semiconductor layer is formed. It is useful in that it prevents dirt or moisture from adhering to the surface.

[0415] Next, the oxide semiconductor layer is selectively etched using a third photomask. Remove the resist mask.

[0416] Next, a second conductive layer is formed over the entire surface by sputtering. Then, a fourth photomask is formed. The resist mask formed by the photolithography process used is selectively used to create a second conductive material. The layers are etched to form conductive layers 5429, 5430, and 5431. The conductive layer 5429 is connected to the conductive layer 5421 via the contact hole 5424. The conductive layers 5429 and 5430 function as source electrodes or drain electrodes. This is possible, and the conductive layer 5431 can function as the other electrode of the capacitive element. However, this is not limited to conductive layer 5429, conductive layer 5430, and conductive layer 54 31 is a part that functions as a wiring, source or drain electrode, or electrode of a capacitive element. It is possible to include it.

[0417] Furthermore, if heat treatment (for example, at 200°C to 600°C) is to be performed afterward, the material must be able to withstand this heat treatment. It is preferable to provide heat resistance to the second conductive layer. Therefore, the second conductive layer is made of Al and Heat-resistant conductive materials (e.g., Ti, Ta, W, Mo, Cr, Nd, Sc, Zr, Ce, etc.) The elements, alloys of these elements, or nitrides containing these elements, etc. It is preferable that the material is a combination of the following. However, it is not limited to this, and the second conductive layer By creating a laminated structure, the second conductive layer can be made heat-resistant. For example, It is possible to provide heat-resistant conductive materials such as Ti or Mo above and below the Al.

[0418] Furthermore, before forming the second conductive layer by sputtering, argon gas is introduced and plastic Reverse sputtering is performed to generate zuma, on the surface of the insulating layer 5423 and the surface of the oxide semiconductor layer. It is preferable to remove any debris adhering to the surface and the bottom surface of the contact hole 5424. However, this is not limited to this, and nitrogen, helium, etc. may be used instead of an argon atmosphere. This is possible. Alternatively, it can be done in an argon atmosphere with added oxygen, hydrogen, N2O, etc. This is possible. Alternatively, it can be done in an argon atmosphere with Cl2, CF4, etc. added. It is possible.

[0419] Furthermore, during the etching of the second conductive layer, a portion of the oxide semiconductor layer is also etched. Then, an oxide semiconductor layer 5425 is formed. This etching process overlaps with the conductive layer 5421. The oxide semiconductor layer 5425 in the portion where the second conductive layer is not formed above it The oxide semiconductor layer 5425 is often thinned because it is shaved off. However, this is not the only example. However, the oxide semiconductor layer may not be etched. n on top of the layer + When a layer is formed, the oxide semiconductor layer is often etched. After that, the resist mask is removed. Transistor 544 is removed when this etching is complete. 1 and the capacitive element 5442 are completed. The cross-sectional view at this stage corresponds to Figure 46(B). ru.

[0420] Here, if reverse sputtering is performed before forming the second conductive layer by the sputtering method, The exposed portion of the insulating layer 5423 may preferably be scraped off by about 2 to 10 nm. Therefore, A recess may be formed in the margin layer 5423. Alternatively, etching of the second conductive layer may be performed. After forming conductive layers 5429, 5430, and 5431, reverse sputtering is performed. As a result, as shown in Figure 46(B), conductive layer 5429, conductive layer 5430, and The edges of the conductive layer 5431 may be curved.

[0421] Next, a heat treatment is performed at 200°C to 600°C in an atmospheric or nitrogen atmosphere. The process causes atomic-level rearrangement of the In-Ga-Zn-O non-single-crystal layer. The processing releases the strain that hinders carrier movement, thus eliminating the need for heat treatment (photo-annealing) here. (including) is important. Note that the timing of this heat treatment is not limited, and oxide semiconductors It can be done at various times once the body has formed.

[0422] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 has a single-layer structure. This is possible, and a laminated structure is also possible. For example, as the insulating layer 5432 is organic When using an insulating layer, the composition that is the material for the organic insulating layer is applied and placed in an atmospheric or nitrogen atmosphere. An organic insulating layer is formed by heat treatment at 200°C to 600°C under atmospheric conditions. By forming an organic insulating layer in contact with the oxide semiconductor layer, a thin film with highly reliable electrical properties can be produced. A film transistor can be fabricated. Note that an organic insulating layer is used as the insulating layer 5432. In such cases, a silicon nitride film or a silicon oxide film can be provided beneath the organic insulating layer.

[0423] In Figure 46(C), a configuration in which an insulating layer 5432 is formed using a non-photosensitive resin is shown. To illustrate, in a cross-section of the region where the contact hole is formed, the end of the insulating layer 5432 is It is angular. However, when an insulating layer 5432 is formed using a photosensitive resin, the contour In the cross-section of the region where a hole is formed, the end of the insulating layer 5432 is curved. This becomes possible. As a result, the coverage of the third conductive layer or pixel electrode that is formed later is improved.

[0424] Alternatively, instead of applying the composition, dipping, spray coating, or ink application can be used depending on the material. Jet method, printing method, doctor knife, roll coater, curtain coater, knife coater It is possible to use a tar, etc.

[0425] Furthermore, without heat treatment after forming the oxide semiconductor layer, the composition which is the material for the organic insulating layer During the heat treatment process, it is possible to simultaneously perform the heat treatment of the oxide semiconductor layer.

[0426] The insulating layer 5432 is formed to a thickness of 200 nm to 5 μm, preferably 300 nm to 1 μm. It is possible to do so.

[0427] Next, a third conductive layer is formed over the entire surface. Then, a photolithograph is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the process, The electrolytic layer 5433 and the conductive layer 5434 are formed. A cross-sectional view at this stage is shown in Figure 46(C). ) corresponds to the conductive layer 5433 and conductive layer 5434, wiring, pixel electrodes, reflective electrodes, transparent It can function as a light electrode or an electrode of a capacitive element. In particular, the conductive layer 5434 Since it is connected to the conductive layer 5422, it can function as an electrode for the capacitive element 5442. However, it is not limited to this, and also includes having the function of connecting the first conductive layer and the second conductive layer. This is possible. For example, by connecting conductive layer 5433 and conductive layer 5434. , conductive layer 5422 and conductive layer 5430 are connected to a third conductive layer (conductive layer 5433 and conductive layer 5434 ) will be able to connect via this method.

[0428] Furthermore, the capacitive element 5442 is connected to the conductive layer 5422 and the conductive layer 5434 by the conductive layer 543 Because the structure involves sandwiching element 1, the capacitance value of the capacitive element 5442 can be increased. Furthermore, it is not limited to this, and one of the conductive layers 5422 and 5434 may be omitted. It is Noh.

[0429] After removing the resist mask by wet etching, under an atmospheric or nitrogen atmosphere... It is possible to perform heat treatment at temperatures of 200°C to 600°C under atmospheric pressure.

[0430] Through the above process, the transistor 5441 and the capacitive element 5442 can be manufactured. .

[0431] Furthermore, as shown in Figure 46(D), an insulating layer 5435 is formed on the oxide semiconductor layer 5425. It is possible to do so. The insulating layer 5435 is acid when the second conductive layer is patterned. It has the function of preventing the crystalline semiconductor layer from being eroded and functions as a channel stop film. Therefore, the thickness of the oxide semiconductor layer can be reduced, thus reducing the transistor's drive voltage. To reduce the current, reduce the off-current, improve the on-off ratio of the drain current, or improve the S value. This is possible. Furthermore, the insulating layer 5435 is formed by continuously forming the oxide semiconductor layer and the insulating layer over the entire surface. The resist was then formed by a photolithography process using a photomask. The insulating layer can be formed by selectively patterning it using a screw. Then, a second conductive layer is formed over the entire surface, and the oxide semiconductor layer is patterned simultaneously with the second conductive layer. To do this, using the same mask (reticle), the oxide semiconductor layer and the second conductive layer This makes it possible to pattern the second conductive layer. In this case, beneath the second conductive layer, there must be an oxide semiconductor A layer is formed. In this way, the insulating layer 5435 is formed without increasing the number of steps. This can be achieved. In such a manufacturing process, an oxide semiconductor layer is located beneath the second conductive layer. This is often the case. However, it is not limited to this, and when an oxide semiconductor layer is patterned... Later, an insulating layer is formed over the entire surface, and the insulating layer is patterned to form the insulating layer 54 It is possible to form 35.

[0432] In Figure 46(D), the capacitive element 5442 is composed of conductive layer 5422 and conductive layer 5431. This structure sandwiches the insulating layer 5423 and the oxide semiconductor layer 5436. However, The oxide semiconductor layer 5436 can be omitted. And the conductive layer 5430 and the conductive layer 5431 is connected via a conductive layer 5437 formed by patterning the third conductive layer. Such a structure can be used, for example, in the pixels of a liquid crystal display device. For example, transistor 5441 functions as a switching transistor and has capacitance. Element 5442 can function as a retaining capacitance. And the conductive layer 5421, The electrolytic layer 5422, conductive layer 5429, and conductive layer 5437 are the gate wire, capacitance wire, and source wire, respectively. It can function as a pixel electrode. However, it is not limited to this. See Figure 4. Similar to 6(D), in Figure 46(C), the conductive layer 5430 and the conductive layer 5431 are also connected to the third It is possible to connect them via a conductive layer.

[0433] Furthermore, as shown in Figure 46(E), after patterning the second conductive layer, the oxide semiconductor layer It is possible to form 5425. By doing so, the second conductive layer becomes patterned If this occurs, the oxide semiconductor layer is not formed, so the oxide semiconductor layer will be removed. Therefore, the thickness of the oxide semiconductor layer can be made thinner, thus reducing the transistor's drive Reduction of dynamic voltage, reduction of off-current, improvement of drain current on-off ratio, or improvement of S value, etc. This can be achieved. Furthermore, the oxide semiconductor layer 5425 has a patterned second conductive layer. After that, an oxide semiconductor layer is formed over the entire surface, and then photolithography is performed using a photomask. A resist mask formed by the FI process is used to selectively pattern the oxide semiconductor layer. It can be formed by doing so.

[0434] In Figure 46(E), the capacitive element consists of a conductive layer 5422 and a third conductive layer patterned with The insulating layer 5423 and insulating layer 5432 are sandwiched between the conductive layer 5439 formed by the process. It has a structure that allows the conductive layer 5422 and conductive layer 5430 to form a third conductive layer. It is connected via a conductive layer 5438 formed by coating. Furthermore, the conductive layer 5439 is It is connected to the conductive layer 5440 formed by patterning two conductive layers. Note that this is shown in Figure 46(E Similarly, in Figures 46(C) and (D), conductive layer 5430 and conductive layer 5422 are It can be connected via the conductive layer 5438.

[0435] Furthermore, the thickness of the oxide semiconductor layer (or channel layer) is the depletion layer when the transistor is off. By making it even thinner, it becomes possible to create a state of complete depletion. In this way, The off-current can be reduced. To achieve this, the thickness of the oxide semiconductor layer is 2 Preferably, it is 0 nm or less. More preferably, it is 10 nm or less. Even more preferably, It is preferable that the wavelength is 6 nm or less.

[0436] Furthermore, the operating voltage of the transistor is reduced, the off-current is reduced, and the on-off ratio of the drain current is improved. In order to improve the S value and other aspects, the thickness of the oxide semiconductor layer is the thickness of the layer that makes up the transistor. Among them, the thinnest is preferable. For example, the film thickness of the oxide semiconductor layer is less than that of the insulating layer 5423. It is preferable that it be as thin as possible. More preferably, the thickness of the oxide semiconductor layer is equal to that of the insulating layer 5423. It is preferable that it be 1 / 2 or less. More preferably, it is preferable that it be 1 / 5 or less. More preferably, it is preferable that it be 1 / 10 or less. However, it is not limited to this, To improve reliability, the thickness of the oxide semiconductor layer can be thicker than that of the insulating layer 5423. It is possible. In particular, when the oxide semiconductor layer is removed, as shown in Figure 46(C), the oxide semiconductor layer Since a thicker conductive layer is preferable, the thickness of the oxide semiconductor layer is greater than that of the insulating layer 5423. It is also possible to make it thicker.

[0437] Furthermore, in order to increase the breakdown voltage of the transistor, the thickness of the insulating layer 5423 is greater than that of the first conductive layer. It is preferable that it be thick. More preferably, the thickness of the insulating layer 5423 is 5 / 4 the thickness of the first conductive layer. It is preferable that it is above this amount. More preferably, it is preferable that it is 4 / 3 or more. Furthermore, not limited to this, in order to increase the mobility of the transistor, the thickness of the insulating layer 5423 It is possible to make it thinner than the first conductive layer.

[0438] Note that the substrate, insulating film, conductive film, and semiconductor layer in this embodiment may differ from those in other embodiments. For example, the material described in Embodiment 10), or a material similar to the material described herein. It is possible to use it.

[0439] The transistor of this embodiment is used in the semiconductor device of Embodiments 1 to 9, and the shift resistor By using it in a display device, the display area can be enlarged. The display can be made highly detailed.

[0440] (Embodiment 13) In this embodiment, an example of an electronic device will be described.

[0441] Figures 39(A) to 39(H) and 40(A) to 40(D) ​​are diagrams showing electronic devices. Yes, these electronic devices consist of a casing 5000, a display unit 5001, a speaker 5003, and an LED. Lamp 5004, operation key 5005 (including operation switch or power switch), connection terminal Child 5006, Sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, (Including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared radiation), Microphone It can have n5008, etc.

[0442] Figure 39(A) shows a mobile computer, and in addition to the above, it includes switch 5009, It may have an infrared port 5010, etc. Figure 39(B) shows a portable device equipped with a recording medium. This is a type of image playback device (for example, a DVD player), and in addition to the above, a second display It may have a section 5002, a recording medium reading section 5011, etc. Figure 39(C) is a goggle. It is a type display, and in addition to the above, it has a second display unit 5002, a support unit 5012, It may have earphones 5013, etc. Figure 39(D) is a portable gaming machine, as described above. In addition to the above, it may also have a recording medium reading unit 5011, etc. Figure 39(E) is It is a projector and, in addition to the above-mentioned components, includes a light source 5033, a projection lens 5034, etc. This is possible. Figure 39(F) is a portable gaming machine, and in addition to the above, a second display unit It may have 5002, a recording medium reading unit 5011, etc. Figure 39(G) is a television receiver. It is an image device, and in addition to the above-mentioned components, it may also have a tuner, an image processing unit, etc. (Figure) 39(H) is a portable television receiver, and in addition to the above, it is capable of transmitting and receiving signals. It may have a charger 5017, etc. Figure 40(A) is a display, and the above In addition to the above, it may have a support base 5018, etc. Figure 40(B) is a camera. In addition to the above, there is an external connection port 5019, a shutter button 5015, and an image receiving unit. 5016, etc. may be included. Figure 40(C) is a computer, as described above. In addition, there is a pointing device 5020, an external connection port 5019, and a reader / writer 5 021, etc. may be included. Figure 40(D) ​​is a mobile phone, and in addition to the above, Antenna 5014, for 1-segment partial reception service for mobile phones and mobile terminals. It may have, etc.

[0443] The electronic devices shown in Figures 39(A) to 39(H) and Figures 40(A) to 40(D) ​​are various It can have various functions. For example, various types of information (still images, videos, text images, etc.) Functions that display information on the display unit, touch panel function, calendar, date or time display, etc. Functions, functions that control processing through various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, and wireless communication functions Functions that use to transmit or receive various data, programs recorded on recording media, or It can have functions such as reading data and displaying it on the display unit. Furthermore, multiple In electronic devices having a display unit, one display unit is primarily used to display image information, and another... A function that primarily displays text information on one display unit, or a function that takes parallax into account on multiple display units. It can have functions such as displaying three-dimensional images by displaying images. Furthermore, Electronic devices having an image receiving unit include functions for taking still images, functions for taking videos, and shooting Functions to automatically or manually correct the captured image, and the recording medium (external or camera) on which the captured image is stored. It can have functions such as saving images internally and displaying captured images on the display unit. Furthermore, the electronic devices shown in Figures 39(A) to 39(H) and Figures 40(A) to 40(D) The functions it can possess are not limited to these, and it can have a variety of functions.

[0444] The electronic device described in this embodiment has a display unit for displaying some kind of information. This embodiment is characterized by the electronic device of this embodiment and the semiconductor device of Embodiments 1 to 9. By combining it with a shift register or display device, reliability and yield can be improved. This allows for improvements in performance, cost reduction, larger display area, and higher resolution display area. .

[0445] Next, we will explain some application examples of semiconductor devices.

[0446] Figure 40(E) shows an example of a semiconductor device being installed as an integral part of a building. ) consists of a housing 5022, a display unit 5023, a remote control device 5024 which is the operating unit, and a speaker 5 Includes 025, etc. The semiconductor equipment is wall-mounted and integrated with the building, and the installation space It can be installed without requiring a large space.

[0447] Figure 40(F) shows another example in which semiconductor equipment is installed within a building and integrated with the building itself. The display panel 5026 is installed together with the unit bath 5027, and the bather This allows viewing of the display panel 5026.

[0448] In this embodiment, walls and a unit bathroom were used as examples of buildings, but the actual form The configuration is not limited to this, and semiconductor devices can be installed in various types of buildings.

[0449] Next, we will show an example in which a semiconductor device is integrated with a mobile device.

[0450] Figure 40(G) shows an example of a semiconductor device installed in an automobile. (Display panel) 5028 is attached to the vehicle body 5029 and is controlled by the movement of the vehicle body or from inside or outside the vehicle body The system can display the entered information on demand. It also includes a navigation function. It's okay to do so.

[0451] Figure 40(H) shows an example of a semiconductor device being integrated with a passenger aircraft. Yes. Figure 40(H) shows a display panel 5031 on the ceiling 5030 above the seats of a passenger airplane. This diagram shows the shape of the unit when installed and in use. The display panel 5031 is located on the ceiling 50 30 is attached integrally with the hinge portion 5032, and the extension and retraction of the hinge portion 5032 Passengers will be able to view the display panel 5031. The display panel 5031 can be operated by passengers. It has the function of displaying information by doing so.

[0452] In this embodiment, examples of mobile bodies include automobile bodies and aircraft bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), and trains (monorails). It can be installed on various things, including railroads, railways, ships, etc. [Explanation of Symbols]

[0453] 101 Circuit 102 circuits 103 Circuits 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 121 routes 122 routes 123 routes 200 circuits 201 Transistors 202 Capacity 203 Transistors 211 Wiring 212 Wiring 213 Wiring 214 Wiring 231 circuits 232 circuits 300 circuits 301 Transistors 302 Transistors 303 Transistors 304 transistors 305 Transistors 400 circuits 401 Transistors 402 transistors 403 Capacitive element 501 Flip-Flops 511 Wiring 512 Wiring 513 Wiring 514 Wiring 515 Wiring 516 Wiring 517 Wiring 520 circuits 521 Circuits 522 circuits 540 pixels 600 circuits 601 Circuit 602 Circuit 603 Transistor 604 Wiring 605 Wiring 614 signal 615 Signal 701 Conductive layer 702 Semiconductor layer 703 Conductive layer 704 Conductive layer 705 Contact Hole 711 Opening 731 width 732 width 101a diode 101pF transistor 102a diode 102pF transistor 112A wiring 112B Wiring 112C wiring 112D Wiring 112G wiring 112H wiring 112I Wiring 112J Wiring 200a terminal 200b terminal 200c terminal 200d terminal 200e terminal 200f terminal 200g terminal 200h terminal 200i terminal 200j terminal 200k terminal 201pF transistor 300a terminal 300b terminal 300c terminal 300d terminal 300e terminal 300f terminal 300g terminal 300h terminal 300i terminal 301pF transistor 302pF transistor 303pF transistor 3020 pixels 3021 Transistor 3022 liquid crystal element 3023 Capacitive element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3042 Voltage 3041_j signal 3042_j signal 400a terminal 400b terminal 400c terminal 400d terminal 400e terminal 400f terminal 403a Transistor 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation Keys 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Leader / Writer 5022 enclosure 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bathroom 5028 Display Panel 5029 Car body 5030 Ceiling 5031 Display Panel 5032 Hinge section 5033 Light source 5034 Projection Lens 5260 circuit board 5261 Insulating layer 5262 Semiconductor layer 5263 Insulating layer 5264 Conductive layer 5265 Insulating layer 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulating layer 5270 Emitting layer 5271 Conductive layer 5300 circuit boards 5301 Conductive layer 5302 Insulating layer 5304 Conductive layer 5305 Insulating layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulating layer 5355 area 5356 Insulating layer 5357 Conductive layer 5358 Insulating layer 5359 Conductive layer 5360 Video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 pixel section 5365 Circuit 5366 Lighting device 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 circuit board 5381 Input terminal 5391 circuit board 5392 Drive Circuit 5393 pixel section 5400 circuit boards 5401 Conductive layer 5402 Insulating layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5408 Insulating layer 5409 Conductive layer 5410 circuit board 5420 circuit board 5421 Conductive layer 5422 Conductive layer 5423 Insulating layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulating layer 5433 Conductive layer 5434 Conductive layer 5435 Insulating layer 5436 Oxide semiconductor layer 5437 Conductive layer 5438 Conductive layer 5439 Conductive layer 5440 Conductive layer 5441 Transistor 5442 Capacitive element 3020A subpixel 3020B subpixels 3021A Transistor 3021B Transistor 3022A Liquid Crystal Element 3022B Liquid Crystal Element 3023A Capacitive element 3023B Capacitive element 3031A Wiring 3031B Wiring 3032A Wiring 3032B Wiring 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a Circuit 5361b circuit 5362a Circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer

Claims

1. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer and a second conductive layer, The second clock signal line has at least a third conductive layer, The first conductive layer has a first opening, The third conductive layer has a second opening, Each of the first conductive layer and the third conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer is a semiconductor device having a region that overlaps with the second opening, It has transistors 1 through 8, The source electrode or drain electrode of the first transistor is always in contact with the gate signal line. The source electrode or the other drain electrode of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. The source electrode or drain electrode of the second transistor is always in contact with the gate signal line. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the third transistor is always in contact with the gate signal line. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the power line. The gate electrode of the third transistor is always in conductivity with the first signal line. Either the source electrode or the drain electrode of the fourth transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The gate electrode of the fourth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the power line. The gate electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the source electrode or drain electrode of the seventh transistor. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The source electrode or the other drain electrode of the seventh transistor is always in electrical contact with the power line. The gate electrode of the seventh transistor is always in conductivity with the third signal line. Either the source electrode or the drain electrode of the eighth transistor is always in contact with the fourth signal line. The gate electrode of the eighth transistor is always in conductivity with the fourth signal line. When the fourth signal line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the fifth transistor, at least through the channel forming region of the eighth transistor, the eighth transistor is on. At least one of the first to eighth transistors is a semiconductor device having an oxide semiconductor layer in a channel formation region.

2. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer and a second conductive layer, The second clock signal line has at least a third conductive layer, The first conductive layer has a first opening, The third conductive layer has a second opening, Each of the first conductive layer and the third conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer is a semiconductor device having a region that overlaps with the second opening, It has transistors 1 through 8, The source electrode or drain electrode of the first transistor is always in contact with the gate signal line. The source electrode or the other drain electrode of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. The source electrode or drain electrode of the second transistor is always in contact with the gate signal line. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the third transistor is always in contact with the gate signal line. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the power line. The gate electrode of the third transistor is always in conductivity with the first signal line. Either the source electrode or the drain electrode of the fourth transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The gate electrode of the fourth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the power line. The gate electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the source electrode or drain electrode of the seventh transistor. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The source electrode or the other drain electrode of the seventh transistor is always in electrical contact with the power line. The gate electrode of the seventh transistor is always in conductivity with the third signal line. The source electrode or drain electrode of the eighth transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the eighth transistor is always in conductivity with the fourth signal line. When the fourth signal line is in a conductive state with the gate electrode of the first transistor and the gate electrode of the fifth transistor, at least through the channel forming region of the eighth transistor, the eighth transistor is on. At least one of the first to eighth transistors is a semiconductor device having an oxide semiconductor layer in a channel formation region.

3. In Claim 1 or Claim 2, The sixth transistor is a semiconductor device having an oxide semiconductor layer in the channel formation region.

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