Sensor control board, display device, and control method for the display device

Abstract

To provide a sensor control board capable of reducing noise included in an image displayed by a display device.SOLUTION: In a display device 10A, a sensor control board 131 of a sensor controller 13 comprises: a clock generation circuit 1310 that generates a clock; and a phase adjustment circuit 1312 that adjusts a phase of the clock such that the phase is inverted at each predetermined timing and outputs the adjusted clock as a transmission signal to a position detector 14 that detects an indicated position on a display unit, wherein the position detector is located at an above or below layer of the display unit in which a plurality of image elements having one end for receiving input of a common potential and another end for receiving input of an individual potential is arrayed in a grid pattern.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a sensor control board, and particularly to a sensor control board, a display device, and a control method for the display device.

Background Art

[0002] Conventionally, a display device having a flat display unit such as a liquid crystal display has been known. In such a display device, pixel elements are arranged at intersections of a plurality of column signal lines arranged horizontally on the display unit and a plurality of row signal lines arranged vertically, and a driver circuit for charging and discharging the pixel elements is provided. The display device displays an image by driving each row signal line in order by the driver circuit and applying the charge applied to the column signal lines to the corresponding pixel elements.

[0003] Regarding this, Patent Document 1 discloses a display device (display) including a display unit (display panel), a circuit board for driving the display unit, and a position detector (sensor board) provided between the display unit and the circuit board for detecting the coordinates of a position indicator in the display unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the technology described in Patent Document 1, when the position detector transmits a transmission signal to the position indicator, fluctuations in the potential of the transmission signal may affect the potential of the reference line connected to the image element. The display device controls the brightness of the pixels corresponding to each image element based on the potential difference between the potential of the reference line and the potential of the column signal lines supplied to each image element. Therefore, in the technology described in Patent Document 1, when the position detector transmits a transmission signal to the position indicator, noise may be included in the image displayed by the display device.

[0006] This invention has been made in view of these problems, and its objective is to provide a sensor control board that can reduce noise contained in images displayed by a display device. [Means for solving the problem]

[0007] To solve the above problems, the first sensor control board according to the present invention is a display device comprising: a display unit in which a plurality of image elements are arranged in a grid pattern, with a common potential input at one end and individual potentials input at the other end; and a position detector arranged above or below the display unit for detecting a position indicated on the display unit, wherein the sensor control board outputs a transmission signal to the position detector, comprising: a clock generation circuit for generating a clock; and a phase adjustment circuit for adjusting the phase of the clock so as to be inverted at predetermined timing intervals, and outputting the transmission signal to the position detector using the adjusted clock as the transmission signal.

[0008] Furthermore, the second sensor control board according to the present invention further includes an output circuit that outputs the clock generated by the clock generation circuit to the phase adjustment circuit or stops the output of the clock to the phase adjustment circuit, the clock generation circuit is connected to the phase adjustment circuit via the output circuit, and the predetermined timing is the timing at which the output circuit outputs the clock to the phase adjustment circuit.

[0009] Furthermore, the third sensor control board according to the present invention further comprises an output circuit that outputs the clock generated by the clock generation circuit to the phase adjustment circuit or stops the output of the clock to the phase adjustment circuit, the clock generation circuit is connected to the phase adjustment circuit via the output circuit, and the output circuit outputs the clock in the first period and the second period in a plurality of third periods consisting of a first period and a plurality of second periods that are after the first period and shorter than the first period, and the predetermined timing is the timing when the third period begins.

[0010] Furthermore, in the fourth sensor control board according to the present invention, the predetermined timing is a timing synchronized with a vertical synchronization signal generated by the display device or input to the display device from an external source.

[0011] Furthermore, the fifth sensor control board according to the present invention further comprises an output circuit that outputs the clock generated by the clock generation circuit to the phase adjustment circuit or stops the output of the clock to the phase adjustment circuit, the clock generation circuit is connected to the phase adjustment circuit via the output circuit, the output circuit alternates the clock at a timing synchronized with a horizontal synchronization signal generated in the display device or input to the display device from an external source, and the output circuit outputs the clock in the first period and the second period in a plurality of third periods consisting of a first period and a plurality of second periods that are after the first period and shorter than the first period.

[0012] Furthermore, the sixth display device according to the present invention comprises a display unit in which a plurality of image elements are arranged in a grid pattern, with a common potential input at one end and individual potentials input at the other end; a position detector arranged above or below the display unit for detecting a position indicated on the display unit; a clock generation circuit for generating a clock; and a phase adjustment circuit for adjusting the phase so as to invert with respect to the clock at predetermined timing intervals, and outputting the adjusted clock as a transmission signal to the position detector.

[0013] Furthermore, the seventh display device according to the present invention further comprises: a timing adjustment circuit that receives a horizontal synchronization signal generated internally or input from an external source and outputs the horizontal synchronization signal at the timing when the potential of the transmission signal rises or falls; and a driver circuit that drives a plurality of image elements row by row in timing according to the horizontal synchronization signal output by the timing adjustment circuit.

[0014] Furthermore, in the eighth display device according to the present invention, the timing adjustment circuit adjusts the frequency of the horizontal synchronization signal to a frequency different from a multiple of the frequency of the transmission signal, thereby outputting the horizontal synchronization signal at the timing when the potential of the transmission signal rises or falls.

[0015] Furthermore, in the ninth display device according to the present invention, the timing adjustment circuit adjusts the phase of the horizontal synchronization signal so that it outputs the horizontal synchronization signal at the timing when the potential of the transmission signal rises or falls.

[0016] Further, the control method of the display device according to the tenth aspect of the present invention is a control method of a display device including a display unit in which a plurality of pixel elements having a common potential input at one end and an individual potential input at the other end are arranged in a grid pattern, and a position detector arranged above or below the display unit for detecting a position indicated on the display unit, the method including generating a clock, alternating the clock or stopping the alternation of the clock, adjusting the phase of the clock to invert at predetermined timings, and transmitting the clock with the adjusted phase as a transmission signal to the position detector.

Effect of the Invention

[0017] According to the present invention, the sensor control board can reduce noise included in an image displayed by the display device.

Brief Description of the Drawings

[0018] [Figure 1] It is a diagram showing an example of a display system. [Figure 2] It is a diagram showing a first example of the circuit configuration of a display control unit and a display unit. [Figure 3] It is a diagram showing an example of a pixel element. [Figure 4] It is a diagram showing an example of the circuit configuration of a sensor control unit and a position detector. [Figure 5] It is an example of a timing chart showing the state transition of a vertical synchronization signal and a transmission signal. [Figure 6] It is a first example of a timing chart showing the state transition of a horizontal synchronization signal, a transmission signal, and a common potential. [Figure 7] It is a flowchart showing an example of the flow of a series of operations of a display system. [Figure 8] It is a diagram showing a second example of the circuit configuration of a display control unit and a display unit. [Figure 9] It is a second example of a timing chart showing the state transition of a horizontal synchronization signal, a transmission signal, and a common potential. [Figure 10]It is a third example of a timing chart showing the state transitions of the horizontal synchronization signal and the transmission signal.

Embodiments for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention (hereinafter referred to as "the present embodiment") will be described with reference to the accompanying drawings. For ease of understanding of the description, the same reference numerals are given to the same components and steps in each drawing as much as possible, and redundant descriptions are omitted.

[0020] ―――First Embodiment――― First, the first embodiment will be described.

[0021] <Configuration> FIG. 1 is a diagram showing an example of a display system 1A according to the first embodiment. The display system 1A is a computer, monitor, or television held by a user, and for example, it is a tablet, smartphone, monitor of a personal computer, a television receiver, etc. In this example, the case where the display device 10A included in the display system 1A is a liquid crystal display will be described, but it is not limited thereto, and the display device 10A may be other display devices such as an organic EL (electro-luminescence) display or a plasma display. The display system 1A is configured to include, for example, a display device 10A and a position indicator 20.

[0022] The display device 10A is, for example, a liquid crystal display. The display device 10A is configured to include a display control unit 11A, a display unit 12, a sensor control unit 13, and a position detector 14.

[0023] The display control unit 11A controls the image display of the display unit 12 according to the image signal input to the image terminal IMG. The display control unit 11A also generates a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC according to the image signal, or extracts the horizontal synchronization signal HSYNC and vertical synchronization signal VSYNC contained in the image signal from the image signal. The display control unit 11A outputs the extracted horizontal synchronization signal HSYNC and vertical synchronization signal VSYNC to the sensor control unit 13 from terminals H and V, respectively.

[0024] The display unit 12 displays an image transmitted from the display control unit 11A in accordance with the control of the display control unit 11A. The display unit 12 is composed of, for example, a backlight 120, a pixel electrode 121, a liquid crystal unit 122, a common electrode 123, and a color filter 124.

[0025] The backlight 120 is a light source that illuminates the pixel electrodes 121 from the back side according to the control of the display control unit 11A, and is located on the furthest back side of the display unit 12.

[0026] The pixel electrode 121 is connected to one end of a plurality of image elements 1210 (see Figure 2) provided in the liquid crystal unit 122, and is a part that supplies an individual potential to each image element 1210, and is provided between the backlight 120 and the liquid crystal unit 122. The pixel electrode 121 drives each image element 1210 of the liquid crystal unit 122 according to the control of the display control unit 11A.

[0027] The liquid crystal section 122 is a part composed of a plurality of image elements 1210 (see Figure 2) divided in a grid pattern, and is provided between the pixel electrodes 121 and the common electrode 123. The liquid crystal section 122 transmits or blocks light irradiated from the backlight 120 to each image element 1210 according to the potential difference applied to both ends of each image element 1210. In the liquid crystal section 122, one end of each image element 1210 is connected to the pixel electrode 121, and the other end of each image element is connected to the common electrode 123.

[0028] The common electrode 123 is connected to the other end of the multiple image elements 1210 provided in the liquid crystal section 122 and is a part that uniformly supplies a common potential VCOM supplied from the display control unit 11A to each image element 1210, and is provided between the liquid crystal section 122 and the color filter 124.

[0029] The color filter 124 is a filter that provides color information to light transmitted through the liquid crystal section 122 by transmitting light, and outputs the light with color information from the display surface side. It is located on the display side of the display section 12. The color filter 124 is composed of, for example, a glass substrate and three types of color resist patterns of red, green, and blue arranged in a grid pattern on the upper layer of the glass substrate.

[0030] The sensor control unit 13 controls the position detector 14 according to the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC input to terminals H and V from the display control unit 11A, respectively, and outputs the position of the position indicator 20 detected by the position detector 14 on the display unit 12 to an external processing unit or an internal processing unit (not shown).

[0031] The position detector 14 is, for example, an electromagnetic induction (EMR: Electro Magnetic Resonance) sensor. Under the control of the sensor control unit 13, it transmits a transmission signal TX to the position indicator 20 and receives a resonant signal returned by the position indicator 20, thereby detecting a predetermined position on the display unit 12 indicated by the position indicator 20. The position detector 14 includes a plurality of sensor coils arranged planarly on the back side of the display unit 12, such that, when the display system 1A is viewed from the display surface side, it includes at least the area of ​​the display surface of the display unit 12. The position detector 14 detects the position of the detection coil with the highest received signal level as the predetermined position on the display unit 12 indicated by the position indicator 20. The position detector 14 also outputs information regarding the detected position to the sensor control unit 13.

[0032] The position indicator 20 is a pointing device that indicates a predetermined position on the display unit 12. The position indicator 20 is composed of a resonant circuit 21 which consists of an inductive element such as a coil and a capacitive element such as a capacitor. The position indicator 20 transmits the predetermined position on the display unit 12 to the position detector 14 by causing the resonant circuit 21 to resonate in response to a signal transmitted from the position detector 14, and transmitting the resonant signal generated by this resonance to the position detector 14.

[0033] Figure 2 shows a first example of the circuit configuration of the display control unit 11A and the display unit 12. As shown in Figure 2, the display control unit 11A is configured to include a control circuit 110, a gate driver circuit 111, and a source driver circuit 112.

[0034] The gate driver circuit 111 is a circuit that drives the row signal lines GL1 to GLn, and is located to the left of the display unit 12 when the display device 10A is viewed from the display surface side. The gate driver circuit 111 drives the row signal lines GL1 to GLn sequentially by outputting gate signals VG1 to VGn to the corresponding row signal lines GL1 to GLn according to the control of the control circuit 110. The gate driver circuit 111 also supplies and extracts charge to the gate electrodes of the corresponding image elements 1210 via the driven row signal lines GL1 to GLn.

[0035] The source driver circuit 112 is a circuit that drives the column signal lines SL1 to SLm, and is located below the display unit 12 when the display device 10A is viewed from the display surface side. The source driver circuit 112 outputs source signals VS1 to VSm, each having a potential set by the control circuit 110 for each column signal line SL1 to SLm, to the corresponding column signal lines SL1 to SLn at timings according to the control circuit 110. The source driver circuit 112 supplies the potential of the source signals VS1 to VSm corresponding to the image element 1210 to the source electrode of the image element 1210 corresponding to the intersection of the row signal lines GL1 to GLn driven by the gate driver circuit 111 and the column signal lines SL1 to SLm.

[0036] The pixel electrode 121 in the display unit 12 is composed of vertically arranged row signal lines GL1 to GLn, horizontally arranged column signal lines SL1 to SLm, and image elements 1210 positioned at each intersection of the row signal lines GL1 to GLn and the column signal lines SL1 to SLm. The pixel electrode 121 drives one of the corresponding row signal lines GL1 to GLn according to the gate signals VG1 to VGn transmitted from the gate driver circuit 111, and drives each image element 1210 corresponding to the source signals VS1 to VSm with the brightness indicated by the source signals VS1 to VSm transmitted from the source driver circuit 112.

[0037] Row signal lines GL1 to GLn are, for example, gate lines, and n of them are arranged vertically in the display device 10A. Row signal lines GL1 to GLn are driven by corresponding gate signals VG1 to VGn transmitted from the gate driver circuit 111, and relay the exchange of charge between the gate electrode of the image element 1210 at the intersection with the column signal lines SL1 to SLm and the gate driver circuit 111.

[0038] The column signal lines SL1 to SLm are, for example, source lines, and m of them are arranged horizontally in the display device 10A. The column signal lines SL1 to SLm are driven by the corresponding source signals VS1 to VSm transmitted from the source driver circuit 112, and relay the charge exchange between the source electrodes of the image element 1210 and the source driver circuit 112 at the intersections with the row signal lines GL1 to GLn.

[0039] The image element 1210 is, for example, a liquid crystal image element, and a total of n × m elements are arranged at the intersections of row signal lines GL1 to GLn and column signal lines SL1 to SLm in the pixel electrode 121. One of the row signal lines GL1 to GLn of the image element 1210 is connected to the gate electrode, and one of the column signal lines SL1 to SLm is connected to the source electrode. When charge is supplied to the gate electrode via the row signal lines GL1 to GLn connected to the gate electrode, the image element 1210 displays the corresponding image with brightness according to the potential of the column signal lines SL1 to SLm connected to the source electrode.

[0040] The control circuit 110 is a circuit for controlling the display unit 12. The control circuit 110 generates a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC according to the image signal input via the image terminal IMG, or extracts the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC contained in the image signal from the image signal. The control circuit 110 outputs the horizontal synchronization signal HSYNC from terminal H to the sensor control unit 13, and outputs the vertical synchronization signal VSYNC from terminal V to the sensor control unit 13.

[0041] Furthermore, the control circuit 110 controls the gate driver circuit 111 to drive the row signal lines GL1 to GLn sequentially in timing according to the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. The control circuit 110 also controls the source driver circuit 112 so that each image element 1210 displays the image corresponding to the image data contained in the image signal.

[0042] Furthermore, the control circuit 110 generates a common potential VCOM to be applied to the common electrode 123 and supplies the generated potential to the common electrode 123 from the common terminal COM. The control circuit 110 also controls the operation of the backlight 120 by transmitting a control signal to the backlight 120 via the backlight terminal BL.

[0043] Figure 3 shows an example of an image element 1210. As shown in Figure 3, the image element 1210 is composed of, for example, a thin-film transistor TFT, a liquid crystal electrode Clc, and a capacitive element Cpx.

[0044] The thin-film transistor TFT functions as a switching element in the image element 1210. The gate electrode of the thin-film transistor TFT is connected to the row signal line GL, the source electrode is connected to the column signal line SL, and the drain electrode is connected to one end of the liquid crystal electrode Clc and the capacitive element Cpx. When charge is supplied to the gate electrode via the row signal line GL, the thin-film transistor TFT makes the state between the source electrode and the drain electrode conductive. Conversely, when charge is withdrawn from the gate electrode via the row signal line GL, the thin-film transistor TFT makes the state between the source electrode and the drain electrode non-conductive. Furthermore, the thin-film transistor TFT maintains the state between the source electrode and the drain electrode when there is no change in the potential applied to the gate electrode.

[0045] The liquid crystal electrode Clc is an electrode for supplying potential to the liquid crystal section 122. One end of the liquid crystal electrode Clc is connected to the drain electrode of the thin-film transistor TFT and one end of the capacitive element Cpx, and the other end is connected to the common electrode 123 via the liquid crystal section 122. The liquid crystal electrode Clc supplies the potential supplied from the capacitive element Cpx to the liquid crystal section 122.

[0046] The capacitive element Cpx is, for example, a capacitor and holds a potential to supply to the liquid crystal electrode Clc. One end of the capacitive element Cpx is connected to the drain electrode of the thin-film transistor TFT and one end of the liquid crystal electrode Clc, and the other end is connected to the common electrode 123. When the thin-film transistor TFT is in a conducting state, the capacitive element Cpx holds the potential supplied from the column signal line SL. When the thin-film transistor TFT is in a non-conducting state, the capacitive element Cpx supplies the held potential to the liquid crystal electrode Clc.

[0047] The image element 1210, configured as described above, when charge is supplied to the gate electrode of the thin-film transistor TFT via the row signal line GL, turns the thin-film transistor TFT into a conductive state, supplies the potential of the column signal line SL to the capacitive element Cpx, and holds the potential supplied via the column signal line SL to the capacitive element Cpx. Furthermore, when charge is withdrawn from the gate electrode of the thin-film transistor TFT via the row signal line GL, the image element 1210 turns the thin-film transistor TFT into a non-conductive state, supplies the potential held by the capacitive element Cpx to the liquid crystal electrode Clc, and controls the state of the liquid crystal section 122 to conform to the supplied potential.

[0048] Figure 4 shows an example of the circuit configuration of the sensor control unit 13 and the position detector 14. As shown in Figure 4, the sensor control unit 13 is composed of a control circuit 130, a sensor control board 131, a switching circuit 132, an amplification circuit 133, and a receiving circuit 134.

[0049] The control circuit 130 controls the sensor control board 131 and the switching circuit 132 according to the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC output from the display control unit 11A, and outputs a signal indicating the position information on the display unit 12 of the position indicator 20, which is output from the receiving circuit 134, to an external processing unit or an internal processing unit (not shown).

[0050] Specifically, the control circuit 130 controls the sensor control board 131 and the switching circuit 132 during the period between alternations of the vertical synchronization signal VSYNC, causing the position detector 14 to perform position detection (scanning) of the position indicator 20 multiple times. The control circuit 130 controls the switching circuit 132 by outputting a selection signal SEL to the switching circuit 132. Here, during the scan period SCAN in which the scan process is performed once, the control circuit 130 sequentially executes burst processing, data transmission / reception processing, and coordinate processing.

[0051] The control circuit 130 performs burst processing during the burst period, which is the first period in the scan period (SCAN). Here, burst processing is performed to allow energy to be stored in the resonant circuit 21 provided in the position indicator 20 by continuously transmitting a transmission signal TX from the position detector 14 to the position indicator 20. During burst processing, the control circuit 130 controls the sensor control board 131 and the switching circuit 132 to continue transmitting the transmission signal TX to the position detector 14. Note that the burst period is longer than the data period (data) in which data transmission and reception processing takes place and the coordinate period (coord) in which coordinate processing takes place.

[0052] The control circuit 130 performs data transmission and reception processing during the data period, which is the period following the burst period in the scan period (SCAN). Here, the data transmission and reception processing is the process of transmitting and receiving information, such as the unique ID of the position indicator 20, between the position detector 14 and the position indicator 20. The control circuit 130 alternately transmits a transmission signal TX to the position detector 14 and receives a reception signal RX from the position detector 14 by alternately switching the connection destination of the switching circuit 132 to either the amplification circuit 133 or the phase adjustment circuit 1312 using a selection signal SEL.

[0053] The control circuit 130 performs coordinate processing in the coordinate period coord, which is the period following the data period data in the scan period SCAN. Here, coordinate processing is a process to detect where the position (coordinates) is on the display unit 12 of the position indicator 20. The control circuit 130 alternately transmits a transmission signal TX to the position detector 14 and receives a reception signal RX from the position detector 14 by alternately switching the connection destination of the switching circuit 132 to either the amplification circuit 133 or the phase adjustment circuit 1312 using a selection signal SEL.

[0054] Furthermore, the control circuit 130 controls the timing at which the output circuit 1311 outputs the clock so that the clock is synchronized with the horizontal synchronization signal HSYNC during the data period data and the coordinate period coord. In addition, the control circuit 130 controls the output circuit 1311 so that it stops outputting the clock while the switching circuit 132 is connected to the amplification circuit 133, while controlling the output circuit 1311 so that it outputs the clock while the switching circuit 132 is connected to the phase adjustment circuit 1312.

[0055] Furthermore, the control circuit 130 controls the phase adjustment circuit 1312 so that the phase of the clock output from the output circuit 1311 inverts at predetermined timings. The predetermined timing is, for example, the timing when the output circuit 1311 outputs a clock to the phase adjustment circuit 1312, the timing when the scan period SCAN starts, and the timing when it synchronizes with the vertical synchronization signal VSYNC (specifically, the timing when the vertical synchronization signal VSYNC alternates).

[0056] The sensor control board 131 generates a transmit signal TX to drive the position detector 14 when the position detector 14 transmits a signal to the position indicator 20, in accordance with the control of the control circuit 130, and transmits the transmit signal TX to the position detector 14 via the switching circuit 132. The sensor control board 131 is configured to include, for example, a clock generation circuit 1310, an output circuit 1311, and a phase adjustment circuit 1312.

[0057] The clock generation circuit 1310 is, for example, an oscillator, which generates a clock with a frequency equal to the resonant frequency of the resonant circuit 21 of the position indicator 20, and outputs the generated clock to the output circuit 1311.

[0058] The output circuit 1311 is, for example, a current driver, and according to the control of the control circuit 130, outputs the clock output from the clock generation circuit 1310 to the phase adjustment circuit 1312 or stops the clock output. Also, when outputting the clock, the output circuit 1311 outputs the clock at a timing synchronized with the horizontal synchronization signal HSYNC during the data period data and the coordinate period coord, according to the control of the control circuit 130.

[0059] The phase adjustment circuit 1312 adjusts the phase of the clock output from the output circuit 1311 to invert at predetermined timing intervals, in accordance with the control of the control circuit 130. Specific examples of the predetermined timing are as described above. The phase adjustment circuit 1312 uses the adjusted clock as the transmission signal TX and outputs the transmission signal TX to the position detector 14 via the switching circuit 132.

[0060] The switching circuit 132 is connected to the control circuit 130, the amplification circuit 133, the phase adjustment circuit 1312, and the position detector 14. According to the control of the control circuit 130, the switching circuit 132 switches the connection destination of the position detector 14 to either the amplification circuit 133 or the phase adjustment circuit 1312. Specifically, the switching circuit 132 switches the connection destination of the position detector 14 to either the amplification circuit 133 or the phase adjustment circuit 1312 according to the selection signal SEL output from the control circuit 130.

[0061] The amplification circuit 133 is, for example, an operational amplifier, and performs signal amplification on the signal indicating the position information of the position indicator 20 supplied from the position detector 14 via the switching circuit 132, and outputs the amplified signal to the receiving circuit 134.

[0062] The receiving circuit 134 performs predetermined processing on the signal indicating the position information of the position indicator 20 supplied from the position detector 14 via the switching circuit 132 and the amplification circuit 133, and outputs the processed signal to the control circuit 130. Specifically, the receiving circuit 134 reduces high-frequency components from the signal indicating the position information of the position indicator 20 supplied from the position detector 14 via the amplification circuit 133 using a low-pass filter or the like, then converts it into a digital signal using an analog-to-digital conversion circuit or the like, and outputs the converted digital signal to the control circuit 130.

[0063] The position detector 14 drives each sensor coil according to the transmission signal TX output from the sensor control board 131 via the switching circuit 132 and transmits the transmission signal TX to the position indicator 20. The position detector 14 also receives the received signal RX transmitted from the position indicator 20 using its sensor coil and transmits the received signal RX to the amplification circuit 133 via the switching circuit 132.

[0064] The configuration of the display system 1A has been described above. Next, the potential transitions of various signals in the display system 1A will be described in detail. Figure 5 is an example of a timing chart showing the state transitions of the vertical synchronization signal VSYNC and the transmission signal TX in the display system 1A according to the first embodiment.

[0065] At time t51, the control circuit 110 of the display control unit 11A alternates the vertical synchronization signal VSYNC. If the predetermined timing described above coincides with the timing of the vertical synchronization signal VSYNC, the control circuit 130 controls the phase adjustment circuit 1312 to invert the phase of the clock.

[0066] At time t501, the control circuit 130 of the sensor control unit 13 starts the first scan process. At time t501, the control circuit 130 first starts the burst period, switches the connection destination of the switching circuit 132 to the phase adjustment circuit 1312, and transmits the transmission signal TX from the output circuit 1311 to the position detector 14 via the phase adjustment circuit 1312 and the switching circuit 132. If the predetermined timing described above is the timing when the scan period SCAN starts, the control circuit 130 controls the phase adjustment circuit 1312 to invert the phase of the clock.

[0067] During the burst period from time t501 to time t502, the position detector 14 transmits a transmission signal TX to the position indicator 20. During the burst period from time t501 to time t502, the position indicator 20 receives the transmission signal TX from the position detector 14 and stores energy in the resonant circuit 21.

[0068] At time t502, the control circuit 130 ends the burst period and starts the data period. During the data period from time t502 to time t503, the control circuit 130 alternately transmits the transmission signal TX to the position detector 14 and receives the reception signal RX from the position detector 14 by alternately switching the connection destination of the switching circuit 132 to either the amplification circuit 133 or the phase adjustment circuit 1312. If the predetermined timing described above is the timing when the output circuit 1311 outputs a clock to the phase adjustment circuit 1312, the control circuit 130 controls the phase adjustment circuit 1312 to invert the phase of the clock each time it starts transmitting the transmission signal TX to the position detector 14. Also, during the data period from time t502 to time t503, the position detector 14 alternately transmits the transmission signal TX to the position indicator 20 and receives the reception signal RX transmitted from the position indicator 20. Furthermore, during the data period data from time t502 to time t503, the position indicator 20 transmits a received signal RX to the position detector 14 in response to the transmitted signal TX transmitted from the position detector 14.

[0069] At time t503, the control circuit 130 ends the data period data and starts the coordinate period coord. During the coordinate period coord from time t503 to time t504, the control circuit 130 alternately transmits the transmission signal TX to the position detector 14 and receives the reception signal RX from the position detector 14 by alternately switching the connection destination of the switching circuit 132 to either the amplification circuit 133 or the phase adjustment circuit 1312. Also during the coordinate period coord from time t503 to time t504, the control circuit 130 identifies the position on the display unit 12 of the position indicator 20 according to the received signal RX and outputs a signal indicating the position information to an external processing unit or an internal processing unit (not shown). If the predetermined timing described above is the timing when the output circuit 1311 outputs a clock to the phase adjustment circuit 1312, the control circuit 130 controls the phase adjustment circuit 1312 to invert the phase of the clock each time it starts transmitting the transmission signal TX to the position detector 14. Furthermore, during the data period data from time t503 to time t504, the position detector 14 alternately transmits a transmission signal TX to the position indicator 20 and receives a reception signal RX transmitted from the position indicator 20. Also, during the data period data from time t503 to time t504, the position indicator 20 transmits a reception signal RX to the position detector 14 in response to the transmission signal TX transmitted from the position detector 14.

[0070] At time t504, the control circuit 130 terminates the coordinate period coord and also terminates the first scan process.

[0071] At times t52 and t53, the control circuit 130 performs the second and third scan processes, respectively, in the same manner as at time t51. If the predetermined timing described above coincides with the start of the scan period SCAN, the control circuit 130 controls the phase adjustment circuit 1312 to invert the clock phase.

[0072] At time t54, the control circuit 110 of the display control unit 11A alternates the vertical synchronization signal VSYNC. If the predetermined timing described above coincides with the timing of the vertical synchronization signal VSYNC, the control circuit 130 controls the phase adjustment circuit 1312 to invert the phase of the clock. After time t54, the display system 1A performs the same processing as after time t51.

[0073] Figure 6 is an example of a timing chart showing the state transitions of the horizontal synchronization signal HSYNC, the transmission signal TX, and the common potential VCOM in the display system 1A according to the first embodiment.

[0074] Graph g1 shows the potential difference applied across the image element 1210 during the data period data or the coordinate period coord. In graph g1, period 1H represents the period of the horizontal synchronization signal HSYNC. Graphs g2 and g3 show the potentials of the horizontal synchronization signal HSYNC, the transmission signal TX, and the common potential VCOM, respectively, when the phase of the transmission signal TX is inverse. As shown in graphs g2 and g3, the common potential VCOM, which is the potential of the common electrode 123, is affected by the transmission signal TX flowing through the position detector 14 located below the common electrode 123, and fluctuates in accordance with the potential of the transmission signal TX.

[0075] Referring to graph g2, at times t601 and t602, the control circuit 110 of the display control unit 11A alternates the horizontal synchronization signal HSYNC. Also at times t601 and t602, the potential of the transmission signal TX becomes high. At times t601 and t602, the common potential VCOM increases by a potential α due to the influence of the potential of the transmission signal TX flowing through the position detector 14.

[0076] Referring to graph g3, at times t605 and t606, the control circuit 110 of the display control unit 11A alternates the horizontal synchronization signal HSYNC. Also at times t605 and t606, the potential of the transmission signal TX becomes low. At times t605 and t606, the common potential VCOM becomes lower by a potential α due to the influence of the potential of the transmission signal TX flowing through the position detector 14.

[0077] Referring to graph g1, during the period when the sensor control unit 13 stops transmitting the transmission signal TX to the position detector 14 and receives the reception signal RX transmitted from the position indicator 20 via the position detector 14, the potential difference applied across the image element 1210 is potential difference Vpx. Also, during the period when the sensor control unit 13 transmits the transmission signal TX to the position detector 14, the potential difference applied across the image element 1210 becomes potential difference Vpx+α or potential difference Vpx-α due to fluctuations in the potential of the common electrode 123 connected to one end of the image element 1210. Note that the potential difference applied across the image element 1210 is approximately potential difference Vpx on average because the phase of the transmission signal TX is inverted at predetermined timings by the control circuit 130.

[0078] The potential transitions of various signals in the display system 1A have been described above. Next, the sequence of processes in the display system 1A will be described in detail. Figure 7 is a flowchart showing an example of the sequence of processes in the display system 1A according to the first embodiment.

[0079] (Step SP10) The display device 10A generates a clock using the clock generation circuit 1310. The display device 10A outputs the clock generated by the clock generation circuit 1310 to the output circuit 1311. Then, the process proceeds to step SP12.

[0080] (Step SP12) The display device 10A controls the clock output by the output circuit 1311 via the control circuit 130 of the sensor control unit 13. During the burst period, the display device 10A causes the output circuit 1311 to output a clock. Furthermore, during the data period and the coordinate period, the display device 10A controls the output circuit 1311 to alternately output and stop the clock output. Then, the process proceeds to step SP14.

[0081] (Step SP14) The display device 10A controls the phase adjustment circuit 1312 by the control circuit 130 of the sensor control unit 13 to invert the clock phase at predetermined timings. The predetermined timing is one of the following, as described above: the timing when the output circuit 1311 outputs a clock to the phase adjustment circuit 1312, the timing when the scan period SCAN starts, and the timing when it synchronizes with the vertical synchronization signal VSYNC. Then, the process moves on to the process of step SP16.

[0082] (Step SP16) The display device 10A uses a clock whose phase has been adjusted by the phase adjustment circuit 1312 as the transmission signal TX, and outputs the transmission signal TX from the position detector 14 to the position indicator 20. Then, the series of processes shown in Figure 11 is completed.

[0083] <Effects> In the first embodiment described above, the sensor control board 131 is a display device 10A comprising a display unit 12 in which a plurality of image elements 1210 are arranged in a grid, with a common potential VCOM input to one end and a corresponding individual potential (any of the potentials of source signals VS1 to VSm) input to the other end, and a position detector 14 arranged above or below the display unit 12 to detect the position indicated on the display unit 12, and outputs a transmission signal TX to the position detector 14. Furthermore, the sensor control board 131 comprises a clock generation circuit 1310 that generates a clock, and a phase adjustment circuit 1312 that adjusts the phase of the clock so as to invert at predetermined timings, and outputs the transmission signal TX to the position detector 14 using the adjusted clock as the transmission signal TX.

[0084] In this configuration, the sensor control board 131 inverts the phase of the clock at predetermined timings. Therefore, the sensor control board 131 can reduce noise in the image displayed by the display device 10A by canceling out fluctuations in the common potential VCOM, which is affected by fluctuations in the potential of the transmitted signal TX.

[0085] In this embodiment, the sensor control board 131 further includes an output circuit 1311 that either outputs the clock generated by the clock generation circuit 1310 to the phase adjustment circuit 1312 or stops the output of the clock to the phase adjustment circuit 1312. Here, the clock generation circuit 1310 is connected to the phase adjustment circuit 1312 via the output circuit 1311. The predetermined timing is the timing at which the output circuit 1311 outputs the clock to the phase adjustment circuit 1312.

[0086] With this configuration, the sensor control board 131 inverts the phase of the clock each time the output circuit 1311 outputs a clock, thereby reducing noise in the image displayed by the display device 10A with higher precision.

[0087] Furthermore, in this embodiment, the output circuit 1311 outputs a clock during the first period and the second period in a plurality of third periods (scan period) which consist of a first period (burst period) and a plurality of second periods (data period and coordinate period) which are after the first period and shorter than the first period. The predetermined timing is the timing when the third period begins.

[0088] With this configuration, the sensor control board 131 inverts the clock phase each time the scan period SCAN starts, thereby reducing noise in the image displayed by the display device 10A, regardless of the specifications regarding the transmission and reception of signals during the scan period.

[0089] Furthermore, in this embodiment, the predetermined timing is a timing that is synchronized with the vertical synchronization signal VSYNC, which is generated in the display device 10A or input to the display device 10A from an external source.

[0090] With this configuration, the sensor control board 131 inverts the clock phase at a timing synchronized with the vertical synchronization signal VSYNC, thereby reducing noise in the image displayed by the display device 10A, regardless of the communication specifications for transmitting and receiving signals between the position detector 14 and the position indicator 20.

[0091] ---Second Embodiment--- Next, a second embodiment will be described.

[0092] <Structure> Figure 8 shows the circuit configuration of the display control unit 11B and the display unit 12 in the display system 1B according to the second embodiment. Furthermore, the display system 1B is the same as the display system 1A in the first embodiment, except that a timing adjustment circuit 113 is added to the display control unit 11B of the display device 10B, so the explanation of the similar parts will be omitted.

[0093] The control circuit 110 outputs the horizontal sync signal HSYNC and the vertical sync signal VSYNC, which are extracted from or generated from the image signal, to the gate driver circuit 111 and the source driver circuit 112 via the timing adjustment circuit 113.

[0094] The timing adjustment circuit 113 receives the horizontal synchronization signal HSYNC from the control circuit 110 and outputs the horizontal synchronization signal HSYNC to the gate driver circuit 111, the source driver circuit 112, and the sensor control circuit 13 at the timing when the potential of the transmission signal TX that the sensor control unit 13 transmits to the position detector 14 rises or falls. In addition, the timing adjustment circuit 113 adjusts the timing of outputting the vertical synchronization signal VSYNC in accordance with the adjustment of the output timing of the horizontal synchronization signal HSYNC, and outputs the vertical synchronization signal VSYNC with the adjusted output timing to the gate driver circuit 111, the source driver circuit 112, and the sensor control circuit 13.

[0095] Specifically, the timing adjustment circuit 113 adjusts the frequency of the horizontal synchronization signal HSYNC, which has a frequency of 133 kHz and is received from the control circuit 110, to a frequency (e.g., 130 kHz) that is different from a multiple of the frequency of the transmission signal TX (e.g., 666 kHz). This enables the horizontal synchronization signal HSYNC to be output to the gate driver circuit 111 at the timing when the potential of the transmission signal TX rises or falls.

[0096] Alternatively, the timing adjustment circuit 113 adjusts the phase of the horizontal synchronization signal HSYNC received from the control circuit 110, thereby enabling the horizontal synchronization signal HSYNC to be output to the gate driver circuit 111 at the timing when the potential of the transmission signal TX rises or falls.

[0097] The configuration of the display system 1B has been described above. Next, the potential transitions of various signals in the display system 1B will be described in detail. Figure 9 is an example of a timing chart showing the state transitions of the horizontal synchronization signal HSYNC, the transmission signal TX, and the common potential VCOM in the display system 1B according to the second embodiment.

[0098] Graph g4 shows the case where the frequency of the horizontal synchronization signal HSYNC is adjusted to a frequency different from a multiple of the frequency of the transmission signal TX. Graph g5 shows the case where the phase of the horizontal synchronization signal HSYNC is advanced by one-quarter of the period of the horizontal synchronization signal HSYNC.

[0099] Referring to graph g4, at times t901 and t902, the control circuit 110 of the display control unit 11B alternates the horizontal synchronization signal HSYNC. Also at time t901, the control circuit 130 of the sensor control unit 13 raises the potential of the transmit signal TX. Also at time t902, the control circuit 130 of the sensor control unit 13 lowers the potential of the transmit signal TX. At times t901 and t902, the common potential VCOM continues to transition from low level to high level or from high level to low level, and becomes approximately the same potential as the potential supplied from the control circuit 110 to the common electrode 123.

[0100] Referring to graph g5, at times t905 and t906, the control circuit 110 of the display control unit 11B alternates the horizontal synchronization signal HSYNC. Also at times t905 and t906, the control circuit 130 of the sensor control unit 13 lowers the potential of the transmission signal TX. At times t905 and t906, the common potential VCOM continues to transition from a high level to a low level, becoming approximately the same potential as the potential supplied from the control circuit 110 to the common electrode 123.

[0101] <Effects> In the second embodiment described above, the display device 10B comprises a display unit 12 in which a plurality of image elements 1210 are arranged in a grid, with a common potential VCOM input to one end and an individual potential (any of the potentials of source signals VS1 to VSm) input to the other end; a position detector 14 arranged above or below the display unit 12 for detecting a position indicated on the display unit 12; and a sensor control board 131 that generates a transmission signal TX and outputs the generated transmission signal TX to the position detector 14. Furthermore, the display device 10B comprises a timing adjustment circuit 113 that receives a horizontal synchronization signal HSYNC generated in the display unit 12 or input to the display device 10B from an external source and outputs the horizontal synchronization signal HSYNC at the timing when the potential of the transmission signal TX rises or falls; and a gate driver circuit 111 (driver circuit) that drives the plurality of image elements 1210 in order row by row at timing according to the horizontal synchronization signal HSYNC output by the timing adjustment circuit 113.

[0102] With this configuration, the display device 10B outputs a horizontal synchronization signal HSYNC from the timing adjustment circuit 113 to the gate driver circuit 111 at the timing when the potential of the transmission signal TX rises or falls, thereby suppressing fluctuations in the common potential VCOM at each timing for driving the image element 1210. Therefore, the display device 10B can reduce noise contained in the image displayed by the display device 10B caused by fluctuations in the common potential VCOM due to fluctuations in the transmission signal TX.

[0103] Furthermore, in this embodiment, the timing adjustment circuit 113 adjusts the frequency of the horizontal synchronization signal HSYNC to a frequency different from the frequency of a multiple of the frequency of the transmission signal TX, thereby outputting the horizontal synchronization signal HSYNC at the timing when the potential of the transmission signal TX rises or falls.

[0104] With this configuration, the display device 10B can reduce noise in the image displayed by the display device 10B caused by fluctuations in the common potential VCOM due to fluctuations in the transmitted signal TX, simply by adding a timing adjustment circuit 113 that adjusts the frequency of the horizontal synchronization signal HSYNC.

[0105] Furthermore, in this embodiment, the timing adjustment circuit 113 adjusts the phase of the horizontal synchronization signal HSYNC so that it outputs the horizontal synchronization signal HSYNC at the timing when the potential of the transmission signal TX rises or falls.

[0106] With this configuration, the display device 10B can reduce noise in the image displayed by the display device 10B caused by fluctuations in the common potential VCOM due to fluctuations in the transmitted signal TX, simply by adding a timing adjustment circuit 113 that adjusts the phase of the horizontal synchronization signal HSYNC.

[0107] ---Third Embodiment--- Next, a third embodiment will be described.

[0108] In the third embodiment, the method of controlling the output circuit 1311 by the control circuit 130 in the sensor control board 131 differs from that of the first embodiment. However, other aspects are the same as the display system 1A in the first embodiment, so the explanation of the similar parts will be omitted.

[0109] Figure 10 is an example of a timing chart showing the state transitions of the horizontal synchronization signal HSYNC and the transmission signal TX in the display device 10 according to the third embodiment.

[0110] At time t101, the control circuit 130 of the sensor control unit 13 starts the scan process. At time t101, the control circuit 130 first starts the burst period, switches the connection destination of the switching circuit 132 to the phase adjustment circuit 1312, and transmits the transmission signal TX from the output circuit 1311 to the position detector 14 via the phase adjustment circuit 1312 and the switching circuit 132.

[0111] Between times t110 and t112, the control circuit 110 of the display control unit 11A alternates the horizontal synchronization signal HSYNC. Also, during the burst period between times t110 and t112, the output circuit 1311 continues to output a clock to the phase adjustment circuit 1312 in accordance with the control of the control circuit 130, so as to synchronize with the horizontal synchronization signal HSYNC.

[0112] The period from time t102 to time t103 is the data period, data. The period from time t103 to time t104 is the coordinate period, coord. The processing performed during the data period data and the coordinate period coord is the same as in the first embodiment, so its explanation is omitted.

[0113] <Effects> In the third embodiment described above, the sensor control board 131 is a display device 10 comprising a display unit 12 in which a plurality of image elements 1210 are arranged in a grid, with a common potential VCOM input to one end and an individual potential (any of the potentials of source signals VS1 to VSm) input to the other end, and a position detector 14 arranged above or below the display unit 12 to detect the position indicated on the display unit 12, and outputs a transmission signal TX to the position detector 14. Furthermore, the sensor control board 131 comprises a clock generation circuit 1310 that generates a clock, and an output circuit 1311 that either outputs the clock generated by the clock generation circuit 1310 to the position detector 14 or stops the output of the clock to the position detector 14. Furthermore, in the sensor control board 131, the output circuit 1311 alternates the clock at a timing synchronized with the horizontal synchronization signal HSYNC generated in the display device 10 or input to the display device from an external source, and outputs the clock to the position detector 14 during the first period and the second period in a plurality of third periods (scan period) which consist of a first period (burst period) and a plurality of second periods (data period and coordinate period) which are after the first period and shorter than the first period.

[0114] In this configuration, the sensor control board 131 synchronizes the transmission signal TX with the horizontal synchronization signal HSYNC not only during the data period and coordinate period, but also during the burst period. This ensures that the fluctuations in the common potential VCOM associated with fluctuations in the transmission signal TX during the burst period are consistent for each scan period. Therefore, the sensor control board 131 can reduce image flicker noise (flickering) that occurs in the image displayed by the display device 10 because the fluctuations in the common potential VCOM during the burst period differ for each scan period.

[0115] ---Revised Version--- It should be noted that the present invention is not limited to the embodiments described above. That is, any design modifications made to the above embodiments by those skilled in the art are also included within the scope of the present invention, as long as they retain the features of the present invention. Furthermore, the elements of the above embodiments and the modifications described later can be combined to the extent that it is technically possible, and any combination thereof is also included within the scope of the present invention, as long as it retains the features of the present invention.

[0116] For example, in the above embodiment, the control circuit 130 performs scan processing three times within one cycle of the vertical synchronization signal VSYNC, but is not limited to this, and may perform any number of scan processing times.

[0117] With this configuration, the sensor control board 131 can reduce noise in the image displayed by the display device 10A, regardless of how many times it performs scan processing within one cycle of the vertical synchronization signal VSYNC.

[0118] Furthermore, in the above embodiment, the position detector 14 is provided on the display device 10A separately from the display control unit 11A, but it is not limited to this. For example, the signal wiring of part or all of the sensor coil of the position detector 14 may be shared with the signal wiring of the display control unit 11A.

[0119] With this configuration, the display device 10A can save space and reduce noise contained in the image displayed by the display device 10A. [Explanation of Symbols]

[0120] 10A…Display device, 12…Display unit, 14…Position detector, 131…Sensor control board, 1210…Image element, 1310…Clock generation circuit, 1312…Phase adjustment circuit, TX…Transmit signal, VCOM…Common potential

Claims

1. A display device comprising: a display unit in which a plurality of image elements, each having a common potential input at one end and individual potential inputs at the other end, are arranged in a grid pattern; and an electromagnetic induction type position detector arranged above or below the display unit and provided in a planar manner, which transmits a transmission signal from a plurality of sensor coils to a position indicator having a resonant circuit, and detects the position indicated on the display unit by the position indicator by receiving the resonant signal transmitted from the position indicator with the sensor coil, wherein the display device comprises a sensor control board that outputs the transmission signal to the position detector, A clock generation circuit that generates a clock having the resonant frequency of the aforementioned resonant circuit, A phase adjustment circuit adjusts the phase of the clock so that it is inverted at predetermined timing intervals, and outputs the adjusted clock as the transmission signal to the position detector. A sensor control board equipped with this feature.

2. The clock generation circuit further comprises an output circuit that outputs the clock generated by the clock generation circuit to the phase adjustment circuit or stops the output of the clock to the phase adjustment circuit. The clock generation circuit is connected to the phase adjustment circuit via the output circuit. The predetermined timing is the timing at which the output circuit outputs the clock to the phase adjustment circuit. The sensor control board according to claim 1.

3. The frequency of the clock is higher than the frequency of the horizontal synchronization signal generated in the display device or input to the display device from an external source. The sensor control board according to claim 1.

4. A display unit in which multiple image elements are arranged in a grid pattern, with a common potential input at one end and individual potentials input at the other end. An electromagnetic induction type position detector that detects the position indicated on the display unit by the position indicator by a plurality of sensor coils arranged in a planar manner on the upper or lower layer of the display unit, transmits a transmission signal from a position indicator having a resonant circuit to a position indicator, and receives the resonant signal transmitted from the position indicator with the sensor coil, thereby detecting the position indicated on the display unit by the position indicator. A sensor control board having a clock generation circuit that generates a clock having the resonant frequency of the resonant circuit, and a phase adjustment circuit that adjusts the phase so as to invert with respect to the clock at predetermined timing intervals, and outputs the adjusted clock as the transmission signal to the position detector, A display device equipped with the following features.

5. A timing adjustment circuit receives a horizontal synchronization signal that is generated internally or input externally, and outputs the horizontal synchronization signal at the timing when the potential of the transmission signal rises or falls. A driver circuit that drives the multiple image elements row by row in sequence according to the timing of the horizontal synchronization signal output by the timing adjustment circuit, The display device according to claim 4, further comprising:

6. The timing adjustment circuit adjusts the phase of the horizontal synchronization signal so that it outputs the horizontal synchronization signal at the timing when the potential of the transmission signal rises or falls. The display device according to claim 5.

7. A control method for a display device comprising: a display unit in which a plurality of image elements, each having a common potential input at one end and individual potential inputs at the other end, are arranged in a grid pattern; and an electromagnetic induction type position detector that transmits a transmission signal from a plurality of sensor coils arranged in a planar manner above or below the display unit to a position indicator having a resonant circuit, and detects the position indicated on the display unit by the position indicator by receiving the resonant signal transmitted from the position indicator with the sensor coil, the control method for a display device comprising: a display unit in which a plurality of image elements are arranged in a grid pattern, each having a common potential input at one end and an individual potential input at the other end; and an electromagnetic induction type position detector that transmits a transmission signal from a plurality of sensor coils arranged in a planar manner above or below the display unit to a position indicator. To generate a clock having the resonant frequency of the aforementioned resonant circuit, To make the aforementioned clock alternate or to stop the alternation of the aforementioned clock, The phase of the aforementioned clock is adjusted so that it is inverted at predetermined timing intervals, The phase-adjusted clock is used as the transmission signal, and the transmission signal is transmitted to the position detector. A method for controlling a display device, including the device itself.

8. A display device comprising: a display unit in which a plurality of image elements, each having a common potential input at one end and individual potential inputs at the other end, are arranged in a grid; and a position detector disposed above or below the display unit for detecting a position indicated on the display unit, wherein a sensor control board outputs a transmission signal to the position detector, A clock generation circuit that generates a clock, An output circuit that outputs the clock generated by the clock generation circuit or stops the output of the clock, A phase adjustment circuit that adjusts the phase of the clock output from the output circuit so that it is inverted at predetermined timing intervals, and outputs the adjusted clock as the transmission signal to the position detector, Equipped with, The output circuit outputs the clock during the first period and the second period in a plurality of third periods, which consist of a first period and a plurality of second periods that are after the first period and shorter than the first period. The predetermined timing is the timing at which the third period begins. Sensor control board.

9. A display device comprising: a display unit in which a plurality of image elements, each having a common potential input at one end and individual potential inputs at the other end, are arranged in a grid pattern; and a position detector disposed above or below the display unit for detecting a position indicated on the display unit, wherein a sensor control board outputs a transmission signal to the position detector, A clock generation circuit that generates a clock, A phase adjustment circuit adjusts the phase of the clock so that it is inverted at predetermined timing intervals, and outputs the adjusted clock as the transmission signal to the position detector. Equipped with, The predetermined timing is a timing synchronized with a vertical synchronization signal generated in the display device or input to the display device from an external source. Sensor control board.

10. A display device comprising: a display unit in which a plurality of image elements, each having a common potential input at one end and individual potential inputs at the other end, are arranged in a grid pattern; and a position detector disposed above or below the display unit for detecting a position indicated on the display unit, wherein a sensor control board outputs a transmission signal to the position detector, A clock generation circuit that generates a clock, An output circuit that outputs the clock generated by the clock generation circuit or stops the output of the clock, A phase adjustment circuit adjusts the phase of the clock so that it is inverted at predetermined timing intervals, and outputs the adjusted clock as the transmission signal to the position detector. Equipped with, The output circuit alters the clock at a timing synchronized with the horizontal synchronization signal generated in the display device or input to the display device from an external source. The output circuit outputs the clock during the first period and the second period in a plurality of third periods, which consist of a first period and a plurality of second periods that are after the first period and shorter than the first period. Sensor control board.

11. A display unit comprising a grid of multiple image elements, each having a common potential input at one end and individual potentials input at the other end, A position detector is positioned above or below the display unit and detects the position indicated on the display unit. A sensor control board having a clock generation circuit that generates a clock, and a phase adjustment circuit that adjusts the phase of the clock so as to invert at predetermined timing intervals, and outputs the adjusted clock as a transmission signal to the position detector, A timing adjustment circuit receives a horizontal synchronization signal that is either generated internally or input externally, and adjusts the frequency of the horizontal synchronization signal to a frequency different from a multiple of the frequency of the transmission signal, thereby outputting the horizontal synchronization signal at the timing when the potential of the transmission signal rises or falls. A driver circuit that drives the multiple image elements row by row in sequence according to the timing of the horizontal synchronization signal output by the timing adjustment circuit, A display device equipped with the following features.

Images