Electronic modules and electronic equipment

Abstract

To increase communication speed in an electronic module.SOLUTION: In an electronic module, a wiring board includes a plurality of wiring layers and a first to a fourth via groups. A first via connected to a first terminal of a first terminal group of a first semiconductor element and a second via connected to a second terminal of the first terminal group are arranged in a first direction. A third via connected to a third terminal of a second terminal group and a fourth via connected to a fourth terminal of the second terminal group and adjacent to the third via are arranged in a second direction intersecting the first direction. A virtual straight line connecting the first via and the second via passes between the third via and the fourth via. First wiring connecting the first via and a fifth via connected to a fifth terminal of a third terminal group of a second semiconductor element and second wiring connecting the second via and a sixth via connected to a sixth terminal of the third terminal group pass between the third via and the fourth via.SELECTED DRAWING: Figure 5A

Description

Technical Field

[0001] The present disclosure relates to an electronic module and an electronic device.

Background Art

[0002] Patent Document 1 discloses a memory system including a memory controller having a plurality of transmission terminals, a memory element having a plurality of terminals, and a printed wiring board on which the memory controller and the memory element are mounted. The transmission terminal of the memory controller and the reception terminal of the memory element are electrically connected by bus wiring provided on the printed wiring board. The memory controller controls the memory element by transmitting a control signal of a command signal and an address signal to the memory element via the bus wiring. Further, the memory controller and the memory element have data terminals for transmitting and receiving data signals. The data terminal of the memory controller is electrically connected to the data terminal of the memory element and the data signal line of the printed wiring board.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to process a large amount of data at high speed, an increase in the communication speed in an electronic module is required. For example, a memory interface, which is an example of an electronic module, operates in synchronization with a clock signal. When the frequency of the clock signal increases due to the increase in speed, the period of the clock signal becomes shorter. Further, the control signal operates in synchronization with the clock signal. Therefore, in order to realize an increase in the communication speed, it is required to reduce the variation in the time when the control signal is received by the memory element. Therefore, this disclosure aims to provide electronic modules and electronic devices that can achieve high communication speeds. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, an electronic module comprising a wiring board and a first semiconductor element and a second semiconductor element mounted on one main surface of the wiring board, wherein the first semiconductor element includes a first terminal group and a second terminal group, the second semiconductor element includes a third terminal group and a fourth terminal group, the wiring board includes a plurality of wiring layers, a first via group having a plurality of through vias connected to a plurality of terminals of the first terminal group, a second via group having a plurality of through vias connected to a plurality of terminals of the second terminal group, a third via group having a plurality of through vias connected to a plurality of terminals of the third terminal group, and a fourth via group having a plurality of through vias connected to a plurality of terminals of the fourth terminal group, the first terminal group of the first semiconductor element being connected to the third terminal group of the second semiconductor element via the first via group and the third via group, and the second terminal group of the first semiconductor element being connected to the second via group and the fourth via group An electronic module is provided, characterized in that the following are connected to the fourth terminal group of a semiconductor element, the first via group having a first via connected to the first terminal of the first terminal group and a second via connected to the second terminal of the first terminal group, the second via group having a third via connected to the third terminal of the second terminal group and a fourth via connected to the fourth terminal of the second terminal group and adjacent to the third via, the third via group having a fifth via connected to the fifth terminal of the third terminal group and a sixth via connected to the sixth terminal of the third terminal group, the first via and the second via are arranged in a first direction, the third via and the fourth via are arranged in a second direction intersecting the first direction, a virtual straight line connecting the first via and the second via passes between the third via and the fourth via, a first wiring connecting the first via and the fifth via and a second wiring connecting the second via and the sixth via pass through between the third via and the fourth via. [Effects of the Invention]

[0006] According to this disclosure, it is possible to achieve higher communication speeds in electronic modules. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing an example of an electronic device according to one embodiment. [Figure 2] This is an explanatory diagram schematically showing an example of the overall configuration of an electronic module according to one embodiment. [Figure 3] This is a cross-sectional view illustrating the structure of wiring layers and vias in an electronic module according to one embodiment. [Figure 4] This is a plan view showing the terminal arrangement structure of a memory element according to one embodiment. [Figure 5A] This is a schematic wiring diagram showing the positional relationship and connection structure between control terminals and vias in the wiring layer of a printed circuit board according to one embodiment. [Figure 5B] This is a schematic wiring diagram showing the connection structure between command / address signal lines and vias in the wiring layer of a printed circuit board according to one embodiment. [Figure 5C] This is a schematic wiring diagram showing the connection structure between command / address signal lines and vias in the wiring layer of a printed circuit board according to one embodiment. [Figure 6A] This is a schematic wiring diagram showing the positional relationship and connection structure between control terminals and vias in the wiring layer of a printed circuit board according to one embodiment. [Figure 6B] This is a schematic wiring diagram showing the connection structure between command / address signal lines and vias in the wiring layer of a printed circuit board according to one embodiment. [Figure 6C] This is a schematic wiring diagram showing the connection structure between command / address signal lines and vias in the wiring layer of a printed circuit board according to one embodiment. [Figure 7] This is a schematic plan view showing the command / address signal lines related to Example 1. [Figure 8A]It is a wiring diagram schematically showing the positional relationship and connection structure between the control terminal and the via in the wiring layer of the printed wiring board according to Example 1. [Figure 8B] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to Example 1. [Figure 8C] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to Example 1. [Figure 9] It is a diagram showing the simulation waveform of Example 1. [Figure 10] It is a plan view schematically showing the command / address signal line according to Example 2. [Figure 11A] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to Example 2. [Figure 11B] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to Example 2. [Figure 11C] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to Example 2. [Figure 12A] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to the reference example. [Figure 12B] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to the reference example. [Figure 12C] It is a wiring diagram schematically showing the connection structure between the command / address signal line and the via in the wiring layer of the printed wiring board according to the reference example. [Figure 13] It is a diagram showing the simulation waveform of the reference example.

Modes for Carrying Out the Invention

[0008] Hereinafter, embodiments for implementing the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to the following embodiments, and can be appropriately modified without departing from the gist thereof. Further, in the drawings described below, those having the same function are denoted by the same reference numerals, and the description thereof may be omitted or simplified. For those having the same or similar functions but different configurations, they will be described with different reference numerals under the same name, and they can also be distinguished by appropriately attaching ordinal numbers such as first and second.

[0009] [One Embodiment] An electronic module according to an embodiment of the present disclosure and an electronic device using the electronic module will be described with reference to FIGS. 1 to 6C.

[0010] Figure 1 is a perspective view showing an example of an electronic device 100 according to this embodiment. The electronic device 100 is not particularly limited, but can be digital devices such as imaging devices, display devices, office equipment, printing devices, industrial equipment, or medical equipment. The electronic device 100 may include an imaging device 101 that handles information such as images. The electronic device 100 may also include a circuit device that handles image data corresponding to an image. The imaging device 101 is, for example, an image acquisition device or an image forming device. The image acquisition device is, for example, an imaging device using a sensor, a drawing device based on user input, or an image generation device using artificial intelligence. The image forming device is, for example, a display device or a printing device. The circuit device can be at least one of a storage device, a communication device, a control device, an input / output device, or an arithmetic device (processing device). For example, the circuit device can output image data based on an image signal obtained by the image acquisition device. The image forming device forms an image based on the image data output by the circuit device. In a camera, the circuit device outputs image data based on an image signal obtained by an imaging device such as a CMOS image sensor, and a display device such as a liquid crystal display or an organic EL display displays (forms) an image based on the image data output by the circuit device. In a photocopier, a circuit unit outputs image data based on an image signal obtained by an imaging device such as a scanner, and an electrophotographic or inkjet printing device prints (forms) the image based on the image data output by the circuit unit. This is not limited to photocopiers; single-function scanners and single-function printers can also be equipped with circuit units and imaging devices.

[0011] In the example shown in Figure 1, the electronic device 100 is an X-ray flat panel detector that can be used as a medical device. As shown in Figure 1, the electronic device 100 comprises an imaging device 101, an electronic module 200, and a housing 102. The circuitry of the electronic device 100 includes this electronic module 200. The electronic module 200 is located on the back of the imaging device 101 and is arranged inside the housing 102 together with the imaging device 101. In an X-ray flat panel detector, the imaging device 101 is an imaging device that outputs image data corresponding to electromagnetic waves such as X-rays incident on the imaging device 101. The imaging device 101 includes a scintillator (not shown), a photodiode, a thin-film transistor array, an analog-to-digital converter, a low-noise amplifier, etc.

[0012] The electronic module 200 is a printed circuit board. The electronic module 200 is connected to the image device 101 in a controllable manner. The image device 101 is a separate electronic module from the electronic module 200. Image data output by the image device 101 is input to the electronic module 200. The electronic module 200 stores the input image data. The electronic module 200 performs image processing on the input image data. Furthermore, the electronic module 200 transmits the image data to other electronic modules via an interface such as LAN (Local Area Network) or USB (Universal Serial Bus). Thus, the electronic module 200 is a circuit device that can function as a control device, a storage device, a processing device, an input / output device, and a communication device. The electronic module 200, as the first electronic module, is connected to the second electronic module.

[0013] Figure 2 is a schematic diagram illustrating an example of the overall configuration of the electronic module 200 according to this embodiment. As shown in Figure 2, the electronic module 200 includes a memory element 611, which is an example of a first semiconductor element; a memory element 612, which is an example of a second semiconductor element; and a memory controller 610, which is an example of a third semiconductor element. The memory controller 610 performs data input and output with the memory elements 611 and 612. The electronic module 200 also includes a connector 301, a connector 302, a connector 303, a conversion chip 201, a resistor 613, and a printed circuit board 500. The memory elements 611, 612, 610, 301, 302, 303, 201, and 613 are mounted on one main surface of the printed circuit board 500. The printed circuit board 500 is, for example, a rigid substrate. The printed circuit board 500 has wiring 401, wiring 402, wiring 403, wiring 404, command / address signal line 710, data signal line 791, and data signal line 792.

[0014] Memory elements 611 and 612 are of the same type. Memory elements 611 and 612 are, for example, DDR (Double Data Rate) 4 memory. However, memory elements 611 and 612 are not limited to DDR4 memory, and may be of other standards or other types of memory.

[0015] The image device 101 is connected to connectors 302 and 303, respectively, via wiring components such as cables and flexible circuit boards (not shown). Image data is input from the image device 101 to connectors 302 and 303 via the respective cables. Connectors 302 and 303 are also electrically connected to the memory controller 610 via wirings 401 and 402 on the printed circuit board 500. The image data input to connectors 302 and 303 is output to the memory controller 610 via wirings 401 and 402, respectively.

[0016] The memory controller 610 stores image data in memory elements 611 and 612. The memory controller 610 also reads the image data stored in memory elements 611 and 612. The memory controller 610 is electrically connected to the conversion chip 201 via wiring 403 on the printed circuit board 500. The memory controller 610 outputs the processed image data to the conversion chip 201 via wiring 403.

[0017] The conversion chip 201 is electrically connected to the connector 301 via wiring 404 on the printed circuit board 500. A cable 304 (wiring component) is connected to the connector 301. The conversion chip 201 converts the image data transmitted from the memory controller 610 into a format specified in the communication standard. Furthermore, the conversion chip 201 outputs the converted image data to the cable 304 via wiring 404 and the connector 301. The cable 304 is a wiring component that connects electronic modules to each other, and is connected, for example, to a computer for image display. The computer for image display is also an electronic module. The image data is input to the computer via cable 304 and undergoes processing such as display processing on a display and storage processing in a memory device.

[0018] Each of the memory controller 610, memory element 611, and memory element 612 is configured as a single semiconductor package. Each of the memory elements 611 and 612 is electrically connected to the memory controller 610 via data signal lines 791 and 792 of the printed circuit board 500. Data signal lines 791 and 792 are bus connections consisting of multiple wires. This establishes a transmission path for image data (data signals) between the memory element 611 and the memory controller 610, and between the memory element 612 and the memory controller 610.

[0019] Furthermore, the memory controller 610, memory element 611, and memory element 612 are electrically connected by a command / address signal line 710 on the printed circuit board 500. The command / address signal line 710 is a bus wiring consisting of multiple signal lines. This establishes a transmission path for command signals and address signals between the memory controller 610, memory element 611, and memory element 612.

[0020] The memory controller 610 transmits command signals and address signals to memory elements 611 and 612 via the command / address signal line 710 using a parallel transmission method. The command signals and address signals, which are parallel signals transmitted from the memory controller 610, are received by the two memory elements 611 and 612 via the command / address signal line 710. The memory controller 610 controls memory elements 611 and 612 by transmitting control signals, command signals, and address signals to memory elements 611 and 612 via the command / address signal line 710. Each of memory elements 611 and 612 performs processing such as storing and erasing image data according to the command signals and address signals from the memory controller 610.

[0021] As described above, the memory system is configured by the memory controller 610, memory element 611, memory element 612, and printed circuit board 500. The memory system is configured as a printed circuit board.

[0022] Figure 3 is a cross-sectional view showing an electronic module 200 according to this embodiment. The printed circuit board 500 has an insulating substrate and conductive conductors that constitute the wiring. The material of the substrate is, for example, glass epoxy resin. The material of the conductors is, for example, copper. The printed circuit board 500 is equipped with a memory controller 610, a memory element 611, and a memory element 612. Note that components other than the memory controller 610, memory element 611, and memory element 612 may also be mounted on the printed circuit board 500.

[0023] The printed circuit board 500 is a laminated substrate having multiple wiring layers. The printed circuit board 500 shown in Figure 3 has, for example, 10 wiring layers 501 to 510. The wiring layers 501 to 510 are stacked in a direction perpendicular to the main surface of the printed circuit board 500 (Z direction in the figure). A base material (i.e., an insulating layer) not shown is provided between the wiring layers 501 to 510. In the Z direction, the wiring layers 501 to 510 are arranged in the order of wiring layer 501, wiring layer 502, wiring layer 503 (first wiring layer), wiring layer 504, wiring layer 505, wiring layer 506, wiring layer 507, wiring layer 508, wiring layer 508 (second wiring layer), and wiring layer 510. Wiring layers 501 and 510 have the main surface of the printed circuit board 500. In other words, wiring layers 501 and 510 are surface layers that are mounting surfaces on which the memory controller 610, memory elements 611, memory elements 612, etc., can be mounted. Wiring layers 502 to 509, located between wiring layers 501 and 510, are inner layers. A protective film, such as solder resist (not shown), may be placed on the surfaces of wiring layers 501 and 510.

[0024] Each of the wiring layers 501 to 510 has a conductor pattern 570 formed on it, which is a conductor film that constitutes the wiring. In addition, through vias 560, 561, and 562 that constitute the wiring are arranged to span across the wiring layers 501 to 510. Vias 560, 561, and 562 are conductors formed in the through holes of the wiring layers.

[0025] Note that Figure 3 is not an accurate representation of the data signal line 711, data signal line 712, and command / address signal line 710 shown in Figure 2, but rather a schematic representation of the cross-section of the printed circuit board 500 to explain the wiring layers 501-510.

[0026] The memory controller 610, memory elements 611 and 612 are mounted on one of the main surfaces, the wiring layer 501. Components such as capacitors and resistors (not shown) are mounted on wiring layers 501 and 510. A conductor pattern mainly serving as ground is formed on wiring layer 502, which is adjacent to wiring layer 501 via an insulating layer. The same applies to wiring layer 505, which is adjacent to wiring layer 506 via an insulating layer. Conductor patterns mainly serving as part of the wiring, such as data signal lines 711, data signal lines 712 and command / address signal lines 710, are formed on wiring layers 503 and 504.

[0027] The memory controller 610, memory element 611, and memory element 612 are joined to the printed circuit board 500 by solder 103. Each of the memory controller 610, memory element 611, and memory element 612 has multiple signal terminals, multiple power terminals, and multiple ground terminals. Of the multiple signal terminals, some (for example, 16) are data terminals. Each terminal of the memory controller 610, memory element 611, and memory element 612 has a ball grid array structure in which the terminals are arranged in a matrix.

[0028] Figure 4 is a plan view showing the terminal arrangement structure of memory elements 611 and 612. In Figure 4, memory elements 611 and 612 are shown as viewed from the side opposite to the side where the terminals are arranged. In Figure 4, each terminal is shown with a dashed line.

[0029] Memory elements 611 and 612 are DDR4-SDRAM. As shown in Figure 4, each of memory elements 611 and 612 has terminals in the 1st to 3rd columns and the 7th to 9th columns of a 16x9 partitioned area. There are no terminals in the 4th to 6th columns. The total number of terminals is 96.

[0030] In Figure 4, among the multiple terminals, the terminals indicated by diagonal lines are the command / address terminals CKE, CS, ODT, A0~A16, BA0, BA1, BG0, ACT, PAR, and TEN. The command / address terminals are control terminals for the memory elements and are located in rows 10 to 16 and columns 2 to 9. The terminals indicated by the mesh are the data terminals DQU0~DQU7, data mask terminal DMU_n, data strobe terminals DQSU_c, DQSU_t, data terminals DQL0~DQL7, data mask terminal DML_n, data strobe terminals DQSL_c, and DQSL_t. The data terminals, data mask terminals, and data strobe terminals are located in rows 1 to 9 and columns 2 to 8. The clock terminals CK_t and CK_c are located in the 7th and 8th columns of row 10. Other terminals include the ALERT terminal, RESET terminal, power terminal, and ground terminal, which are not shown in the diagram.

[0031] Generally, memory elements 611 and 612 are arranged so that their respective data terminals face the memory controller 610. The data terminals of memory elements 611 and 612 and the data terminals of the memory controller 610 are electrically connected to each other via data signal lines 711 and 712.

[0032] In each of the memory elements 611 and 612, the command / address terminal is located on the side furthest from the memory controller 610. The command / address signal line 710 has a fly-by wiring structure consisting of multiple wires that function as multiple signal lines. The command / address terminals of each of the memory elements 611 and 612 are electrically connected to the command / address terminal of the memory controller 610 via the command / address signal line 710. One end of the command / address signal line 710 is connected to a resistor 613. The resistor 613 is a termination element and is a chip resistor pulled up to the termination voltage. As shown in Figure 2, the command / address signal line 710 may be connected to the memory elements 611 and 612 by wiring bent in a roughly L-shape.

[0033] The configuration of the memory interface when wiring is connected to the command / address terminals of memory elements 611 and 612 will be explained below with reference to Figure 4. When using memory elements with a data width of 16 bits in 8Gb addressing of DDR4 memory, one clock enable signal (CKE) line, one chip select signal (CS) line, and one on-die termination signal (ODT) line are used. In addition, one bank group signal (BG) line, two bank address signal (BA) lines, and 17 address signal (A) lines are used. Furthermore, one active command signal (ACT) line, one parity signal (PAR) line, and one test enable signal (TEN) line are used. Therefore, a total of 26 signal lines are used.

[0034] The memory interface operates in synchronization with the clock signal. As the frequency of the clock signal increases, the period of the clock signal shortens. To achieve high-speed communication in the memory interface, it is effective to reduce the variation in the time it takes for the command / address signals output from the memory controller 610 to reach memory elements 611 and 612. For example, the period of the command / address signal in the DDR3-800 memory interface is 2500 picoseconds. If the allowable variation in arrival time is 10% of the period, that allowable value is 250 picoseconds. If the wiring delay time for a 1mm trace is 7 picoseconds, then a variation in arrival time between command / address signal lines of approximately 35.7mm is acceptable. On the other hand, when using the faster DDR4-2400 memory interface, the period of the address signal is 375 picoseconds. If the allowable variation in arrival time is 10% of the period, that allowable value is 37.5 picoseconds. In this case, the allowable variation in length between command / address signal lines is approximately 5.4 mm. As speed increases, it becomes necessary to further suppress variations in wiring length between the multiple wires that make up the command / address signal lines.

[0035] One method for aligning the lengths of command / address signal lines is meander wiring. Meander wiring is a wiring structure that adjusts the length of the wiring by making it meander. When attempting to align the lengths of wiring using meander wiring, it is necessary to adjust the length of the command / address signal bus wiring to match the longest signal line. As a result, the wiring becomes longer overall. Consequently, as communication speeds in memory interfaces increase, the effect of frequency loss of electrical signals due to wiring becomes negligible. Frequency loss increases the amplitude voltage drop and the rise and fall times of the signal waveform, reducing the voltage noise margin and timing margin. Therefore, longer wiring hinders the speed increase of memory interfaces. To achieve higher communication speeds in memory interfaces, it is necessary to reduce the frequency loss of electrical signals due to wiring, in other words, to shorten the wiring.

[0036] Thus, in order to increase the communication speed in the memory interface, variations in the length of the 26 wires connecting the control terminals of memory element 611 and memory element 612 must be suppressed, and the amount of wiring adjustment by meander wiring or the like must be reduced.

[0037] The wiring structure of the command / address signal line 710 in the electronic module according to this embodiment will be described in detail below. Figure 5A is a schematic wiring diagram showing the positional relationship and connection structure of control terminals and vias in the wiring layer 501 of the printed circuit board 500. The area 611r enclosed by the dashed line indicates the area in the wiring layer 501 where the memory element 611 is mounted. Of the area 611r, areas R1 and R2 are areas where the command / address control terminals are located. The memory element 611 includes two groups of terminals.

[0038] The first terminal group in region R1 includes multiple terminals located in columns 2 and 3 of rows 10 through 16. The second terminal group in region R2 includes multiple terminals located in columns 7 and 8 of rows 11 through 16 and column 8 of row 14. In an electronic module equipped with multiple memory elements, control terminals with the same function are connected by wiring. Therefore, command / address wiring is routed in the left-right direction (X direction in the figure) of region 611r where the memory elements are located in Figure 5A. The 14 command / address wires connected to the first terminal group cross region R2 where the second terminal group is located via vias in the layers inside wiring layer 501 (inner layers). Similarly, the 12 command / address wires connected to the second terminal group cross region R1 where the first terminal group is located in the inner layers.

[0039] In Figure 5A, vias are connected to each terminal of the first terminal group and the second terminal group, respectively. The printed circuit board 500 includes a first via group having multiple vias connected to multiple terminals of the first terminal group, and a second via group having multiple vias connected to multiple terminals of the second terminal group, in the region 611r on which the memory element 611 is mounted.

[0040] Specifically, via 562a (first via) of the first via group is connected to control terminal 611a (first terminal) of the first terminal group. via 562b (second via) of the first via group is connected to control terminal 611b (second terminal) of the first terminal group. Control terminals 611a and 611b are located in row M(12). via 562c (third via) of the second via group is connected to control terminal 611c (third terminal) of the second terminal group. Control terminal 611c is located in row L(11). via 562d (fourth via) of the second via group is connected to control terminal 611d (fourth terminal).

[0041] Control terminal 611d is located in row N(13). Via 562d is adjacent to via 562c in the Y direction. Vias 562a and 562b are arranged in the X direction (first direction). Vias 562c and 562d are arranged in the Y direction (second direction) intersecting the X direction. An imaginary line connecting via 562a and via 562b passes between via 562c and via 562d. Also, control terminals 611a (first terminal) and 611b (second terminal) are arranged in the X direction (fourth direction). Control terminals 611i (ninth terminal) and 611b (second terminal) are arranged in the Y direction (third direction).

[0042] Furthermore, in Figure 5A, the control terminal (A14 signal terminal) 611n is located in row L(11) and connected to via 562n by wiring. Via 562n is located in row V1a, spaced apart from row L(11). Similar structures are provided in multiple locations, as shown in Figure 5A. By arranging the vias in this way, in the first terminal group, the number of rows of vias is 5 rows from row V1a to row V1e, compared to the number of rows of control terminals, which are 7 rows from row K(10) to row T(16). In the first terminal group, the number of rows of vias is less than the number of rows of control terminals. The control terminals, arranged in 7 rows and 2 columns, are transformed into a matrix arrangement of 5 rows and 3 columns of vias.

[0043] Similarly, in the second terminal group, the control terminals are arranged in six rows from row L(11) to row T(16), while the vias are arranged in four rows from row V2a to row V2d. In the third terminal group as well, the number of via rows is less than the number of control terminal rows. The control terminals, arranged in a 6x2 grid, are transformed into a 4x3 via arrangement.

[0044] As shown in Figure 5A, rows V1a, V1b, V1c, V1d, and V1e, where vias connected to the first terminal group are located, are arranged alternately with rows V2a, V2b, V2c, and V2d, where vias connected to the second terminal group are located.

[0045] Figure 5B is a schematic wiring diagram showing the positional relationship between vias and wiring in the wiring layer 503 of the printed circuit board 500. Wiring S1 (first wiring) extending from via 562a is a command / address wiring connected to the via (fifth via) on the memory element 612 side, which will be described later. Wiring S2 (second wiring) extending from via 562b is a command / address wiring connected to the via (second via) on the memory element 612 side, which will be described later. The first signal (control signal) from the memory controller 610 is supplied to memory elements 611 and 612 via wiring S1. Similarly, the second signal (control signal) from the memory controller 610 is supplied to memory elements 611 and 612 via wiring S2.

[0046] Furthermore, in Figure 5B, four command / address wires are positioned between via 562m and via 562b. Wiring S3 connected to via 562c is not obstructed by vias 562m and 562b, and is therefore mostly linear. Linear wiring allows memory elements to be connected with short wires. To illustrate with wiring S3 as an example, it is wired in the X direction between row V1a and row V1b. The same applies to wiring S4 extending from via 562d.

[0047] Furthermore, since multiple vias are arranged regularly, the wiring can also be arranged regularly. For this reason, wirings of similar shapes can be used, for example, wirings S3, S4, S13, and S14. By using wirings of similar shapes, variations in the length between wirings between memory elements can be reduced. In Figure 5B, wiring S1 (first wiring) and wiring S2 (second wiring) extending from via 562b have slightly different shapes, but the difference in length between wiring S1 and wiring S2 is preferably within 10% or less of the length of the reference wiring (for example, wiring S1 or wiring S2), and more preferably within 5% or less. Within this range, the variation in the lengths of the two wirings can be considered small.

[0048] Figure 5C is a schematic wiring diagram showing the positional relationship of multiple vias in the wiring layer 508 of the printed circuit board 500. In row V1b, via 562i (the 9th via) is located between via 562a and via 562b. Via 562i is connected to the control terminal 611b (the 2nd terminal) of the first terminal group shown in Figure 5A. Wiring S5 (the 5th wiring) extending from via 562i is connected to the via (the 10th via) on the memory element 612 side, which will be described later. Wirings S1 and S2 described above are wirings formed on wiring layer 503, one of the multiple wiring layers. In contrast, wiring S5 is formed on a different wiring layer from wirings S1 and S2.

[0049] As shown in Figure 5C, multiple vias are placed between rows V1a and V1b. Two command / address wires are placed between via 562b and via 562m. Wiring S21 connected to via 562o is not obstructed by vias 562b and 562m, and therefore is mostly a straight wire. As a result, memory elements can be connected with short wires.

[0050] Furthermore, because the vias are arranged regularly, the wiring can also be arranged regularly. For example, wirings of similar shapes can be used, such as wirings S21, S22, S23, and S24. This reduces variations in wiring length between multiple wirings connecting memory elements 611 and 612.

[0051] Figure 6A is a schematic wiring diagram showing the positional relationship of control terminals, vias, and wiring in the wiring layer 501 of the printed circuit board 500. The area 612r enclosed by the dashed line indicates the area on the wiring layer 501 where the memory element 612 is mounted. Similar to the memory element 611, the memory element 612 includes two sets of terminals. Within area 612r, areas R3 and R4 are areas where command / address control terminals are located.

[0052] The third terminal group in region R3 includes multiple terminals located in columns 2 and 3 of rows 10 through 16. The fourth terminal group in region R4 includes multiple terminals located in columns 7 and 8 of rows 11 through 16 and column 8 of row 14. As in Figure 5A, the command / address wiring is routed in the left-right direction (X direction in the figure) of region 612r where the memory elements are located in Figure 6A. The 14 command / address wires connected to the third terminal group traverse region R4 where the fourth terminal group is located via vias in layers inside wiring layer 501. Similarly, the 12 command / address wires connected to the fourth terminal group traverse region R3 where the third terminal group is located via vias in layers inside wiring layer 501.

[0053] In Figure 6A, vias are connected to each control terminal of the third terminal group and the fourth terminal group, respectively. The printed circuit board 500 includes a third via group having multiple vias connected to multiple terminals of the third terminal group, and a fourth via group having multiple vias connected to multiple terminals of the fourth terminal group, in the region 612r on which the memory element 612 is mounted. The first terminal group of the memory element 611 shown in Figure 5A is connected to the third terminal group of the memory element 612 via the first via group and the third via group. Similarly, the second terminal group of the memory element 611 is connected to the fourth terminal group of the memory element 612 via the second via group and the fourth via group, respectively.

[0054] Specifically, via 562e (5th via) of the 3rd via group is connected to control terminal 612e (5th terminal) of the 3rd terminal group. via 562f (6th via) of the 3rd via group is connected to control terminal 612f (6th terminal) of the 3rd terminal group. via 562g (7th via) of the 4th via group is connected to control terminal 612g (7th terminal) of the 4th terminal group. via 562h (8th via) is connected to control terminal 612h (8th terminal). vias 562e and 562f are adjacent in the Y direction. vias 562e and 562f are arranged in the X direction. vias 562g and 562h are arranged in the Y direction, intersecting in the X direction. The imaginary line connecting vias 562e and 562f passes between vias 562g and 562h. In this embodiment, since the memory elements 611 and 612 are arranged side by side on the main surface of the printed circuit board 500, the virtual line connecting via 562e and via 562f and the virtual line connecting via 562a and via 562b mentioned above lie on the same virtual line.

[0055] Furthermore, in Figure 6A, the control terminal 612u is located in row L(11) and connected to via 562u by wiring. Via 562u is located in row V1a, spaced apart from row L(11) in the Y direction. Similar structures are provided in multiple locations. By arranging the vias in this way, in the third terminal group, the number of rows of vias is 5 rows from row V1a to row V1e, compared to the number of rows of control terminals, which are 7 rows from row K(10) to row T(16). In the third terminal group, the number of rows of vias is less than the number of rows of control terminals.

[0056] Similarly, in the fourth terminal group, the control terminals are arranged in six rows from row L(11) to row T(16), while the vias are arranged in four rows from row V2a to row V2d. In the fourth terminal group as well, the number of via rows is less than the number of control terminal rows.

[0057] As shown in Figure 6A, rows V1a, V1b, V1c, V1d, and V1e, where vias connected to the third terminal group are located, are arranged alternately with rows V2a, V2b, V2c, and V2d, where vias connected to the fourth terminal group are located.

[0058] Figure 6B is a schematic wiring diagram showing the positional relationship between vias and wiring in the wiring layer 503 of the printed circuit board 500. In Figure 6B, multiple vias are arranged between row V2a and row V2b. Therefore, four command / address wirings can be arranged between row V2a and row V2b. Wiring S1 (first wiring) is a command / address wiring that connects via 562e to via 562a (first via) shown in Figure 5A. Wiring S2 (second wiring) is a command / address wiring that connects via 562f to via 562b (second via) shown in Figure 5A. Wiring S3 (third wiring) is a command / address wiring that connects via 562g to via 562c (third via) shown in Figure 5A. Wiring S4 (fourth wiring) is a command / address wiring that connects via 562h to via 562d (fourth via) shown in Figure 5A. Wires S1 and S2 pass between wires S3 and S4. Wire S1 is generally straight because its path is not obstructed by vias 562g and 562h. The same applies to wire S2, which is connected to via 562f. The length of wire S1 is the length from via 562a (first via) to via 562e (fifth via), and the length of wire S2 is the length from via 562b (second via) to via 562f (sixth via). Similarly, the length of other wires is the length between the two vias they connect.

[0059] Furthermore, because multiple vias are arranged regularly, the wiring can also be arranged regularly. For this reason, wirings of similar shapes can be used, for example, wirings S3 and S4. By using wirings of similar shapes, variations in the length between wirings of memory elements can be reduced.

[0060] Figure 6C is a schematic wiring diagram showing the positional relationship of multiple vias in the wiring layer 508 of the printed circuit board 500. In row V1b, via 562j (the 10th via) is located between via 562e and via 562f. Via 562j is connected to control terminal 611j (the 10th terminal) of the third terminal group shown in Figure 6A. Via 562j is connected to via 562i (the 9th via) shown in Figure 5C by wiring S5 (the 5th wiring). Wiring S5 passes between via 562g and via 562h in the Y direction. Wiring S5 is not obstructed by vias 562g and 562h.

[0061] Furthermore, because the vias are arranged regularly, the wiring can also be arranged regularly. In addition, wiring of similar shapes can be used. By using wiring of similar shapes, variations in wiring length can be reduced between multiple wirings connecting memory element 611 and memory element 612.

[0062] As described above, the via arrangement according to this embodiment suppresses variations in wiring length between multiple wirings and reduces the need for wiring adjustments such as meander wiring. Furthermore, by suppressing variations in wiring length, it is possible to reduce variations in the arrival time of control signals received by the memory elements. As a result, it is possible to increase the communication speed in the memory interface.

[0063] In this embodiment, a memory element (storage element) was described as an example of a semiconductor element, but the semiconductor elements in the electronic module 200 according to this embodiment are not limited to memory elements. The semiconductor elements in the electronic module 200 may be sensor elements, display elements, control elements, power supply elements, communication elements, arithmetic elements, control elements, etc. The wiring board in the electronic module 200 may be a printed circuit board that includes a printed wiring board having a wiring structure similar to that of the printed wiring board 500.

[0064] [Examples] Next, with reference to Figures 7 to 13, a more specific configuration of the printed circuit board 500 according to this embodiment will be described using Example 1, Example 2, and a reference example. (Example 1) Figure 7 is a schematic plan view showing the command / address signal lines according to Embodiment 1. As shown in Figure 7, the memory controller 610 is arranged on the printed circuit board 500 with a gap between it and the memory elements 611 and 612 in the Y direction, which is perpendicular to the X and Z directions.

[0065] The command / address signal lines 710 have a fly-by wiring structure. Below, the connection structure of one of the 25 command / address signal lines 710 will be described. The command / address terminal 610a of the memory controller 610 and via 561 are connected by a data signal line 711 formed on the wiring layer 501, which is the surface layer of the printed circuit board 500. In this description, the data signal line 711 is described as an inner layer wiring, but it may also be described as a surface layer wiring. Via 561 and via 560 are connected to a data signal line 712 provided on the inner layer. Via 560 and via 562a, which is located close to the memory element 611, are connected by the data signal line 712, which is an inner layer wiring.

[0066] In Embodiment 1, the data signal line 712 is formed in the wiring layer 503. Via 562k and the control terminal 611k, which is the command / address terminal of the memory element 611, are connected by surface wiring 713. Via 562k and via 562s, which is positioned close to the memory element 612, are connected by inner layer wiring 714 formed in the inner layer wiring layer 508. Via 562s and the command / address terminal 612s of the memory element 612 are connected by surface wiring 715 formed in the surface layer wiring layer 501. Via 562s and via 562u are connected by wiring 716 formed in the inner layer wiring layer 503. Via 562u and resistor 613 are connected by wiring 717 formed on the surface. In this way, the wiring connecting the first memory element and the second memory element has a structure in which the wiring layer switches for each intervening via. Similarly, the wiring other than the command / address signal line 710 also has a structure in which the wiring layer switches for each via. For wiring layers connecting memories, it is preferable that they be inner layers close to the surface layer. In this embodiment, the inner wiring layers 502 and 509 are ground plane layers. The command / address wiring connecting memories is located in wiring layers 503 and 508, which are inside the ground plane layer.

[0067] Next, the structure of the command / address wiring connecting memory element 611 and memory element 612 will be explained with reference to Figures 8A to 8C. Figure 8A is a wiring structure diagram of wiring layer 501 viewed from the Z direction. Figure 8B is a wiring structure diagram of wiring layer 503. Figure 8C is a wiring structure diagram of wiring layer 508. The via arrangement in Figures 8A to 8C is the same as the via arrangement shown in Figures 5A to 6C. The command / address wiring connecting memory element 611 and memory element 612 can be routed in a straight line. Straight wiring allows memory elements to be connected with short wiring. Furthermore, because the vias are arranged regularly, the wiring can also be arranged regularly. For example, wirings S3, S4, S13, and S14 in Figure 8B have similar shapes. Similarly, wirings S21, S22, S23, and S24 in Figure 8C have similar shapes. By using wiring with similar shapes, the variation in length between wirings between memory elements can be reduced.

[0068] In Example 1, the center distance L between memory elements 611 and 612 is 13.6 mm. For the CKE signal wiring, CS signal wiring, ODT signal wiring, A14 signal wiring, A15 signal wiring, and A16 signal wiring, the lengths of the inner layer wiring between memory elements 611 and 612 are as shown in Table 1. The length excluding the 13.6 mm memory center distance is 0.3 mm to 0.7 mm. It can be seen that the memories can be connected with short wiring. The length variation is 0.4 mm, which shows that the variation in wiring length is suppressed. Because the command / address wiring is short, the signal driving capability of the memory controller can be reduced. The variation in wiring length between multiple wirings is preferably 10% or less of the length of the reference wiring, and more preferably 5% or less. [Table 1]

[0069] Figure 9 shows the waveform simulation results of the command / address signal in Example 1. In Figures 9(a) to (c), the data transfer rate was changed to the equivalent of 2400 Mbps, 4800 Mbps, and 6400 Mbps, and the waveform degradation was compared. Here, the amount of delay time variation (jitter) was observed under voltage conditions where the rising and falling edges of the waveform intersect. In Figures 9(a) to (c), no significant increase in the amount of delay time variation was observed. That is, it was confirmed that the command / address wiring in Example 1 is suitable for increasing the communication speed in the memory interface.

[0070] As described above, the via arrangement shown in Example 1 suppresses variations in wiring length and reduces the need for wiring adjustments such as meander wiring, thereby enabling faster communication speeds in the memory interface.

[0071] (Example 2) Figure 10 is a schematic plan view showing the command / address signal lines according to Embodiment 2. Here, a part of the memory controller 610 and parts of the memory elements 611 and 612 are shown when the electronic module 200 is viewed from above, i.e., in the Z direction. Figures 11A to 11C are schematic wiring diagrams showing the connection structure between the command / address signal lines and vias in the wiring layer of the printed circuit board according to Embodiment 2. As shown in Figure 10, the memory controller 610 is arranged on the printed circuit board 500 with spacing in the Y direction for the four memory elements (memory element 611-1, memory element 612-1, memory element 611-2, and memory element 612-2).

[0072] Because the vias are arranged regularly, the wiring can also be arranged regularly. For example, wiring of similar shape can be used, as shown in Figure 11B with the four wires S11a, S12a, S13a, and S14a. Wiring of similar shape can be used in the X direction, as shown in wires S11b, S12b, S13b, and S14b. Similarly, wiring of similar shape can be used in the Y direction, as shown in the wires S21a to S24a in Figure 11C, and wiring of similar shape can be used in the X direction, as shown in wires S21b to S24b.

[0073] As described above, with the via arrangement shown in Example 2, similar wiring can be used in the X and Y directions. Even when the number of memory elements is increased, variations in wiring length can be suppressed, and wiring adjustments using meander wiring, etc., can be reduced, thereby increasing the communication speed in the memory interface.

[0074] (Reference example) Figures 12A to 12C are schematic wiring diagrams showing the connection structure between command / address signal lines and vias in the wiring layer of a printed circuit board according to a reference example. Here, a portion of areas 611x and 612x, where two memory elements are mounted, is schematically shown. To shorten the stub wiring, vias are arranged so that the wiring between control terminals and vias is short. For example, via 562bx is placed close to the control terminal (ODT signal terminal) 611bx and connected by wiring. In this arrangement, since vias are placed at the same interval as the control terminal spacing in the Y direction, vias are placed consecutively between control terminals. In area R1, seven vias are placed consecutively in the Y direction. If one wire is placed between vias, the number of wires that can cross area R1 will be eight or nine, which is insufficient for the 26 command / address wires. Therefore, the number of wiring layers must be increased, or the wiring in the Y direction must be routed outside the areas 611x and 612x where the memory is located. Because the wiring becomes longer due to the detour, the length of the wiring that is not detouring must be adjusted using meander wiring or similar methods so that it is approximately the same length as the length increased by the detour.

[0075] In the reference example, the distance L between the centers of regions 611x and 612x where memory elements are located is 13.6 mm, which is the same distance as in Example 1. For the CKE signal wiring, CS signal wiring, ODT signal wiring, and A14, A15, and A16 signal wiring, the lengths of the inner layer wiring in regions 611x and 612x are as shown in Table 2. The lengths excluding the memory center spacing of 13.6 mm range from 1.3 mm to 5.3 mm. The wiring becomes longer due to the detours. The variation in length was 4.0 mm, which was found to be greater than in Example 1. [Table 2]

[0076] Due to the length of the command / address wiring, the signal driving capability of the memory controller must be increased. Figure 13 shows the waveform simulation results of the command / address signal for a reference example. Figures 13(a) to (c) show the waveform simulation results when the data transfer rate is changed to the equivalent of 2400Mbps, 4800Mbps, and 6400Mbps, respectively, and the degradation of the waveform is compared. Here, the amount of delay time variation (jitter) was observed under voltage conditions where the rising and falling edges of the waveform intersect. In Figures 13(a) to (c), unlike the embodiment described above, an increase in the amount of delay time variation was observed.

[0077] As described above, according to Embodiments 1 and 2 of this disclosure, unlike the reference example, variations in wiring length are suppressed and the wiring can be shortened, thereby enabling faster communication speeds in the memory interface.

[0078] [Modified Embodiment] This disclosure is not limited to the embodiments described above, and many modifications are possible within the technical concept of this disclosure. For example, examples in which some components of one embodiment are added to other embodiments, or in which some components of other embodiments are replaced, are also embodiments of this disclosure. Furthermore, the effects described in the embodiments are merely a list of the most preferred effects that result from this disclosure, and the effects of this disclosure are not limited to those described in the embodiments.

[0079] For example, in the embodiment described above, memory elements 611 and 612 were positioned at the same location in the Y direction on one main surface of the printed circuit board 500 and arranged along the X direction. Therefore, multiple wires extended in parallel in the X direction from the terminal group of memory element 611 to the terminal group of memory element 612. However, the relative positions of memory elements 611 and 612 are not limited to this. That is, memory elements 611 and 612 may be offset in the Y direction. In this case, the wires extend in parallel diagonally from the terminal group of memory element 611 to the terminal group of memory element 612, but variations in the length of the wires between multiple wires can be suppressed, as in the embodiment described above.

[0080] Furthermore, in the above-described embodiment, memory element 611 and memory element 612 have a common structure, and the positional relationship between the terminal group and via group in memory element 611 is the same as the positional relationship between the terminal group and via group in memory element 612. Therefore, region R2 (second terminal group) is located between region R1 (first terminal group) and region R3 (third terminal group), and region R3 (third terminal group) is located between region R2 (second terminal group) and region R4 (fourth terminal group). However, the structures of memory element 611 and memory element 612 may be different. For example, memory element 611 and memory element 612 may have mirror-image symmetric structures. For example, region R2 (second terminal group) may be located between region R1 (first terminal group) and region R3 (third terminal group), and region R4 (fourth terminal group) may be located between region R2 (second terminal group) and region R3 (third terminal group).

[0081] Furthermore, although the embodiments described above described cases in which the electronic device includes an imaging device, the electronic device to which the electronic module of this disclosure can be applied is not limited to cases that include an imaging device. For example, it may be an information device or communication device that does not have an imaging device, display device, or printing device.

[0082] This disclosure includes the following components: (Composition 1) Wiring board and An electronic module comprising a first semiconductor element and a second semiconductor element mounted on one main surface of the aforementioned wiring board, The first semiconductor element includes a first terminal group and a second terminal group, The second semiconductor element includes a third terminal group and a fourth terminal group, The wiring board includes a plurality of wiring layers, a first via group having a plurality of through vias connected to a plurality of terminals of the first terminal group, a second via group having a plurality of through vias connected to a plurality of terminals of the second terminal group, a third via group having a plurality of through vias connected to a plurality of terminals of the third terminal group, and a fourth via group having a plurality of through vias connected to a plurality of terminals of the fourth terminal group. The first group of terminals of the first semiconductor element is connected to the third group of terminals of the second semiconductor element via the first group of vias and the third group of vias, and the second group of terminals of the first semiconductor element is connected to the fourth group of terminals of the second semiconductor element via the second group of vias and the fourth group of vias, respectively. The first via group comprises a first via connected to the first terminal of the first terminal group and a second via connected to the second terminal of the first terminal group. The second via group comprises a third via connected to the third terminal of the second terminal group, and a fourth via connected to the fourth terminal of the second terminal group and adjacent to the third via. The third via group includes a fifth via connected to the fifth terminal of the third terminal group and a sixth via connected to the sixth terminal of the third terminal group. The first via and the second via are arranged in a first direction, the third via and the fourth via are arranged in a second direction intersecting the first direction, a virtual straight line connecting the first via and the second via passes between the third via and the fourth via, a first wiring connecting the first via and the fifth via, and a second wiring connecting the second via and the sixth via passes between the third via and the fourth via. An electronic module characterized by the following features. (Configuration 2) The fourth via group comprises a seventh via connected to the seventh terminal of the fourth terminal group, and an eighth via connected to the eighth terminal of the fourth terminal group and adjacent to the seventh via. The earlier vias 7 and 8 are arranged in the earlier direction 2. The first and second wirings pass between the third wiring connecting the third via and the seventh via, and the fourth wiring connecting the fourth via and the eighth via. The electronic module according to configuration 1, characterized by the above. (Composition 3) The fifth via and the sixth via are located between the third wiring and the fourth wiring. The electronic module according to configuration 2, characterized in that it is a feature of the electronic module described in configuration 2. (Composition 4) The fifth via and the sixth via are arranged in the first direction, and a virtual straight line connecting the fifth via and the sixth via passes between the seventh via and the eighth via. The electronic module according to configuration 2, characterized in that it is a feature of the electronic module described in configuration 2. (Composition 5) The imaginary line connecting the first via and the second via, and the imaginary line connecting the fifth via and the sixth via, are located on the same imaginary line. An electronic module according to any one of configurations 1 to 4, characterized by the above. (Composition 6) The first via group has a ninth via connected to the ninth terminal of the first terminal group, The virtual straight line connecting the first via and the second via passes through the ninth via, The second terminal and the ninth terminal are arranged in a third direction intersecting the first direction. The electronic module according to configuration 1, characterized by the above. (Composition 7) The 9th via is located between the 1st via and the 2nd via. The electronic module according to configuration 6, characterized in that it is a feature of the electronic module according to configuration 6. (Composition 8) The first terminal and the second terminal are arranged in a fourth direction that intersects the third direction. The electronic module according to configuration 6, characterized in that it is a feature of the electronic module according to configuration 6. (Composition 9) The fourth via group comprises a seventh via connected to the seventh terminal of the fourth terminal group, and an eighth via connected to the eighth terminal of the fourth terminal group and adjacent to the seventh via. The third via group has a 10th via connected to the 10th terminal of the third terminal group, The fifth wiring connecting the ninth via and the tenth via passes between the seventh via and the eighth via. The electronic module according to configuration 6, characterized in that it is a feature of the electronic module according to configuration 6. (Composition 10) The third via group has a 10th via connected to the 10th terminal of the third terminal group, The 10th via is located between the 5th via and the 6th via. The electronic module according to configuration 8, characterized by the above. (Composition 11) The first wiring and the second wiring are provided in the first wiring layer of the plurality of wiring layers, The fifth wiring is provided in the second wiring layer among the plurality of wiring layers. The electronic module according to configuration 9, characterized by the features described therein. (Composition 12) The difference between the length of the first wiring and the length of the second wiring is 10% or less of the length of either the first wiring or the second wiring. The electronic module according to configuration 1, characterized by the above. (Composition 13) The first and second wirings have a fly-by wiring structure. The electronic module according to configuration 1, characterized by the above. (Composition 14) A first signal is supplied to the first semiconductor element and the second semiconductor element via the first wiring, and a second signal is supplied to the first semiconductor element and the second semiconductor element via the second wiring. The electronic module according to configuration 1, characterized by the above. (Composition 15) The first semiconductor element and the second semiconductor element are a memory, A memory controller mounted on the aforementioned wiring board performs data input and output with the first semiconductor element and the second semiconductor element. The electronic module according to configuration 1, further comprising the following: (Composition 16) The first terminal, the second terminal, the fifth terminal, and the sixth terminal are control terminals. The electronic module according to configuration 1, characterized by the above. (Composition 17) The first terminal group, the second terminal group, the third terminal group, and the fourth terminal group have a ball grid array structure. The electronic module according to configuration 1, characterized by the above. (Composition 18) The aforementioned wiring board further comprises a plurality of connectors mounted on it. The electronic module according to configuration 1, characterized by the above. (Composition 19) A first electronic module which is an electronic module described in any of configurations 1 to 18, The second electronic module, A wiring member for connecting the first electronic module and the second electronic module, Electronic devices equipped with these features. (Composition 20) Image acquisition device, An electronic device comprising a circuit device that outputs image data based on an image signal obtained by the image acquisition device, The circuit device includes an electronic module as described in any of configurations 1 to 18. An electronic device characterized by the following features. (Composition 21) The image forming apparatus includes an image forming apparatus that forms an image based on the aforementioned image data. The electronic device according to configuration 20, characterized by the features described above. (Composition 22) A circuit device that outputs image data, An electronic device comprising an image forming apparatus that forms an image based on the aforementioned image data, The circuit device includes an electronic module as described in any of configurations 1 to 18. An electronic device characterized by the following features. (Composition 23) The image forming apparatus is a display device. The electronic device according to configuration 22, characterized by the features described above. (Composition 24) The image forming apparatus is a printing apparatus. The electronic device according to configuration 22, characterized by the features described above.

[0083] The disclosures in this specification include not only what is explicitly stated herein, but also all matters that can be understood from this specification and the drawings attached thereto. Furthermore, the disclosures in this specification include the complement of the individual concepts described herein. That is, if this specification states, for example, "A is B," then even if it omits the statement "A is not B," it can be said that this specification discloses "A is not B." This is because the statement "A is B" presupposes that the case "A is not B" is being considered. [Explanation of Symbols]

[0084] 100...Electronic equipment 200... Electronic Modules 500... Printed circuit board 501, 502, 503, 504, 505, 506, 507, 508, 509, 510...Wiring layer 562a, 562b, 562c, 562d, 562e, 562f, 562g, 562h, 562i, 562j... Beer 610...Memory Controller 611, 612...memory elements

Claims

1. Wiring board and An electronic module comprising a first semiconductor element and a second semiconductor element mounted on one main surface of the aforementioned wiring board, The first semiconductor element includes a first terminal group and a second terminal group, The second semiconductor element includes a third terminal group and a fourth terminal group, The wiring board includes a plurality of wiring layers, a first via group having a plurality of through vias connected to a plurality of terminals of the first terminal group, a second via group having a plurality of through vias connected to a plurality of terminals of the second terminal group, a third via group having a plurality of through vias connected to a plurality of terminals of the third terminal group, and a fourth via group having a plurality of through vias connected to a plurality of terminals of the fourth terminal group. The first group of terminals of the first semiconductor element is connected to the third group of terminals of the second semiconductor element via the first group of vias and the third group of vias, and the second group of terminals of the first semiconductor element is connected to the fourth group of terminals of the second semiconductor element via the second group of vias and the fourth group of vias, respectively. The first via group comprises a first via connected to the first terminal of the first terminal group and a second via connected to the second terminal of the first terminal group. The second via group comprises a third via connected to the third terminal of the second terminal group, and a fourth via connected to the fourth terminal of the second terminal group and adjacent to the third via. The third via group includes a fifth via connected to the fifth terminal of the third terminal group and a sixth via connected to the sixth terminal of the third terminal group. The first via and the second via are arranged in a first direction, and in a plan view, the first via and the second via overlap the first semiconductor element; the third via and the fourth via are arranged in a second direction intersecting the first direction; a virtual line connecting the first via and the second via passes between the third via and the fourth via; a first wiring connecting the first via and the fifth via, and a second wiring connecting the second via and the sixth via pass between the third via and the fourth via. An electronic module characterized by the following features.

2. The fourth via group comprises a seventh via connected to the seventh terminal of the fourth terminal group, and an eighth via connected to the eighth terminal of the fourth terminal group and adjacent to the seventh via. The seventh via and the eighth via are arranged in the second direction. The first and second wirings pass between the third wiring connecting the third via and the seventh via, and the fourth wiring connecting the fourth via and the eighth via. The electronic module according to feature 1.

3. The fifth via and the sixth via are located between the third wiring and the fourth wiring. The electronic module according to feature 2.

4. The fifth via and the sixth via are arranged in the first direction, and a virtual straight line connecting the fifth via and the sixth via passes between the seventh via and the eighth via. The electronic module according to feature 2.

5. The imaginary line connecting the first via and the second via, and the imaginary line connecting the fifth via and the sixth via, are located on the same imaginary line. The electronic module according to feature 1.

6. The first via group has a ninth via connected to the ninth terminal of the first terminal group, The imaginary straight line connecting the first via and the second via passes through the ninth via, The second terminal and the ninth terminal are arranged in a third direction intersecting the first direction. The electronic module according to feature 1.

7. The ninth via is located between the first via and the second via. The electronic module according to feature 6.

8. The first terminal and the second terminal are arranged in a fourth direction that intersects the third direction. The electronic module according to feature 6.

9. The fourth via group comprises a seventh via connected to the seventh terminal of the fourth terminal group, and an eighth via connected to the eighth terminal of the fourth terminal group and adjacent to the seventh via. The third via group has a tenth via connected to the tenth terminal of the third terminal group, The fifth wiring connecting the ninth via and the tenth via passes between the seventh via and the eighth via. The electronic module according to feature 6.

10. The third via group has a tenth via connected to the tenth terminal of the third terminal group, The 10th via is located between the 5th via and the 6th via. The electronic module according to feature 8.

11. The first wiring and the second wiring are provided in the first wiring layer among the plurality of wiring layers. The fifth wiring is provided in the second wiring layer among the plurality of wiring layers. The electronic module according to feature 9.

12. The difference between the length of the first wiring and the length of the second wiring is 10% or less of the length of the first wiring or the second wiring, and / or The first and second wirings have a fly-by wiring structure. The electronic module according to feature 1.

13. A first signal is supplied to the first semiconductor element and the second semiconductor element via the first wiring, and a second signal is supplied to the first semiconductor element and the second semiconductor element via the second wiring. The electronic module according to feature 1.

14. The first semiconductor element and the second semiconductor element are a memory, A memory controller mounted on the aforementioned wiring board performs data input and output with the first semiconductor element and the second semiconductor element. The electronic module according to claim 1, further comprising the following:

15. The first terminal, the second terminal, the fifth terminal, and the sixth terminal are control terminals. The electronic module according to feature 1.

16. The first terminal group, the second terminal group, the third terminal group, and the fourth terminal group have a ball grid array structure, and / or The aforementioned wiring board further comprises a plurality of connectors mounted on it. The electronic module according to feature 1.

17. A first electronic module which is the electronic module described in claim 1, The second electronic module, A wiring member for connecting the first electronic module and the second electronic module, Electronic devices equipped with these features.

18. Image acquisition device, An electronic device comprising a circuit device that outputs image data based on an image signal obtained by the image acquisition device, The circuit device includes the electronic module described in claim 1. An electronic device characterized by the following features.

19. A circuit device that outputs image data, An electronic device comprising an image forming apparatus that forms an image based on the aforementioned image data, The circuit device includes the electronic module described in claim 1. An electronic device characterized by the following features.

20. The image forming apparatus is a display device or a printing apparatus. The electronic device according to feature 19.

Images