Method for manufacturing metal wiring, method for manufacturing transistors, and metal wiring

Abstract

The present invention provides a method for manufacturing a metal wiring on a substrate, the method comprising a step for forming a first layer including a first material on at least part of the substrate, a step for forming a crack in the first layer so as to form a first layer having a crack, and a step for forming a second layer including a second material on the first layer having the crack.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a metal wiring, a method for manufacturing a transistor, and a metal wiring. This application claims priority based on Japanese Patent Application No. 2021-125285 filed in Japan on July 30, 2021, and incorporates its content herein.

Background Art

[0002] Conventionally, as a method for manufacturing devices such as transistors, the application of a solution process, which is inexpensive and suitable for large-scale production, has been studied. When the solution process is adopted, it becomes possible to manufacture transistors and the like at a lower temperature than before. Further, by forming an organic semiconductor layer using an organic semiconductor material on a flexible substrate using a resin material, it is also possible to manufacture a flexible organic transistor.

[0003] In such a method for manufacturing a transistor, electroless plating (non-electrolytic plating), which is a plating method using reduction by the contact action on the material surface, can be used. Since no electric energy is used in electroless plating, it is possible to perform plating on resin materials, glass, etc., which are insulators.

[0004] For example, Patent Document 1 describes a method for manufacturing a thin-film transistor in which source electrodes and drain electrodes are selectively formed by performing an electroless plating process. On the other hand, for example, when a flexible substrate is used, it is preferable that the conductivity of wiring and the like is maintained even when the substrate is bent.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] A first aspect of the present invention is a method for manufacturing metal wiring on a substrate, comprising: a first layer forming step of forming a first layer containing a first material on at least a portion of the substrate; a step of forming cracks in the first layer to form a first layer having cracks; and a step of forming a second layer containing a second material on the first layer having cracks.

[0007] A second aspect of the present invention is a metal wiring provided on a substrate, wherein the metal wiring has a gold layer or a copper layer on top of a nickel-phosphorus layer, and the resistance increase rate of the resistance value of the metal wiring before and after a bending test using a planar unloaded U-shaped stretch tester with a bending radius of 5 mm and 100 bending cycles is 7.0% or less.

[0008] A third aspect of the present invention is a metal wiring provided on a substrate, the metal wiring comprising a first layer, a second layer, and a third layer, wherein, in a direction perpendicular to a predetermined plane including the substrate, the first layer is a layer comprising a first material, the second layer comprises a first region comprising the first material and a second region comprising the second material, and the third layer comprises the second material. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram illustrating an example of a method for manufacturing metal wiring according to this embodiment. [Figure 2] This is a schematic diagram illustrating an example of a method for manufacturing metal wiring according to this embodiment. [Figure 3] This is a schematic diagram illustrating an example of a method for manufacturing metal wiring according to this embodiment. [Figure 4] This is a schematic diagram illustrating an example of a method for manufacturing metal wiring according to this embodiment. [Figure 5] This is a schematic diagram illustrating an example of a method for manufacturing metal wiring according to this embodiment. [Figure 6] This is a schematic diagram illustrating an example of a method for manufacturing metal wiring according to this embodiment. [Figure 7]This is a schematic diagram showing the overall configuration of the substrate processing equipment. [Figure 8] This is a schematic diagram showing a part of the configuration of a substrate processing apparatus. [Figure 9] This is a schematic diagram showing a part of the configuration of a substrate processing apparatus. [Figure 10] This is a schematic diagram of the side view of metal wiring. [Modes for carrying out the invention]

[0010] Preferred embodiments of the metal wiring manufacturing method of the present invention will be described below. However, the present invention is not limited to these embodiments.

[0011] <Method of manufacturing metal wiring> This embodiment is a method for manufacturing metal wiring on a flexible substrate. This embodiment comprises the steps of: forming a first layer containing nickel-phosphorus (first material) on at least a portion of a substrate by electroless plating; forming cracks in the first layer to form a first layer having cracks; and bringing a displacement gold plating bath or a displacement copper plating bath into contact with the first layer having cracks to form a second layer containing gold or copper (second material).

[0012] In the crack formation process, cracks are intentionally formed in the first layer in a direction substantially perpendicular to the substrate. The shape of the cracks is not particularly limited, but it is preferable that, for example, a mesh-like crack is uniformly formed.

[0013] In this embodiment, the crack may be formed shallowly near the surface of the first layer, or it may be formed so that the first layer is divided by the crack. In this embodiment, by forming cracks in the first layer, nickel-phosphorus layers and gaps are formed alternately.

[0014] In this specification, "crack" means fine cracks occurring in the first layer, damages such as cracks or fine delaminations, or a state where the first layer is disconnected. The depth of the crack is not particularly limited. For example, when the thickness of the first layer is 50 to 100 nm, the depth of the crack may be 50 to 100 nm.

[0015] When a displacement gold plating bath or a displacement copper plating bath is brought into contact with the first layer having cracks, a displacement gold plating layer or a displacement copper plating layer is formed so as to fill the gaps of the formed cracks.

[0016] For example, a flexible substrate on which a metal wiring formed of nickel-phosphorus as a forming material is formed is assumed to be used after being bent. When cracks occur in the nickel-phosphorus wiring due to bending, the conductivity is impaired, and problems such as an increase in the resistance value and disconnection occur.

[0017] In the present embodiment, cracks are intentionally formed in the first layer, and then a displacement gold plating bath or a displacement copper plating bath is brought into contact therewith to form a second layer containing gold or copper, so that even when the manufactured substrate is bent, new cracks are unlikely to occur and the conductivity is maintained.

[0018] Hereinafter, preferred embodiments of the present invention will be described.

[0019] ≪First Embodiment≫ The first embodiment will be described with reference to FIG. 1. The first embodiment includes, in this order, a step of forming a first layer, a step of forming cracks, a step of removing a resist layer, and a step of forming a second layer.

[0020] [First layer forming step] First, in the step of forming the first layer, as shown in FIG. 1(a), a nickel-phosphorus layer 32 is formed on a substrate 31 by electroless plating.

[0021] Next, as shown in FIG. 1(b), a resist layer 33 is formed on the nickel-phosphorus layer 32.

[0022] Next, the resist layer 33 is irradiated with pattern light and developed. After development, the resist layer 33 and the nickel-phosphorus layer 32 are etched. As a result, as shown in Figure 1(c), a nickel-phosphorus layer 32a and a resist layer 33a with a predetermined pattern shape are formed on the substrate 31.

[0023] [Crack formation process] Cracks 34 are formed in the nickel-phosphorus layer 32a by a crack-forming means. The crack-forming means will be described later. As a result, a nickel-phosphorus layer 32b with cracks formed on it is formed on the substrate 31, as shown in Figure 1(d).

[0024] [Resist layer removal process] After forming the crack 34, the resist layer 33a is removed. As a result, a nickel-phosphorus layer 32b with cracks formed on it is created on the substrate 31, as shown in Figure 1(e).

[0025] [Second layer formation process] Subsequently, a second layer 35a containing gold or copper is formed by bringing a substitution gold plating bath or a substitution copper plating bath into contact with the first layer 32b having cracks (the nickel-phosphorus layer 32b in which the cracks were formed). As a result, the second layer 35a containing gold or copper is formed to fill the gaps of the formed cracks, as shown in Figure 1(f).

[0026] ≪Second Embodiment≫ A second embodiment will be described with reference to Figure 2. The second embodiment comprises the steps of forming a first layer, forming a crack, forming a resist layer, and forming a second layer, in this order.

[0027] [First layer formation process] First, as shown in Figure 2(a), in the process of forming the first layer, a nickel-phosphorus layer 32 is formed on the substrate 31 by electroless plating.

[0028] [The process of forming cracks] Next, cracks 34 are formed in the nickel-phosphorus layer 32 by a crack-forming means. The crack-forming means will be described later. As a result, a nickel-phosphorus layer 32c with cracks 34 is formed on the substrate 31, as shown in Figure 2(b).

[0029] [Process for forming a resist layer] Next, as shown in Figure 2(c), a resist layer 33 is formed on the nickel-phosphorus layer 32c in which the crack 34 is formed.

[0030] Next, the resist layer 33 is irradiated with pattern light and developed. After development, the resist layer 33 and the nickel-phosphorus layer 32c are etched. As a result, as shown in Figure 2(d), a nickel-phosphorus layer 32b and a resist layer 33a with a predetermined pattern shape having cracks are formed on the substrate 31.

[0031] [Resist layer removal process] Subsequently, the resist layer 33a is removed. As a result, a nickel-phosphorus layer 32b with cracks is formed on the substrate 31, as shown in Figure 2(e).

[0032] [Second layer formation process] Subsequently, a second layer 35a containing gold or copper is formed by bringing a substitution gold plating bath or a substitution copper plating bath into contact with the first layer 32b having cracks. As a result, the second layer 35a containing gold or copper is formed to fill the gaps of the formed cracks, as shown in Figure 2(f).

[0033] ≪Third Embodiment≫ The third embodiment will be described with reference to Figure 3. The third embodiment comprises the steps of forming a first layer, forming a crack, forming a second layer, and forming a resist layer, in this order.

[0034] [First layer formation process] First, as shown in Figure 3(a), in the process of forming the first layer, a nickel-phosphorus layer 32 is formed on the substrate 31 by electroless plating.

[0035] [The process of forming cracks] Next, cracks 34 are formed in the nickel-phosphorus layer 32 by a crack-forming means. The crack-forming means will be described later. As a result, a nickel-phosphorus layer 32c with cracks 34 is formed on the substrate 31, as shown in Figure 3(b).

[0036] [Second layer formation process] Subsequently, a second layer 35 containing gold or copper is formed by bringing a substitution gold plating bath or a substitution copper plating bath into contact with the first layer 32c having cracks. As a result, the second layer 35 containing gold or copper is formed to fill the gaps of the formed cracks, as shown in Figure 3(c).

[0037] [Process for forming a resist layer] Next, as shown in Figure 3(d), a resist layer 33 is formed on the second layer 35 containing gold or copper.

[0038] Next, the resist layer 33 is irradiated with pattern light and developed. After development, the resist layer 33, the second layer 35 containing gold or copper, and the nickel-phosphorus layer 32c are etched. As a result, as shown in Figure 3(e), a nickel-phosphorus layer 32b, the second layer 35a containing gold or copper, and the resist layer 33a are formed on the substrate 31, each having a predetermined pattern shape with cracks.

[0039] [Resist layer removal process] Subsequently, the resist layer 33a is removed. As a result, a nickel-phosphorus layer 32b with a predetermined pattern shape having cracks, and a second layer 35a containing gold or copper are formed on the substrate 31, as shown in Figure 3(f).

[0040] ≪Fourth Embodiment≫ A fourth embodiment will be described with reference to Figure 4. The fourth embodiment comprises, in this order, the steps of forming a resist layer on a substrate, irradiating the resist layer with pattern light and developing it, forming a first layer on the substrate exposed after development, forming cracks, forming a second layer, and removing the resist layer.

[0041] [Resist layer formation process] In this embodiment, first, a resist layer 33 is formed on the substrate 31, as shown in Figure 4(a). Next, the resist layer 33 is irradiated with patterned light and developed. As a result, as shown in Figure 4(b), after development, the exposed substrate portion P and the resist layer 33a are formed on the substrate 31.

[0042] [Step to form the first layer] A nickel-phosphorus layer 32a is formed on the exposed portion P of the substrate by electroless plating. As a result, a resist layer 33a and a nickel-phosphorus layer 32a are formed on the substrate 31, as shown in Figure 4(c).

[0043] [The process of forming cracks] Next, cracks 34 are formed in the nickel-phosphorus layer 32a by a crack-forming means. The crack-forming means will be described later. As a result, a nickel-phosphorus layer 32b with cracks 34 is formed on the substrate 31, as shown in Figure 4(d).

[0044] [Step to form the second layer] Subsequently, a second layer 35a containing gold or copper is formed by bringing a substitution gold plating bath or a substitution copper plating bath into contact with the first layer 32b having cracks. As a result, the second layer 35a containing gold or copper is formed to fill the gaps of the formed cracks, as shown in Figure 4(e).

[0045] [Resist layer removal process] Subsequently, the resist layer 33a is removed. As a result, a nickel-phosphorus layer 32b with a predetermined pattern shape having cracks, and a second layer 35a containing gold or copper are formed on the substrate 31, as shown in Figure 4(f).

[0046] ≪Fifth Embodiment≫ A fifth embodiment will be described with reference to Figure 5. The fifth embodiment comprises, in this order, the steps of forming a resist layer on a substrate, irradiating the resist layer with pattern light and developing it, forming a first layer on the substrate exposed after development, removing the resist layer, forming cracks, and forming a second layer.

[0047] [Resist layer formation process] In this embodiment, first, a resist layer 33 is formed on the substrate 31, as shown in Figure 5(a). Next, the resist layer 33 is irradiated with patterned light and developed. As a result, as shown in Figure 5(b), after development, the substrate exposed portion P and the resist layer 33a are formed on the substrate 31.

[0048] [Step to form the first layer] A nickel-phosphorus layer 32a is formed on the exposed substrate P by electroless plating. As a result, as shown in Figure 5(c), the resist layer 33a and the nickel-phosphorus layer 32a are alternately formed on the substrate 31.

[0049] [Resist layer removal process] Subsequently, the resist layer 33a is removed. As a result, a nickel-phosphorus layer 32a with a predetermined pattern shape is formed on the substrate 31, as shown in Figure 5(d).

[0050] [The process of forming cracks] Next, cracks 34 are formed in the nickel-phosphorus layer 32a by a crack-forming means. The crack-forming means will be described later. As a result, a nickel-phosphorus layer 32b with a predetermined pattern shape in which cracks 34 are formed is formed on the substrate 31, as shown in Figure 5(e).

[0051] [Step to form the second layer] Subsequently, a second layer 35a containing gold or copper is formed by bringing a substitution gold plating bath or a substitution copper plating bath into contact with the first layer 32b having a predetermined pattern shape with cracks. As a result, the second layer 35a containing gold or copper is formed to fill the gaps in the formed cracks, as shown in Figure 5(f).

[0052] ≪Sixth Embodiment≫ The sixth embodiment will be described with reference to Figure 6. The sixth embodiment comprises, in this order, the steps of forming a resist layer on a substrate, irradiating the resist layer with pattern light and developing it, forming a first layer on the substrate exposed after development, forming cracks, removing the resist layer, and forming a second layer.

[0053] [Resist layer formation process] In this embodiment, first, a resist layer 33 is formed on the substrate 31, as shown in Figure 6(a). Next, the resist layer 33 is irradiated with patterned light and developed. As a result, as shown in Figure 6(b), the substrate exposed portion P, where the substrate is exposed after development, and the resist layer 33a are formed on the substrate 31.

[0054] [Step to form the first layer] A nickel-phosphorus layer 32a is formed on the exposed substrate P by electroless plating. As a result, as shown in Figure 6(c), the resist layer 33a and the nickel-phosphorus layer 32a are alternately formed on the substrate 31.

[0055] [The process of forming cracks] Next, cracks 34 are formed in the nickel-phosphorus layer 32a by a crack-forming means. The crack-forming means will be described later. As a result, as shown in Figure 6(d), the resist layer 33a and the nickel-phosphorus layer 32b with cracks formed on it are alternately formed on the substrate 31.

[0056] [Resist layer removal process] Subsequently, the resist layer 33a is removed. This creates cracks, as shown in Figure 6(e), and a nickel-phosphorus layer 32b having a predetermined pattern shape is formed on the substrate 31.

[0057] [Step to form the second layer] Subsequently, a second layer 35a containing gold or copper is formed by bringing a substitution gold plating bath or a substitution copper plating bath into contact with the first layer 32b having cracks. As a result, the second layer 35a containing gold or copper is formed to fill the gaps of the formed cracks, as shown in Figure 6(f).

[0058] The metal wiring of the first to sixth embodiments will be described with reference to Figure 10. Figure 10 is a side view of the metal wiring. The metal wiring can be considered to have a three-layer structure separated by the dashed lines in Figure 10. More specifically, it consists of three layers: layer A (first layer) 32a having a nickel-phosphorus layer which is the first material; layer B (second layer) 36 having a first region containing nickel-phosphorus and a second region containing gold or copper which is the second material; and layer C (third layer) 35a having gold or copper. Layer B becomes a layer having a first region and a second region by having gold or copper, the second material, fill the crack gaps in the nickel-phosphorus.

[0059] In the first to sixth embodiments described above, the first material of the first layer was described as nickel-phosphorus and the second material of the second layer as gold or copper, but the invention is not limited to these, and the first and second materials may be appropriately selected from materials used as metal wiring.

[0060] <<Substrate Processing Equipment>> Figure 7 shows a schematic diagram of the overall configuration of the substrate processing apparatus used in the manufacturing method of metal wiring according to this embodiment. The substrate processing apparatus 100 shown in Figure 7 comprises a processing tank BT1 for contacting an electroless plating solution with a long sheet substrate S, a processing tank BT2 for etching, a crack forming means CR, and a processing tank BT3 for displacement gold plating or copper plating.

[0061] These devices are appropriately installed along the transport path of the sheet substrate S, enabling production using a so-called roll-to-roll method.

[0062] In the metal wiring manufacturing method of this embodiment, an XYZ coordinate system is set as shown in Figure 7, and this XYZ coordinate system will be used as appropriate in the following explanation. In the XYZ coordinate system, for example, the X and Y axes are set along the horizontal plane, and the Z axis is set upward along the vertical direction. The substrate processing apparatus 100 transports the sheet substrate S along the X axis as a whole, from the negative side (- side) to the positive side (+ side). At that time, the width direction (short length direction) of the sheet substrate S is set along the Y axis direction.

[0063] In the substrate processing apparatus 100, the sheet substrate S to be processed can be, for example, a resin film. For example, the resin film can be made from materials such as polyolefin resin, polysilicone resin, polyethylene resin, polypropylene resin, polyester resin, ethylene vinyl copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, polycarbonate resin, polystyrene resin, or vinyl acetate resin.

[0064] The width (short dimension) of the sheet substrate S is formed to be approximately 1m to 2m, for example, and the length (long dimension) is formed to be 10m or more. Of course, these dimensions are merely examples and are not limited to them. For example, the Y-direction dimension of the sheet substrate S may be 50cm or less, or 2m or more. Also, the X-direction dimension of the sheet substrate S may be 10m or less.

[0065] The sheet substrate S is preferably formed in a manner that provides flexibility. Here, flexibility refers to the property that the substrate can be bent without breaking or fracturing even when a force of approximately its own weight is applied to it. The property of bending under a force of approximately its own weight is also included in flexibility.

[0066] Furthermore, the above-mentioned flexibility varies depending on the material, size, thickness, and environmental factors such as temperature of the substrate. The following describes each step in forming metal wiring using the roll-to-roll method.

[0067] [Process for forming an electroless plating layer] In this process, it is preferable to first apply an electroless plating catalyst to the surface of the sheet substrate S to form a catalyst layer. The electroless plating catalyst is a catalyst that reduces metal ions contained in the electroless plating solution, and examples include silver and palladium.

[0068] Subsequently, the sheet substrate S is immersed in a treatment tank BT1, which is an electroless plating bath, to reduce metal ions on the catalyst surface and deposit a plating layer on the sheet substrate S. If the reduction is insufficient at this time, the sheet substrate S may be immersed in a reducing agent solution such as sodium hypophosphite or sodium borohydride to actively reduce the metal ions on the amine.

[0069] In this embodiment, nickel-phosphorus (NiP) is used as the plating material. In this embodiment, the phosphorus content constituting the plating layer is preferably less than the nickel content. Specifically, the phosphorus content may be 1% by mass or more and 13% by mass or less, with a lower limit of 5% by mass, more preferably 7% by mass, and an upper limit of 12% by mass, more preferably 10% by mass. If the phosphorus content is within the above range, cracks are more likely to form in the wiring during the crack formation process described later.

[0070] [Process for forming a resist film] A resist film is formed on the manufactured plating layer. First, a resist material R is applied onto the plating layer, and this is pre-baked to form an unpatterned resist layer. The resist material R may be either a positive-type photoresist or a negative-type photoresist.

[0071] Subsequently, the resist layer is exposed by irradiating it with ultraviolet light L through a mask that has openings in the areas where wiring is to be formed and light-shielding sections in the areas where wiring is not to be formed.

[0072] Next, the resist layer irradiated with ultraviolet light is developed with developer D to form a resist film with the openings provided and patterned.

[0073] The obtained resist film is preferably cleaned using cleaning means C.

[0074] [Process for forming metal wiring] A sheet substrate S, in which a plated layer and a patterned resist film are laminated in this order, is immersed in an etching tank BT2. This allows the plated layer to be etched using the resist film as a mask, forming the desired metal wiring on the sheet substrate S.

[0075] [Process for removing the resist film] Subsequently, the resist film is removed with a known developer A.

[0076] [The process of forming cracks] Subsequently, the sheet substrate S on which the desired metal wiring has been formed is transported to the crack forming means CR. The crack forming means CR is used to intentionally form cracks on the surface of the metal wiring. Preferably, the crack forming means CR is used to form cracks perpendicular to the sheet substrate S by applying physical impact.

[0077] In this embodiment, it is preferable to form cracks in the sheet substrate transport process using the dancer roller mechanism DR shown in Figure 8. Since the crack-forming means CR also serves as the transport process, cracks can be formed in the metal wiring simultaneously with the transport.

[0078] The dancer roller mechanism DR has support rollers 20a, 20b, and 20c that are movable up, down, left, and right, allowing a desired tension to be applied to the sheet substrate S during transport. By applying tension with the dancer roller mechanism DR, cracks can be formed on the surface of the metal wiring.

[0079] The number of support rollers is not limited to the schematic diagram shown in Figure 8, and can be increased or decreased as appropriate.

[0080] In this embodiment, it is preferable to form cracks in the sheet substrate transport process using a rolling roller mechanism equipped with rollers 10 and 11 as shown in Figure 9.

[0081] Since the surface of the formed cracks is prone to oxidation, it is preferable to perform the crack formation process immediately before the immersion in the displacement gold plating bath or displacement copper plating bath.

[0082] [Step of immersion in a gold or copper plating bath] A sheet substrate S equipped with cracked metal wiring is immersed in a treatment tank BT3 for displacement gold plating or copper plating. By immersing in the treatment tank BT3, gold or copper is displacement deposited to cover the surface of the cracked metal wiring pattern. As a result, the cracked areas are filled with gold or copper, and a two-layer metal wiring structure is produced in which a gold plating layer or copper plating layer is formed on top of the metal wiring, which is made of nickel-phosphorus as the forming material.

[0083] <Metal wiring> The manufacturing method of this embodiment described above makes it possible to manufacture metal wiring provided on a substrate. The metal wiring consists of a nickel-phosphorus layer and a gold or copper layer on top of the nickel-phosphorus layer. The metal wiring exhibits a resistance increase of 7.0% or less before and after a bending test using a planar unloaded U-shaped expansion and contraction tester, with a bending radius of 5 mm and 100 bending cycles.

[0084] Specifically, first, the resistance of the metal wiring placed on the circuit board is measured. This measured value is taken as the resistance value before the bending test. Subsequently, a bending test is performed using a planar unloaded U-shaped stretch tester with a bending radius of 5 mm and 100 bending cycles. After the bending test, the resistance value of the metal wiring is measured. This measured value is defined as the resistance value after the bending test. The resistance increase rate is calculated from the resistance values ​​of the metal wiring before and after the bending test using the following formula. Resistance increase rate (%) = (Resistance value after bending test - Resistance value before bending test) / Resistance value before bending test × 100

[0085] For a planar body unloaded U-shaped expansion / contraction tester, for example, the DMLHB-FS-C manufactured by Yuasa Systems Corporation can be used.

[0086] In this embodiment, the resistance increase rate of the metal wiring measured by the above method is preferably 0% or more and 7.0% or less, and more preferably 0% or more and 3.0% or less.

[0087] <Transistor manufacturing method> Furthermore, a method for manufacturing a transistor using the metal wiring obtained by the above-described method for manufacturing metal wiring as the gate electrode will be explained.

[0088] First, an insulating layer is formed on the electroless plating pattern formed by the metal wiring manufacturing method described above. The insulating layer may be formed by applying a coating solution obtained by dissolving one or more resins, such as UV-curable acrylic resin, epoxy resin, ene-thiol resin, or silicone resin, in an organic solvent. By irradiating the coating film with ultraviolet light through a mask having openings corresponding to the area where the insulating layer is to be formed, it is possible to form the insulating layer in a desired pattern.

[0089] A source electrode and a drain electrode are formed on the insulating layer by a known method.

[0090] For example, a hydrophilic region can be formed in the area where the source electrode and drain electrode are to be formed, a catalyst for electroless plating can be supported on the hydrophilic region to form a catalyst layer, and then electroless plating can be performed to form a plating layer (source electrode) and the other plating layer (drain electrode).

[0091] A semiconductor layer is formed between the plating layer (source electrode) and the other plating layer (drain electrode). The semiconductor layer can be made of commonly known inorganic or organic semiconductor materials. As an inorganic semiconductor material, for example, IGZO (indium gallium zinc oxide) can be used. As an organic semiconductor material, for example, p-type semiconductors such as copper phthalocyanine (CuPc), pentacene, rubrene, tetracene, and P3HT (poly(3-hexylthiophene-2,5-diyl)) can be used, as well as n-type semiconductors such as fullerenes such as C60 and perylene derivatives such as PTCDI-C8H (N,N'-dioctyl-3,4,9,10-perylene tetracarboxylic diimide).

[0092] In particular, soluble pentacenes such as TIPS pentacene (6,13-Bis(triisopropylsilylethynyl)pentacene) and organic semiconductor polymers such as P3HT are preferred because they are soluble in organic solvents such as toluene.

[0093] The material may also be formed by preparing a solution of an organic semiconductor material soluble in such an organic solvent by dissolving it in the organic solvent, and then applying and drying the solution between the plating layer (source electrode) and the other plating layer (drain electrode).

[0094] Alternatively, the semiconductor layer may be formed by adding one or more insulating polymers, such as PS (polystyrene) or PMMA (polymethyl methacrylate), to the above solution, and then coating and drying the solution containing the insulating polymers. When a semiconductor layer is formed in this manner, the insulating polymer is concentrated beneath the semiconductor layer.

[0095] When polar groups such as amino groups are present at the interface between the organic semiconductor and the insulating layer, transistor characteristics tend to deteriorate. However, by providing the organic semiconductor via the insulating polymer described above, the deterioration of transistor characteristics can be suppressed. In this way, it is possible to manufacture transistors.

[0096] Furthermore, there are no particular restrictions on the structure of the transistor, and it can be appropriately selected according to the purpose. For example, top-contact, bottom-gate type, top-contact, top-gate type, and bottom-contact, top-gate type transistors may be manufactured. [Examples]

[0097] The present invention will be described in detail below with reference to examples, but it is not limited to the following examples.

[0098] <Manufacturing of test boards> A nickel-phosphorus layer was formed on a polyethylene naphthalate (PEN) substrate measuring 5 cm x 1 cm with a film thickness of 100 μm by electroless plating. SE-680, manufactured by Nippon Kanigen Co., Ltd., was used for the electroless plating. At this point, no cracks had occurred in the nickel-phosphorus layer.

[0099] Subsequently, a resist material was applied to the nickel-phosphorus layer, exposed through a mask of a predetermined pattern, and developed to form a resist pattern. Using the resist pattern as a mask, the nickel-phosphorus layer was etched, and nickel-phosphorus was used as the forming material to manufacture metal wiring with a width of 1 mm and a length of 40 mm on a PEN substrate. The resist film was removed using a developer.

[0100] During these processes, the PEN substrate containing the nickel-phosphorus layer was bent to apply stress, creating cracks in the nickel-phosphorus layer. Subsequently, cracks were confirmed to have formed in the nickel-phosphorus layer using an optical microscope.

[0101] Subsequently, the surface of the cracked nickel-phosphorus wiring was subjected to displacement gold plating, forming a two-layer metal wiring structure with a gold plating layer on top of the nickel-phosphorus wiring.

[0102] Example 1 The resistance of a two-layer metal wiring structure formed on a PEN substrate was measured. This measured value was defined as the "resistance value before bending test." Subsequently, the two-layer metal wiring structure formed on the PEN substrate was subjected to a bending test of 100 times using the following planar no-load U-shaped stretch tester, and the resistance value was measured. This measured value was defined as the "resistance value after bending test." The resistance increase rate is calculated from the resistance values ​​of the metal wiring before and after the bending test using the following formula. Resistance increase rate (%) = (Resistance value after bending test - Resistance value before bending test) / Resistance value before bending test × 100

[0103] The results are shown in Table 1. In Table 1, "Resistance value before bending test" is labeled "Before test," and "Resistance value after bending test" is labeled "After test."

[0104] (Unloaded U-shaped expansion and contraction testing machine for planar materials) The following equipment was used for the unloaded U-shaped expansion and contraction test of planar materials. Equipment used: DMLHB-FS-C (manufactured by Yuasa Systems Corporation) Bending radius: 5mm

[0105] Examples 2-5 The resistance of the metal wiring was measured using the same method as in Example 1, except that the number of bends was changed to the numbers shown in Table 1.

[0106] ≪Comparative Example 1≫ The resistance of cracked nickel-phosphorus wiring that had not undergone substitution gold plating was measured and designated as Comparative Example 1.

[0107] [Table 1]

[0108] As shown in Table 1 above, Examples 1 to 5 showed good conductivity, with a resistance increase rate of 6.06% or less from before the bending test to after the bending test. In Comparative Example 1, where substitution gold plating was not performed, the resistance value exceeded the detection range even with zero bending cycles, making it impossible to measure the resistance value. [Explanation of symbols]

[0109] 10, 11: Rollers, 20a: Support roller, 31: Substrate, 32, 32a: First layer (nickel-phosphorus layer), 32b, 32c: First layer with cracks formed (nickel-phosphorus layer with cracks formed), 33, 33a: Resist layer, 34: Crack, 35a: Second layer, 100: Substrate processing apparatus, A: Developer, BT1: Processing tank, BT2: Processing tank, BT3: Processing tank, C: Cleaning means, CR: Crack forming means, D: Developer, DR: Dancer roller mechanism, L: Ultraviolet light, P: Substrate exposed area, R: Resist material, S: Sheet substrate, U: Planar body (no load)

Claims

1. Metal wiring provided on a circuit board, The metal wiring comprises a first layer containing a first material and a second layer containing a second material on top of the first layer. The second layer is formed so as to fill the gaps in the cracks of the first layer, with a portion of it extending into the interior of the first layer. The resistance increase rate of the metal wiring before and after a bending test using a planar body unloaded U-shaped stretch tester is 7.0% or less, and the test conditions for the bending test are a length of 40 mm for the metal wiring, a bending radius of 5 mm, and 100 bending cycles. metal wiring.

2. The metal wiring according to claim 1, wherein the second layer covers the side and top surfaces of the first layer.

3. The metal wiring according to claim 1, wherein the first material is an alloy.

4. The metal wiring according to claim 3, wherein the alloy comprises nickel and phosphorus.

5. The metal wiring according to claim 1, wherein the second material comprises gold or copper.

6. The metal wiring according to claim 1, wherein the substrate is flexible.

7. The metal wiring according to claim 1, wherein the substrate is made of a resin material.

8. A metal wiring provided on a substrate, The aforementioned metal wiring has a first layer and a second layer in the film thickness direction, from bottom to top. The first layer includes a first region containing a first material and a second region containing a second material. The aforementioned second layer comprises the aforementioned second material, In the first layer, the second region is a metal wiring that fills the gaps in the cracks of the first region.

9. The metal wiring has a third layer below the first layer in the film thickness direction. The third layer is a layer containing the first material. The metal wiring according to claim 8.

10. A transistor in which at least one electrode among the gate electrode, source electrode, and drain electrode is formed of the metal wiring described in claim 1 or 8.

11. An electronic device comprising the transistor described in claim 10.

12. A method for manufacturing metal wiring on a circuit board, A step of forming a first layer containing a first material on at least a portion of the substrate, The process of forming a crack in the first layer, The process includes the step of forming a second layer containing a second material inside and on the first layer so as to fill the cracks in the first layer. A method for manufacturing metal wiring.

13. The method for manufacturing a metal wiring according to claim 12, further comprising the step of etching the first layer before the step of forming the second layer.

14. After the step of forming the second layer described above, A step of forming a resist layer on the second layer, The process involves irradiating the resist layer with patterned light and developing it, A step of etching the first layer and the second layer after the development, A step after the etching process to remove the resist layer after development, A method for manufacturing metal wiring according to claim 12, comprising:

15. The step of forming the first layer is: A step of forming a resist layer on the substrate, The process involves irradiating the resist layer with patterned light and developing it, The process includes forming a first material layer containing the first material on the substrate that is exposed after development, The method for manufacturing metal wiring according to claim 12.

16. The method for manufacturing a metal wiring according to claim 12, wherein the first material comprises nickel and phosphorus.

17. The method for manufacturing a metal wiring according to claim 12, wherein in the step of forming the first layer, a layer containing nickel and phosphorus is formed on at least a portion of the substrate by electroless plating.

18. The method for manufacturing metal wiring according to claim 12, wherein the second material comprises gold or copper.

19. The method for manufacturing a metal wiring according to claim 12, wherein in the step of forming the second layer, a substitution gold plating bath or a substitution copper plating bath is brought into contact with the first layer having the cracks to form the second layer containing gold or copper.

20. The method for manufacturing metal wiring according to claim 12, wherein the substrate is flexible.

21. The method for manufacturing a metal wiring according to claim 12, wherein the substrate is made of a resin material.

22. The method for manufacturing metal wiring according to claim 12, wherein the substrate is in the form of a sheet.

23. In the process of forming the aforementioned crack, A method for manufacturing a metal wiring device according to claim 12, wherein the crack is formed by transporting the substrate using a dancer roller mechanism or a rolling roller mechanism.

24. The method for manufacturing a metal wiring according to claim 12, wherein the phosphorus content of the first layer is less than the nickel content.

25. The method for manufacturing a metal wiring according to claim 12, wherein the metal wiring corresponds to a circuit pattern for an electronic device.

26. A method for manufacturing a transistor, comprising the step of forming at least one electrode among a gate electrode, a source electrode, and a drain electrode by the method for manufacturing metal wiring described in claim 12.

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