Flexible circuit board and chip package including the same

Abstract

To provide a flexible circuit board for all-in-one COF capable of mounting a plurality of chips on one substrate, a chip package including the same, and an electronic device including the flexible circuit board.SOLUTION: A flexible circuit board according to an embodiment of the present invention includes: a substrate; a first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface opposite the first surface of the substrate; a first dummy pattern part disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed; a first protective layer disposed on the first wiring pattern layer; and a second protective layer disposed on the second wiring pattern layer and the first dummy pattern part. At least a part of the first dummy pattern part overlaps with the first wiring pattern layer in a vertical direction.SELECTED DRAWING: Figure 5a

Description

【Technical Field】 【0001】 The present invention relates to a flexible circuit board for all-in-one COF and a chip package including the same. Specifically, the present invention is a flexible circuit board on which different types of chips can be mounted on one substrate and a chip package including the same. 【0002】 【Background Art】 【0003】 Recently, various electronic products have become thinner, smaller, and lighter. Along with this, various studies have been conducted to mount semiconductor chips at high density in a narrow area of electronic devices. Among them, the COF (Chip On Film) method uses a flexible substrate, so it can be applied to both flat panel displays and flexible displays. 【0004】 That is, the COF method has attracted attention in that it can be applied to various wearable electronic devices. Also, since the COF method can implement fine pitches, it can be used to implement a high-resolution (QHD) display by increasing the number of pixels. 【0005】 COF (Chip On Film) is a method of mounting a semiconductor chip on a flexible circuit board in the form of a thin film. For example, the semiconductor chip can be composed of an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip. 【0006】 <000003y> 【0007】 On the other hand, recently, in order to cope with the trend of miniaturization, thinning, and weight reduction of electronic products, high-density semi- As a mounting technology for conductive chips, various COF (Chip-on-Fiber) packaging technologies using flexible substrates are being developed. It has been proposed. [Overview of the Initiative] [Problems that the invention aims to solve] 【0007】 This invention provides an all-in-one flexible COF that allows multiple chips to be mounted on a single substrate. We will provide a circuit board, a chip package including the same, and an electronic device including the same. Let's assume that. 【0008】 This invention is an all-in-one solution that can remove pinholes that occur during solder resist printing. Flexible circuit board for COF and chip package including the same, and electronics including the same We will try to provide a device. 【0009】 This invention allows for the design of a product while taking into account the solder resist printing process. Flexible circuit board for in-one COF and chip package including the same, and including the We aim to provide electronic devices. 【0010】 The technical challenges to be addressed in the proposed embodiment are limited to the technical challenges mentioned above. This is not limited to, and other technical challenges not mentioned may be proposed in the following description. The examples should be clearly understandable to anyone with ordinary knowledge in the technical field to which they belong. [Means for solving the problem] 【0011】 A flexible circuit board according to an embodiment of the present invention comprises a substrate and a first surface of the substrate. A first wiring pattern layer is provided, and a second surface of the substrate opposite to the first surface is provided. The second wiring pattern layer, and the first dummy pattern portion disposed on the second surface of the substrate where the second wiring pattern layer is not disposed, and disposed on the first wiring pattern layer The first protective layer, and the second protective layer disposed on the second wiring pattern layer and the first dummy pattern portion, and at least a part of the first dummy pattern portion overlaps the first wiring Pattern layer in a vertical direction. 【0012】 Also, a second dummy pattern portion disposed on the first surface of the substrate where the first wiring pattern layer is not disposed, and at least a part of which overlaps the second wiring pattern layer in a vertical direction Is further included. 【0013】 【0014】 Also, the first dummy pattern portion has the same width as the first wiring pattern layer, and one end is Disposed on the same vertical line as one end of the first wiring pattern layer. 【0015】 Also, the first dummy pattern portion has a wider width than the first wiring pattern layer, and one end Is closer to the end of the substrate than one end of the first wiring pattern layer. 【0016】 ]](The first surface is the upper surface of the substrate, the second surface is the lower surface of the substrate, and the first dummy pattern portion is disposed on the leftmost side of the first wiring pattern layer 【0017】 Also, the second dummy pattern portion is disposed on the right side of the second wiring pattern layer disposed on the rightmost side of the second wiring pattern layer Is disposed on the right side of the second wiring pattern layer. Also, a first plating layer containing tin (Sn) disposed on the first wiring pattern layer, and the first 【0018】It further includes a second plating layer containing tin (Sn) disposed on the two wiring pattern layers, and the first The dummy pattern portion includes a first dummy pattern layer corresponding to the second wiring pattern layer and the a second dummy pattern layer corresponding to the second plating layer, and the second dummy pattern portion a third dummy pattern layer corresponding to the first wiring pattern layer and the a fourth dummy pattern layer corresponding to the first plating layer. 【0018】 On the other hand, the package according to the embodiment, the flexible circuit board for all-in-one COF, a substrate, a conductive pattern portion disposed on the substrate, a dummy a pattern portion, a protection portion disposed on an area above the conductive pattern portion and above the dummy pattern portion, The conductive pattern portion includes a first wiring pattern layer disposed on the first surface of the substrate, a first plating layer disposed on the first wiring pattern layer, a second wiring pattern layer disposed on the second surface of the substrate opposite to the first surface of the substrate, and the a second plating layer disposed on the second wiring pattern layer, and the tin (Sn) content of the plating layer in the first open region of the protection layer is more than the tin (Sn) content of the plating layer in the second open region of the protection layer, a first chip disposed in the first open region and a second chip disposed in the second open region, and the dummy pattern portion is disposed on the second surface of the substrate where the second wiring pattern layer is not disposed, and at least a first dummy pattern portion that at least partially overlaps the first wiring pattern layer in a vertical direction, and the [[ID=3,6]]a second dummy pattern portion disposed on the first surface of the substrate where the first wiring pattern layer is not disposed, and at least partially overlaps the second wiring pattern layer in a vertical direction. 【0019】 Furthermore, the first surface is the upper surface of the substrate, and the second surface is the lower surface of the substrate. The first dummy pattern section is the first wiring pattern layer located on the leftmost side. Located to the left of the wiring pattern layer, the second dummy pattern section is the second wiring pattern It is positioned to the right of the second wiring pattern layer, which is located on the far right of the layer. 【0020】 Furthermore, the first chip is a drive IC chip, and the second chip is diode chips, power IC chips, touch sensor IC chips, MLCC chips, B All-in-one C includes at least one of the following: GA chip and chip capacitor. Includes flexible circuit board for OF (Optical Flight). 【0021】 On the other hand, an electronic device according to an embodiment of the present invention comprises a substrate and a conductive material disposed on the substrate. Conductive pattern portion, dummy pattern portion disposed on the substrate, and conductive pattern portion A protective portion is partially disposed in a region on the base, and the conductive pattern portion is the base A first wiring pattern layer is placed on the first surface of the board, and a first wiring pattern layer is placed on the first wiring pattern layer A first plating layer is formed, and a second plating layer is placed on the second surface of the substrate opposite to the first surface. It includes a wiring pattern layer and a second plating layer disposed on the second wiring pattern layer, The tin (Sn) content of the plating layer in the first open region of the protective layer is the first open region of the protective layer. All-in-one containing a higher amount of tin (Sn) than the tin (Sn) content of the plating layer in the open region. A flexible circuit board for COF and one end of the all-in-one flexible circuit board The connected display panel and the one end of the all-in-one flexible circuit board The dummy pattern section includes a main board connected to the other end opposite to the front The second wiring pattern layer is placed on the second surface of the substrate where it is not located, and at least A first dummy pattern portion, in part, overlaps the first wiring pattern layer in a perpendicular direction, and the Displaced on the first surface of the substrate where no wiring pattern layer is arranged, at least It includes a second dummy pattern portion that partially overlaps the second wiring pattern layer in a perpendicular direction. 【0022】 Furthermore, the first connection portion and the other portion are located on the one region and the other region of the conductive pattern portion, respectively. A second connection part is positioned, and a first chip is positioned on the first connection part, and the second connection part The second chip is placed on top. 【0023】 Furthermore, the display panel and the main board are arranged to face each other, The all-in-one flexible circuit board includes the display panel and the main board. It is folded and positioned between them. [Effects of the Invention] 【0024】 According to an embodiment of the present invention, a first chip and a second chip of different types are combined into one An all-in-one CO2 that can be mounted on flexible circuit boards and offers improved reliability. We can provide a flexible circuit board chip package for F. 【0025】 Furthermore, according to the embodiment of the present invention, a flexible circuit for an all-in-one COF is provided. The display panel and the main board are directly connected via a circuit board, and the power generated from the display panel is generated from the display panel. The size and thickness of the flexible circuit board used to transmit the signal to the main board have been reduced. This allows for expansion of space for other components and / or battery space. It is possible. 【0026】 Furthermore, according to the embodiment of the present invention, the connection of multiple PCBs (printed circuit boards) is Since it is not required, the convenience of the process and the reliability of the electrical connection are improved, thereby, All-in-one flexible cable for COF, suitable for electronic devices with high-resolution display sections. We can provide a sible circuit board. 【0027】 Furthermore, according to the embodiment of the present invention, a circuit pattern arranged on the first surface of the substrate corresponds to A dummy pattern is placed on the second surface of the substrate, and the second surface of the substrate is arranged in such a way. By arranging a dummy pattern on the first surface of the substrate to correspond to the path pattern, Solder resist generated during printing of solder resist on the first or second surface of the substrate This can solve problems such as uneven coating and pinholes. [Brief explanation of the drawing] 【0028】 [Figure 1a] This is a cross-sectional view of an electronic device equipped with a display section including a conventional PCB. [Figure 1b] This is a cross-sectional view of the PCB shown in Figure 1a in a folded form. [Figure 1c] This is a plan view of the PCB shown in Figure 1a in a folded form. [Figure 2a] This is a cross-sectional view of an electronic device equipped with a display section including a flexible circuit board for an all-in-one COF according to an embodiment. [Figure 2b]Figure 2a is a cross-sectional view of the all-in-one COF flexible circuit board in a bent form. [Figure 2c] Figure 2a is a plan view of the all-in-one COF flexible circuit board in a folded form. [Figure 3a] This is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one COF according to an embodiment. [Figure 3b] This is another cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one COF according to an embodiment. [Figure 4a] This is a cross-sectional view of a flexible circuit board that does not include a dummy pattern, relating to a comparative example. [Figure 4b] This is a cross-sectional view of a flexible circuit board including a lower dummy pattern portion DP1 according to an embodiment of the present invention. [Figure 5a] Figure 4b is a diagram showing various modified examples of the lower dummy pattern section DP1. [Figure 5b] Figure 4b is a diagram showing various modified examples of the lower dummy pattern section DP1. [Figure 5c] Figure 4b is a diagram showing various modified examples of the lower dummy pattern section DP1. [Figure 5d] Figure 4b is a diagram showing various modified examples of the lower dummy pattern section DP1. [Figure 6] This is a drawing showing the upper dummy pattern section DP2 according to an embodiment of the present invention. [Figure 7a] This is another cross-sectional view of the flexible circuit board for a double-sided all-in-one COF according to the embodiment. [Figure 7b] Figure 7a is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one COF. [Figure 8] This is another cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one COF according to an embodiment. [Figure 9]This is an enlarged cross-sectional view of one area of ​​a flexible circuit board for a double-sided all-in-one COF according to an embodiment. [Figure 10] Figure 7a is a plan view of the double-sided all-in-one flexible circuit board for COF. [Figure 11] Figure 7a is a bottom view of the double-sided all-in-one flexible circuit board for COF. [Figure 12a] Figure 7b is a schematic plan view of a chip package including a flexible circuit board for a double-sided all-in-one COF. [Figure 12b] Figure 7b is a schematic plan view of a chip package including a flexible circuit board for a double-sided all-in-one COF. [Figure 13a] Figure 7b is a diagram illustrating the process of manufacturing a chip package containing the double-sided all-in-one COF flexible circuit board shown in Figure 7a. [Figure 13b] Figure 7b is a diagram illustrating the process of manufacturing a chip package containing the double-sided all-in-one COF flexible circuit board shown in Figure 7a. [Figure 14a] Figure 7b is a diagram illustrating the process of manufacturing a chip package containing the double-sided all-in-one COF flexible circuit board shown in Figure 7a. [Figure 14b] Figure 7b is a diagram illustrating the process of manufacturing a chip package containing the double-sided all-in-one COF flexible circuit board shown in Figure 7a. [Figure 15a] Figure 7b is a diagram illustrating the process of manufacturing a chip package containing the double-sided all-in-one COF flexible circuit board shown in Figure 7a. [Figure 15b] Figure 7b is a diagram illustrating the process of manufacturing a chip package containing the double-sided all-in-one COF flexible circuit board shown in Figure 7a. [Figure 16] Figure 15 is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one COF. [Figure 17] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Figure 18] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Figure 19a] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Figure 19b] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Figure 19c] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Figure 20] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Figure 21] These are drawings of various electronic devices, including flexible circuit boards for all-in-one COF (Chip-on-Fiber) systems. [Modes for carrying out the invention] 【0029】 In the description of the examples, each layer, region, pattern or structure is a substrate, each layer, region, pack The statement that it is formed "on" or "under" a do or pattern is directly ( This includes those formed directly or through other layers. Criteria above or below each layer. This will be explained based on the drawings. 【0030】 Furthermore, if one part is said to be "connected" to another part, this is called "direct connection." This applies not only when such a connection is made, but also when other components are placed in between to "indirectly connect" them. This also includes combinations. Furthermore, when a part "includes" a certain component, this is especially true in contrast to the opposite. Unless otherwise stated, the provision is not to exclude other components, but rather to further include other components. It means that it is possible. 【0031】 In the drawings, the thickness and size of each layer, area, pattern, or structure are described clearly and For convenience, the dimensions may be altered, and therefore do not reflect the actual size. 【0032】 The embodiments of the present invention will be described in detail below with reference to the attached drawings. 【0033】 Refer to Figures 1a to 1c to explain the PCB (printed circuit board) related to the comparative example. . 【0034】 An electronic device having a display unit transmits the display panel signals to the main board. To transmit the signal, at least two PCBs are required. 【0035】 The electronic device including the display unit in the comparative example contains at least two PCBs. It is possible to become. 【0036】 The electronic device including the display section in the comparative example is the first PCB10 and the second PCB2 It can contain 0. 【0037】 The first PCB10 can consist of an FPCB (Flexible Printed Circuit Board). Specifically, the first PCB10 consists of an FPCB for COF (Chip On Film). This is possible. The first PCB10 is made from a COF FPCB on which the first chip C1 is mounted. It is possible. More specifically, the first PCB10 is a drive IC chip This can consist of an FPCB for COF to position the COF. 【0038】 The second PCB20 may consist of an FPCB. Specifically, the second PCB2 0 is from the FPCB for arranging a second chip C2 of a different type from the first chip C1. It can become so. Here, the second chip C2 is the drive IC chip. Other components include chips other than the drive IC chip, semiconductor elements, and so This refers to various chips that are placed on top of FPCBs, such as ketches, for electrical connection. Yes, it is possible. The second PCB20 is made from an FPCB for arranging multiple second chips C2. For example, the second PCB20 can have multiple second chips C of different types. It can consist of an FPCB for positioning 2a and C2b. 【0039】 The first PCB 10 and the second PCB 20 may have different thicknesses from each other. The thickness of the second PCB20 is less than the thickness of the first PCB10. This is possible. For example, the first PCB 10 has a thickness of approximately 20 μm to 100 μm. The second PCB20 can have a thickness of approximately 100 μm to 200 μm. For example, the sum of the thicknesses of the first PCB10 and the second PCB, t1, is 200 μm~2 It can have a thickness of 50 μm. 【0040】 The electronic device equipped with a display unit according to the comparative example includes a display panel and a main body Since the first and second PCBs are required between the layers, the overall thickness of the electronic device increases. Specifically, the electronic device equipped with a display unit according to the comparative example is vertical Since stacked first and second PCBs are required, the overall thickness of the electronic device increases. This will happen. 【0041】 The first PCB 10 and the second PCB 20 are formed by different processes. For example, the first PCB 10 may be manufactured by a roll-to-roll process. The second PCB20 may be manufactured using a sheet method. 【0042】 On the first PCB10 and the second PCB20, there are different types of chips. The spacing (pitch) of the conductive pattern sections where the chips are positioned and connected to each chip is They may be different from each other. For example, the conductive pattern portion placed on the second PCB 20 The spacing (pitch) is the spacing (pitch) of the conductive pattern portion placed on the first PCB 10. Larger gaps can be made. For example, conductive materials placed on the second PCB 20 The spacing (pitch) of the patterned portion is 100 μm or more, and is placed on the first PCB 10. The spacing (pitch) of the conductive patterned portions may be less than 100 μm. 【0043】 Specifically, the first P has conductive pattern portions arranged at fine intervals (fine pitch). CB10 is manufactured through a roll-to-roll process, resulting in an efficient process and reduced process costs. It can be made possible. On the other hand, it has conductive patterned parts arranged at intervals of 100 μm or more. Since the aforementioned second PCB20 is difficult to handle in a roll-to-roll process, a sheet process is used. It was common practice to do so. 【0044】 Since the first and second PCBs in the comparative example are formed by different processes, the process efficiency is It decreases. 【0045】 Furthermore, the chip packages including the flexible circuit board in the comparative example are of different types. Due to the difficulty of the process of placing the chips on a single substrate, separate first and second PCs are used. B is required. 【0046】 Furthermore, the chip packages including the flexible circuit board in the comparative example are of different types. There is a problem in that it is difficult to connect these chips on a single circuit board. 【0047】 Furthermore, the flexible circuit board in the comparative example has an upper circuit pattern and a lower circuit pattern. The design takes into account only the respective signal transmission characteristics. That is, the frame according to the comparative example A flexible circuit board has a protective layer (e.g., solder resist) placed on the outermost layer of the board. Without considering the reliability of the printing process, the upper circuit pattern and lower circuit pattern Design the turn. Therefore, the flexible circuit board according to the comparative example has the protective layer, Pinholes caused by the positional difference between the upper circuit pattern and the lower circuit pattern during the printing process There are problems that arise from this. 【0048】 On the other hand, the first and second PCBs are positioned between the conventional display panel and the main board. It will be done. 【0049】 To control, process, or transmit R, G, and B signals generated from the display panel 30. The first PCB 10 is connected to the display panel 30, and the first PCB 10 is again connected to the second The second PCB20 is connected to PCB20, and the second PCB20 is connected to the main board 40. 【0050】 One end of the first PCB 10 is connected to the display panel 30. The flannel 30 is connected to the first PCB 10 by the adhesive layer 50. 【0051】 The other end of the first PCB 10, opposite to the aforementioned end, is connected to the second PCB 20. The first PCB 10 is connected to the second PCB 20 by the adhesive layer 50. 【0052】 One end of the second PCB 20 is connected to the first PCB 10, and the second PCB 20 The other end opposite to the aforementioned end is connected to the main board 40. The second PCB 20 is, The main board 40 is connected by the adhesive layer 50. 【0053】 An electronic device equipped with a display unit according to a comparative example includes the display panel 30 and Between the first PCB10, between the first PCB10 and the second PCB20, the second PC A separate adhesive layer 50 is required between B20 and the main board 40. That is, The electronic device with a display section according to the comparative example requires a large number of adhesive layers, There is a problem in that the reliability of electronic devices is reduced due to poor bonding of the adhesive layer. Also, the top and bottom The adhesive layer placed between the connected first PCB10 and second PCB20 is electronic Increase the thickness of the device. 【0054】 Referring to Figures 1b and 1c, the first P, which serves as a housing, is located within the electronic device of the comparative example. This document describes CB10, the second PCB20, the display panel30, and the main board40. . 【0055】 Figure 1b is a cross-sectional view of the PCB in a folded form, and Figure 1c is This is a plan view of the lower surface of Figure 1b. 【0056】 The display panel 30 and the main board 40 are arranged facing each other. Between the display panel 30 and the main board 40, which are arranged in this manner, there is a bend. The first PCB 10, which includes the bending region, is placed there. 【0057】 The first PCB 10 has one region that is folded and the first chip in the region that is not folded P C1 is positioned. 【0058】 Furthermore, the second PCB 20 is positioned opposite the display panel 30. The second chip C2 is positioned in the non-bendable region of the second PCB20. 【0059】 Referring to Figure 1c, the comparative example requires multiple substrates, so the length L in one direction is 1 is the sum of the lengths of the respective first PCB10 and second PCB20. The length L1 in one direction of the first PCB10 and the second PCB20 is It is the sum of the length of the shorter side of the first PCB and the length of the shorter side of the second PCB20. For example, the first P The length L1 of CB10 and the second PCB20 in one direction is 30mm to 40mm. It is possible. However, depending on the type of chip and electronic device to be implemented, The length L1 in one direction of the first PCB10 and the second PCB20 can vary in size. It is possible to have. 【0060】 The electronic device in the comparative example requires multiple PCBs, so to mount other components... The space for the main unit or for locating the battery 60 is reduced. 【0061】 Recently, electronic devices such as smartphones have been focusing on user convenience and security. To enhance it, components with various functions are added. For example, smartphones Electronic devices such as smartwatches have multiple camera modules (dual cameras). It may be equipped with modules, and may have a variety of functions such as iris recognition and VR (Virtual Reality). Additional components have been added. Therefore, securing space for mounting these additional components is important. be. 【0062】 Furthermore, a variety of electronic devices, including wearable devices, offer user convenience. To improve performance, an increase in battery space is required. 【0063】 Therefore, replacing multiple PCBs used in existing electronic devices with a single PCB. Therefore, to make space for mounting new components or to increase the size of the battery The importance of securing space is becoming apparent. 【0064】 The electronic device in the comparative example has a first chip and a second chip of different types, respectively It is placed on the separate first PCB10 and second PCB30. The thickness of the adhesive layer 50 between the two PCBs 30 and the thickness of the second PCB 30 are determined by the electronic device There was a problem with increasing the thickness. 【0065】 Furthermore, the size of the second PCB30 is used to accommodate the battery space or other components. There was a problem with the reduction in available space. 【0066】 Furthermore, poor bonding of the first and second PCBs can lead to problems that reduce the reliability of electronic devices. there were. 【0067】 The embodiment addresses these problems by enabling the mounting of multiple chips on a single substrate. A new structure all-in-one flexible circuit board for COF and a chip pack including the same. A cage and an electronic device containing the same can be provided. The same figure for both the example and the comparative example. The surface symbols represent the same components, and explanations that overlap with the comparative examples mentioned earlier will be omitted. 【0068】 Refer to Figures 2a to 2c, all-in-one flexible circuit board for COF according to the embodiment. This describes an electronic device that includes a plate. 【0069】 The electronic device according to the embodiment transmits the signal from the display panel to the main board. One PCB can be used for this purpose. Electronic data including the display unit according to the embodiment The PCB included in the vise can consist of one FPCB. Therefore, the embodiment is as follows: The flexible circuit board 100 for all-in-one COF (All in one chip on film) is The display is bent between the opposing display section and the main board. The I section and the main board can be connected. 【0070】 Specifically, the flexible flex for all-in-one COF (All in one chip on film) according to the example The double circuit board 100 is made from a single board for arranging multiple chips of different types. It is possible to become one. 【0071】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example Board 100 is a substrate for arranging first chips C1 and second chips C2 of different types. It can consist of 【0072】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example The thickness t2 of plate 100 can be 20 μm to 100 μm. For example, as shown in the example... All-in-one COF (All in one chip on film) flexible circuit board 100 thickness The thickness t2 can be 30 μm to 80 μm. For example, the all-in-one according to the example The thickness t2 of the flexible circuit board 100 for COF (All in one chip on film) is 50μ It can have a thickness of m~75μm. However, the type of chip for mounting, the electronic device Depending on the type of film, the all-in-one COF (All in one chip on film) application shown in the example The thickness of the flexible circuit board 100 can be designed to vary. 【0073】 Here, if the thickness t2 of the flexible circuit board 100 is less than 20 μm, A problem occurred where the bull circuit board 100 would break when it was bent (or twisted). There is a possibility that damage may occur due to heat generated in the implemented chip. There is. 【0074】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example The thickness t2 of plate 100 is 1 / 5 to 1 / 2 of the thickness t1 of the multiple first and second PCBs in the comparative example. It can have a thickness of about 2 / 2. That is, the all-in-one COF (All i) according to the example. The thickness t2 of the flexible circuit board 100 for (n one chip on film) is multiple compared to the comparative example. The thickness of the first and second PCBs can be approximately 20% to 50% of the thickness t1. For example, the flexible rotation for all-in-one COF (All in one chip on film) according to the embodiment. The thickness t2 of the substrate 100 is 25% of the thickness t1 of the multiple first and second PCBs in the comparative example. It can have a thickness of approximately 40%. For example, the all-in-one CO2 according to the example. The thickness t2 of the flexible circuit board 100 for F (All in one chip on film) is relative to the comparative example. Multiple first and second PCBs can have a thickness of approximately 25% to 35% of the total thickness t1. Cut. 【0075】 The electronic device equipped with a display unit according to the embodiment includes a display panel and a main body A single all-in-one COF (All in one chip on film) flexible cable between the two. Since a circuit board 100 is required, the overall thickness of the electronic device can be reduced. Specifically, the electronic device equipped with a display unit according to the embodiment requires a single-layer PCB. Therefore, the overall thickness of the electronic device is reduced. 【0076】 Furthermore, the example omits the adhesive layer 50 between the first and second PCBs included in the comparative example. It can include a chip package containing a flexible circuit board for all-in-one COF. This can reduce the overall thickness of electronic devices, including those containing this technology. 【0077】 Furthermore, in this embodiment, the adhesive layer 50 between the first PCB and the second PCB can be omitted. This eliminates problems caused by poor connection, thereby improving the reliability of electronic devices. It is possible. 【0078】 Furthermore, the bonding process for multiple PCBs can be eliminated, increasing process efficiency and reducing process costs. This is reduced. 【0079】 Furthermore, by replacing substrates managed in separate processes with a single process, process efficiency and product quality can be improved. The yield can be improved. 【0080】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example The plate 100 may include a bent region and a non-bent region. All-in-one according to the embodiment The flexible circuit board 100 for COF (All in one chip on film) includes a bending region. The display panel 30 and the main board 40, which are positioned opposite each other, are then connected. It is possible. 【0081】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example The non-bending region of the plate 100 is positioned opposite the display panel 30. Flexible circuit board for all-in-one COF (All in one chip on film) according to the example. The first chip C1 and the second chip C2 are placed on the non-bent region of the plate 100. , Flexible circuit base for all-in-one COF (All in one chip on film) according to the embodiment The board 100 enables stable mounting of the first chip C1 and the second chip C2. 【0082】 Figure 2c is a plan view of the lower surface of Figure 2b. 【0083】 Referring to Figure 2c, since the embodiment requires one substrate, the length L in one direction is... 2 is the length of one substrate. All in one chip o according to the embodiment The length L2 in one direction of the flexible circuit board 100 for n film is as follows according to the embodiment. The length of the short side of flexible circuit board 100 for Ruin-One COF (All in One Chip on Film) As an example, the All-in-One COF (All in one chip on film) according to the embodiment. The length L2 of the flexible circuit board 100 in one direction is 10 mm to 50 mm. This can be done. For example, for all-in-one COF (All in one chip on film) according to the example. The length L2 of the flexible circuit board 100 in one direction shall be between 10 mm and 30 mm. This can be done. For example, the all-in-one COF (All in one chip on film) according to the embodiment. The length L2 of the flexible circuit board 100 in one direction is 15 mm to 25 mm. Yes, it is possible. However, the examples are not limited to these, and the types of chips to be placed can also be used. And / or, depending on the number and type of electronic device, it can be designed to come in a variety of sizes. Yes. As shown in the example, by mounting multiple chips on a single substrate, flexible The length of the circuit board can be reduced to 50 mm or less. The length of the flexible circuit board can be reduced to 10 If the size is reduced to less than a millimeter, the design freedom of the numerous chips to be implemented will decrease, and the spacing between chips will also decrease. Because the space is narrow, it can affect the interelectrical characteristics. 【0084】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example The length L2 of the plate 100 in one direction is the same as the length of the multiple first and second PCBs in the comparative example. The length can be about 50% to 70% of the length L1 in the example. The flexible circuit board 100 for all-in-one COF (All in one chip on film) The length L2 in one direction is the length in one direction of the multiple first and second PCBs in the comparative example. It can have a length of approximately 55% to 70% of L1. All-in-one according to the example. Length in one direction of the flexible circuit board 100 for COF (All in one chip on film) L2 is 60% to 7% of the length L1 in one direction of the multiple first and second PCBs in the comparative example. It can have a length of approximately 0%. 【0085】 Therefore, the embodiment is an all-in-one COF (All in one chip on film) within an electronic device. The size of the chip package, including the flexible circuit board 100 for the battery, is reduced. The space for arranging 60 is expanded. Also, the all-in-one COF (All i The chip package, which includes a flexible circuit board 100 for one chip on film, has a flat area of This reduces the size, freeing up space for other components. 【0086】 The following describes an all-in-one COF (All in one chip on fi) according to an embodiment, with reference to the drawings. A flexible circuit board 100 for lm and its chip package are described below. 【0087】 Figure 3a is a cross-sectional view of a flexible circuit board according to the first embodiment of the present invention, and Figure 3b is a cross-sectional view of a flexible circuit board according to the first embodiment of the present invention. Figure 4a shows a modified example of the flexible circuit board of 3a, with the dummy pattern section of the comparative example being shown. Figure 4b is a cross-sectional view of a flexible circuit board that does not include the lower dummy according to an embodiment of the present invention. —These are cross-sectional views of the flexible circuit board including the pattern section DP1, and Figures 5a to 5d are from Figure 4. Figure 6 shows various modifications of the lower dummy pattern section DP1 shown in b, and Figure 6 is the main Figure 7a is a drawing showing the upper dummy pattern section DP2 according to an embodiment of the invention. Figure 7b is another cross-sectional view of the flexible circuit board for the double-sided all-in-one COF. Chip package including a flexible circuit board for double-sided all-in-one COF related to 7a This is a cross-sectional view, and Figure 8 shows a flexible circuit board for a double-sided all-in-one COF according to an embodiment. Another cross-sectional view of the chip package. 【0088】 Figures 3a, 3b, 4a, 4b, 5a, 5b, 5c, 5d, 6, 7a, Referring to Figures 7b and 8, the All-in-One COF (All in one chip on fi The flexible circuit board 100 for lm has electrode pattern portions on both sides and is double-sided all-in It can consist of a flexible circuit board for one COF. 【0089】 Flexible circuit board for all-in-one COF (All in one chip on film) according to the example The board 100 consists of a substrate 110, a wiring pattern layer 120 placed on the substrate 110, and Layer 130, upper dummy pattern section DP2, lower dummy pattern section DP1 and protective layer 14 It can contain 0. 【0090】 On one side of the substrate 110 according to the embodiment, a wiring pattern layer 120, a plating layer 130, and an upper layer After placing the Mie pattern section DP2 and the protective layer 140, on the other surface opposite to the one surface mentioned above Wiring pattern layer 120, plating layer 130, lower dummy pattern section DP1 and protective layer 140 It can be placed. 【0091】 That is, on one side of the substrate 110 according to the embodiment, an upper wiring pattern layer, an upper plating layer, and an upper The dummy pattern section DP2 and the upper protective layer are placed on the other surface opposite to the aforementioned surface. A wiring pattern layer, a lower plating layer, a lower dummy pattern section DP1, and a lower protective layer are arranged. It can be done. 【0092】 The upper wiring pattern layer may contain a metallic material corresponding to the lower wiring pattern layer. Therefore, process efficiency is improved. However, the examples are not limited to these, and other examples may be provided. It is, of course, possible to include conductive materials. 【0093】 The thickness of the upper wiring pattern layer may correspond to the thickness of the lower wiring pattern layer. Therefore, Process efficiency will improve. 【0094】 The upper plating layer may contain the same metallic material as the lower plating layer. Therefore, the process Efficiency is improved. However, the examples are not limited to these, and other conductive materials may be used. It can certainly be included. 【0095】 The thickness of the upper plating layer may correspond to the thickness of the lower plating layer. Therefore, process efficiency is improved. To rise. 【0096】 The upper dummy pattern section DP2 is located on the lower surface of the substrate 110, within the upper surface of the substrate 110. Positioned in the location corresponding to the lower wiring pattern layer, lower dummy pattern section DP1 This corresponds to the upper wiring pattern layer located on the upper surface of the substrate 110, which is part of the lower surface of the substrate. It is positioned in such a location. Therefore, in the present invention, in the printing process of the upper protective layer or the lower protective layer This solves the pinhole problem caused by the difference in height between the upper and lower parts of the substrate 110. This can be done, and the reliability of the PCB can be improved. 【0097】 The substrate 110 supports the wiring pattern layer 120, the plating layer 130, and the protective layer 140. It can consist of a support substrate. 【0098】 The substrate 110 may include a bent region and a region other than the bent region. The substrate 110 may include a bendable region and a non-bendable region other than the bendable region. ru. 【0099】 The substrate 110 can be made of a flexible substrate. This allows for partial bending. That is, the substrate 110 is made of flexible plastic. It may include a polyimide substrate. This is possible. However, the examples are not limited to polyethylene tere phthalate (polyethylene terephthalate), polyethylene naphthalate (polyethylene naphthalate) The substrate can be made of a polymer material such as phthalate. The flexible circuit board, including board 110, is equipped with a variety of curved display devices. It can be used in child devices. For example, a flexible circuit board including the substrate 110. Because of its excellent flexibility, it is used to mount semiconductor chips in wearable electronic devices. It is suitable for electronic devices including curved displays. ru. 【0100】 The substrate 110 can be made of an insulating substrate. That is, the substrate 110 can be made of various materials. It can consist of an insulating substrate that supports the wiring pattern. 【0101】 The substrate 110 can have a thickness of 20 μm to 100 μm. For example, the substrate The plate 110 can have a thickness of 25 μm to 50 μm. For example, the substrate 100 is It can have a thickness of 30 μm to 40 μm. The thickness of the substrate 100 is 100 μm. If it exceeds this, the overall thickness of the flexible circuit board will increase. If the thickness of 100 is less than 20 μm, the first chip C1 and the second chip C2 are processed simultaneously. It becomes difficult to place them. If the thickness of the substrate 110 is less than 20um, a large number of chips In the process of mounting the chips, the substrate 110 is susceptible to heat / pressure, and multiple chips are mounted simultaneously. It becomes difficult to place. Wiring is arranged on the substrate 110. The wiring is pattern It may also be a plurality of wires that have been converted. For example, on the substrate 110, the plurality of wires They are arranged at a distance from each other. That is, the wiring pattern layer 120 is arranged on one surface of the substrate 110. It is placed. 【0102】 The area of ​​the substrate 110 is larger than the area of ​​the wiring pattern layer 120. This can be done. Specifically, the planar area of ​​the substrate 110 is the planar area of ​​the wiring pattern layer 120. It can have a larger surface area. That is, on the substrate 110, the wiring pattern The wiring pattern layer 120 is partially arranged. For example, the lower surface of the wiring pattern layer 120 is The circuit board 110 is in contact with the circuit board 110, and the circuit board 110 is exposed between the multiple wirings. The turn layer 120 may contain a conductive material. 【0103】 The substrate 110 may include through holes. It may include holes. The plurality of through holes in the substrate 110 may be made by mechanical or chemical processes. They are formed individually or simultaneously by a specific process. For example, multiple throughs of the substrate 110 Through holes are formed by a drilling process or an etching process. As an example, the base The through-holes in the plate are formed through laser punching and desmearing processes. The desmearing process is a process of removing polyimido smear that has adhered to the inner surface of the through hole. This may also be the case. The desmearing process results in the inner surface of the polyimide substrate being straight and similar. It can have similar inclined surfaces. 【0104】 On the substrate 110 are a wiring pattern layer 120, a plating layer 130, and a dummy pattern section D. P1, DP2 and protective layer 140 are arranged. Specifically, on both sides of the substrate 110 Wiring pattern layer 120, plating layer 130, dummy pattern sections DP1, DP2 and protective layer 1 40 are arranged in order. At this time, the dummy pattern sections DP1 and DP2 are in front It has a height corresponding to the wiring pattern layer 120 and the plating layer 130. Preferably, In the first embodiment of the present invention, the dummy pattern portions DP1 and DP2 are the wiring pattern It is made of the same metallic material as the wiring pattern layer 120 and has a greater thickness than the wiring pattern layer 120. This is possible. Preferably, the dummy pattern sections DP1 and DP2 are the wiring pattern The thickness can be the sum of the thickness of the chrome layer 120 and the thickness of the plating layer 130. 【0105】 The wiring pattern layer 120 is subjected to evaporation, plating, sputtering, It is formed by at least one of the following methods (sputtering). 【0106】 As an example, the wiring layer for forming a circuit is created by sputtering followed by electroplating. It is formed. For example, a wiring layer for forming a circuit is formed by electroless plating. It can consist of a copper-plated layer. Alternatively, the wiring layer may be electroless plated and electrolytically plated. It can consist of a copper plating layer formed by plating. 【0107】 Next, after laminating the light film onto the wiring layer, exposure, development, and etching are performed. Through the molding process, the patterned design is applied to both sides of the flexible circuit board, namely the top and bottom surfaces. A line layer can be formed. Therefore, the wiring pattern layer 120 can be formed. ru. 【0108】 For example, the wiring pattern layer 120 can contain a metallic substance with excellent electrical conductivity. More specifically, the wiring pattern layer 120 may include copper (Cu). However, The examples are not limited to those shown, but may include copper (Cu), aluminum (Al), chromium (Cr), nickel, etc. Among the following, less than: kel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti), and their alloys. Of course, both can contain a single metal. 【0109】 The wiring pattern layer 120 is arranged with a thickness of 1 μm to 15 μm. For example, the wiring The pattern layer 120 is arranged with a thickness of 1 μm to 10 μm. For example, the wiring pattern layer 120 is arranged with a thickness of 2 μm to 10 μm. 【0110】 If the thickness of the wiring pattern layer 120 is less than 1 μm, Resistance increases. If the thickness of the wiring pattern layer 120 exceeds 10 μm, the fine pattern It becomes difficult to realize the concept. 【0111】 The via holes V1, V2, and V3 that penetrate the substrate 110 are filled with a conductive material. The conductive material filling the inside of the via hole corresponds to the wiring pattern layer 120. It can consist of a material or different conductive materials. For example, the inside of a beer hall is filled with The conductive materials used are copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), and silver (Ag). Contains at least one metal from among molybdenum (Mo), gold (Au), titanium (Ti), and alloys thereof. It is possible. The electrical signal of the conductive pattern portion CP on the upper surface of the substrate 110 is the same as the The conductive pattern portion CP on the lower surface of the substrate 110 is transmitted through the conductive material filling the ahole. It will be transmitted to. 【0112】 Next, a plating layer 130 is formed on the wiring pattern layer 120. The plating layer 130 may include a first plating layer 131 and a second plating layer 132. 【0113】 A first plating layer 131 is placed on the wiring pattern layer 120, and the first plating The second plating layer 132 is placed on top of the first plating layer 131. The second plating layer 132 is intended to prevent the formation of whiskers (whisker-kr00000374075b1). Therefore, the wiring pattern layer 1 is formed in two layers on top of the wiring pattern layer 120. Short circuits between the 20 patterns can be prevented. Also, the wiring pattern layer 120 Since two plating layers are placed on top, the bonding characteristics with the chip are improved. If the wiring pattern layer contains copper (Cu), the wiring pattern layer is directly connected to the first chip C1. It cannot be bound and requires a separate bonding process. On the other hand, the wiring If the plating layer placed on the pattern layer contains tin (Sn), the surface of the plating layer Since it is a pure tin layer, bonding with the first tip C1 becomes easy. At this time, the first tip The wire connected to the C1 tip is easily joined using only a pure tin layer, heat, and pressure. This can improve the accuracy of wire bonding and the convenience of the manufacturing process. 【0114】 The region in which the first plating layer 131 is placed is the region in which the second plating layer 132 is placed. It may correspond to the area. That is, the area in which the first plating layer 131 is placed is the area in which the second plating layer This may correspond to the area in which layer 132 is placed. 【0115】 The plating layer 130 may contain tin (Sn). For example, the first plating layer 131 The second plating layer 132 may contain tin (Sn). 【0116】 As an example, the wiring pattern layer 120 is made of copper (Cu), and the first plating layer 131 and The second plating layer 132 can be made of tin (Sn). When included, tin (Sn) has excellent corrosion resistance, thus preventing oxidation of the wiring pattern layer 120. It is possible. 【0117】 On the other hand, the material of the plating layer 130 has lower electrical conductivity than the material of the wiring electrode layer 120. i. The plating layer 130 can be electrically connected to the wiring electrode layer 120. 【0118】 The first plating layer 131 and the second plating layer 132 are formed of the same tin (Sn), or formed in a separate process. 【0119】 In the manufacturing process of the flexible circuit board according to the embodiment, a heat treatment process such as heat curing is included If so, diffusion of copper (Cu) in the wiring pattern layer 120 or tin (Sn) in the plating layer 130 occurs. Specifically, through the curing of the protective layer 140, diffusion of copper (Cu) in the wiring pattern layer 12 0 or tin (Sn) in the plating layer 130 occurs. As a result, in the first plating layer 131, the diffusion concentration of copper (Cu) decreases toward the surface of the second plating layer 132, so that the copper (Cu) content continuously decreases. On the other hand 【0120】 In the first plating layer 131, the tin (Sn) content continuously increases toward the surface of the second plating layer 132. Therefore, the uppermost part of the plating layer 130 can contain pure tin. That is, due to the chemical action at the lamination interface between the wiring pattern layer 120 and the plating layer 130, at least a part of the plating layer 130 can be composed of an alloy of tin and copper. The thickness of the alloy of tin and copper after curing the protective layer 140 on the plating layer 130 is greater than the thickness of the alloy of tin and copper after forming the plating layer 130 on the wiring pattern layer 120. 【0121】 That is, due to the chemical action at the lamination interface between the wiring pattern layer 120 and the plating layer 130, at least a part of the plating layer 130 can be composed of an alloy of tin and copper. The alloy of tin and copper contained in at least a part of the plating layer 130 has a chemical formula of Cu Sn and 0 < x + y < 12. For example, in the chemical formula, the sum of x and y is 4 ≤ x 【0122】 The alloy of tin and copper contained in at least a part of the plating layer 130 has a chemical formula of Cu x Sn y and has a chemical formula, and 0 < x + y < 12. For example, in the chemical formula, the sum of x and y is 4 ≤ x ​​​​+y ≤ 11. For example, the tin and copper alloy contained in the plating layer 130 is Cu3S It may include at least one of n and Cu6Sn5. Specifically, the first The layer 131 can consist of an alloy layer of tin and copper. 【0123】 Furthermore, the tin and copper content of the first plating layer 131 and the second plating layer 132 is relative. They may be different. The first plating layer 131 that is in direct contact with the copper wiring pattern layer is Note: The copper content is higher than that of the second plating layer 132. 【0124】 The second plating layer 132 has a higher tin content than the first plating layer 131. The second plating layer 132 may contain pure tin. Here, pure tin refers to a tin (Sn)-containing layer. Those containing 50 atomic percent or more, 70 atomic percent or more, 90 atomic percent or more This can mean that. In this case, elements other than tin can consist of copper. For example The second plating layer 132 may have a tin (Sn) content of 50 atomic percent or more. For example The second plating layer 132 may have a tin (Sn) content of 70 atomic percent or more. For example The second plating layer 132 may have a tin (Sn) content of 90 atomic percent or more. For example The second plating layer 132 may have a tin (Sn) content of 95 atomic percent or more. For example The second plating layer 132 may have a tin (Sn) content of 98 atomic percent or more. 【0125】 The plating layer in the example undergoes electrochemical migration by Cu / Sn diffusion development. (Electrochemical Migration Resistance) is prevented, blocking short-circuit failures caused by metal growth. It is possible. 【0126】 However, the embodiments are not limited thereto, and the plating layer 130 may be Ni / A u alloy, gold (Au), electroless nickel immersion gold (ENIG) , Ni / Pd alloy, or organic solderability preservative (OSP). Of course, any one of them can be included. 【0127】 The first plating layer 131 and the second plating layer 132 may have corresponding or different thicknesses. The total thickness of the first plating layer 131 and the second plating layer 132 can be 0 .3 μm to 1 μm. The total thickness of the first plating layer 131 and the second plating layer 132 can be 0.3 μm to 0.7 μm. The total thickness of the first plating layer 131 and the second plating layer 132 can be 0.3 μm to 0..5 μm. Any one of the first plating layer 131 and the second plating layer 132 can have a thickness of 0.05 μm to 0.15 μm or less. For example, any one of the first plating layer 131 【0128】 and the second plating layer 132 can have a thickness of 0.07 μm to 0.13 μm or less. 【0129】 After that, the protection part PP can be screen printed on the conductive pattern part CP. It can be achieved. The protective layer 140 can cover the plating layer 130 and prevent damage or peeling due to oxidation of the wiring pattern layer 120 and the plating layer 130. 【0130】 The protective layer 140 is partially disposed in a region excluding a region for electrically connecting to the display panel 30, the main board 40, the first chip C1, or the second chip C2. 【0131】 Thus, the protective layer 140 may partially overlap with the wiring pattern layer 120 and / or the plating layer 130. 【0132】 The area of the protective layer 140 can have an area smaller than the area of the substrate 110. The protective layer 140 is disposed in a region excluding the end of the substrate and can include a plurality of open regions. 【0133】 The protective layer 140 can include a first open region OA1 in the shape of a hole. The first open region OA1 may be a non-disposed region of the protective layer 140 for the wiring pattern layer 120 and / or the plating layer 130 to be electrically connected to the first chip C1. 【0134】 The protective layer 140 can include a second open region OA2 in the shape of a hole. The second open region OA2 may be a non-disposed region of the protective layer 140 for the wiring pattern layer 120 and / or the plating layer 130 to be electrically connected to the second chip C2. Thus, in the second open region OA2, the plating layer 130 is exposed to the outside. <00^00926> ​​​​​​​​​​​【0135】 In the second open region OA2, the copper content of the plating layer 130 is 50 atoms. It may be % or more. For example, the copper content in the plating layer 130 may be 60 atomic percent or less. It may be above. For example, the copper content in the plating layer 130 may be 60 atomic% to 80 It may be atomic percent. Specifically, the first... The copper content of the layer 131 may be 60 atomic% to 80 atomic%. 【0136】 The protective layer 140 is electrically connected to the main board 40 or the display panel 30. It does not need to be placed on a conductive pattern portion for being interconnected. The embodiment is as described above. Conductive power for electrically connecting to the inboard 40 or the display panel 30 It includes a third open area OA3 which is a non-placed area of ​​the protective layer 140 above the turn portion. Therefore, in the third open region OA3, the plating layer 130 is not exposed to the outside. It can be done. 【0137】 In the third open region OA3, the copper content of the plating layer 130 is 50 atoms. It may be % or more. Alternatively, in the third open region OA3, the plating layer 1 The copper content of 30 may be less than 50 atomic percent. The third open region OA3 is It can be located at the outer edge of the substrate from the first open region OA1. Also, the third The open region OA3 can be located at the outer edge of the substrate, relative to the second open region OA2. ru. 【0138】 The first open region OA1 and the second open region OA2 are the third open region It can be located in the central region of the substrate from region OA3. 【0139】 The protective layer 140 is disposed in the bending region. Therefore, the protective layer 140 can disperse the stress that may occur when folding. Therefore, the reliability of the all-in-one COF flexible circuit board according to the embodiment can be improved. 【0140】 The protective layer 140 can include an insulating material. The protective layer 140 can include various substances that are applied and then heated and cured to protect the surface of the conductive pattern portion. The protective layer 140 can be made of a resist layer. For example, the protective layer 140 can be made of a solder resist layer containing an organic polymer material. As an example, the protective layer 140 can include an epoxy acrylate-based resin. Specifically, the protective layer 140 can include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. However, the embodiment is not limited thereto, and the protective layer 140 can of course be any one of a photosolder resist layer, a coverlay, and a polymer material. 【0141】 The thickness of the protective layer 140 can be 1 μm to 20 μm. The thickness of the protective layer 140 can be 1 μm to 15 μm. For example, the thickness of the protective layer 140 can be 5 μm to 20 μm. When the thickness of the protective layer 140 exceeds 20 μm , the thickness of the all-in-one COF flexible circuit board will increase. When the thickness of the protective layer 140 is less than 1 μm, the all-in-one COF flexible ​​​​The reliability of the conductive pattern portion included in the circuit board decreases. 【0142】 In other words, the single-sided all-in-one flexible circuit board 100 for COF according to the embodiment is a board 110, conductive pattern section CP and dummy pattern section DP1, which are arranged on one side of the substrate. DP2 and the dummy pattern portions DP1, DP2 and the conductive pattern portion CP A protective portion PP may be included, formed by partially distributing a protective layer 140 in the region. 【0143】 The conductive pattern portion CP includes the wiring pattern layer 120 and the plating layer 130. It is possible. 【0144】 The protective portion PP is arranged on one region and the other region of the conductive pattern portion CP. It's not necessary. 【0145】 Then, the protective part PP is placed on top of the dummy pattern parts DP1 and DP2. ru. 【0146】 As a result, the conductive pattern portion CP has a conductive pattern on one region and on the other region. The substrate 110 between the pattern portion CP and the separated conductive pattern portion CP is exposed. On one region and the other region of the conductive pattern portion CP, there are a first connection portion 70 and a second connection portion Each of the 80s is arranged. Specifically, the conductive pattern in which the protective part PP is not arranged A first connecting portion 70 and a second connecting portion 80 are positioned on the upper surface of the CP portion. 【0147】 The first connecting portion 70 and the second connecting portion 80 may have different shapes from each other. For example, the first connecting portion 70 may have a hexahedral shape. Specifically, The cross-section of the first connecting portion 70 may include a rectangular shape. More specifically, the first connecting portion The cross-section of 70 may include a rectangular or square shape. For example, the second connecting portion 8 0 may include a spherical shape. The cross-section of the second connecting portion 80 may include a circular shape. Alternatively, the second connecting portion 80 may include a partially or entirely rounded shape. Yes, it is possible. For example, the cross-sectional shape of the second connecting portion 80 is flat on one side, and This may include objects that have a curved surface on one side opposite to the other side described. 【0148】 The first connecting portion 70 and the second connecting portion 80 can have different sizes from each other. The first connecting portion 70 may be smaller in size than the second connecting portion 80. . 【0149】 The widths of the first connecting portion 70 and the second connecting portion 80 can be different from each other. For example, the width D1 between the two sides of one first connecting part 70 is the width between the two sides of one second connecting part 80 It can have a width smaller than the width D2 between the sides. 【0150】 The first chip C1 is placed on the first connection portion 70. It may contain a conductive material. Therefore, the first connection part 70 is the first connection part 7 The first chip C1 is positioned on the upper surface of 0 and the first connection portion 70 is positioned on the lower surface of 0. The conductive pattern section CP can be electrically connected. 【0151】 The second chip C2 is positioned on the second connection portion 80. It may include a conductive material. Therefore, the second connection part 80 is the second connection part 8 The second chip C2 is positioned on the upper surface of 0 and the front is positioned on the lower surface of the second connection part 80. The conductive pattern section CP can be electrically connected. 【0152】 On the same side of the single-sided all-in-one COF flexible circuit board 100 according to the embodiment Two different types of chips, the first chip C1 and the second chip C2, are arranged therein. Specifically, On the same side of the single-sided all-in-one COF flexible circuit board 100 used in the example, A single first chip C1 and a plurality of second chips C2 may be arranged. This can improve the efficiency of the top packaging process. 【0153】 The first chip C1 may include a drive IC chip. 【0154】 The aforementioned second chip C2 refers to a chip other than the drive IC chip. This is possible. The second chip C2 is a socket other than the drive IC chip. This can mean a variety of chips including elements. For example, the second chip C2 is a Iode chips, power IC chips, touch sensor IC chips, MLCC chips, BGA It may include at least one of the following: a chip or a chip capacitor. 【0155】 Multiple second chips are placed on the all-in-one COF flexible circuit board 100 C2 consists of a diode chip, a power supply IC chip, a touch sensor IC chip, and an MLCC chip. This means that at least one of the following will be placed in multiples: a chip, a BGA chip, or a chip capacitor. It can be tasted. For example, all-in-one COF flexible circuit board 100 Multiple MLCC chips are placed on top of it. 【0156】 Furthermore, the second chip C2 includes a diode chip, a power supply IC chip, and a touch sensor I Includes at least two of the following: C chip, MLCC chip, BGA chip, and chip capacitor. It is possible to do so. That is, on the all-in-one COF flexible circuit board 100, Multiple second chips C2a, C2b of different types are arranged. For example, all-in-one On the flexible circuit board 100 for COF, there are diode chips, power supply IC chips, Among touch sensor IC chips, MLCC chips, BGA chips, and chip capacitors Either one second chip C2a and diode chip, power IC chip, touch sensor One of the following: IC chip, MLCC chip, BGA chip, or chip capacitor It may include a different second chip C2b. 【0157】 Specifically, on the all-in-one COF flexible circuit board 100, there are diodes. Chips, power IC chips, touch sensor IC chips, MLCC chips, BGA chips, Multiple instances of the second chip capacitor C2a, one of the chip capacitors, are arranged, and the diode Top, power IC chip, touch sensor IC chip, MLCC chip, BGA chip, chip Multiple second chip capacitors C2b, each different from one of the aforementioned chip capacitors, are arranged. This can include things like: a flexible circuit board for all-in-one COF. Above 100, there are multiple MLCC chips C2a and multiple power IC chips C2b. This is possible. For example, on the all-in-one COF flexible circuit board 100, It may include multiple MLCC chips C2a and multiple diode chips C2b. As an example, on the all-in-one COF flexible circuit board 100, multiple MLs It can include a CC chip C2a and multiple BGA chips C2b. 【0158】 In the embodiment, the type of the second chip is not limited to two, but the drive IC chip It goes without saying that all the various chips, excluding the top chip, can be included in the second chip. 【0159】 One end of the flexible circuit board 100 for the all-in-one COF is a display panel It is connected to the 30. One end of the all-in-one COF flexible circuit board 100 is The display panel 30 and the adhesive layer 50 are connected. Specifically, the adhesive layer 50 The display panel 30 is positioned on the upper surface, and the adhesive layer 50 is positioned on the lower surface. The flexible circuit board 100 for the all-in-one COF is placed there. The play panel 30 and the flexible circuit board 100 for the all-in-one COF are as follows: The two parts are bonded together, with the adhesive layer 50 in between. 【0160】 The other end opposite to the one end of the all-in-one COF flexible circuit board 100 This is connected to the main board 40. The flexible circuit board for the all-in-one COF. The other end of 100, opposite to the aforementioned one end, is connected to the main board 40 by an adhesive layer 50. Specifically, the main board 40 is placed on the upper surface of the adhesive layer 50, and the adhesive layer 50 The flexible circuit board 100 for the all-in-one COF is placed on the lower surface. The main board 40 and the flexible circuit board 100 for the all-in-one COF These are bonded together, with the adhesive layer 50 in between. 【0161】 The adhesive layer 50 may contain conductive material. It may be dispersed within the adhesive material. For example, the adhesive layer 50 may be an anisotropic conductive film. It can consist of a Room (ACF). 【0162】 As a result, the adhesive layer 50 is connected to the display panel 30 and the all-in-one CO To transmit electrical signals between the flexible circuit board 100 for F and the main board 40. Furthermore, it allows for the stable connection of other components. 【0163】 On the other hand, the dummy pattern sections DP1 and DP2 described above are arranged on the substrate 110. It is placed there. That is, the upper dummy pattern section DP2 is placed on the upper surface of the substrate 110, and the front The lower dummy pattern section DP1 is located on the lower surface of the substrate 110. 【0164】 The upper dummy pattern portion DP2 is located on the upper surface of the substrate 110, above the upper wiring pattern. It is placed in an area where no layer is present. Preferably, the upper dummy pattern portion DP2 is , the lower wiring pattern layer located on the lower surface of the substrate 110 and the upper part of the substrate that is vertically overlapped with the lower wiring pattern layer located on the lower surface of the substrate 110 It is placed on the area of ​​the surface where the upper wiring pattern layer is not located. 【0165】 The lower dummy pattern portion DP1 is located on the lower surface of the substrate 110, the lower wiring pattern portion It is placed in an area where no layer is placed. Preferably, the lower dummy pattern portion DP1 is , the upper wiring pattern layer located on the upper surface of the substrate 110 and the lower part of the substrate which is vertically overlapped with the upper wiring pattern layer of the substrate 110 It is placed on the area of ​​the surface where the upper wiring pattern layer is not located. 【0166】 That is, the upper wiring pattern layer and the lower wiring pattern layer arranged on the substrate 110 The positions are not necessarily corresponding, but rather depend on the function and number of signal wiring lines each has. They are designed and placed on each surface of the substrate 110. 【0167】 Therefore, the area in which the upper wiring pattern layer and the upper plating layer are arranged overlaps perpendicularly. The lower surface of the substrate 110 does not have the lower wiring pattern layer and the lower plating layer. It is also possible to have the lower wiring pattern layer and the lower plating layer perpendicular to the region where they are located. The upper surface of the substrate 110 that is superimposed on the upper wiring pattern layer and the upper plating layer It does not need to be placed. 【0168】 At this time, the protective layer 140 is placed on the substrate 110 by a printing process. The protective layer 140 is preferentially printed on one surface of the substrate 110, and the markings on that surface After the printing process is completed, a printing process is performed on the other side of the substrate 110. 【0169】 Here, with respect to the side of the substrate on which the protective layer 140 is printed first, This refers to the area on the opposite side where no wiring pattern layer / plating layer is placed, and the wiring pattern layer / A step is created when areas with plating layers coexist. If the step exists on the opposite side to the side on which the protective layer 140 is printed, the protective layer 1 In 40 printing processes, problems occurred such as the protective layer 140 not being placed and pinholes. This significantly impacts the reliability of the PCB. 【0170】 Therefore, in order to solve the above-mentioned problems, the present invention provides a solution that eliminates the step. On the opposite side of the surface on which the protective layer 140 is printed, there is a dummy pattern portion DP1 as described above. , forming DP2. 【0171】 At this time, the printing process for the protective layer 140 is preferentially applied to the upper surface of the substrate 110. When the procedure is performed, the dummy pattern sections DP1 and DP2 are located in the lower dummy pattern section D It may include only P1. That is, the protective layer 140 is printed on the upper surface of the substrate 110. In this case, the lower dummy pattern portion DP1 located on the lower surface of the substrate 110 creates a pattern. The unevenness is resolved, and as a result, the upper surface of the substrate 110 has a uniform height protective layer. Layer 140 is placed. 【0172】 Then, after the printing process of the protective layer 140 on the upper surface of the substrate 110 is completed, When the printing process for the protective layer 140 is performed on the lower surface of the substrate 110, The protective layer 140 formed on the surface has a step between the upper wiring pattern layer and the upper plating layer. The problem is resolved, and a uniform protective layer 140 is formed on the lower surface of the substrate 110. ru. 【0173】 However, of the two surfaces of the substrate 110, the surface on which the protective layer 140 is printed first is This will change depending on the manufacturing environment of the PCB. Therefore, in the present invention, Considering such a PCB manufacturing environment, the upper surface of the substrate 110 has the lower wiring pattern An upper dummy pattern portion DP2 is formed at a position corresponding to the layer and the lower plating layer, and the substrate On the lower surface of 110, at positions corresponding to the upper wiring pattern layer and the upper plating layer, the lower da A Mie pattern portion DP1 is formed. Here, the corresponding position is on one surface of the substrate 110. This refers to the position on the other side of the substrate that overlaps perpendicularly with the wiring pattern layer and plating layer. . 【0174】 The aforementioned dummy pattern sections DP1 and DP2 may consist of a single layer. Preferably, The dummy pattern sections DP1 and DP2 described above may include only the dummy pattern layer. The dummy pattern layer may contain the same metallic material as the wiring pattern layer. However, The present invention is not limited thereto, and the dummy pattern layer may be the wiring pattern The layer may contain a different material. For example, the dummy pattern layer may contain a nonmetallic material. It can include. 【0175】 In contrast, as shown in Figure 3b, the dummy pattern sections DP1 and DP2 This includes the first dummy pattern layer 151, the second dummy pattern layer 152, and the third dummy pattern It may include layer 153. 【0176】 The first dummy pattern layer 151 corresponds to the wiring pattern layer 120. The dummy pattern layer 151 contains the same metallic material as the wiring pattern layer 120. The dummy pattern layer 151 may be part of the wiring pattern layer 120. On the surface of the circuit board 110 are wiring patterns that are electrically connected to the chip and transmit signals. The first dummy layer 120 is placed together with the wiring pattern layer 120. A turn layer 151 can be formed. That is, a pattern layer can be formed on the substrate 110. This is achieved, and this involves a wiring pattern layer 120 and the first dummy for transmitting the electrical signal. - This will include a pattern layer 151. The first dummy pattern layer 151 is the wiring Unlike the turn layer 120, it does not transmit electrical signals, and thereby the wiring pattern layer 1 It is not electrically connected to 20. That is, the first dummy pattern layer 151 is not electrically connected to the substrate 11 On the surface of 0, in the area where the wiring pattern layer 120 is not placed, the wiring pattern It is arranged independently without being connected to layer 120. 【0177】 The second dummy pattern layer 152 is placed on top of the first dummy pattern layer 151. The second dummy pattern layer 152 may be part of the first plating layer 131. The third dummy pattern layer 152 is placed on top of the second dummy pattern layer 152. The third dummy pattern layer 153 may be part of the second plating layer 132. . 【0178】 In other words, the dummy pattern sections DP1 and DP2 in the present invention are the conductive pattern section CP Unlike the layered structure of the above, it can consist of a single layer. Also, the dummy pattern part DP1 and DP2 have a three-layer structure similar to the layer structure of the conductive pattern portion CP. It is possible. 【0179】 On the other hand, the protective layer 140 is placed on the dummy pattern portions DP1 and DP2. That is, the protective layer 140 is the surface of a part of the conductive pattern portion CP that is to be opened. The surface is exposed. And the dummy pattern parts DP1 and DP2 are not exposed to the outside. This also results in the protective layer 14 being placed on top of the dummy pattern sections DP1 and DP2. A 0 is placed there. 【0180】 On the other hand, referring to Figure 3a, the area of ​​the wiring pattern layer 120 is equal to the area of ​​the plating layer 130. This may correspond to the area of ​​the first plating layer 131 and the area of ​​the second plating layer 132. I can accommodate that. 【0181】 Referring to Figure 7, the area of ​​the wiring pattern layer 120 is different from that of the plating layer 130. This may also be the case. The area of ​​the wiring pattern layer 120 corresponds to the area of ​​the first plating layer 131. The area of ​​the first plating layer 131 may be different from the area of ​​the second plating layer 132. This is also acceptable. For example, the area of ​​the first plating layer 131 is larger than the area of ​​the second plating layer 132. It can have a large area. 【0182】 Referring to Figure 8, the area of ​​the wiring pattern layer 120 is different from that of the plating layer 130. That's fine. 【0183】 Referring to Figure 9, the area of ​​the wiring pattern layer 120 on one surface of the substrate 110 Unlike the plating layer 130, the wiring pattern layer is on the other side of the substrate 110. The area of ​​120 may correspond to the area of ​​the plating layer 130. 【0184】 The protective layer 140 is placed in direct contact with the substrate 110, or the wiring pattern It is placed in direct contact with the plate layer 120 or in direct contact with the first plating layer 131. They are positioned as such, or positioned in direct contact with the second plating layer 132. The protective layer 140 is positioned in direct contact with the dummy pattern portions DP1 and DP2. 【0185】 Referring to Figures 3a and 3b, the first plating layer 1 is placed on the wiring pattern layer 120. 31 is positioned, and the second plating layer 132 is formed on the first plating layer 131, The protective layer 140 is partially placed on the second plating layer 132. The protective layer 140 is placed over the pattern sections DP1 and DP2. 【0186】 Referring to Figures 7a and 7b, the first plating layer 13 is placed on the wiring pattern layer 120. 1 is placed, and the protective layer 140 is partially placed on the first plating layer 131. The second plating layer 132 is located on the area where the protective layer 140 is placed on the plating layer 131. It is placed in an area other than the designated zone. 【0187】 The first plating layer 131, which is in contact with the lower surface of the protective layer 140, is made from a copper and tin alloy layer. It can become. The second plating layer 132 in contact with the side surface of the protective layer 140 is pure It may contain tin. This prevents the protective layer from peeling off due to the formation of this part, and prevents the formation of whiskers. The adhesion strength of the protective layer can be increased. Therefore, the embodiment can include two plating layers. This allows us to provide highly reliable electronic devices. 【0188】 Furthermore, a single layer of tin plating 131 is placed on top of the wiring pattern layer 120, When a protective layer 140 is placed on top of two tin plating layers 131, the protective layer 140 is heat-cured. When the tin plating layer 131 is heated, copper is diffused into the tin plating layer 131. Therefore, the tin plating layer 131 becomes an alloy layer of tin and copper, and the first has an Au bump. There is a problem in that the chip mounting becomes weak. Therefore, the plating layer 130 in the embodiment is from the substrate The first plating layer 131 and the second plating layer 132 are required, in which the tin concentration increases continuously as the distance increases. It is required. 【0189】 Then, as shown in Figure 7a, the dummy pattern sections DP1 and DP2 are the wiring pattern The first plating layer 131 includes a single layer dummy pattern layer corresponding to the first plating layer 120. can. 【0190】 Furthermore, as shown in Figure 7b, the dummy pattern sections DP1 and DP2 are the wiring patterns A first dummy pattern layer 151 corresponding to layer 120, and a first dummy pattern layer 151 corresponding to the first plating layer 131. Two dummy pattern layers 152, and a third dummy pattern corresponding to the second plating layer 132. It may include layer 153. 【0191】 Referring to Figure 8, the first plating layer 131 is placed on the wiring pattern layer 120. Then, the protective layer 140 is partially placed on the first plating layer 131. The plating layer 132 is located in an area other than the area on the plating layer 131 where the protective layer 140 is placed. It will be placed in the area. 【0192】 At this time, the wiring pattern layer 120 consists of the first wiring pattern layer 121 and the second wiring pattern It may include a layer 122. That is, a plurality of wiring pattern layers are arranged on the substrate. It will be done. 【0193】 Also, although not shown in the diagram, between the substrate 110 and the first wiring pattern layer 121 , a metal seed to improve the adhesion between the substrate 110 and the first wiring pattern layer 121 Further layers may be included. In this case, the metal seed layer is formed by sputtering. It is possible. The metal seed layer may contain copper. 【0194】 The first wiring pattern layer 121 and the second wiring pattern layer 122 are mutually corresponding It can be formed by a series of or mutually different processes. 【0195】 The first wiring pattern layer 121 is made of copper sputtered to a thickness of 0.1 μm to 0.5 μm. The first wiring pattern layer 121 is formed by the upper and lower parts of the substrate and through holes. It is positioned on the inner surface. At this time, since the thickness of the first wiring pattern layer 121 is thin, it penetrates. The inner surfaces of the halls are separated from each other. 【0196】 Next, the second wiring pattern layer 122 is placed on top of the first wiring pattern layer 121. Furthermore, the second wiring pattern layer 122 is plated to completely cover the inside of the through-hole. To be satisfied. 【0197】 Since the first wiring pattern layer 121 is formed by sputtering, the substrate It has the advantage of excellent adhesion to 110 or the metal seed layer, but the manufacturing cost is high. Then, the second wiring pattern layer 1 is plated again on top of the first wiring pattern layer 121. By forming 22, manufacturing costs can be reduced. In addition, separate through-holes in the substrate Without filling the holes with conductive material, the second wiring pattern layer 121 is placed on top of the first wiring pattern layer 121. As the line pattern layer 122 is placed, copper is filled into the via holes, thus improving process efficiency. It improves performance. Furthermore, it prevents voids from forming within the via hole, resulting in a more reliable operation. To provide a flexible circuit board for Ruin One COF and an electronic device including the same. can. 【0198】 Furthermore, the dummy pattern sections DP1 and DP2 correspond to the first wiring pattern layer 121. The first dummy pattern layer 151 and the second dummy corresponding to the second wiring pattern layer 122 A pattern layer 152 and a third dummy pattern layer 153 corresponding to the first plating layer 131 This may include a fourth dummy pattern layer 154 corresponding to the second plating layer 132. 【0199】 Referring to Figure 9, a plurality of protective layers 140 are arranged on one surface of the substrate. The layers may include a first protective layer 141 and a second protective layer 142. 【0200】 For example, the first protective layer 141 is partially placed on one surface of the substrate, and the protective layer 14 The wiring pattern layer 120 is placed in an area other than the area where 1 is placed. 【0201】 The second protective layer 142 is placed on top of the protective layer 141. 2 covers the first protective layer 141 and the wiring pattern layer 120, and the first protective layer 14 It is placed in an area greater than 1. 【0202】 The protective layer 142 covers the upper surface of the first protective layer 141 and is opposite to the protective layer 141. It is placed on the corresponding area. The width of the second protective layer 142 is greater than that of the protective layer 141. It can have width. Therefore, the lower surface of the second protective layer 142 is the wiring pattern layer 120 and the first protective layer 141 can come into contact. Therefore, the second protective layer 14 2. Stress concentration occurs at the interface between the first protective layer 141 and the wiring pattern layer 120. This can be mitigated. Therefore, the flexible circuit for all-in-one COF according to the embodiment This can reduce the occurrence of film loss or cracking that may occur when the substrate is bent. 【0203】 In areas other than the area where the second protective layer 142 is placed, the plating layer 130 is placed. Specifically, in areas other than the area where the second protective layer 142 is placed, the wiring pattern The first plating layer 131 is placed on top of the first plating layer 120, and the first plating layer 131 is placed on top of the first plating layer 131. The second plating layer 132 is arranged in order. 【0204】 A wiring pattern layer 120 is placed on the other side of the substrate opposite to the one side mentioned above. The plating layer 130 is placed on top of the line pattern layer 120. A protective layer 140 is partially placed on top. 【0205】 The widths of the protective layer disposed on one side of the substrate and the protective layer disposed on the other side of the substrate are mutual They can be compatible, or they can be mutually different. 【0206】 The drawing shows a configuration where multiple protective layers are placed on only one side of the substrate, but the embodiment is as follows: The substrate may include multiple protective layers on each of its two sides. Of course, this is possible. Also, multiple or a single protective layer is placed on only one side of the substrate. Of course, that's good too. 【0207】 Furthermore, the structure of one or both sides of the substrate is shown in Figures 3a, 3b, 7a, 7b, and 8. The structures of the conductive pattern section and protective section, at least one of which are shown in Figure 9, can be combined and arranged in various ways. Of course. 【0208】 Referring to Figures 4a and 4b, the flexible circuit board in the comparative example is the substrate 110 An upper conductive pattern section CP is positioned on the upper surface, and a lower conductive pattern is positioned on the lower surface of the substrate 110. The conductive pattern portion CP is positioned. At this time, the upper conductive pattern portion CP and the lower conductive pattern The CP section is designed without considering the printing process of the protective layer 140. Therefore, The upper conductive pattern portion CP is present on the upper surface of the substrate 110, but the substrate 11 The lower surface of 0 may include a region where the lower conductive pattern portion CP does not exist. That is, On the lower surface of the substrate 110 that is perpendicular to the surface on which the upper conductive pattern portion CP is arranged, There is a region where the aforementioned lower conductive pattern portion CP is not placed. 【0209】 In this case, the flexible circuit board according to the comparative example has the bottom surface as the lower conductive pattern. In the region where the part CP exists, it becomes the lower surface of the lower conductive pattern part CP, and the lower conductive In areas where the pattern portion CP does not exist, this becomes the lower surface of the substrate 110. 【0210】 Then, in the step of printing the protective layer 140 on the upper surface of the substrate 110, the lower conductive pattern For the region that overlaps perpendicularly with the region where the CP portion is not placed, the bottom surface is the substrate 1 It is identical to the lower surface of 10, and therefore no pinhole development occurs. At this time, the lower part In a state in which the protective layer 140 is printed in an area where the conductive pattern portion CP does not exist, When the lower conductive pattern portion CP suddenly appears, the end of the lower conductive pattern portion CP is perpendicular to it. In the upper region of the substrate 110 that overlaps, a sudden step occurs, causing the development to jump up. Therefore, conventionally, the lower dummy pattern portion DP1 is the first end to be placed. The aforementioned splashing development occurs in the region, and as a result the protective layer 140 is positioned This would result in a pinhole problem that is not addressed. 【0211】 On the other hand, as shown in Figure 4b, in the present invention, the upper conductive pattern portion CP is arranged The lower dummy pattern portion DP1 is placed on the lower surface of the substrate 110 that overlaps perpendicularly with the area that was created. By arranging them in this manner, the occurrence of the aforementioned steps is eliminated, thereby forming a uniform protective layer 140. It is possible. 【0212】 The lower dummy pattern section DP1 is then connected to the upper conductive pattern section CP. They are arranged to correspond to this. That is, as shown in Figure 4b, the lower conductive pattern portion CP On the upper surface of the substrate 110 that overlaps perpendicularly with the area where the conductive pads are not located, there are three upper conductive pads. It can be confirmed that the turn section CP is located on the substrate 110. On the lower surface, corresponding to each of the three upper conductive pattern sections CP, there is a first lower section. Dummy pattern section DP1, second lower dummy pattern section DP1 and third lower dummy pattern Each of the DP1 units is positioned accordingly. 【0213】 On the other hand, the pinhole development of the protective layer 140 as described above occurs on the substrate on which the protective layer 140 is printed. The position where the first upper conductive pattern portion CP begins on the upper surface of 110, and the lower surface of the substrate This is because the starting positions of the first lower conductive pattern section CP are different. Preferably With respect to the left edge of the substrate, the position where the first upper conductive pattern portion CP begins is lower This is because the starting point of the partially conductive pattern section CP is far away. 【0214】 Therefore, pinhole development is performed at the position where the first upper conductive pattern portion CP begins and the This can also be solved by making the starting position of the lower conductive pattern section CP the same. 【0215】 That is, as shown in Figure 5a, when area A in Figure 3a is magnified, the upper surface of the substrate 110 Confirm that four upper conductive pattern sections CP are arranged, centered on the left edge. This is possible. And on the lower surface of the substrate 110, there are two lower conductive pads centered on the left end. It can be confirmed that the turn section CP is positioned. That is, the four upper conductions At the position of the upper conductive pattern section CP, which is the third position among the conductive pattern sections CP, the lower conductive It can be confirmed that the conductive pattern section CP starts first. 【0216】 Therefore, in the present invention, the first upper conductive pattern portion on the lower surface of the substrate 110 The lower dummy pattern section DP1 is placed on the region that overlaps perpendicularly with CP. At this time, the first The left end of the upper conductive pattern portion of the eye and the left end of the lower dummy pattern portion DP1 are in a phase They can be positioned on the same vertical line. That is, on the upper and lower surfaces of the substrate 110, The starting position of the first upper conductive pattern section CP and the lower dummy pattern section DP1 The starting position was made the same. And the region that overlaps perpendicularly with the second upper conductive pattern section CP. The lower conductive pattern section CP and the lower dummy pattern section DP1 are arranged above. It's fine. 【0217】 That is, below the substrate 110 which overlaps with the starting position of the first upper conductive pattern portion CP. If the lower conductive pattern portion CP is not placed on the surface, the first upper conductive portion The lower dummy pattern is placed only on the lower surface of the substrate 110 that overlaps with the starting position of the turn section CP. By arranging the DP1 section, the pinhole development problem can be solved. 【0218】 However, by using the aforementioned lower dummy pattern section DP1, the pinhole development is perfect. To solve this problem, the width of the lower dummy pattern portion DP1 is set to the width of the first upper conductive pattern. It is preferable to make it larger than the width of the CP section. 【0219】 In contrast to this, as shown in Figure 5b, the first upper conductive material of the lower surface of the substrate 110 The lower dummy pattern section DP1 is placed on the region that overlaps perpendicularly with the pattern section CP. At that time, the left end of the first upper conductive pattern portion and the lower dummy pattern portion DP1 The leftmost edges are not located on the same vertical line. That is, on the upper and lower surfaces of the substrate 110. , the starting position of the first upper conductive pattern section CP and the lower dummy pattern section DP1 The starting positions are not the same. In this case, under the above conditions, the pinhole development is To solve this, the first pattern placed on the surface on which the protective layer 140 is printed (conductive From the starting position of the pattern section CP and dummy pattern sections DP1 and DP2, the print The starting position of the pattern initially placed on the opposite side of the surface being treated needs to be early. 【0220】 Therefore, in the present invention, the substrate is located from the starting position of the first upper conductive pattern portion CP. The starting position of the lower dummy pattern section DP1, which is positioned above the bottom surface of 110, is set to be earlier. The lower surface of the substrate 110 that overlaps perpendicularly with the first upper conductive pattern portion CP The lower dummy pattern section DP1 is formed. 【0221】 That is, the distance from the left edge of the substrate 110 to the left edge of the lower dummy pattern portion DP1 The distance is from the left edge of the substrate 110 to the left edge of the first upper conductive pattern portion CP. Make it closer than that distance. 【0222】 In conclusion, from the left end of the first upper conductive pattern section CP to the lower dummy pattern A difference of the first interval a occurs up to the left end of the n section DP1. And the first upper conduction The width of the pattern portion CP has a first width b, and the width of the lower dummy pattern portion DP1 is the The second width c is wider than the first width b. 【0223】 According to this, in the present invention, by forming a minimum dummy pattern portion, the pinhole This can solve the problem of film development. 【0224】 Furthermore, as shown in Figure 5c, the lower dummy pattern portion DP1 has a third width d. Yes, it is possible. At this time, the third width d is the width of the first upper conductive pattern portion CP, and the second The width of the second upper conductive pattern portion CP, and the first upper conductive pattern portion CP This corresponds to the total width of the gaps between the second upper conductive pattern sections CP. 【0225】 That is, in Figure 4b, below the first upper conductive pattern portion CP, A first lower dummy pattern section DP1 having the same width as the conductive pattern section CP is formed, and Below the second upper conductive pattern section CP, the same as the second upper conductive pattern section CP A second lower dummy pattern section DP1 having a width was formed. 【0226】 In contrast to this, as shown in Figure 5c, the starting position of the first upper conductive pattern portion CP is Then, on the lower surface of the substrate 110 corresponding to the end position of the second upper conductive pattern portion CP, Only one conductive pattern portion CP can be formed. 【0227】 On the other hand, the dummy pattern portions DP1 and DP2 in the present invention have a variety of shapes. This is possible. That is, the dummy pattern portions DP1 and DP2 are the markings of the protective layer 140. Since it is placed at the bottom of the brush surface to eliminate the step, the thickness of the pattern part is conductive It is sufficient to maintain the same thickness as the pattern portion CP. Therefore, the dummy pattern portion DP1 and DP2 can have a bar shape that extends horizontally, as shown in Figure 5d(a). (b) It can have a bar shape that extends vertically, as in (c) and a circular shape. It can have, and can have a circular shape (ring shape) with an open center as in (d). , it can have a rectangular shape (ladder shape) with the center open, as in (e). The shapes of the dummy pattern portions DP1 and DP2 in the invention are not limited to these. It can be transformed into a variety of shapes, such as elliptical, sector, polygonal, and triangular. 【0228】 Furthermore, as shown in Figure 6, when area B in Figure 3a is enlarged, the upper surface of the substrate 110 shows the upper part The dummy pattern section DP2 is positioned. The formation position and pattern of the upper dummy pattern section DP2 The matter is the same as the formation position and conditions of the lower dummy pattern portion DP1. That is, the base Centered on the right edge of plate 110, in front of the starting position of the initially located lower conductive pattern section CP. If the starting position of the upper conductive pattern section CP is delayed, the lower conductive pattern section that was initially located The upper dummy pattern section DP2 is located on the upper surface of the substrate 110, which is perpendicular to the start of the turn section CP. This forms the upper dummy pattern portion DP2, which is formed by the lower conductive pattern. Multiple units are arranged to correspond to the CP in the n section, and unlike this, the lower conductive pattern that starts first One may be formed to correspond to the CP section. 【0229】 Refer to Figures 3a, 3b, 7a, 7b, 8, 10, and 11 to see the embodiments. First chip C mounted on a double-sided all-in-one COF flexible circuit board 100 1. The connection relationship between the display panel 30 and the main board 40 will be explained. 【0230】 The double-sided all-in-one COF flexible circuit board 100 according to the embodiment has through holes A substrate 100 including the through-hole and wiring parts arranged on both sides of the substrate including the through-hole A turn layer 120 and a first plating layer 131 placed on the wiring pattern layer 120, The second plating layer 132 is placed on the first plating layer 131, and the wiring pattern layer It may include a protective layer 140 that is partially positioned on top. 【0231】 The area in which the protective layer 140 is formed is the protective part PP. The conductive pattern portion in the region other than the protective portion PP where the protective layer is not formed. The CP is exposed to the outside. That is, it is kept on the open areas or conductive pattern areas of the protective layer. In the region where the protective part is not placed, the conductive pattern part CP is the first chip C1, the D It is electrically connected to the display panel 30 and the main board 40. 【0232】 Lead pattern portion and tape of the flexible circuit board for all-in-one COF according to the embodiment. The lead pattern portion does not need to overlap with the protective portion. That is, the lead pattern portion and the The test pattern area is located in an open region not covered by a protective layer. It can refer to the lead pattern section, and depending on the function, it can be divided into a lead pattern section and a test pattern section. They can be separated. 【0233】 The lead pattern portion comprises the first chip, the second chip, and the display panel. Alternatively, it can mean a conductive pattern section for connection to the main board. 【0234】 The test pattern section is a flexible circuit board for an all-in-one COF according to the embodiment. and conductive pattern section for checking for defects in the chip package product including therein It can mean that. 【0235】 The aforementioned lead pattern portion is divided into an inner lead pattern portion and an outer lead portion depending on its position. It can be distinguished as a turn portion. It is placed relatively close to the first chip C1, and A region of the conductive pattern that does not overlap due to the protective layer is referred to as the inner lead pattern. It is possible to do so. It is located relatively far from the first chip C1 and is covered by a protective layer. A region of the conductive pattern area that does not conform to this can be described as the outer lead pattern area. ru. 【0236】 Referring to Figures 3a, 3b, 7a, 7b, 8, 10, and 11, the embodiments are as follows: The all-in-one flexible circuit board 100 for COF has a first inner lead pattern Part I1, second inner lead pattern part I2, third inner lead pattern part I3 and 4. Inner lead pattern section I4 can be included. 【0237】 The flexible circuit board 100 for the all-in-one COF according to the embodiment is the first outer ring Lead pattern section O1, second outer lead pattern section O2, third outer lead pattern It may include part O3 and the fourth outer lead pattern part O4. 【0238】 The all-in-one COF flexible circuit board 100 according to the embodiment is a first test pattern It can include a test pattern section T1 and a second test pattern section T2. 【0239】 On one side of the flexible circuit board 100 for all-in-one COF according to the embodiment, The first inner lead pattern portion I1, the second inner lead pattern portion I2, the 3 Inner lead pattern portion I3, the first outer lead pattern portion O1, and the The outer lead pattern section O2 is positioned. 【0240】 The one side of the flexible circuit board 100 for the all-in-one COF according to the embodiment is opposite to the aforementioned side. On the other side, the fourth inner lead pattern portion I4 and the third outer lead portion Turn section O3, the fourth outer lead pattern section O4, the first test pattern section T1 The second test pattern section T2 may also be included. 【0241】 On one side of the all-in-one COF flexible circuit board 100 according to the embodiment The first chip C1 is connected to the first inner lead pattern portion through the first connection portion 70. I1, the second inner lead pattern portion I2 or the third inner lead pattern portion It is connected to I3. 【0242】 Depending on their position and / or function, the first connection portion 70 is a first sub-second connection portion 71, a second sub It may include a first connection part 72 and a third sub-first connection part 73. 【0243】 On one side of the all-in-one COF flexible circuit board 100 according to the embodiment The first chip C1 is connected to the first inner re It is electrically connected to the pattern section I1. 【0244】 The first inner lead pattern portion I1 is along the upper surface of the substrate 110 and the second via The electrical signal can be transmitted to the first outer lead pattern section O1 adjacent to the lead V2. Yes, it is possible. The second via hole V2 and the first outer lead pattern portion O1 are electrically It is connected to the first inner lead pattern portion I1 and the first outer lead The pattern portion O1 may be one end and the other end of a conductive pattern portion that extends in one direction. stomach. 【0245】 For example, the main board 40 is in contact with the first outer lead pattern portion O1. They are connected through the coating layer 50. Therefore, the signal transmitted from the first chip is the first The inner lead pattern portion I1 and the first outer lead pattern portion O1 are connected to the The information is transmitted to the inboard 40. 【0246】 Furthermore, the first inner lead pattern portion I1 extends along the upper surface of the substrate 110 to form a second inner lead pattern portion I1. A conductive material electrically connected to via hole V2 and filling the second via hole V2. A third outer via adjacent to the second via hole V2 along the lower surface of the substrate 110 The electrical signal can be transmitted to the lead pattern section O3. The second via hole V2 This is electrically connected to the third outer lead pattern portion O3. Therefore, as shown in the figure However, the main board 40 is bonded to the third outer lead pattern portion O3. It can, of course, be electrically connected through 50. 【0247】 On one side of the all-in-one COF flexible circuit board 100 according to the embodiment The first chip C1 is connected to the second inner ream via the second sub-first connection portion 72. It is electrically connected to the pattern section I2. 【0248】 The second inner lead pattern portion I2, which is positioned on the upper surface of the substrate 110, Conductive A fourth via hole adjacent to the first via hole V1 is located along the lower surface of the substrate 110 through a material. The inner lead pattern section I4 and the first test pattern section T1 transmit electrical signals. This is possible. The first via hole V1, the first test pattern section T1 and the fourth via hole V1 The inner lead pattern section I4 is electrically connected on the underside of the substrate. 【0249】 The fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 are equipped with The display panel 30 is attached. 【0250】 The first test pattern section T1 is electrically transmitted through the first via hole V1. A signal defect can be confirmed. For example, through the first test pattern section T1, The accuracy of the signal transmitted to the fourth inner lead pattern section I4 can be confirmed. Specifically, by measuring the voltage or current in the first test pattern section T1, the Short circuits or short circuits in the conductive pattern located between the first chip and the display panel. The presence or location of the occurrence can be confirmed, thereby improving the reliability of the product. 【0251】 On one side of the all-in-one COF flexible circuit board 100 according to the embodiment The first chip C1 is connected to the third inner ream via the third sub-first connection portion 73. It is electrically connected to the pattern section I3. 【0252】 The third inner lead pattern portion I3 is formed along the upper surface of the substrate 110, and the third via The electrical signal can be transmitted to the second outer lead pattern section O2 adjacent to the lead V3. Yes, it is possible. The third via hole V3 and the second outer lead pattern portion O2 are electrically It is connected to the third inner lead pattern portion I3 and the second outer lead. The pattern portion O2 may be one end and the other end of a conductive pattern portion that extends in one direction. stomach. 【0253】 Furthermore, the third inner lead pattern portion I3 is located along the upper surface of the substrate 110. A conductive material electrically connected to via hole V3 and filling the third via hole V3. The fourth outer via adjacent to the third via hole V3 along the lower surface of the substrate 110 The lead pattern section O4 and the second test pattern section T2 are used to transmit electrical signals. can. 【0254】 The second via hole V2, the fourth outer lead pattern section O4 and the second test The pattern section T2 is electrically connected to the underside of the substrate. 【0255】 As mentioned above, the fourth inner lead pattern portion I4 and the fourth outer lead pattern The display panel 30 is attached to the rumble section O4 via the adhesive layer 50. 【0256】 The second test pattern section T2 is electrically transmitted through the third via hole V3. A signal defect can be confirmed. For example, through the second test pattern section T2, The accuracy of the signal transmitted to the fourth outer lead pattern section O4 can be confirmed. Specifically, by measuring the voltage or current in the second test pattern section T2, the Short circuits or short circuits in the conductive pattern located between the first chip and the display panel. The presence or location of the occurrence can be confirmed, thereby improving the reliability of the product. 【0257】 The all-in-one COF flexible circuit board according to the embodiment is such that the first chip C1 is The display panel 30 can be placed on the opposite side from the side on which it is positioned, allowing for design flexibility. The degree can be improved. Also, on the opposite side of the surface where multiple chips are mounted By arranging the display panel, effective heat dissipation becomes possible. Therefore, the embodiment This improves the reliability of flexible circuit boards for all-in-one COFs. 【0258】 Figure 10 is a plan view of Figure 7a, and Figure 11 is a bottom view of Figure 7a. 【0259】 Referring to Figures 10 and 11, the flexible circuit base for the all-in-one COF of the embodiment For ease of manufacture or processing, the plate 100 has sprocket holes on both sides of its exterior in the longitudinal direction. It can be equipped with a flexible circuit board 100 for all-in-one COF. It is wound by the sprocket hole in a ROLL-to-ROLL (ROLL-to-ROLL) method, or to a certain extent They are sometimes treated badly. 【0260】 The flexible circuit board 100 for the all-in-one COF is based on the cut section shown by the dotted line. The internal region IR and the external region OR can be defined. 【0261】 The internal region IR of the all-in-one COF flexible circuit board 100 contains the first chip. Conductive circuits for connecting the second chip, display panel, and main board, respectively. The turning section is positioned. 【0262】 Sprocket holes are formed on the flexible circuit board 100 for all-in-one COF. By cutting off the excess portion and placing the chip on the substrate, an all-in-one COF flexible board is created. A chip package containing a double circuit board 100 and an electronic device containing the same are processed. It is possible. 【0263】 Referring to Figure 11, the upper surface of the all-in-one COF flexible circuit board 100 Then, through the first open region OA1 of the protective layer 140, a portion of the conductive pattern portion CP The first inner lead pattern portion I1 and the second inner lead pattern portion I are located in the region. 2 and the third inner lead pattern portion I3 are exposed to the outside. 【0264】 Furthermore, on the upper surface of the all-in-one COF flexible circuit board 100, the protection The third open region OA3 of layer 140 is a region of the conductive pattern portion CP. 1. The outer lead pattern portion O1 is exposed to the outside. 【0265】 The first inner lead pattern portion I1 and the third inner lead pattern portion I3 are Alternatively, it may be a conductive pattern portion that is connected to the chip through the first connection portion. 【0266】 The end portion of the first inner lead pattern portion I1 and the third inner lead pattern portion The ends of I3 are arranged in a row. For example, multiple I3s in the lateral direction (x-axis direction) of the substrate. The first inner lead pattern portions I1 are separated from each other, and the first inner lead pattern portion I The ends of 1 are arranged in a row. For example, multiple 3 in the lateral direction (x-axis direction) of the substrate. The inner lead pattern portions I3 are separated from each other, and the third inner lead pattern portion I3 The ends are arranged in a single row. Therefore, the first inner lead pattern portion I1 and the third The inner lead pattern section I3 exhibits excellent bonding with the first connection section and the first tip. 【0267】 In the lateral direction (x-axis direction) of the substrate, the multiple second via holes V2 are spaced apart from each other and arranged in a line. The multiple third via holes V3 are spaced apart from each other in the lateral direction (x-axis direction) of the substrate. They are then arranged in a single line. 【0268】 The end of the first inner lead pattern portion I1 is the second inner lead pattern portion The ends of I2 are separated from each other. 【0269】 The second inner lead pattern portion I2 is conductive and not bonded to the first chip. It may also be a pattern. Of the two ends of the second inner lead pattern portion I2 At least one end does not have to be arranged in a straight line. 【0270】 For example, in the lateral direction (x-axis direction) of the substrate, there are multiple second inner lead pattern portions I 2 may be separated from each other. Also, one end and the other end of the second inner lead pattern portion I2 At least one of the ends is such that the first inner edge extends further in the lateral direction (x-axis direction) of the substrate. The distance from the end of the lead pattern portion I1 is reduced. The second inner lead pattern portion At least one of the two ends of I2 is such that as you move along the transverse direction (x-axis direction) of the substrate... The distance between the end of the first inner lead pattern portion I1 and the other end increases. 【0271】 In the lateral direction (x-axis direction) of the substrate, the multiple first via holes V1 are spaced apart from each other, and different They are arranged in a column. 【0272】 The length between one end and the other end of the second inner lead pattern portion I2 is in the lateral direction of the substrate. The first set portion of the second inner lead pattern portion I2 gradually decreases as it moves in the x-axis direction. It may include. Specifically, one end and the other end of the second inner lead pattern portion I2 The length between the first and second lengths gradually decreases as you move along the lateral direction (x-axis direction) of the substrate. The first set portion of the second inner lead pattern portion I2 may be included. The length can be greater than the second length. Multiple The first set is placed on the substrate 110, from the first length to the second length The second inner lead pattern portion I2 can be included, in which the length gradually decreases. The second inner lead pattern portion I2 having a length and the second inner lead pattern adjacent to it The section I2 can again have a first length. Therefore, in the lateral direction (x-axis direction) of the substrate The second inner lead pattern portion I, whose length gradually decreases from the first length to the second length as time goes on. The first set portion of 2 and the second inner lead whose length gradually decreases from the first length to the second length. The first set of pattern section I2 is repeatedly arranged. 【0273】 At least one of the two ends of the second inner lead pattern portion I2 is The further you go in the lateral direction (x-axis direction) of the substrate, the closer the end of the first inner lead pattern portion I1 is to the substrate. The separation distance decreases. 【0274】 Multiple first inner lead pattern portions I1 are separated by a first interval. In the region between the two adjacent first inner lead pattern portions I1, the second inner - One end of the lead pattern section I2 can be positioned. 【0275】 In the lateral direction of the substrate, the end of the first inner lead pattern portion I1 and the second One end of the inner lead pattern section I2 is arranged alternately. 【0276】 Referring to Figure 11, the lower surface of the all-in-one COF flexible circuit board 100 Then, through the third open region OA3 of the protective layer 140, a portion of the conductive pattern portion CP The area of ​​the fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 It will be exposed to the outside. 【0277】 Refer to Figures 7b and 12-16, and the double-sided all-in-one COF flexible pipe according to the embodiment. Chip package including first chip C1 and second chip C2 on a single circuit board 100 I will explain this in detail. 【0278】 Figure 12 includes a double-sided all-in-one flexible circuit board 100 for COF according to an embodiment. This is a schematic plan view of a chip package. 【0279】 Referring to Figures 12a and 12b, the flexible rotation for double-sided all-in-one COF according to the embodiment The circuit board 100 is a circuit board in which the first chip C1 and the second chip C2 are arranged on the same surface. It can include. 【0280】 The flexible circuit board 100 for double-sided all-in-one COF according to the embodiment has a lateral direction (x The length in the axial direction can be greater than the length in the vertical direction (y-axis direction). That is, The double-sided all-in-one flexible circuit board 100 for COF according to the embodiment has two lateral directions It can include a long side and two short sides in the vertical direction. 【0281】 The length of the first chip C1 and the second chip C2 is such that the length in the horizontal direction (x-axis direction) is the same as the length of the vertical chip. It can have a length greater than the length in the direction (y-axis direction). That is, the first tip C1 The second chip C2 may include two long sides in the horizontal direction and two short sides in the vertical direction. Cut. 【0282】 The long side of the double-sided all-in-one COF flexible circuit board 100 according to the embodiment is the same as above Since they are arranged parallel to the long side of the first chip C1 and the long side of the second chip C2, Multiple chips can be effectively mounted on a single double-sided all-in-one COF flexible circuit board 100. They can be arranged proportionally. 【0283】 The lateral length (long side) of the first chip C1 is equal to the lateral length (long side) of the second chip C2. The length of the first chip C1 in the vertical direction (short side) can be greater than the length of the side. The length can be smaller than the vertical length (short side) of the second chip C2. Figure 1 Referring to 3a, the second chip C2 is positioned below the first chip C1. The longer side of the first chip C1 and the longer side of the second chip C2 may overlap vertically. 【0284】 Referring to Figure 13b, the second chip C2 is positioned on the side of the first chip C1. The long side of the first chip C1 and the long side of the second chip C2 do not need to overlap vertically. . 【0285】 The first chip C1 is a driver IC chip, and the second chip C2 is a diode chip. Top, power IC chip, touch sensor IC chip, MLCC chip, BGA chip, chip One of the top capacitors, the second chip C2a, the diode chip, and the power supply IC. Chips, touch sensor IC chips, MLCC chips, BGA chips, chip capacitors This may include one second chip C2b that is different from any one of the aforementioned. 【0286】 Refer to Figures 13 to 16, and the flexible tube for double-sided all-in-one COF according to the embodiment. This section describes the manufacturing stages of the chip package, including the circuit board. 【0287】 Figure 13 shows the flat surface of the double-sided all-in-one COF flexible circuit board 100 according to the embodiment. This is a view drawing. 【0288】 Referring to Figures 13a and 13b, the double-sided all-in-one flexible COF according to the embodiment The protective layer 140 located on one side of the sible circuit board 100 includes a plurality of holes. Yes, it is possible. That is, the protective layer 140 can include a plurality of open areas. 【0289】 The first open area OA1 of the protective layer is exposed in order to be connected to the first connection part 70. It may also be a region. Conductive pattern portion exposed in the first open region OA1 of the protective layer The CP may include pure plating on the surface facing the first connection portion. That is, the protective layer In the first open region OA1, the tin of the second plating layer included in the conductive pattern portion CP The content may be 50 atomic percent or more. 【0290】 The second open area OA2 of the protective layer is exposed in order to be connected to the second connection part 80. It may also be a region. Conductive pattern portion exposed in the second open region OA2 of the protective layer The CP may include a copper-tin alloy layer on the surface facing the second connection portion. The second plating included in the conductive pattern portion CP in the second open region OA2 of the protective layer The tin content of the layer may be less than 50 atomic percent. 【0291】 The first open region OA1 may be a region for connecting the first chip. The first outer lead pattern portion O1 located in the third open region OA3 extends from the third open region OA3. The first inner lead pattern portion I1 that extends into the first open region OA1 is They can be mutually corresponding or have different widths. For example, the first outer lead putter The width W1 of the inner lead section O1 may correspond to the width W2 of the first inner lead pattern section I1. For example, the width W1 of the first outer lead pattern portion O1 is the first inner lead The pattern portion I1 can have a width greater than the width W2. Specifically, the first outer - The width W1 of the lead pattern portion O1 is equal to the width W2 of the first inner lead pattern portion I1. The difference can be within 20%. 【0292】 The first inner lead pattern extends toward the interior of the first open region OA1 The lead portion I1 and the third inner lead pattern portion I3 have corresponding widths. It is possible. 【0293】 The first outer region extends from the first open region OA1 toward the outer edge of the substrate. The lead pattern portion O1 and the second outer lead pattern portion O2 have corresponding widths. Therefore, a first chip with a fine line width and requiring a large number of first connection points A second chip with a large line width and requiring a small number of second connection points can be integrated into one all-in-one chip. All components can be mounted on a single COF flexible circuit board 100. At this time, the fine line widths are , the first outer lead pattern portion O1 and the second outer lead pattern portion O2 Either one of the line widths is the fifth outer lead pattern section O5 and the sixth outer lead pattern. This can mean that the line width of part O6 is smaller than any one of the line widths. On the other hand, the larger line The width is either outer lead pattern section O5 or outer lead pattern section O6. One line width is the first outer lead pattern portion O1 and the second outer lead pattern The line width of any one of the n section O2 is the fifth outer lead pattern section O5 and the sixth outer lead This means that it is relatively larger than any one of the line widths in the code pattern section O6. ru. 【0294】 The flexible circuit board 100 for the all-in-one COF in this embodiment is of a different type from each other. Multiple second open regions OA2 for connecting the two chips C2a and C2b respectively It can include. 【0295】 One of the second open regions OA2 is a region for connecting one second chip C2a. This may also apply. A fifth inner lead pattern located within the second open region OA2. The fifth outer lead pattern portion O5, which extends from portion I5 toward the outer edge of the substrate, It can have different widths. For example, the width W of the fifth inner lead pattern portion I5. 3 can have a width greater than the width W4 of the fifth outer lead pattern portion O5. Specifically, the width W3 of the fifth inner lead pattern portion I5 is the width W3 of the fifth outer lead. The width of the pattern section O5 may be 1.5 times or more than the width W4. 【0296】 The other second open region OA2 connects to the other second chip C2b. It may also be in the second open region OA2. The sixth inner lead is located within the second open region OA2. The sixth outer lead pattern portion O6 extends from the pattern portion I6 toward the outer edge of the substrate. These can have different widths. For example, the sixth inner lead pattern portion I The width W5 of 6 is greater than the width W6 of the 6th outer lead pattern portion O6. This is possible. Specifically, the width W5 of the sixth inner lead pattern portion I6 is the sixth A The width of the outer lead pattern section O6 may be 1.5 times or more than the width W6. 【0297】 The width W3 of the fifth inner lead pattern portion I5 exposed through the second open region and The width of any one of the widths W5 of the sixth inner lead pattern portion I6 is the width of the first O A width greater than the width W2 of the first inner lead pattern portion I1 exposed through the open region It can have a first and second connecting part of various sizes / shapes. Since a patterned section can be formed, the degree of design freedom can be improved. In other words, implementation Examples include inner reels of various sizes that fit into the first and second chips of different types. The lead pattern section can include inner lead pattern sections of various shapes, making it optimal. This makes chip packaging possible. 【0298】 The shape of the inner lead pattern located at the bottom of the first chip is similar to the shape of the inner lead pattern located at the bottom of the second chip. The shape of the inner lead pattern portion may differ from that of the inner lead pattern portion. Therefore, the embodiments may differ from each other. The first chip and second chip of a certain type can each have excellent adhesion characteristics. It can include inner lead pattern portions of different shapes. Therefore, according to the embodiment, The flexible circuit board for RuinOne COF has a bond between the first and second chips. It has superior characteristics. 【0299】 In other words, the inner lead pattern sections, which have different shapes, are arranged on a single substrate. The first and second chips of the same type are mounted, and the optimal pattern ensures a certain level of bonding strength. It is an ingenious design. 【0300】 The shape of the first inner lead pattern portion I1 in the plane is a square stripe. It may also be a pattern. Specifically, on the plane of the first inner lead pattern portion I1 The resulting shape was a striped pattern of squares with a uniform width, extending in one direction. It may also be the case that the widths of one end and the other end of the first inner lead pattern portion I1 are They may be the same. 【0301】 For example, the fifth inner lead pattern portion I5 or the sixth inner lead pattern The shape of part I6 in the plane can be polygonal, circular, elliptical, hammer-shaped, T-shaped, or random. The protruding patterns may be of various shapes, such as the fifth inner lead pad. The shape of the turn portion I5 or the sixth inner lead pattern portion I6 in the plane is variable. A polygon, circle, ellipse, hammer-shaped, T-shaped shape having a width and extending in a direction different from the aforementioned one direction. The protruding patterns may be letter-shaped, random shapes, etc. As an example, the fifth inner At least one of the lead pattern portion I5 and the sixth inner lead pattern portion I6 The inner lead pattern portion may have different widths at one end and the other end. The fifth inner lead The protective layer of the lead pattern portion I5 and the sixth inner lead pattern portion I6 is located at one end close to the protective layer. The width of the other end, which is the end furthest from the protective layer, may be greater than the width of the first end. However, the embodiment is , but not limited to, the fifth inner lead pattern portion I5 and the sixth The width of the inner lead pattern portion I6 at one end close to the protective layer is greater than the width at the end farther from the protective layer. Of course, the width of the other end, which is the part, can also be small. 【0302】 For example, if the second chip is an MLCC chip, the inner lead pattern portion is The fifth inner lead pattern portion I5 in Figure 13b can have a T-shape. 【0303】 For example, if the second chip is a BGA chip, the inner lead pattern portion is: It can have a circular shape, such as the sixth inner lead pattern portion I6 in Figure 13a. Alternatively, if the second chip is a BGA chip, the inner lead pattern portion is as shown in Figure 13b. The sixth inner lead pattern portion I6 has a semicircular shape or a rounded end. It can have a certain appearance. 【0304】 The shapes of the first inner lead pattern portion and the first connection portion may be the same. For example, the planar shape (top view) of the first inner lead pattern portion and the first connection portion is , it can have a rectangular shape. Here, the first inner lead pattern portion and the The fact that the shape of the first connection point is identical means that the planar shape is the same polygon. This can include items of different sizes. 【0305】 The shapes of the fifth inner lead pattern portion and the second connection portion are either identical or different. The shapes of the sixth inner lead pattern portion and the second connection portion may be the same as each other. They may be different. 【0306】 Referring to Figures 13a and 14a, the planar shape of the fifth inner lead pattern portion I5 The shape is polygonal, and the planar shape of the second connecting portion may be circular. The planar shape of the sixth inner lead pattern portion I6 is circular, and the second connection portion is It can have a circular shape. 【0307】 Referring to Figures 13b and 14b, the planar shape of the fifth inner lead pattern portion I5 The shape is polygonal, and the second connecting portion is a quadrilateral or elliptical shape with rounded corners. It may have the following: The planar shape of the sixth inner lead pattern portion I6 is a long semicircle. The shape is such that the second connecting portion may have a circular shape. 【0308】 The planar shape of the first connecting portion 70 is such that the horizontal length and vertical length (aspect ratio) correspond to or differ from each other. It is also acceptable. For example, the planar shape of the first connecting portion 70 is such that the horizontal length and vertical length (aspect ratio) are They have corresponding square shapes or rectangular shapes with different widths and heights (aspect ratios). It is possible. 【0309】 The planar shape of the second connecting portion 80 is such that the horizontal length and vertical length (aspect ratio) correspond to or differ from each other. It is also acceptable. For example, the planar shape of the second connecting portion 80 is such that the horizontal length and vertical length (aspect ratio) are Having corresponding circular shapes or elliptical shapes with different horizontal and vertical lengths (aspect ratio) can. 【0310】 The interval (pitch) between adjacent first outer lead pattern portions O1 is, Adjacent fifth outer lead pattern portion O5 and sixth outer lead pattern portion The second interval (pitch) is the distance between at least one outer lead pattern portion of O6. ) may be smaller than ). In this case, the first and second intervals are two adjacent conductive patterns This can mean the average spacing between the n-sections. 【0311】 The first interval P1 may be less than 100 μm. For example, the first interval may be 30 μm. It may be less than 1 μm. For example, the first interval can be 1 μm to 25 μm. 【0312】 The second interval P2 may be 100 μm or more. For example, the second interval may be 100 μm The second interval can be between 100 μm and 300 μm. It can have. 【0313】 This will result in the connection between the conductive pattern portions that are linked to the first chip and the second chip, respectively. This can prevent signal interference and improve signal accuracy. 【0314】 In the first open region OA1, the plane of the first inner lead pattern portion I1 The product may correspond to or differ from that of the first connection part 70. 【0315】 The width of the first inner lead pattern portion I1 and the width of the first connection portion 70 are the same. There may be a difference of 20% or less. Therefore, the first inner lead putter The part I1 and the first connection part 70 enable stable mounting. Also, the first inner - The adhesion characteristics between the lead pattern portion I1 and the first connection portion 70 are improved. 【0316】 In the second open region OA2, the fifth inner lead pattern portion I5 and the front The plane of any one of the inner lead pattern parts I6 described in the sixth inner lead pattern part The product may correspond to or differ from that of the second connection part 80. 【0317】 As an example, the width of the second connection portion 80 is the width of the fifth inner lead pattern portion I5 and Width of any one of the six inner lead pattern sections I6 It may be 1.5 times or more larger. Therefore, the width of the second connecting portion 80 is the fifth inner - Either the lead pattern section I5 or the sixth inner lead pattern section I6 and the front The second connection part 80 has improved adhesion characteristics. 【0318】 Refer to Figures 14a and 14b, and the all-in-one COF flexible circuit board 10 of the embodiment. The step of placing the first connection part 70 and the second connection part 80 on top of 0 will be described. 【0319】 The first inner lead pattern portion I1 exposed through the first open region OA1 And a first connecting portion 70 is arranged on the third inner lead pattern portion I3. For example, the first connection portion 70 is the first inner lead pattern portion I1 and the The upper surface of the third inner lead pattern portion I3 can be covered entirely or partially. 【0320】 Multiple first inner lead pattern portions I1 and other portions that are spaced apart from each other The total number of the multiple third inner lead pattern portions I3 arranged therein is the first connection portion 7 It can also be associated with the number of zeros. 【0321】 For example, referring to Figures 15a and 15b, a plurality of the first are arranged at a distance from each other. The number of inner lead pattern sections I1 is nine, and multiple of the aforementioned sections are arranged spaced apart from each other. The number of inner lead pattern sections I3 is 9, and the number of the first connection sections 70 is as 1 Number of inner lead pattern sections I1 and a plurality of the third insulated sections arranged spaced apart from each other The number of elements in the Gnarled pattern section I3 is 18, which is the sum of 9 elements. 【0322】 The fifth inner lead pattern portion I5 is exposed through the second open region OA2. And a second connection portion 80 is arranged on the sixth inner lead pattern portion I6. For example, the second connection portion 80 is the fifth inner lead pattern portion I5 and the The upper surface of the sixth inner lead pattern portion I6 can be covered entirely or partially. 【0323】 The number of the multiple fifth inner lead pattern portions I5 arranged at mutual distance from each other is the 5 The number of the second connection parts 80 arranged on the inner lead pattern part I5 corresponds to good. 【0324】 For example, referring to Figures 15a and 15b, there are multiple 5s arranged at a distance from each other. The number of inner lead pattern sections I5 is two, and the fifth inner lead pattern section I There are two second connecting portions 80 positioned on top of 5. 【0325】 The number of the multiple sixth inner lead pattern portions I6 arranged at mutual distance from each other is the Even if the number of the second connection parts 80 arranged on the inner lead pattern part I6 is the same as the number of the second connection parts 80 arranged on the inner lead pattern part I6 good. 【0326】 For example, referring to Figures 15a and 15b, there are multiple 6 I arranged at a distance from each other. The number of inner lead pattern sections I6 is three, and the sixth inner lead pattern section I6 The number of the second connecting portion 80 positioned on top of is three. 【0327】 The second connection portion 80 may be larger than the first connection portion 70. The fifth inner lead pattern portion I5 or the sixth inner lead portion exposed through the area The width of the turn portion I6 is such that the first inner lead part is exposed through the first open region. Since it is larger than the width of the turn portion I1, the second connecting portion 80 is larger than the first connecting portion 70. stomach. 【0328】 Refer to Figures 15a and 15b, the flexible circuit base for the all-in-one COF of the embodiment. The next step involves placing the first chip C1, the second chips C2a, and C2b on the board 100. 【0329】 A first chip C1 is placed on the first connection portion 70. 【0330】 The first chip C2 is placed on the second connection portion 80. 【0331】 The first chip C1 and the second chip C2 are subject to defects such as signal interference or disconnection, and heat To prevent problems such as defects caused by these devices, they are arranged at a certain distance apart. 【0332】 Figure 16 shows the flexible circuit board for double-sided all-in-one COF related to Figures 15a and 15b. This is a cross-sectional view of a chip package including a plate. 【0333】 The first chip C1 and the second chip C2 are arranged on the same surface at different sizes. They are placed. For example, the second chip C2 is larger than the first chip C1. 【0334】 Via holes are arranged at the bottom of the first chip C1 and the second chip C2. , the substrate 1 in the region corresponding to the first open region OA1 and the second open region OA2 10 can include a beer hall. 【0335】 The electrical signal of the second chip C2 passes through a conductive material located in the fourth via hole V4. Therefore, the signal is transmitted from the top surface to the bottom surface of the substrate. Thus, the embodiment has a large number of conductive pattern sections. It can be included on one substrate. 【0336】 The flexible circuit board 100 for the all-in-one COF according to the embodiment has fine particles on both sides. It is possible to realize the conductive pattern part of the chip and have an electronic display part with high resolution It fits the device. 【0337】 Furthermore, the flexible circuit board 100 for all-in-one COF according to the embodiment is flexible Because it is lightweight, small in size, and thin, it can be used in a variety of electronic devices. ru. 【0338】 For example, referring to Figure 17, an all-in-one flexible circuit for COF according to an embodiment. The substrate 100 can reduce the bezel size, so it can be used in edge displays. Cut. 【0339】 For example, referring to Figure 18, an all-in-one flexible circuit for COF according to an embodiment. The substrate 100 can be included in a flexible electronic device. Therefore, touch device devices including this can be considered flexible touch device devices. Yes, it is possible. Therefore, users can bend and bend it by hand. Such flexible Touch windows can be applied to wearable touch devices and other applications. 【0340】 For example, referring to Figure 19, an all-in-one flexible circuit for COF according to an embodiment. The substrate 100 is applicable to a variety of electronic devices to which foldable display devices are applied. It is possible to do so. Referring to Figures 19a to 19c, the foldable display device is The foldable cover window can be folded. Foldable display case The term can be included in a variety of portable electronic products. Specifically, foldable displays Ray devices are included in mobile terminals (mobile phones), notebooks (portable computers), etc. Therefore, it is possible to increase the display area of ​​portable electronic products while also maximizing storage and The size of the device can be reduced when moving, increasing its portability. This can improve the convenience of users of electronic products for use with bands. However, the embodiments are not limited to these. Foldable display devices are not limited to those that can be used in a variety of electronic products. Of course. 【0341】 Referring to Figure 19a, the foldable display device has one fold in the screen area It may include areas. For example, a foldable display device is a folded shape It can have a C shape in this state. That is, the foldable display device has one end and the front The other end opposite to the first end can be superimposed. In this case, the first and second ends are close to each other. They are arranged such that, for example, one end and the other end face each other. 【0342】 Referring to Figure 19b, the foldable display device has two folds in the screen area. It may include areas. For example, a foldable display device may have a folded form. It can have a G shape. That is, the foldable display device has one end and the The two ends, opposite each other, are bent in corresponding directions, allowing them to overlap. At that time, the one end and the other end are arranged to be separated from each other. For example, the one end and the other end are They are arranged parallel to each other. 【0343】 Referring to Figure 19c, the foldable display device has two folds in the screen area. It may include areas. For example, a foldable display device is a folded shape It can have an S shape in this state. That is, the foldable display device has one end and the front The other end, opposite to the first end, is bent in opposite directions. The ends are arranged to be spaced apart from each other. For example, one end and the other end are arranged parallel to each other. 【0344】 Also, although not shown in the figures, a flexible circuit base for an all-in-one COF according to the embodiment Board 100 can, of course, be applied to a rollable display. 【0345】 Referring to Figure 20, the flexible circuit board 10 for all-in-one COF according to the embodiment 0 can be included in a variety of wearable touch devices, including curved displays. Therefore, the all-in-one COF flexible circuit board 100 according to the embodiment includes Child devices can be made slimmer, smaller, or lighter. 【0346】 Referring to Figure 21, the flexible circuit board 10 for all-in-one COF according to the embodiment 0 is a variety of electronic devices that have a display part, such as TVs, monitors, and notebooks. It can be used for chairs. 【0347】 The examples are not limited to those shown, and the all-in-one COF according to the examples is also applicable. The flexible circuit board 100 has a multi-display portion that is flat or curved in shape. It can, of course, be used in various electronic devices. 【0348】 According to an embodiment of the present invention, a first chip and a second chip of different types are combined into one An all-in-one CO2 that can be mounted on flexible circuit boards and offers improved reliability. We can provide a flexible circuit board chip package for F. 【0349】 Furthermore, according to the embodiment of the present invention, a flexible circuit for an all-in-one COF is provided. The display panel and the main board are directly connected via a circuit board, and the power generated from the display panel is generated from the display panel. The size and thickness of the flexible circuit board used to transmit the signal to the main board have been reduced. This allows for expansion of space for other components and / or battery space. It is possible. 【0350】 Furthermore, according to the embodiment of the present invention, since it is not necessary to connect multiple PCBs, the process Convenience and reliability of electrical connections are improved, and as a result, a high-resolution display unit is available. We provide an all-in-one flexible circuit board for COF that is compatible with electronic devices. It is possible. 【0351】 Furthermore, according to the embodiment of the present invention, a circuit pattern arranged on the first surface of the substrate corresponds to A dummy pattern is placed on the second surface of the substrate, and the second surface of the substrate is arranged in such a way. By arranging a dummy pattern on the first surface of the substrate to correspond to the path pattern, Solder resist generated during printing of solder resist on the first or second surface of the substrate This can solve problems such as uneven coating and pinholes. 【0352】 The features, structures, and effects described in the above-described examples are at least one embodiment of the present invention. The examples are included and are not necessarily limited to a single embodiment. Features, structure, effects, etc., are described by a person with ordinary skill in the field to which the examples belong, and may differ from other examples. It is possible to implement this by combining or modifying the examples. The matters concerned should be interpreted as being within the scope of the present invention. 【0353】 Furthermore, although the above description has focused on examples, these are merely illustrative and do not limit the present invention. Rather than that, a person with ordinary skill in the art to which this invention belongs would understand the essence of this embodiment. Within the bounds of not deviating from its inherent characteristics, a wide variety of modifications and applications not exemplified above are possible. For example, each component specifically presented in the examples can be modified and implemented. The differences relating to such modifications and applications are defined in the present invention as specified in the attached claims. It should be interpreted as being included within the scope of [the relevant category].

Claims

[Claim 1] circuit board and A first conductive pattern portion is disposed beneath the substrate, A second conductive pattern portion and a first dummy pattern portion are arranged on the substrate, A first protective layer disposed beneath the first conductive pattern portion, The second conductive pattern portion and the first dummy pattern portion are disposed on top of each other, and the second protective layer is disposed on top of each other. The first dummy pattern portion overlaps the first conductive pattern portion, the first protective layer, and the second protective layer, which are located on the outermost edge of the substrate, in a direction perpendicular to each other. The first conductive pattern portion is, The first wiring pattern layer, Displaced beneath the first wiring pattern layer, and comprising a first plating layer containing tin, The first dummy pattern section is, The second wiring pattern layer, Displaced on the second wiring pattern layer, and comprising a second plating layer containing tin, A flexible circuit board in which the thickness of the second plating layer of the first dummy pattern portion beneath the second protective layer is different from the thickness of the first plating layer of the first conductive pattern portion above the first protective layer. [Claim 2] The flexible circuit board according to claim 1, wherein the thickness of the second plating layer of the first dummy pattern portion beneath the second protective layer is thinner than the thickness of the first plating layer of the first conductive pattern portion above the first protective layer. [Claim 3] The flexible circuit board according to claim 1, wherein the left end of the first dummy pattern portion is closer to the left edge of the substrate than the left end of the second conductive pattern portion located furthest to the left among the second conductive pattern portions. [Claim 4] The second plating layer of the first dummy pattern portion is A second-first plating layer is placed on the second wiring pattern layer, The flexible circuit board according to claim 1, further comprising a second-second plating layer disposed on the second-first plating layer. [Claim 5] The flexible circuit board according to claim 1, further comprising a second conductive pattern portion disposed in a region of the lower surface of the substrate in which the first conductive pattern portion is not disposed, and at least a portion of which is disposed on the outermost edge of the substrate, the first protective layer and a second dummy pattern portion overlapping the second protective layer in a direction perpendicular to it. [Claim 6] The first dummy pattern portion has the same layer structure as the second conductive pattern portion, The flexible circuit board according to claim 5, wherein the second dummy pattern portion has the same layer structure as the first conductive pattern portion. [Claim 7] The second dummy pattern portion includes the first wiring pattern layer and the first plating layer, The first plating layer of the second dummy pattern portion is A first-first plating layer disposed below the first wiring pattern layer, The flexible circuit board according to claim 6, further comprising a first-second plating layer disposed beneath the first-first plating layer. [Claim 8] The flexible circuit board according to claim 1, wherein the horizontal distance between the left edge of the substrate and the first conductive pattern portion closest to the left edge of the substrate is greater than or equal to the horizontal distance between the left edge of the substrate and the first dummy pattern portion closest to the left edge of the substrate. [Claim 9] circuit board and A first conductive pattern portion and a second dummy pattern portion are arranged on the lower surface of the substrate, A second conductive pattern portion is disposed on the upper surface of the substrate, A first protective layer disposed beneath the first conductive pattern portion and the second dummy pattern portion, The present invention includes a second protective layer disposed on the second conductive pattern portion, The second dummy pattern portion overlaps the second conductive pattern portion, the first protective layer, and the second protective layer, which are located on the outermost edge of the substrate, in a direction perpendicular to each other. The second dummy pattern section is, The first wiring pattern layer, Displaced beneath the first wiring pattern layer, and comprising a first plating layer containing tin, The second conductive pattern portion comprises a second wiring pattern layer and Displaced on the second wiring pattern layer, and comprising a second plating layer containing tin, A flexible circuit board in which the thickness of the first plating layer of the second dummy pattern portion on the first protective layer is different from the thickness of the second plating layer of the second conductive pattern portion below the second protective layer. [Claim 10] The flexible circuit board according to claim 9, wherein the thickness of the first plating layer of the second dummy pattern portion on the first protective layer is greater than the thickness of the second plating layer of the second conductive pattern portion below the second protective layer. [Claim 11] The flexible circuit board according to claim 9, wherein the right end of the second dummy pattern portion is closer to the right end of the substrate than the right end of the first conductive pattern portion located at the far right of the first conductive pattern portion. [Claim 12] The first plating layer of the second dummy pattern portion is A first-first plating layer disposed below the first wiring pattern layer, The flexible circuit board according to claim 9, further comprising a first-second plating layer disposed beneath the first-first plating layer. [Claim 13] The flexible circuit board according to claim 9, further comprising a first conductive pattern portion disposed in an area of ​​the upper surface of the substrate where the second conductive pattern portion is not disposed, and at least a portion of which is disposed on the outermost edge, a first dummy pattern portion overlapping the first protective layer and the second protective layer in a direction perpendicular to it. [Claim 14] The first dummy pattern portion has the same layer structure as the second conductive pattern portion, The flexible circuit board according to claim 13, wherein the second dummy pattern portion has the same layer structure as the first conductive pattern portion. [Claim 15] The first dummy pattern portion includes the second wiring pattern layer and the second plating layer, The second plating layer of the first dummy pattern portion is A second-first plating layer is placed on the second wiring pattern layer, The flexible circuit board according to claim 14, further comprising a second-second plating layer disposed on the second-first plating layer. [Claim 16] The flexible circuit board according to claim 9, wherein the horizontal distance between the right edge of the substrate and the second conductive pattern portion closest to the right edge of the substrate is greater than or equal to the horizontal distance between the right edge of the substrate and the second dummy pattern portion closest to the right edge of the substrate. [Claim 17] A chip package including a flexible circuit board, The aforementioned flexible circuit board is circuit board and A first conductive pattern portion is disposed on the lower surface of the substrate, A second conductive pattern portion and a first dummy pattern portion are arranged on the upper surface of the substrate, A first protective layer disposed beneath the first conductive pattern portion, The second conductive pattern portion and the first dummy pattern portion are disposed on top of each other, and the second protective layer is disposed on top of each other. The first dummy pattern portion overlaps the first conductive pattern portion, the first protective layer, and the second protective layer, which are located on the outermost edge of the substrate, in a direction perpendicular to each other. The first conductive pattern portion is, The first wiring pattern layer, Displaced beneath the first wiring pattern layer, and comprising a first plating layer containing tin, The first dummy pattern section is, The second wiring pattern layer, Displaced on the second wiring pattern layer, and comprising a second plating layer containing tin, A chip package in which the thickness of the second plating layer of the first dummy pattern portion beneath the second protective layer is different from the thickness of the first plating layer of the first conductive pattern portion above the first protective layer. [Claim 18] The chip package according to claim 17, wherein the thickness of the second plating layer of the first dummy pattern portion beneath the second protective layer is thinner than the thickness of the first plating layer of the first conductive pattern portion above the first protective layer. [Claim 19] The chip package according to claim 17, comprising a second conductive pattern portion disposed in a region of the lower surface of the substrate where the first conductive pattern portion is not disposed, and at least a portion of which is disposed on the outermost edge, a first protective layer, and a second dummy pattern portion overlapping the second protective layer in a direction perpendicular to it. [Claim 20] The first dummy pattern portion has the same layer structure as the second conductive pattern portion, The second dummy pattern portion has the same layer structure as the first conductive pattern portion, The second plating layer of the first dummy pattern portion is A second-first plating layer is placed on the second wiring pattern layer, The second-second plating layer is disposed on the second-first plating layer, The second dummy pattern portion includes the first wiring pattern layer and the first plating layer, The first plating layer of the second dummy pattern portion is A first-first plating layer disposed below the first wiring pattern layer, The chip package according to claim 19, further comprising a first-second plating layer disposed beneath the first-first plating layer.

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