Voltage-type gate drive with shunt capacitor and shunt resistor

Abstract

To provide an improved voltage-type gate driver and an improved power system.SOLUTION: In a power system 10, a shunt capacitor CGSNT and a shunt resistor RGSNT are serially connected to each other and are connected to both ends of a gate driver resistor network 18 of a voltage-type gate driver 12. The shunt capacitor and the shunt resistor separate the influence of a gate delay and a switching speed of a gate resistor RG. The shunt capacitor provides an initial high charge voltage and discharge gate current and reduces a gate delay time. The shunt resistor corrects a gate current and an effective gate resistance which affects a resultant switching speed. The shunt capacitor and the shunt resistor are determined to control a predetermined switching speed at the minimum gate delay time. When a plurality of power devices 14 are in parallel, each power device is provided with a split gate resistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 387,784, filed December 16, 2022, entitled "Voltage-Source Gate Drive Using Shunt Capacitor and Resistor that Decouples Switching Speed ​​Control and Gate Delay Time," which is expressly incorporated herein by reference in its entirety.

[0002] This disclosure relates to power semiconductor devices, and more specifically, to voltage-type gate drive circuits for driving power semiconductor devices. [Background technology]

[0003] Power semiconductor devices are typically used in power electronics circuits to provide power conversion functionality. In applications, faster switching speeds are beneficial to the operation of power semiconductor devices because they reduce switching losses associated with them.

[0004] Nevertheless, as switching speeds increase, electromagnetic interference increases and the risk of vibration rises. In this regard, there is a correlation between gate delay and switching speed of semiconductor power devices. As switching speeds decrease, switching losses increase and gate delays become longer, which can be undesirable from a control or protection standpoint. As switching speeds increase, challenges arise in complying with industry standards for electromagnetic compatibility and electromagnetic interference, causing voltage spikes, ringing, and electromagnetic interference, which makes it even more difficult to achieve electromagnetic compatibility and avoid vibrations. Furthermore, longer gate delays negatively impact the protection, parallel synchronization, and circuit operation of power electronics circuits. Another challenge in optimizing the switching speed and gate delay of power electronics circuits is the input capacitance (C) of semiconductor power devices. ISSThe need to address this is that semiconductor power devices have a high input capacitance (C) that is proportional to the die size of the semiconductor power device. ISS ) may result in long gate delays. Therefore, depending on the design, structure, or application of the semiconductor power device, the gate delay may be such that, for example, if the semiconductor power device has parallel transistors, each parallel branch of the semiconductor power device has a characteristic input capacitance (C). ISS This results in a longer and more pronounced effect. Therefore, an improved voltage-type gate driver is needed. [Overview of the project]

[0005] Disclosed are embodiments for controlling a semiconductor power device using an improved voltage-type gate driver, which isolates the control of the switching speed and gate delay time of the power device. One embodiment describes a voltage-type gate driver. The voltage-type gate driver includes a power converter having an input configured to receive a first gate signal and supply a regulated output voltage to an output node. The voltage-type gate driver further includes a gate driver resistor network having at least one gate resistor coupled between the output node of the power converter and the output terminal of the voltage-type gate driver, and a shunt capacitor connected in parallel across the gate driver resistor network. Thus, the output terminal is configured to provide a second gate signal to the gate of a semiconductor power device.

[0006] In one embodiment, the shunt capacitor has a value calculated using the following formula.

number

[0007] Here, the equation is: shunt capacitor C GSNT The solution was found for V, in the equation DD V is a positive power supply voltage, EE This is a negative power supply voltage, and C ISSV is the input capacitance of a semiconductor power device. TH This is the threshold voltage of a semiconductor power device.

[0008] In one embodiment, the voltage-type gate driver further comprises a shunt resistor connected in series with a shunt capacitor, and the shunt resistor and shunt capacitor are connected in parallel across the gate driver resistor network. The first shunt resistor is in the range of 0Ω to 10MΩ.

[0009] In one embodiment, the gate driver resistor network has an equivalent resistance value in the range of 0Ω to 10MΩ.

[0010] In another embodiment, the power converter comprises one of a voltage rectifier, regulator, inverter, or converter.

[0011] In one embodiment, the voltage-type gate driver further comprises a solid-state circuit breaker.

[0012] In one embodiment, the semiconductor power device comprises a half-bridge circuit topology.

[0013] In one embodiment, the semiconductor power device is a parallel transistor connection circuit topology.

[0014] In one embodiment, the semiconductor power device has a common source circuit topology.

[0015] In one embodiment, the semiconductor power device is one of the following topologies: a half-bridge circuit topology, a parallel transistor connection circuit topology, or a common-source circuit topology.

[0016] In one embodiment, the semiconductor power device is a metal oxide field-effect transistor.

[0017] In one embodiment, the semiconductor power device is one of an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), or a high electron mobility transistor (HEMT).

[0018] In another aspect, a power system comprising a voltage-mode gate driver and a semiconductor power device is disclosed. The voltage-mode gate driver includes a power converter having an input configured to receive a first gate signal and provide a controlled output voltage at an output node, a gate driver resistor network having at least one gate resistor coupled between the output node of the power converter and an output terminal of the voltage-mode gate driver, and a shunt capacitor connected in parallel across both ends of the gate driver resistor network, wherein the output terminal is configured to provide a second gate signal. The semiconductor power device includes a gate terminal, a drain terminal, and a source terminal, and the semiconductor power device is configured to receive the second gate signal at the gate terminal.

[0019] In one embodiment, the shunt capacitor has a value calculated using the following equation.

Equation

[0020] where the equation is solved for the shunt capacitor C GSNT and in the equation, V DD is the positive supply voltage, V EE is the negative supply voltage, C ISS is the input capacitance of the semiconductor power device, and V TH is the threshold voltage of the semiconductor power device.

[0021] In one embodiment, the power system further includes a shunt resistor connected in series with the shunt capacitor, and the shunt resistor and the shunt capacitor are connected in parallel across both ends of the gate driver resistor network. The first shunt resistor is in the range of 0 Ω to 10 MΩ.

[0022] In one embodiment, the gate driver resistor network has an equivalent resistance value in the range of 0Ω to 10MΩ.

[0023] In another embodiment, the power converter comprises one of a voltage rectifier, regulator, inverter, or converter.

[0024] In one embodiment, the semiconductor power device is a metal oxide field-effect transistor.

[0025] In one embodiment, the semiconductor power device is one of the following topologies: a half-bridge circuit topology, a parallel transistor connection circuit topology, or a common-source circuit topology.

[0026] In one embodiment, the semiconductor power device is one of the following: an insulated-gate bipolar transistor (IGBT), a junction-gate field-effect transistor (JFET), or a high-electron-mobility transistor (HEMT).

[0027] Those skilled in the art will understand the scope of this disclosure and recognize other embodiments thereto after reading the following detailed description relating to the attached drawings. [Brief explanation of the drawing]

[0028] The accompanying drawings incorporated herein and forming part thereof illustrate several aspects of this disclosure and serve to illustrate the principles of this disclosure together with the description.

[0029] [Figure 1] Figure 1 shows an exemplary power system having a voltage-type gate driver connected to a semiconductor power device.

[0030] [Figure 2] Figure 2 shows another exemplary power system having multiple MOSFETs connected in parallel as part of a semiconductor power device.

[0031] [Figure 3A] Figures 3A to 3C show exemplary circuit topologies applied in various embodiments of this disclosure as part of the semiconductor power devices of the power system shown in Figure 1.

[0032] Figure 3A shows an exemplary half-bridge circuit topology.

[0033] [Figure 3B] Figure 3B shows an exemplary parallel transistor connection circuit topology.

[0034] [Figure 3C] Figure 3C shows an exemplary common-source circuit topology.

[0035] [Figure 4A] Figures 4A and 4B are graphs showing the voltage and current characteristics of semiconductor power devices in the power system shown in Figure 1, where a shunt capacitor CGSNT is present but a shunt resistor RGSNT is absent (RGSNT = 0Ω).

[0036] Figure 4A is a graph showing the voltage and current characteristics of the semiconductor power devices of the power system shown in Figure 1 during the turn-off transition. The power system includes a shunt capacitor C. GSNT Equipped with a shunt resistor R GSNT (R GSNT (=0Ω).

[0037] [Figure 4B] Figure 4B is a graph showing the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1 during the turn-on transition. The power system includes a shunt capacitor CGSNT but lacks a shunt resistor RGSNT (RGSNT=0Ω).

[0038] [Figure 5A]Figures 5A and 5B are graphs showing the voltage and current characteristics of the semiconductor power devices (i.e., discrete devices) of the power system shown in Figure 1, which includes a shunt capacitor CGSNT and a shunt resistor RGSNT.

[0039] Figure 5A shows the shunt capacitor C. GSNT and shunt resistor R GSNT This graph shows the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1 during the turn-off transition.

[0040] [Figure 5B] Figure 5B is a graph showing the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1, which has a shunt capacitor CGSNT and a shunt resistor RGSNT, during the turn-on transition.

[0041] [Figure 6A] Figures 6A and 6B are graphs showing the voltage and current characteristics of the semiconductor power device (i.e., the half-bridge 30 power module) of the power system shown in Figure 1, which has a shunt capacitor CGSNT, a shunt resistor RGSNT, and a series split-gate resistor RG.

[0042] Figure 6A shows the shunt capacitor C GSNT Shunt resistor R GSNT , and a series split-gate resistor R G This graph shows the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1 during the turn-off transition.

[0043] [Figure 6B] Figure 6B is a graph showing the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1 during turn-on transition, with a shunt capacitor CGSNT, a shunt resistor RGSNT, and a series split-gate resistor RG.

[0044] [Figure 7A] Figures 7A and 7B are graphs showing the voltage and current characteristics of semiconductor power devices in the power system shown in Figure 1, generated using different values ​​for the turn-on gate resistor RG-ON and the turn-off gate resistor RG-OFF.

[0045] Figure 7A shows different values ​​(R G-ON =R G-OFF =100Ω, R G-ON =R G-OFF =150Ω, and R G-ON =R G-OFF (=200Ω) Sharp turn-on gate resistor R G-ON and turn-off gate resistor R G-OFF This graph, generated using [the specified method], shows the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1 during the turn-off transition.

[0046] [Figure 7B] Figure 7B is a graph showing the voltage and current characteristics of discrete semiconductor power devices in the power system shown in Figure 1 during the turn-on transition, generated using turn-on gate resistors RG-ON and turn-off gate resistors RG-OFF with different values ​​(RG-ON=RG-OFF=100Ω, RG-ON=RG-OFF=150Ω, and RG-ON=RG-OFF=200Ω).

[0047] [Figure 8A] Figures 8A and 8B are graphs showing the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1, without the shunt capacitor CGSNT and shunt resistor RGSNT, demonstrating that discrete semiconductor power devices have electrical characteristics suitable for low-speed switching applications.

[0048] Figure 8A shows the shunt capacitor C GSNT and shunt resistor R GSNTFigure 1 shows a graph illustrating the voltage and current characteristics of the semiconductor power device in the power system shown, during the turn-off transition, demonstrating that the semiconductor power device possesses electrical characteristics suitable for low-speed switching applications.

[0049] [Figure 8B] Figure 8B is a graph showing the voltage and current characteristics of the discrete semiconductor power devices in the power system shown in Figure 1 during turn-on transition, without the shunt capacitor CGSNT and shunt resistor RGSNT, demonstrating that the semiconductor power devices possess electrical characteristics suitable for low-speed switching applications.

[0050] [Figure 9A] Figures 9A and 9B are graphs showing the voltage and current characteristics of the semiconductor power devices in the power system shown in Figure 1, which includes a shunt capacitor CGSNT and a shunt resistor RGSNT. The semiconductor power devices have electrical characteristics suitable for low-speed switching applications.

[0051] Figure 9A shows the shunt capacitor C. GSNT and shunt resistor R GSNT This graph shows the voltage and current characteristics of the discrete semiconductor power device in the power system shown in Figure 1 during the turn-off transition, and the discrete semiconductor power device has electrical characteristics suitable for low-speed switching applications.

[0052] [Figure 9B] Figure 9B is a graph showing the voltage and current characteristics of the semiconductor power device in the power system shown in Figure 1 during turn-on transition, which includes a shunt capacitor CGSNT and a shunt resistor RGSNT. The semiconductor power device has electrical characteristics suitable for low-speed switching applications. [Modes for carrying out the invention]

[0053] The embodiments described below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate best modes of practice. After reading the following description in reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize the applications of these concepts not specifically described herein. Naturally, these concepts and applications are included within the scope of this disclosure and the accompanying claims.

[0054] In this specification, various elements may be described using terms such as first, second, etc., but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be called the second element, and similarly, the second element may be called the first element. The term "and / or" as used herein includes all combinations of one or more of the related enumerated items.

[0055] When an element such as a layer, region, or substrate is described as being "on top of" or "extending upward" of another element, it will be understood that there may also be elements directly on top of, extending directly upward, or intervening to the other element. In contrast, when an element is described as being "directly on top of" or "extending directly upward" of another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is described as being "on top of" or "extending upward" of another element, it will be understood that there may also be elements directly on top of, extending directly upward, or intervening to the other element. In contrast, when an element is described as being "directly on top of" or "extending directly upward" of another element, there are no intervening elements. Furthermore, when an element is described as being "connected" or "joined" to another element, it will be understood that there may also be elements that are directly connected or joined to the other element, or intervening elements. In contrast, when one element is said to be "directly linked" or "directly connected" to another element, there are no intervening elements.

[0056] As shown in the figure, relative terms such as "below" or "above" or "upper" or "lower" may be used herein to describe the relationship between one element, layer, or region and another. It is understood that these terms and those mentioned above are intended to encompass different orientations of the apparatus in addition to the orientation depicted in the figure.

[0057] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the disclosure. Where used herein, the singular forms "a," "an," and "the" are intended to include the plural form unless otherwise clearly indicated by the context. Where used herein, "comprises," "comprising," "includes," and / or "including" identify the presence of a described feature, integer, process, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, processes, operations, elements, and / or groups thereof.

[0058] Unless otherwise defined, all terms used herein (including technical and academic terms) have the same meaning as those generally understood by those skilled in the art to which this disclosure belongs. Furthermore, terms used herein should be interpreted as having the meaning consistent with their meaning in the context of this specification and related art, and it will be understood that they should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0059] This specification describes embodiments with reference to schematic drawings of embodiments of the present disclosure. Therefore, the actual dimensions of layers and elements may differ and are expected to differ from the shapes shown, for example, as a result of manufacturing techniques and / or tolerances. For example, areas illustrated or described as squares or rectangles may be round or curved, and areas shown as straight lines may have some irregularities. Thus, the areas illustrated in the drawings are schematic, and their shapes are not intended to illustrate the exact shapes of areas in the device, nor are they intended to limit the scope of this disclosure. Furthermore, the size of structures or areas may be exaggerated in comparison to other structures or areas for illustrative purposes, and are therefore provided to illustrate the general structure of the subject matter, and may or may not be drawn to scale. Elements common to both drawings are indicated here by common element numbers and will not be described again later.

[0060] Figure 1 shows an exemplary power system 10 having a voltage-type gate driver 12 connected to a semiconductor power device 14. The voltage-type gate driver 12 receives an input gate signal V at input terminal 22. IN It receives the signal and provides a controlled and amplified drive signal at the output terminal 24 which is electrically coupled to the semiconductor power device 14. In this way, the voltage-type gate driver 12 acts as a current buffer and signal converter and includes a power converter 16 and a gate driver resistor network 18 connected in series between the input terminal 22 and the output terminal 24 of the voltage-type gate driver 12. A shunt capacitor C is used to effectively control the switching speed and gate delay of the semiconductor power device 14. GSNT and shunt resistor R GSNT It is connected in series between the first internal node 28 and the second internal node 38. Furthermore, a shunt capacitor C is connected in series. GSNT and shunt resistor R GSNTThe first internal node 28 is connected in parallel with the gate driver resistor network 18 such that it is connected to the output node 26 of the power converter 16 and the second internal node 38 is connected to the output terminal 24 of the voltage-type gate driver 12. In this way, the shunt capacitor C GSNT and shunt resistor R GSNT This is used as part of the voltage-type gate driver 12 to isolate the switching speed of the semiconductor power device 14 from the gate delay of the semiconductor power device 14, and can prevent any spurious gate-loop oscillation and / or gate-loop triggering in the semiconductor power device 14, as will be described in more detail elsewhere in this specification.

[0061] The semiconductor power device 14 may be a metal oxide semiconductor field-effect transistor (MOSFET) Q3 having an integrated body diode D3. However, the scope of this disclosure is not limited thereto. The semiconductor power device 14 further comprises a gate terminal G, a drain terminal D, and a source terminal S. The body diode D3 provides an internal current conduction path from the source terminal S to the drain terminal D and blocks high voltage and high current from the drain terminal D to the source terminal S. Furthermore, the MOSFET Q3 has a gate-source capacitance C GS , drain-source capacitance C GS , and gate-drain capacitance C GD It has a characteristic capacitance including the input capacitance C. ISS The gate-source capacitance C GS and gate-drain capacitance C GD This is the total.

[0062] The drain terminal D and source terminal S can be connected to the load 20 at the first load node 34 and the second load node 36, respectively. The semiconductor power device 14 in the power system 10 may be used to rectify, invert, convert, or otherwise manipulate electrical energy using a voltage-type gate driver, for example, a voltage-type gate driver 12. The source terminal S of the MOSFET Q3 of the semiconductor power device 14 is connected to the capacitor C DDand capacitor C EE The positive power supply voltage V is stabilized by DD and negative power supply voltage V EE It is connected to reference node 32 between and and uses that as the reference. Here, the positive power supply voltage V DD This may refer to a positive rail voltage within the range of 5V to 30V, 10V to 20V, or 12V to 15V. Negative power supply voltage V EE This may refer to negative rail voltages that are within the ranges of 0V to -30V, -3V to -20V, -5V to -15V, or connected to ground. Alternatively, it may refer to negative power supply voltage V EE The positive power supply voltage V depends on whether the semiconductor power device 14 is a normally-on or normally-off semiconductor power device. DD It may be used instead. For a normally off semiconductor power device 14 to turn on, a positive gate-source voltage V GS Therefore, a gate-source voltage V is required. GS When the voltage is 0 volts, the normally off semiconductor power device 14 is in the off state. For the normally on semiconductor power device 14 to turn off, a negative gate-source voltage V is required. GS Therefore, a gate-source voltage V is required. GS When the voltage is 0 volts, the semiconductor power device 14, which is a normally-on device, is in the ON state.

[0063] The voltage-type gate driver 12 operates as a current buffer and signal converter, and includes a power converter 16 and a gate driver resistor network 18 connected in series between the input terminal 22 and output terminal 24 of the voltage-type gate driver 12. The power converter 16 can be formed by a first transistor Q1 which is an N-channel MOSFET and a second transistor Q2 which is a P-channel MOSFET. Here, the drain terminal D of the first transistor Q1 Q1 The positive power supply voltage V DD Connect to the drain terminal D of the second transistor Q2. Q2 The negative power supply voltage V EEConnect to the source terminal S of the first transistor Q1. Q1 This is the source terminal S of transistor Q2. Q2 It is connected to and electrically coupled to output node 26. Furthermore, the gate terminal G of transistor Q1 Q1 This is the gate terminal G of transistor Q2. Q2 It is connected to and electrically coupled to input terminal 22. During operation, the power converter 16 supplies the input gate signal V to input terminal 22 of the voltage-type gate driver 12. IN The output voltage V is adjusted at the output node 26 connected to the gate driver resistor network 18. REG In another embodiment, the power converter 16 may be one of a voltage rectifier, regulator, inverter, or converter.

[0064] The gate driver resistor network 18 is connected between the output node 26 and output terminal 24 of the voltage-type gate driver 12. The gate driver resistor network 18 is connected to the turn-on gate resistor R G-ON and turn-off gate resistor R G-OFF It may include one or more resistors, including a turn-on gate resistor R. G-ON teeth, The turn-on gate resistor R G-ON For rectifying the current flowing in the first direction through First diode D1 is connected To be continued Turn-off gate resistor R G-OFF teeth, The turn-off gate resistor R G-OFF For rectifying the current flowing in the opposite direction to the first direction through this Connect to the second diode D2. To be continued Here, the turn-on gate resistor R is connected to the first diode D1. G-ON Then, the turn-off gate resistor R is connected to the second diode D2. G-OFF These are connected in parallel as shown in Figure 1. Here, the turn-on gate resistor R G-ON The value is in the range of 0Ω to 10MΩ, 1kΩ to 5MΩ, or 100kΩ to 3MΩ, and the turn-off gate resistor R G-OFFThe value ranges from 0 to 10 MΩ, from 1 kΩ to 5 MΩ, or from 100 kΩ to 3 MΩ. The gate driver resistor network 18 can have an equivalent resistance value in the range of 0 Ω to 10 MΩ, 1 kΩ to 5 MΩ, or 100 kΩ to 3 MΩ.

[0065] Furthermore, the series split gate resistor R G is used to electrically couple (i.e., connect them in series) the output terminal 24 of the voltage - type gate driver 12 and the gate terminal G of the semiconductor power device 14. In this way, the gate driver resistor network 18 uses the series split gate resistor R G with a value in the range of 0 Ω to 10 MΩ, 1 kΩ to 5 MΩ, or 100 kΩ to 3 MΩ to supply a resistively rectified current and voltage to the output terminal 24 of the voltage - type gate driver 12 connected to the gate terminal G of the semiconductor power device 14. Therefore, the turn - on gate resistor R G-ON , the turn - off gate resistor R G-OFF , and the series split gate resistor R G values can affect the charging and discharging current of the input capacitance C ISS of the semiconductor power device 14. The input capacitance C ISS must be charged or discharged depending on whether it is above or below the threshold voltage V TH of the semiconductor power device 14 before the state of the semiconductor power device 14 changes. So, as the values of the turn - on gate resistor R G-ON and the turn - off gate resistor R G-OFF increase, the gate delay increases and the switching speed of the semiconductor power device 14 from the off state to the on state, or vice versa, decreases. Therefore, as the values of the turn - on gate resistor R G-ON and the turn - off gate resistor R G-OFF increase, the switching losses of the semiconductor power device 14 during the operation of the power system 10 increase. Here, the series split gate resistor R GThe value can be increased so that the power system 10 meets electromagnetic compatibility and electromagnetic interference industry standards while avoiding vibrations. Nevertheless, without the shunt capacitor C GSNT and the shunt resistor R GSNT when increasing the value of the series split gate resistor R G undesirable, longer gate delays and higher switching losses are introduced in the operation of the semiconductor power device 14.

[0066] The introduction of the series-connected shunt capacitor C GSNT and the shunt resistor R GSNT connected in parallel across both ends of the gate driver resistor network 18 enables the separation of the switching speed of the semiconductor power device 14 from the gate delay of the semiconductor power device 14. This is particularly advantageous because it enables controlling the switching speed of the semiconductor power device 14 while the semiconductor power device 14 maintains a reduction in gate delay. Here, the shunt capacitor C GSNT enables the initial high charging and discharging of the input capacitance C ISS of the semiconductor power device 14 that reduces the gate delay. Thus, during the turn-on period and the turn-off period, the shunt capacitor C GSNT functions as a series-connected capacitive voltage divider having the input capacitance C ISS of the semiconductor power device 14 to establish the gate-source voltage V GS , while the shunt resistor R GSNT serves to prevent any false gate loop oscillation and / or gate loop triggering in the semiconductor power device 14. The application of the shunt capacitor C GSNT and the shunt resistor R GSNT is further advantageous because it eliminates the need for an external high-voltage RC snubber circuit between the drain terminal D and the source terminal S of the semiconductor power device 14.

[0067] Here, the shunt capacitor C GSNTThe value of can be determined (i.e., calculated) using equations (1) and (2) for the desired turn-on and turn-off performance of the power semiconductor device 14.

number

[0068] Therefore, the shunt resistor R GSNT The value may be in the range of 0Ω to 10MΩ, 1kΩ to 5MΩ, or 100kΩ to 3MΩ. Shunt resistor R GSNT To achieve vibration damping, a shunt capacitor C is used. GSNT Note that it is not necessary to connect it directly in series. Therefore, as long as sufficient resistance is present as part of the gate drive loop, the vibration damping function is achieved. Here, the gate drive loop is connected to the power supply voltage V DD or V EE This is a gate current path comprising a gate driver resistor network 18 and a semiconductor power device 14.

[0069] It is important to note that the semiconductor power device 14 shown in Figure 1 is a MOSFET Q3, but the scope of this disclosure is not limited thereto. The MOSFET Q3 may be either a P-type MOSFET or an N-type MOSFET. Those skilled in the art will understand that the semiconductor power device 14 may be one of the following: an insulated-gate bipolar transistor (IGBT), a junction-gate field-effect transistor (JFET), a high-electron-mobility transistor (HEMT), etc. Furthermore, the semiconductor power device 14 may comprise a half-bridge circuit topology 30, a parallel transistor connection circuit topology 30', or a common-source circuit topology 30'', as illustrated and described with reference to Figures 3A to 3C. Here, the semiconductor power device 14 may form an individual package or a power module.

[0070] Figure 2 shows multiple MOSFETs Q31~Q3 connected in parallel as part of the semiconductor power device 14'. nAn exemplary power system 10' having multiple MOSFETs Q31~Q3 is shown. n Integrated body diodes D31 to D3 (where n is the count) are provided and each is connected in parallel. n Except for the semiconductor power device 14' having a common drain node and a common source node (not shown for simplicity of illustration) of the semiconductor power device 14', the power system 10' shown in Figure 2 is substantially the same as the power system 10 described in Figure 1. The common drain node and common source node (not shown for simplicity of illustration) of the semiconductor power device 14' may be connected to the load 20 at the first load node 34 and the second load node 36, respectively. The elements shown in Figure 2, which were mentioned in relation to Figure 1, are not described here for brevity.

[0071] As shown in Figure 2, MOSFETs Q31~Q3 n Each of these is a series split-gate resistor R G1 ~R Gn It is further equipped with a series split-gate resistor R. G1 ~R Gn This is parallel MOSFET Q31~Q3 n It is used to dampen and avoid vibrations between them. Furthermore, a series split-gate resistor R G1 ~R Gn By increasing the respective values ​​of the semiconductor power device 14' MOSFET Q31~Q3 n The switching speed of one of them is reduced. Alternatively, a series split-gate resistor R G1 ~R Gn By reducing each of the values, the MOSFET Q31~Q3 of the semiconductor power device 14' nThe switching speed of one of these is increased. In one embodiment, a current buffer stage (not shown here for simplicity of the figure) can be applied between the power converter 16 and the gate driver resistor network 18 as part of the voltage-type gate driver 12. The current buffer can increase the gate current capability of the voltage-type gate driver 12 in high-current, high-power applications. This is particularly advantageous when multiple semiconductor power devices are connected in parallel, as shown in semiconductor power device 14'. Here, shunt capacitor C GSNT and shunt resistor R GSNT This operates similarly to the above, utilizing the increased current-driving capability of the current buffer to further minimize gate delay without affecting the switching speed.

[0072] Figures 3A to 3C illustrate exemplary circuit topologies applied in various embodiments of this disclosure as part of the semiconductor power devices 14 of the power system 10 shown in Figure 1. Here, the half-bridge circuit topology 30, the parallel transistor connection circuit topology 30', and the common source circuit topology 30'' (hereinafter also referred to as half-bridge 30, parallel transistor connection 30, and common source circuit 30'') can be integrated and applied to separate packages or power modules as part of the semiconductor power devices 14 of the power system 10 to rectify, invert, convert, or otherwise manipulate electrical energy using a voltage-type gate driver 12 that separates the control of switching speed and gate delay associated with the semiconductor power devices 14, as shown in Figure 1.

[0073] As illustrated in Figures 3A to 3C, the half-bridge circuit topology 30, the parallel transistor connection circuit topology 30', and the common source circuit topology 30'' each comprise a first transistor and a second transistor, and the first and second transistors may be one of the following: metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), junction-gate field-effect transistors (JFETs), high electron-mobility transistors (HEMTs), etc.

[0074] Figure 3A shows an exemplary half-bridge circuit topology 30. The half-bridge circuit topology 30 (also called half-bridge 30) comprises a high-side power semiconductor switching device labeled as high-side, including a first MOSFET device M1, and a low-side power semiconductor switching device labeled as low-side, including a second MOSFET device M2, a power supply in the form of a bulk capacitor bank DC link, and a decoupling capacitor Cd electrically coupled between a positive DC busbar DC+ and a negative DC busbar DC-. The first MOSFET device M1 comprises a first gate terminal G1, a first source terminal S1, and a first drain terminal D1, and the second MOSFET device M2 comprises a second gate terminal G2, a second source terminal S2, and a second drain terminal D2. As shown, the first drain terminal D1 of the first MOSFET device M1 is connected to the positive DC busbar DC+, the second source terminal S2 of the second MOSFET device M2 is connected to the negative DC busbar DC-, and the first source terminal S1 of the first MOSFET device M1 is connected to the second drain terminal D2 of the second MOSFET device M2, forming a phase node N1 to which the phase terminal T1 is connected. This configuration is commonly used in various topologies, including but not limited to multilevel converters, current source inverters, and solid-state circuit breakers.

[0075] Figure 3B shows a parallel transistor connection circuit topology 30' in which a first MOSFET device M1 and a second MOSFET device M2 are connected to form a common source node N3 and a common drain node N2. The first MOSFET device M1 includes a first gate terminal G1, a first source terminal S1, and a first drain terminal D1, while the second MOSFET device M2 includes a second gate terminal G2, a second source terminal S2, and a second drain terminal D2. As shown in Figure 3B, the first drain terminal D1 of the first MOSFET device M1 and the second drain terminal D2 of the second MOSFET device M2 are electrically connected to form a common drain node N2 and a common drain input / output terminal T2. Similarly, the first source terminal S1 of the first MOSFET device M1 and the second source terminal S2 of the second MOSFET device M2 are electrically connected to form a common source node N3 and a common source input / output terminal T3. The parallel transistor connection circuit topology 30' can be used in high-power applications where individual transistors cannot carry the large currents required for high-power applications. For example, the semiconductor power device 14 shown in Figure 1 may further include power MOSFETs M1 and M2 connected in parallel to each other, as shown in Figure 3B. Note that parallel transistor connections, such as the parallel transistor connection circuit topology 30' shown in Figure 3, are particularly advantageous because they further increase the power level associated with the semiconductor power device 14 shown in Figure 1. Here, Figure 2 illustrates, for example, multiple transistors connected in parallel in a discrete package as part of the semiconductor power device 14'. Here, multiple MOSFETs Q31 to Q3 are connected in parallel. n A single shunt resistor R is used for the entire semiconductor power device 14' which includes the above. GSNT and a single shunt capacitor C GSNT Multiple MOSFETs Q31~Q3 may be used. n Each of these consists of parallel MOSFETs Q31~Q3 that form part of the semiconductor power device 14'. n To avoid gate oscillations between them, each split-gate resistor R G1 ~RGn A system will be established.

[0076] Figure 3C illustrates a common source circuit topology 30”. As illustrated, the common source transistor circuit topology 30 comprises a first MOSFET M1 having a first gate terminal G1, a first source terminal S1, and a first drain terminal D1, and a second MOSFET M2 having a second gate terminal G2, a second source terminal S2, and a second drain terminal D2. In this configuration, the first source S1 of the first MOSFET device M1 and the second source S2 of the second MOSFET device M2 are electrically connected to form a common source node N4. Furthermore, the first drain D1 of the first MOSFET device M1 forms an upper input / output terminal T4, and the second drain D2 of the second MOSFET device M2 forms a lower input / output terminal T5. The upper input / output terminal T4 and the lower input / output terminal T5 are coupled between a voltage source (not shown) configured to supply a DC supply voltage and a load, forming a bidirectional switch with the function of interrupting current in both directions and providing an on-state voltage or an off-state voltage. This configuration provides bidirectional voltage blocking capability, from the first drain terminal D1 to the second drain terminal D2, or from the second drain terminal D2 to the first drain terminal D1. Therefore, the common source circuit topology 30" is particularly advantageous for enabling various power conversion functions.

[0077] Figures 4A and 4B show the shunt capacitor C GSNT There is a shunt resistor R GSNT (R GSNT (R = 0Ω), Figure 1 is a graph showing the voltage and current characteristics of the semiconductor power device 14 of the power system 10. The power system 10 includes a voltage-type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device. However, the shunt resistor (R) GSNT ) is not connected to the shunt capacitor (C GSNTThese elements cause vibrations during the turn-off and turn-on of the semiconductor power device 14, as shown in Figures 4A and 4B, respectively. The elements described in Figures 4A and 4B, which were mentioned in relation to Figures 1-3, are not described here for brevity.

[0078] Here, Figures 4A and 4B respectively show a positive power supply voltage of 15V V DD -5V negative power supply voltage V EE , and the gate-source voltage over time (V) based on measurements obtained under a bus voltage of 800V. GS -Time), drain-source voltage over time (V DS -time), and drain-source current over time (I DS A graph of the time (-time) is provided. The semiconductor power device 14 is a MOSFET with a rated drain-source voltage of 1200V V DS , and a rated drain-source current of 120A I DS Furthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25°C and an input capacitance C of 8.5 nF. ISS , 75Ω turn-on gate resistor R G-ON , 75Ω turn-off gate resistor R G-OFF , 0Ω series split-gate resistor R G , and a threshold voltage of 5V V TH It has a shunt capacitor C. GSNT This is calculated to be 8.5nF using equations (1) and (2) above.

[0079] Figure 4A is a graph showing the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-off transition. The power system 10 includes a shunt capacitor C. GSNT Equipped with a shunt resistor R GSNT (R GSNT (=0Ω). The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned off. GS (V GSThe second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned off. DS (I DS -Time) is shown. Here, the turn-off time (t) off The turn-off delay time was measured to be approximately 200 ns. td(off) The turn-off current rate (di / dt) was measured to be approximately 180 ns, and the turn-off current rate (di / dt) was measured to be approximately 180 ns. off The measured value was approximately 4 A / ns, and the turn-off voltage speed (dv / dt) was also measured. off The voltage rise time (t) was measured to be approximately 20V / ns. r The measured value is approximately 20 ns. Large oscillations are observed in the gate-source voltage V GS , drain-source voltage V DS , and drain-source current I DS It is related to the shunt resistor R GSNT This is due to the absence of such a thing.

[0080] Figure 4B is a graph showing the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-on transition. The power system 10 includes a shunt capacitor C. GSNT Equipped with a shunt resistor R GSNT (R GSNT (=0Ω). The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned on. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned on. DS (I DS -Time) is shown. Here, the turn-on time (t) onThe turn-on delay time (t) was measured to be approximately 120 ns, and the turn-on delay time (t) was measured to be approximately 120 ns. d(on) The measured value was approximately 80 ns, and the turn-on current rate (di / dt) was also measured. on The measured value was approximately 1 A / ns, and the turn-on voltage rate (dv / dt) was also measured. on The drain-source voltage (V) was measured to be approximately 15V / ns. DS ) fall time (t f The measured value is approximately 20 ns. As shown, large oscillations occur in the gate-source voltage V GS , drain-source voltage V DS , and drain-source current I DS It is related to the shunt resistor R GSNT This is due to the absence of a shunt resistor (R) (as shown in Figures 5A and 5B) in order to maintain stability. GSNT Using this, gate vibration of the semiconductor power device 14 can be prevented.

[0081] Figures 5A and 5B show the shunt capacitor C GSNT and shunt resistor R GSNT This is a graph showing the voltage and current characteristics of the semiconductor power device 14 (i.e., discrete device) of the power system 10 shown in Figure 1. The power system 10 includes a voltage-type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device. The elements described in Figures 5A and 5B, which were mentioned earlier in relation to Figures 1-3, are not described here for brevity.

[0082] Here, Figures 5A and 5B respectively show a positive power supply voltage of 15V V DD -5V negative power supply voltage V EE , and the gate-source voltage over time (V) based on measurements obtained under a bus voltage of 800V. GS -Time), drain-source voltage over time (V DS -time), and drain-source current over time (I DSA graph of the time (-time) is provided. The semiconductor power device 14 is a MOSFET with a rated drain-source voltage of 1200V V DS , and a rated drain-source current of 120A I DS Furthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25°C and a turn-on gate resistor R of 75 Ω. G-ON , 75Ω turn-off gate resistor R G-OFF , 0Ω series split-gate resistor R G , input capacitance C of 8.5nF ISS , and a threshold voltage of 5V V TH It has a shunt capacitor C. GSNT This is calculated to be 8.5nF using equations (1) and (2) as described above. As a result, the shunt resistor R GSNT The value of is determined to be 22Ω. As shown, the vibrations during turn-off and turn-on transitions are significantly reduced in Figures 5A and 5B compared to Figures 4A and 4B. This is because the shunt resistor R is large enough to dampen the vibrations. GSNT This is a result of its implementation.

[0083] Figure 5A shows the shunt capacitor C. GSNT and shunt resistor R GSNT The graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-off transition. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned off. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned off. DS (I DS -Time) is shown. Here, the turn-off time (t) off The turn-off delay time (t) was measured to be approximately 200 ns, and the turn-off delay time (t) was measured to be approximately 200 ns. d(off)The turn-off current rate (di / dt) was measured to be approximately 180 ns, and the turn-off current rate (di / dt) was measured to be approximately 180 ns. off The measured value was approximately 4 A / ns, and the turn-off voltage speed (dv / dt) was also measured. off The voltage rise time (t) was measured to be approximately 20V / ns. r The measured value was approximately 20 ns. Therefore, the shunt resistor R GSNT It has been shown that incorporating this feature helps reduce and eliminate vibrations.

[0084] Figure 5B shows the shunt capacitor C GSNT and shunt resistor R GSNT The graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-on transition. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned on. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned on. DS (I DS -Time) is shown. Here, the turn-on time (t) on The turn-on delay time (t) was measured to be approximately 120 ns, and the turn-on delay time (t) was measured to be approximately 120 ns. d(on) The measured value was approximately 80 ns, and the turn-on current rate (di / dt) was also measured. on The measured value was approximately 1 A / ns, and the turn-on voltage rate (dv / dt) was also measured. on The drain-source voltage (V) was measured to be approximately 15V / ns. DS ) fall time (t f The measured value was approximately 20 ns.

[0085] Figures 6A and 6B show the shunt capacitor C GSNT Shunt resistor R GSNT , and a series split-gate resistor R GThis is a graph showing the voltage and current characteristics of the semiconductor power device 14 (i.e., the half-bridge 30 power module) of the power system 10 shown in Figure 1. The power system 10 includes a voltage-type gate driver 12 coupled to the semiconductor power device 14, which is the half-bridge 30 power module, as shown in Figure 3A. The elements described in Figures 6A and 6B, which were mentioned earlier in relation to Figures 1-3, are not described here for brevity.

[0086] Here, Figures 6A and 6B respectively show a positive power supply voltage of 15V V DD -5V negative power supply voltage V EE , and based on measurements obtained under conditions where a bus voltage of 800V is used, the gate-source voltage over time (V GS -Time), drain-source voltage over time (V DS -time), and drain-source current over time (I DS A graph of the time (-time) is provided. The semiconductor power device 14 is a half-bridge 30 with a rated drain-source voltage of 1200V V DS , and a rated drain-source current of 50A I DS Furthermore, the half-bridge power module as part of the semiconductor power device 14 has a drain-source on-state resistor Rds(ON) of 19 mΩ at 25°C and a turn-on gate resistor R of 75 Ω. G-ON , 75Ω turn-off gate resistor R G-OFF , 0Ω series split-gate resistor R G , 3nF input capacitance C ISS , and a threshold voltage of 5V V TH It has a shunt capacitor C. GSNT The value is calculated to be 3nF using equations (1) and (2) as described above. As a result, the shunt resistor R GSNT The value of is determined to be 15Ω. As shown, shunt capacitor C GSNT and shunt resistor R GSNT This is a series split-gate resistor R GThe introduction of a series split-gate resistor R mitigates the longer gate delay and higher switching losses that may result. G This may be introduced to ensure that the semiconductor power device 14 meets electromagnetic compatibility and electromagnetic interference industry standards while avoiding vibration.

[0087] Figure 6A shows the turn-off transition in progress, with the shunt capacitor C GSNT Shunt resistor R GSNT , and a series split-gate resistor R G The first graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned off. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned off. DS (I DS -Time) is shown. Here, the turn-off time (t) off The measured value was approximately 68 ns, and the turn-off delay time (t d(off) The measured value was approximately 48 ns, and the turn-off current rate (di / dt) was also measured. off The measured value was approximately 6 A / ns, and the turn-off voltage speed (dv / dt) was also measured. off The voltage was measured to be approximately 37.5 V / ns, and the voltage rise time (t) was also measured to be approximately 37.5 V / ns. r The measured value was approximately 20 ns.

[0088] Figure 6B shows the turn-on transition in progress, with the shunt capacitor C GSNT Shunt resistor R GSNT , and a series split-gate resistor R GThe first graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned on. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned on. DS (I DS -Time) is shown. Here, the turn-on time (t) on The turn-on delay time (t) was measured to be approximately 72 ns. d(on) The measured value was approximately 56 ns, and the turn-on current rate (di / dt) was also measured. on The measured value was approximately 2 A / ns, and the turn-on voltage speed (dv / dt) was also measured. on The voltage was measured to be approximately 37.5 V / ns, and the voltage drop time (t) was also measured to be approximately 37.5 V / ns. f The measured duration was approximately 16 ns.

[0089] Figures 7A and 7B show the turn-on gate resistor R G-ON and turn-off gate resistor R G-OFF This is a graph showing the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1, generated using different values. The power system 10 includes a voltage-type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device. The elements described in Figures 7A and 7B, mentioned above in relation to Figures 1-3, are not shown here for brevity.

[0090] Here, Figures 7A and 7B respectively show a positive power supply voltage of 15V V DD -5V negative power supply voltage V EE , and based on measurements obtained under conditions where a bus voltage of 800V is used, the gate-source voltage over time (V GS -Time), drain-source voltage over time (V DS-time), and drain-source current over time (I DS A graph of the time (-time) is provided. The semiconductor power device 14 is a MOSFET with a rated drain-source voltage of 1200V V DS , and a rated drain-source current of 120A I DS Furthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25°C and an input capacitance C of 8.5 nF. ISS , and a threshold voltage V which is 5V TH It has a shunt capacitor C. GSNT This is calculated to be 8.5nF using equations (1) and (2) as described above. As a result, the shunt resistor R GSNT The value of is determined to be 22Ω. Here, V GS -Time, V DS -Time, and I DS- Three graphs are generated for each time interval, and each of the three graphs has a different value (R G-ON =R G-OFF =100Ω, R G-ON =R G-OFF =150Ω, and R G-ON =R G-OFF (=200Ω) Sharp turn-on gate resistor R G-ON and turn-off gate resistor R G-OFF It is based on one of the three values. As shown, shunt capacitor C GSNT and shunt resistor R GSNT This reduces longer gate delays.

[0091] Figure 7A shows the turn-off transition in progress, with different values ​​(R G-ON =R G-OFF =100Ω, R G-ON =R G-OFF =150Ω, and R G-ON =R G-OFF (=200Ω) Sharp turn-on gate resistor R G-ON and turn-off gate resistor R G-OFFThe graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1, generated using [the specified method]. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned off. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned off. DS (I DS -Time) is shown. Here, R G-ON =R G-OFF A turn-on gate resistor R with a value of =100Ω G-ON and turn-off gate resistor R G-OFF Regarding the turn-off time (t off The turn-off delay time (t) was measured to be approximately 240 ns, and the turn-off delay time (t) was measured to be approximately 240 ns. d(off) The turn-off current rate (di / dt) was measured to be approximately 200 ns, and the turn-off current rate (di / dt) was measured to be approximately 200 ns. off The measured value was approximately 6 A / ns, and the turn-off voltage speed (dv / dt) was also measured. off The measured voltage rise time (t) was approximately 26V / ns, and the voltage rise time (t) was also measured. r ) was measured and is approximately 30 ns. Furthermore, R G-ON =R G-OFF A turn-on gate resistor R with a value of =150Ω G-ON and turn-off gate resistor R G-OFF Regarding the turn-off time (t off The turn-off delay time (t) was measured to be approximately 280 ns, and the turn-off delay time (t) was measured to be approximately 280 ns. d(off) The turn-off current rate (di / dt) was measured to be approximately 240 ns, and the turn-off current rate (di / dt) was measured to be approximately 240 ns. off The measured turn-off voltage speed (dv / dt) was approximately 2.5 A / ns, and the turn-off voltage speed (dv / dt) was also measured to be approximately 2.5 A / ns. off The measured voltage rise time (t) was approximately 16V / ns, and the voltage rise time (t) was also measured. r ) was measured and is approximately 50 ns. Finally, R G-ON =R G-OFF A turn-on gate resistor R with a value of 200ΩG-ON and turn-off gate resistor R G-OFF Regarding the turn-off time (t off The turn-off delay time (t) was measured to be approximately 320 ns, and the turn-off delay time (t) was measured to be approximately 320 ns. d(off) The turn-off current rate (di / dt) was measured to be approximately 280 ns, and the turn-off current rate (di / dt) was measured to be approximately 280 ns. off The turn-off voltage speed (dv / dt) was measured to be approximately 1.6 A / ns, and the turn-off voltage speed (dv / dt) was measured to be approximately 1.6 A / ns. off The measured voltage rise time (t) was approximately 12V / ns, and the voltage rise time (t) was also measured. r The measured duration was approximately 70 ns.

[0092] Figure 7B shows the turn-on transition, with different values ​​(R G-ON =R G-OFF =100Ω, R G-ON =R G-OFF =150Ω, and R G-ON =R G-OFF (=200Ω) Sharp turn-on gate resistor R G-ON and turn-off gate resistor R G-OFF The graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1, generated using [the specified method]. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned on. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned on. DS (I DS -Time) is shown. Here, R G-ON =R G-OFF A turn-on gate resistor R with a value of =100Ω G-ON and turn-off gate resistor R G-OFF Regarding the turn-on time (t on The turn-on delay time (t) was measured to be approximately 240 ns, and the turn-on delay time (t) was measured to be approximately 240 ns. d(on) The turn-on current rate (di / dt) was measured to be approximately 160 ns, and the turn-on current rate (di / dt) was measured to be approximately 160 ns. onThe turn-on voltage speed (dv / dt) was measured to be approximately 1.5 A / ns, and the turn-on voltage speed (dv / dt) was measured to be approximately 1.5 A / ns. on The voltage drop time (t) was measured to be approximately 15V / ns. f ) was measured and is approximately 40 ns. Furthermore, R G-ON =R G-OFF A turn-on gate resistor R with a value of =150Ω G-ON and turn-off gate resistor R G-OFF Regarding the turn-on time (t on The turn-on delay time (t) was measured to be approximately 280 ns, and the turn-on delay time (t) was measured to be approximately 280 ns. d(on) The turn-on current rate (di / dt) was measured to be approximately 200 ns, and the turn-on current rate (di / dt) was measured to be approximately 200 ns. on The measured value was approximately 1 A / ns, and the turn-on voltage rate (dv / dt) was also measured. on The voltage drop time (t) was measured to be approximately 12V / ns. r ) was measured and is approximately 50 ns. Finally, R G-ON =R G-OFF A turn-on gate resistor R with a value of 200Ω G-ON and turn-off gate resistor R G-OFF Regarding the turn-on time (t on The turn-on delay time (t) was measured to be approximately 320 ns, and the turn-on delay time (t) was measured to be approximately 320 ns. d(on) The turn-on current rate (di / dt) was measured to be approximately 240 ns, and the turn-on current rate (di / dt) was measured to be approximately 240 ns. on The turn-on voltage speed (dv / dt) was measured to be approximately 0.75 A / ns, and the turn-on voltage speed (dv / dt) was measured to be approximately 0.75 A / ns. on The voltage drop time (t) was measured to be approximately 10V / ns. f The measured duration was approximately 60 ns.

[0093] Figures 8A and 8B show the shunt capacitor C GSNT and shunt resistor R GSNTFigure 1 shows a graph illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10, which has electrical characteristics suitable for low-speed switching applications, such as circuit breakers. The power system 10 is a discrete semiconductor device and includes a voltage-type gate driver 12 coupled to the semiconductor power device 14, which is suitable for low-speed switching applications, such as solid-state circuit breakers. The elements described in Figures 8A and 8B, mentioned above in relation to Figures 1-3, are not described here for brevity.

[0094] Here, Figures 8A and 8B respectively show a positive power supply voltage of 15V V DD -6V negative power supply voltage V EE , and the gate-source voltage over time (V) based on measurements obtained under a bus voltage of 800V. GS -Time), drain-source voltage over time (V DS -time), and drain-source current over time (I DS A graph of the time (-time) is provided. The semiconductor power device 14 is a MOSFET with a rated drain-source voltage of 1200V V DS , and a rated drain-source current of 120A I DS Furthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25°C and a turn-on gate resistor R of 1.5 kΩ. G-ON , 3kΩ turn-off gate resistor R G-OFF , 0Ω series split-gate resistor R G , input capacitance C of 8.5nF ISS , and a threshold voltage of 5V V TH It holds.

[0095] Figure 8A shows the shunt capacitor C GSNT and shunt resistor R GSNTThe first graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-off transition, where the semiconductor power device 14 has electrical characteristics suitable for low-speed switching applications. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned off. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned off. DS (I DS -Time) is shown. Here, the turn-off time (t) off The measured value was approximately 22 ns, and the turn-off delay time (t d(off) The measured value was approximately 21 ns, and the turn-off current rate (di / dt) was also measured. off The turn-off voltage speed (dv / dt) was measured to be approximately 0.09 A / ns, and the turn-off voltage speed (dv / dt) was measured to be approximately 0.09 A / ns. off The voltage was measured to be approximately 0.89 V / ns, and the voltage rise time (t) was also measured to be approximately 0.89 V / ns. r The measured value was approximately 1 μs.

[0096] Figure 8B shows the shunt capacitor C GSNT and shunt resistor R GSNT The first graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-on transition, and the semiconductor power device 14 has electrical characteristics suitable for low-speed switching applications. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned on. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned on. DS (I DS-Time) is shown. Here, the turn-on time (t) on The measured turn-on delay time (t) was approximately 12 μs, and the turn-on delay time (t) was measured to be approximately 12 μs. d(on) The turn-on current rate (di / dt) was measured to be approximately 11 μs, and the turn-on current rate (di / dt) was measured to be approximately 11 μs. on The measured turn-on voltage speed (dv / dt) was approximately 0.13 A / ns, and the turn-on voltage speed (dv / dt) was also measured to be approximately 0.13 A / ns. on The voltage was measured to be approximately 0.93 V / ns, and the voltage drop time (t) was also measured to be approximately 0.93 V / ns. f The measured value was approximately 1 μs.

[0097] Figures 9A and 9B show the shunt capacitor C GSNT and shunt resistor R GSNT Figure 1 shows a graph illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10, which has electrical characteristics suitable for low-speed switching applications. The power system 10 is a discrete semiconductor device and includes a voltage-type gate driver 12 coupled to the semiconductor power device 14, which is suitable for low-speed switching applications, such as solid-state circuit breakers. The elements described in Figures 9A and 9B, which were mentioned above in relation to Figures 1-3, are not described here for brevity.

[0098] Here, Figures 9A and 9B respectively show a positive power supply voltage of 15V V DD -6V negative power supply voltage V EE , and based on measurements obtained under conditions where a bus voltage of 800V is used, the gate-source voltage over time (V GS -Time), drain-source voltage over time (V DS -time), and drain-source current over time (I DS A graph of the time (-time) is provided. The semiconductor power device 14 is a MOSFET with a rated drain-source voltage of 1200V V DS , and a rated drain-source current of 120A I DSFurthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25°C and a turn-on gate resistor R of 1.5 kΩ. G-ON , 3kΩ turn-off gate resistor R G-OFF , 0Ω series split-gate resistor R G , input capacitance C of 8.5nF ISS , and a threshold voltage of 5V V TH It has a shunt capacitor C. GSNT This is calculated to be 8.5nF using equations (1) and (2) as described above. As a result, the shunt resistor R GSNT The value of this value is determined to be 22Ω.

[0099] Figure 9A shows the shunt capacitor C. GSNT and shunt resistor R GSNT The first graph shows the voltage and current characteristics of the discrete semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-off transition, and the discrete semiconductor power device 14 has electrical characteristics suitable for low-speed switching applications. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned off. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned off. DS (I DS -Time) is shown. Here, the turn-off time (t) off The measured turn-off delay time (t) was approximately 3 μs, and the turn-off delay time (t) was also measured to be approximately 3 μs. d(off) The turn-off current rate (di / dt) was measured to be approximately 2 μs, and the turn-off current rate (di / dt) was measured to be approximately 2 μs. off The turn-off voltage speed (dv / dt) was measured to be approximately 0.05 A / ns, and the turn-off voltage speed (dv / dt) was measured to be approximately 0.05 A / ns. off The voltage was measured to be approximately 0.88 V / ns, and the voltage rise time (t) was also measured to be approximately 0.88 V / ns. r The measured value was approximately 1 μs.

[0100] Figure 9B shows the shunt capacitor C GSNT and shunt resistor R GSNT The first graph shows the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in Figure 1 during the turn-on transition, and the semiconductor power device 14 has electrical characteristics suitable for low-speed switching applications. The first graph shows the gate-source voltage V over time when the semiconductor power device 14 is turned on. GS (V GS The second graph shows the drain-source voltage V over time when the semiconductor power device 14 is turned on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 is turned on. DS (I DS -Time) is shown. Here, the turn-on time (t) on The turn-on delay time (t) was measured to be approximately 5.5 μs, and the turn-on delay time (t) was measured to be approximately 5.5 μs. d(on) The turn-on current rate (di / dt) was measured and was approximately equal to 4.5 μs. on The measured value was approximately 0.07 A / ns, and the turn-on voltage speed (dv / dt) was also measured. on The voltage was measured to be approximately 0.87 V / ns, and the voltage drop time (t) was also measured to be approximately 0.87 V / ns. f The measured value was approximately 1 μs.

[0101] Therefore, as shown in Figures 9A and 9B, the turn-off delay time (t d(off) ) and turn-on delay time (t d(on) ) is a shunt capacitor C GSNT and shunt resistor R GSNT The introduction of this feature significantly reduces the effect compared to those shown in Figures 8A and 8B.

[0102] Any of the embodiments described herein, and / or various other embodiments and features described herein, may be combined to obtain further advantages. Any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments unless otherwise specifically stated herein.

[0103] Those skilled in the art will recognize improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are deemed to be within the scope of the concepts disclosed herein and the following claims.

Images