Method and apparatus for a page-local delta-based prefetcher

Abstract

The method includes recording a first set of consecutive memory access deltas, each consecutive memory access delta representing a difference between two memory addresses accessed by the application; updating values ​​of a prefetch training table based on the first set of memory access deltas; and predicting one or more memory addresses to prefetch based on the values ​​of the prefetch training table in response to a second set of consecutive memory access deltas.

Claims

1. It is a method, A computing device records a first set of consecutive memory access deltas, each of which represents the difference between two memory addresses accessed by one or more processors. Depending on whether the first set of consecutive memory access deltas includes a threshold amount of memory access deltas, the computing device updates the values ​​of the prefetch training table based on the first set of consecutive memory access deltas by copying a first subset of the first set of consecutive memory access deltas to the prefetch training table. The computing device predicts one or more memory addresses to prefetch based on the updated values ​​of the prefetch training table, This includes prefetching one or more predicted memory addresses, method.

2. The aforementioned prefetch training table includes a pattern history table that stores one or more entries, Each of the one or more entries includes a sequence of memory access delta values ​​and an age field. The method according to claim 1.

3. The aforementioned prediction is performed in accordance with a second set of consecutive memory access deltas. The method according to claim 1.

4. Calculating each of the first set of consecutive memory access deltas based on the memory address located in the first memory page, Calculate each of the second set of consecutive memory access deltas based on the memory address located in the second memory page, The further includes storing a first set of the consecutive memory access deltas and a second set of the consecutive memory access deltas in different entries. The method according to claim 3.

5. In accordance with the determination that the first entry contains at least m memory access deltas (where m is an integer greater than or equal to 2), Calculating a hash based on the program counter associated with the most recent memory access and a second set of the consecutive memory access deltas, The process involves performing a lookup of the hash in a correlation table that associates the hash with the identifier of an entry in the prefetch training table, thereby identifying an entry in the prefetch training table that contains the value, wherein the correlation table stores, for each entry, the hash value, the prefetch training table entry identifier, and the age field. This further includes selecting the value from the prefetch training table, The method according to claim 3.

6. The value selected from the prefetch training table includes one or more of the first set of consecutive memory access deltas. The method further includes predicting one or more prefetch addresses based on the selected value and the memory address of the most recent memory access by the application. The method of claim 5.

7. The aforementioned prefetch training table includes a correlation weight table, The values ​​in the prefetch training table represent the weights in the correlation weight table. Updating the values ​​in the prefetch training table means that for each memory access delta in the subset of the first set of memory access deltas, In the aforementioned correlation weight table, The aforementioned memory access delta, The most recent memory access delta and The sequence distance of the memory access delta from the most recent memory access delta, Further including incrementing one of the weights associated with The method according to claim 1.

8. The aforementioned prefetch training table includes a correlation weight table, The method described above, depending on the determination that the local pattern buffer contains at least n memory access deltas, For each of the at least n memory access deltas, From the correlation weight table, select a set of weight values ​​corresponding to the memory access delta and the sequence position of the memory access delta relative to the sequence position of the future memory access delta. This further includes adding the selected weight value to each cumulative weight value in the sum register vector, Predicting one or more memory addresses for prefetching is based on the index of the maximum cumulative weight value in the sum register vector after the sum of the selected weight values ​​has been performed for all of the at least n memory access deltas. The method according to claim 1.

9. Depending on whether the maximum cumulative weight value is determined to exceed a threshold, the process further includes performing a prefetch based on one or more predicted memory addresses. The method of claim 8.

10. The aforementioned prefetch training table includes a correlated weight table that stores multiple weight values, Each weight value represents the correlation between the memory access delta and the candidate for future access delta. Updating the values ​​in the prefetch training table includes, for each memory access delta in a subset of memory access deltas from a first set of memory access deltas, incrementing one of the following weight values ​​in the correlation weight table: the weight value associated with the memory access delta, the weight value associated with the most recent memory access delta stored after the subset, and the weight value associated with the sequence distance between the memory access delta and the most recent memory access delta. The index of the maximum cumulative weight value represents the predicted future memory access delta. Predicting one or more additional memory addresses to prefetch by performing a search within the correlation weight table based on the predicted future memory access delta and the most recent memory access delta, wherein the search includes selecting weight values ​​from the correlation weight table corresponding to the predicted future memory access delta and the most recent memory access delta and the respective sequence positions for the next future memory access delta, and accumulating the selected weight values ​​to identify the next predicted future memory access delta. The method according to claim 1.

11. The aforementioned prefetch training table includes a correlated weight table that stores multiple weight values, Each weight value represents the correlation between the memory access delta and the candidate for future access delta. The method further includes, upon detecting the evicting of unused prefetched data from the cache, decrementing each of the set of weights associated with the evicted prefetched data in the correlation weight table, wherein the set of weights includes weight values ​​used to predict the memory address corresponding to the evicted prefetched data. The method according to claim 1.

12. A computing device, A storage device configured to store a first set of consecutive memory access deltas, each of which represents the difference between two memory addresses accessed by an application, A memory configured to store prefetch training data in a prefetch training table, wherein the prefetch training table is updated based on the pattern of input delta values ​​and stores prefetch training data accessed during the prefetch prediction phase for predicting future delta values ​​based on the delta pattern history. Equipped with prefetch logic, The aforementioned prefetch logic is: Depending on whether the first set of consecutive memory access deltas includes a threshold amount of memory access deltas, the values ​​in the prefetch training table are updated based on the first set of consecutive memory access deltas by copying a first subset of the first set of consecutive memory access deltas to the prefetch training table. Based on the values ​​in the aforementioned prefetch training table, predict one or more memory addresses to prefetch, Prefetching one or more predicted memory addresses, It is configured to do, Computing device.

13. The aforementioned prefetch training table includes a pattern history table that stores one or more entries, Each of the one or more entries includes a sequence of memory access delta values ​​and an age field. The computing device according to claim 12.

14. The prefetch logic is configured to predict one or more memory addresses to prefetch in accordance with a second set of consecutive memory access deltas. The computing device according to claim 12.

15. The system further comprises a hash engine configured to compute a hash based on a program counter associated with the most recent memory access and a second set of consecutive memory access deltas. The aforementioned prefetch logic is: In accordance with the determination that the first entry contains at least m memory access deltas (where m is an integer greater than or equal to 2), The system is further configured to select the value from the prefetch training table by performing a lookup of the hash in a correlation table that associates the hash with the identifier of an entry in the prefetch training table, thereby identifying an entry in the prefetch training table that contains the value. The aforementioned correlation table stores, for each entry, a hash value, a prefetch training table entry identifier, and an age field. The computing device according to claim 12.

16. The value selected from the prefetch training table includes one or more of the first set of consecutive memory access deltas. The prefetch logic is further configured to predict one or more prefetch addresses based on the selected value and the memory address of the most recent memory access by the application. The computing device according to claim 15.

17. The aforementioned prefetch training table includes a correlation weight table, The values ​​from the prefetch training table represent the weights in the correlation weight table, The aforementioned prefetch logic is: For each memory access delta within a subset of the first set of memory access deltas, In the aforementioned correlation weight table, The aforementioned memory access delta, The most recent memory access delta and The sequence distance of the memory access delta from the most recent memory access delta, The values ​​in the prefetch training table are updated by incrementing one of the weights associated with the value. The computing device according to claim 12.

18. A computing system, Main memory and Cache memory and The system comprises a prefetcher coupled to the main memory and the cache memory, The aforementioned prefetcher is Recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents the difference between two memory addresses in the main memory accessed by the application, The method involves updating the values ​​in the prefetch training table based on the first set of consecutive memory access deltas, by copying a first subset of the first set of consecutive memory access deltas to the prefetch training table, wherein the prefetch training table is updated based on the pattern of input delta values ​​and stores prefetch training data accessed during the prefetch prediction phase for predicting future delta values ​​based on the delta pattern history. Based on the values ​​in the prefetch training table, data is prefetched from one or more prefetch memory addresses in the main memory to the cache memory, Prefetching one or more predicted memory addresses, It is configured to do, Computing system.

19. The aforementioned prefetch training table includes a pattern history table that stores one or more entries, Each of the one or more entries includes a sequence of memory access delta values ​​and an age field. The computing system according to claim 18.

20. The aforementioned prefetcher is Calculating each of the first set of consecutive memory access deltas based on the memory address located in the first memory page, Calculate each of the second set of consecutive memory access deltas based on the memory addresses located in the second memory page, The first set of consecutive memory access deltas and the second set of consecutive memory access deltas are stored in different entries. It is further configured to do the following: The computing system according to claim 18.

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