Thin-film transistors and methods for manufacturing them, memory and methods for manufacturing them, and electronic devices

Abstract

To provide a thin film transistor and a manufacturing method, a memory and a manufacturing method, and an electronic device, and relate to the field of memory technologies, to reduce a size of the thin film transistor, improve area utilization, and reduce routing difficulty.SOLUTION: A thin film transistor includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate. The first electrode and the second electrode are electrically connected to the semiconductor layer respectively.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Technical Field

[0002] This application relates to the field of memory technology, and particularly to thin film transistors and manufacturing methods, memories and manufacturing methods, and electronic devices.

Background Art

[0003] Thin film transistors (TFTs) have advantages such as low leakage current, low growth temperature, and high mobility. Therefore, thin film transistors have been widely used in various devices such as memories.

[0004] The structure of an existing thin film transistor is shown in FIG. 1. The thin film transistor 10 includes a semiconductor layer (sometimes referred to as an active layer) 102 disposed on a substrate 101, a source 103 and a drain 104 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102, a gate insulating layer 105 disposed on the semiconductor layer 102, and a gate 106 disposed on the gate insulating layer 105.

[0005] The semiconductor layer 102 of the existing thin film transistor 10 extends along a plane parallel to the gate 106, and the source 103 and the drain 104 are located in the same layer. Therefore, the size of the thin film transistor 10 is relatively large and the area utilization rate is low. In addition, since the source electrode 103 and the drain electrode 104 are located in the same layer, a short circuit easily occurs during the routing of the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104. This does not contribute to the routing and increases the difficulty of the process.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Embodiments of the present invention provide thin-film transistors and manufacturing methods, memory and manufacturing methods, and electronic devices for reducing the size of thin-film transistors, improving area utilization, and reducing routing difficulties. [Means for solving the problem]

[0007] To achieve the aforementioned objectives, this application employs the following technical solutions.

[0008] According to the first aspect, a thin-film transistor is provided. The thin-film transistor includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at the top and a gate body extending from the gate base to the bottom. The first electrode is located at the bottom. The second electrode is located between the first electrode and the gate base. The first dielectric layer is positioned between the second electrode and the first electrode, and the first dielectric layer is configured to isolate the first electrode from the second electrode. The semiconductor layer is positioned along the side of the gate body, and the second dielectric layer isolates the semiconductor layer from the gate. The first electrode and the second electrode are each electrically connected to the semiconductor layer.

[0009] Compared to the prior art, the semiconductor layer is arranged along a plane parallel to the gate (the gate in the prior art is equivalent to the gate base in this embodiment of the present application), and the second electrode and the first electrode are located in the same layer. In this embodiment of the present application, the semiconductor layer is arranged along the side of the gate body, the first electrode is located at the bottom, and the second electrode is located between the first electrode and the gate base, and the first electrode and the second electrode are electrically connected to the semiconductor layer, respectively. Therefore, the thin-film transistor provided in this embodiment of the present application has a relatively small size on a plane parallel to the gate base. Thus, in this embodiment of the present application, the size of the thin-film transistor is reduced and the area utilization rate is improved. In addition, since the second electrode and the first electrode of the thin-film transistor in this embodiment of the present application are located in different layers, short circuits that occur during routing of signal lines electrically connected to the second electrode and signal lines electrically connected to the first electrode can be avoided, thereby reducing process difficulties.

[0010] In one possible implementation, the second electrode is positioned near the gate base. This avoids direct electrical contact between the first and second electrodes during manufacturing.

[0011] In one possible implementation, the boundary of the projection of the gate body onto the gate base lies within the boundary of the gate base. In this case, the gate body is located in the central region of the gate base.

[0012] In one possible implementation, the boundary of the projection of the gate body onto the gate base partially overlaps with the boundary of the gate base. In this case, the gate body is positioned in the edge region of the gate base.

[0013] In one possible implementation, the gate body is hollow, and the outer boundary of the projection of the gate body onto the gate base coincides with the boundary of the gate base. Because the gate body is hollow, the second dielectric layer, semiconductor layer, second electrode, and first dielectric layer can be placed within the hollow structure.

[0014] In one possible implementation, the semiconductor layer further includes an extension that extends along the surface of the gate base. In this way, the area of ​​the semiconductor layer can be increased, thereby increasing the electrical connection area between the semiconductor layer and the second electrode, and improving the switching speed of the thin-film transistor.

[0015] In one possible implementation, the semiconductor layer further includes an extension located between the gate body and the first electrode. In this way, the area of ​​the semiconductor layer can be increased, thereby increasing the electrical connection area between the semiconductor layer and the first electrode, and improving the switching speed of the thin-film transistor.

[0016] In one possible implementation, the semiconductor layer is arranged around the entire side of the gate body. In this way, the area of ​​the semiconductor layer can be increased, improving the switching speed of the thin-film transistor.

[0017] In one possible implementation, the semiconductor layer surrounds the entire side of the gate body.

[0018] In one possible implementation, the second electrode is located on the semiconductor layer side, away from the second dielectric layer.

[0019] In one possible implementation, the second electrode is placed between the semiconductor layer and the second dielectric layer.

[0020] In one possible implementation, the material of the second dielectric layer is a ferroelectric material, and the thin-film transistor further includes a third dielectric layer positioned between the semiconductor layer and the second dielectric layer. The gate, the second dielectric layer, and the third dielectric layer can form a composite gate structure. By using a composite gate structure, the thin-film transistor can achieve the performance of a negative capacitance transistor, and the gate control capability of the thin-film transistor can be improved by using negative capacitance. When the thin-film transistor is used in memory, the performance of the memory can be improved.

[0021] In one possible implementation, the thin-film transistor further includes a first conductive layer positioned between a second dielectric layer and a third dielectric layer. A composite gate structure including the gate, the second dielectric layer, the first conductive layer, and the third dielectric layer can enable the thin-film transistor to achieve the performance of a negative capacitance transistor, and the gate control capability of the thin-film transistor can be improved by using negative capacitance. When the thin-film transistor is used in memory, the performance of the memory can be improved.

[0022] In one possible implementation, the thin-film transistor further includes a fourth dielectric layer positioned between the second electrode and the semiconductor layer, and / or a fifth dielectric layer positioned between the first electrode and the semiconductor layer. The fourth dielectric layer is positioned between the second electrode and the semiconductor layer to avoid the diffusion problem of the second electrode in the contact region with the semiconductor layer and to reduce the Fermi-level pinning problem of the contact between the second electrode and the semiconductor layer. The fifth dielectric layer is positioned between the first electrode and the semiconductor layer to avoid the diffusion problem of the first electrode in the contact region with the semiconductor layer and to reduce the Fermi-level pinning problem of the contact between the first electrode and the semiconductor layer.

[0023] In one possible implementation, the thickness of both the fourth and fifth dielectric layers is in the range of 0.1 nm to 2 nm. This allows the second and first electrodes to conduct through the semiconductor layer when a voltage is applied to the gate, ensuring that it does not affect the performance of the thin-film transistor.

[0024] In one possible implementation, the thin-film transistor further includes a modulated gate electrode positioned between a first electrode and a second electrode, the modulated gate electrode positioned on the side of the semiconductor layer away from the gate body, and the modulated gate electrode is surrounded by a first dielectric layer such that it is spaced apart from the first electrode, the second electrode, and the semiconductor layer. The modulated gate electrode can be used to adjust the threshold voltage of the thin-film transistor.

[0025] In one possible implementation, the first electrode is the drain and the second electrode is the source; or the first electrode is the source and the second electrode is the drain.

[0026] According to a second aspect, a memory is provided. The memory includes at least one layer of a memory array disposed on a substrate, and each layer of the memory array includes a plurality of memory cells, write word lines, write bit lines, read word lines, and read bit lines distributed within the array; the memory cells include a stacked second thin film transistor and a first thin film transistor, the gate of the second thin film transistor is electrically connected to the write word line, and the second electrode is electrically connected to the write bit line; the second electrode and the first electrode of the first thin film transistor are electrically connected to the read word line and the read bit line, respectively. The second thin film transistor and the first thin film transistor are the thin film transistors described above. The first electrode of the second thin film transistor is close to the gate of the first thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the gate of the first thin film transistor. The second thin film transistor and the first thin film transistor in the memory are the thin film transistors described above, and the second thin film transistor and the first thin film transistor have the same technical effects as those in the foregoing embodiments, so the details are not described again here.

[0027] In one possible implementation, the memory cell further includes a connection electrode disposed between the first thin film transistor and the second thin film transistor, and the gate of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor by using the connection electrode.

[0028] In one possible implementation, the gates of the second thin-film transistors in multiple memory cells sequentially arranged within each layer of the memory array along the first direction are electrically connected to the same write word line, and the second electrodes of the second thin-film transistors in multiple memory cells sequentially arranged within each layer of the memory array along the second direction are electrically connected to the same write bit line, with the first direction intersecting the second direction. In each layer of the memory array, the gates of the second thin-film transistors in multiple memory cells sequentially arranged along the first direction are electrically connected to the same write word line, and the second electrodes of the second thin-film transistors in multiple memory cells sequentially arranged along the second direction are electrically connected to the same write bit line. Thus, in the write operation process, a first switch signal can be provided to multiple write word lines row by row, thereby turning on multiple rows of the second thin-film transistors row by row. When a first switch signal is provided to the write word line of the current row, logical information is simultaneously written to multiple storage cells electrically connected to the write word line of the current row by using multiple write bit lines, thereby writing logical information to the storage cells row by row, and thus enabling rapid writing to multiple storage cells in the storage array.

[0029] In a possible implementation, the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read bit line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read word line; the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read word line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read bit line; the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read bit line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read word line; or the second electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a second direction are electrically connected to the same read word line, and the first electrodes of the first thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along a first direction are electrically connected to the same read bit line. Here, the first direction intersects the second direction. In the read operation process, a third level signal can be provided to each row of the plurality of read word lines. When the third level signal is provided to the read word line of the current row, the current on each read bit line is detected. In this way, the logical information stored in the plurality of memory cells electrically connected to the read word line of the current row can be read out simultaneously. Thereby, the logical information stored in the memory cells can be read out row by row, thereby implementing a rapid readout of the plurality of memory cells in the memory array.

[0030] In a possible implementation, the first direction and the second direction are orthogonal.

[0031] In one possible implementation, the first thin-film transistor further includes a first modulated gate electrode positioned between a first electrode and a second electrode, the first modulated gate electrode positioned on the side of the semiconductor layer away from the gate body, and the first modulated gate electrode is surrounded by a first dielectric layer of the first thin-film transistor so as to be spaced apart from the second electrode, the first electrode, and the semiconductor layer; the first modulated gate electrodes of multiple first thin-film transistors located in the same layer are electrically connected together; and / or, the second thin-film transistor further includes a second modulated gate electrode positioned between a first electrode and a second electrode, the second modulated gate electrode positioned on the side of the semiconductor layer away from the gate body, and the second modulated gate electrode is surrounded by a first dielectric layer of the second thin-film transistor so as to be spaced apart from the second electrode, the first electrode, and the semiconductor layer; the second modulated gate electrodes of multiple second thin-film transistors located in the same layer are electrically connected together. Since the first thin-film transistor includes a first modulated gate electrode, the threshold voltage of the first thin-film transistor can be adjusted using the first modulated gate electrode. Furthermore, since the first modulation gate electrodes of multiple first thin-film transistors are electrically connected together, simultaneous modulation of multiple first thin-film transistors can be achieved. Since the second thin-film transistor includes a second modulation gate electrode, the threshold voltage of the second thin-film transistor can be adjusted using the second modulation gate electrode. Also, since the second modulation gate electrodes of multiple second thin-film transistors are electrically connected together, simultaneous modulation of multiple second thin-film transistors can be achieved. Based on this, the memory's storage performance can be adjusted more flexibly.

[0032] In one possible implementation, the memory further includes an integrated circuit, and the storage array is located on the integrated circuit. In this case, the memory is on-chip memory.

[0033] In one possible implementation, the memory cell is electrically connected to an integrated circuit. In this way, the memory cell can be controlled using the integrated circuit.

[0034] According to a third aspect, an electronic device is provided. The electronic device includes a circuit board and a memory electrically connected to the circuit board, the memory being the aforementioned memory. The electronic device has the same technical effects as those in the previously described embodiments, and further details will not be described here.

[0035] A fourth aspect provides a method for manufacturing a thin-film transistor. The method for manufacturing a thin-film transistor includes: first, forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, wherein the first electrode, the first dielectric layer, and the second electrode are stacked in order, the first dielectric layer separating the first electrode from the second electrode, the semiconductor layer being formed on the side surface of the first dielectric layer, and both the second electrode and the first electrode being electrically connected to the semiconductor layer; and then, sequentially forming a second dielectric layer and a gate, wherein the gate includes a gate base located at the top and a gate body extending from the gate base to the bottom, and the second dielectric layer separating the gate from the semiconductor layer, the first electrode, and the second electrode. The method for manufacturing a thin-film transistor has the same technical effects as those in the embodiments described above, and further details will not be described here.

[0036] In one possible implementation, the first electrode is formed as a drain and the second electrode is formed as a source; or the first electrode is formed as a source and the second electrode is formed as a drain.

[0037] In one possible implementation, the steps of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate include: first, sequentially forming a first conductive thin film, a first dielectric thin film, and a second conductive thin film stacked on the substrate; then, patterning the first conductive thin film, the first dielectric thin film, and the second conductive thin film to form a sequentially stacked first electrode, a first dielectric layer, and a second electrode; and then, forming a semiconductor layer on the sides of the first dielectric layer and the sides of the second electrode.

[0038] In one possible implementation, the steps of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate include: first, forming a first conductive thin film and a third dielectric thin film sequentially stacked on the substrate; then, forming a modulated gate electrode on the third dielectric thin film; then, forming a fourth dielectric thin film surrounding the modulated gate electrode; then, forming a second conductive thin film on the fourth dielectric thin film; then, patterning the first conductive thin film to form a first electrode, patterning the fourth and third dielectric thin films to form a first dielectric layer, and patterning the second conductive thin film to form a second electrode; and forming semiconductor layers on the sides of the first dielectric layer and the sides of the second electrode. The modulated gate electrode can be used to adjust the threshold voltage of the thin-film transistor.

[0039] In one possible implementation, the steps of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate include: first, forming a first conductive thin film and a first dielectric thin film sequentially stacked on the substrate; then, patterning the first conductive thin film and the first dielectric thin film to form a first electrode and a first dielectric layer sequentially stacked; then, forming a semiconductor layer on the side of the first dielectric layer; and then, forming a second electrode on the first dielectric layer.

[0040] In one possible implementation, the material of the second dielectric layer is a ferroelectric material; after the semiconductor layer is formed and before the second dielectric layer is formed, the manufacturing method further includes the step of forming a third dielectric layer, the third dielectric layer being formed on the side surface of the first dielectric layer. The third dielectric layer has the same technical effects as in the embodiments described above, and further details will not be described here.

[0041] In one possible implementation, after the third dielectric layer is formed and before the second dielectric layer is formed, the manufacturing method further includes the step of forming a first conductive layer, the first conductive layer being formed on the side of the first dielectric layer. The first conductive layer has the same technical effects as in the embodiments described above, and further details will not be described here.

[0042] In one possible implementation, after the first electrode is formed and before the semiconductor layer is formed, the manufacturing method further includes the step of forming a fifth dielectric layer, wherein the fifth dielectric layer is in contact with the first electrode and the semiconductor layer, respectively. In this way, the problem of diffusion of the first electrode in the contact region with the semiconductor layer can be avoided, and the Fermi-level pinning problem of contact between the first electrode and the semiconductor layer can be reduced.

[0043] In one possible implementation, after the second electrode is formed but before the semiconductor layer is formed; or after the semiconductor layer is formed but before the second electrode is formed, the manufacturing method further includes the step of forming a fourth dielectric layer, the fourth dielectric layer being in contact with the second electrode and the semiconductor layer, respectively. In this way, the problem of diffusion of the second electrode in the contact region with the semiconductor layer can be avoided, and the Fermi-level pinning problem of contact between the second electrode and the semiconductor layer can be reduced.

[0044] A fifth aspect provides a memory manufacturing method. The memory manufacturing method includes forming at least one layer of a memory array on a substrate. A method for manufacturing any layer of a memory array is: first, forming a plurality of parallel first signal lines on a substrate; then, forming a plurality of array-distributed first thin-film transistors and a plurality of parallel second signal lines on the plurality of first signal lines, wherein the first thin-film transistors are manufactured using the above-described method for manufacturing thin-film transistors, the first electrode of the first thin-film transistors is electrically connected to the first signal line, and the second electrode of the first thin-film transistors is electrically connected to the second signal line; the first signal line is one of a read bit line and a read word line, and the second signal line is the other of a read bit line and a read word line; then, first The present invention provides a memory comprising the steps of: forming a plurality of second thin-film transistors distributed in an array on a thin-film transistor and a plurality of parallel write bit lines, wherein the second electrodes of the second thin-film transistors are electrically connected to the write bit lines, the second thin-film transistors are manufactured using the aforementioned thin-film transistor manufacturing method, one second thin-film transistor corresponds to one first thin-film transistor, and the first electrodes of the second thin-film transistors are electrically connected to the gate of the corresponding first thin-film transistor; and forming a plurality of parallel write word lines on the second thin-film transistors, wherein the gates of the second thin-film transistors are electrically connected to the write word lines. Both the first and second thin-film transistors in the memory are manufactured using the above-described thin-film transistor manufacturing method, and as a result, the size of the first and second thin-film transistors in the manufactured memory is relatively small, thereby improving area utilization.

[0045] In one possible implementation, before forming a plurality of first thin-film transistors distributed in an array and a plurality of second signal lines arranged in parallel on a plurality of first signal lines, and before forming a plurality of second thin-film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the first thin-film transistors, the method for manufacturing any layer of a memory array further includes the step of forming a plurality of connecting electrodes distributed in an array, the gates of the first thin-film transistors being electrically connected to the first electrodes of the corresponding second thin-film transistors by using the connecting electrodes. [Brief explanation of the drawing]

[0046] [Figure 1] This is a schematic diagram of the structure of a conventional thin-film transistor.

[0047] [Figure 2a] This is a schematic diagram of the structure of a memory cell within a 2T0C structure.

[0048] [Figure 2b] This is a schematic diagram of the structure of the second thin-film transistor and the first thin-film transistor in a memory cell.

[0049] [Figure 2c] This is a schematic diagram showing the structure of the second thin-film transistor and the first thin-film transistor in another memory cell.

[0050] [Figure 3] This is a schematic diagram of the structure of an electronic device according to one embodiment of the present invention.

[0051] [Figure 4] This is a schematic diagram of the memory structure according to one embodiment of the present invention.

[0052] [Figure 5] This is a schematic diagram of the structure of a storage array according to one embodiment of the present invention.

[0053] [Figure 6a] This is a schematic diagram of the structure of a storage array according to another embodiment of the present invention.

[0054] [Figure 6b] This is a schematic cross-sectional view along the first direction in Figure 6a.

[0055] [Figure 6c] This is a schematic cross-sectional view along the second direction in Figure 6a.

[0056] [Figure 6d] This is a schematic cross-sectional view along direction AA in Figure 6b or Figure 6c.

[0057] [Figure 6e] This is another schematic cross-sectional view along direction AA in Figure 6b or Figure 6c.

[0058] [Figure 7] This is a schematic diagram of the memory structure according to another embodiment of the present invention.

[0059] [Figure 8a] This is a schematic diagram of the structure of a thin-film transistor according to one embodiment of the present invention.

[0060] [Figure 8b] Figure 8a is a schematic cross-sectional view along direction BB.

[0061] [Figure 8c] This is another schematic cross-sectional view along direction BB in Figure 8a.

[0062] [Figure 9] This is a schematic diagram of the structure of a thin-film transistor according to another embodiment of the present invention.

[0063] [Figure 10] This is a schematic diagram of the structure of a thin-film transistor according to yet another embodiment of the present invention.

[0064] [Figure 11] This is a schematic diagram of the structure of a thin-film transistor according to yet another embodiment of the present invention.

[0065] [Figure 12a] This is a schematic diagram of the structure of a thin-film transistor according to another embodiment of the present invention.

[0066] [Figure 12b] This is a schematic diagram of the structure of a thin-film transistor according to yet another embodiment of the present invention.

[0067] [Figure 12c] This is a schematic diagram of the structure of a thin-film transistor according to yet another embodiment of the present invention.

[0068] [Figure 13] This is a schematic diagram of the structure of a thin-film transistor according to another embodiment of the present invention.

[0069] [Figure 14] This is a schematic diagram of the structure of a thin-film transistor according to yet another embodiment of the present invention.

[0070] [Figure 15] This is a schematic diagram of the structure of a thin-film transistor according to yet another embodiment of the present invention.

[0071] [Figure 16] This is a schematic diagram of the structure of a thin-film transistor according to another embodiment of the present invention.

[0072] [Figure 17a] This is a schematic diagram of the structure of a storage array according to yet another embodiment of the present invention.

[0073] [Figure 17b] Figure 17a is a schematic cross-sectional view along direction CC.

[0074] [Figure 17c]This is another schematic cross-sectional view along direction CC in Figure 17a.

[0075] [Figure 18] This is a schematic flowchart of a thin-film transistor manufacturing method according to one embodiment of the present invention.

[0076] [Figure 19] This is a schematic diagram of the structure of a thin-film transistor manufacturing process according to one embodiment of the present invention.

[0077] [Figure 20] This is a schematic diagram of the structure of another thin-film transistor preparation process according to one embodiment of the present invention.

[0078] [Figure 21] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0079] [Figure 22] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0080] [Figure 23] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0081] [Figure 24] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0082] [Figure 25] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0083] [Figure 26] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0084] [Figure 27] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0085] [Figure 28] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0086] [Figure 29] This is a schematic diagram of the structure of yet another thin-film transistor preparation process according to one embodiment of the present invention.

[0087] [Figure 30] This is a schematic flowchart of a memory preparation method according to one embodiment of the present invention.

[0088] Reference number:

[0089] 1-Antenna, 2-Antenna, 10-Thin film transistor, 100-Electronic device, 101-Substrate, 102-Semiconductor layer, 103-Source, 104-Drain, 105-Gate insulating layer, 106-Gate, 107-Interlayer dielectric layer, 108-Second electrode, 109-First electrode, 110-Processor, 111-Connecting electrode, 112-Second dielectric layer, 113-First dielectric layer, 114-Fourth dielectric layer, 115-Fifth dielectric layer, 116-Third dielectric layer, 117-First conduction layer, 118-Modulated gate electrode, 118a-First modulated gate electrode, 118b-Second modulated gate electrode, 120-External memory interface, 121-Internal memory, 130-USB interface, 140-Charge management Modules, 141-Power Management Module, 142-Battery, 150-Mobile Communication Module, 160-Wireless Communication Module, 170-Audio Module, 180-Sensor Module, 190-Button, 191-Motor, 192-Indicator, 193-Camera, 194-Display Screen, 195-SIM Card Interface, 200-Memory, 201-Memory Array, 201A-Memory Cell, 202-Sixth Dielectric Layer, 203-Integrated Circuit, 1080-Second Conductive Thin Film, 1090-First Conductive Thin Film, 1121-First Dielectric Layer, 1122-Second Dielectric Layer, 1130-First Dielectric Thin Film, 1131-Third Dielectric Thin Film, and 1132-Fourth Dielectric Thin Film. [Modes for carrying out the invention]

[0090] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It will be clear that the embodiments described are not all, but only some, of the embodiments of the present application.

[0091] The following terms, such as "first," "second," etc., are intended solely for the purpose of facilitating explanation and should not be understood as indicating or implying relative importance, or implicitly indicating the quantity of the technical features shown. Therefore, features limited by "first," "second," etc., may explicitly or implicitly include one or more of those features. In this description, unless otherwise specified, "multiple" means two or more.

[0092] In the embodiments of this application, unless otherwise explicitly specified and limited, the term “connection” should be understood in a broad sense. For example, “connection” may be a fixed connection, a detachable connection, or an integral connection; or a direct connection; or an indirect connection through an intermediate medium. Similarly, the term “electrically connected” may be a direct electrical connection or an indirect electrical connection through an intermediate medium. In addition, the term “joined” may indicate that two or more components are in direct physical or electrical contact, or that two or more components are not in direct contact with each other but are electrically connected or interacting with each other through an intermediate medium.

[0093] In embodiments of this application, the words “example” or “for example” are used to indicate that an example, illustration, or explanation is being given. Any embodiment or design solution described as “example” or “for example” in embodiments of this application should not be described as being preferable or having more advantages than another embodiment or design solution. More precisely, the words “example” or “for example” are intended to concretely present relative concepts.

[0094] In embodiments of the present application, the terms "and / or" describe an association between related objects and may indicate that three relationships exist. For example, A and / or B may indicate: A exists only, both A and B exist, or B exists only, where A and B may be singular or plural. The symbol " / " generally indicates an "or" relationship between related objects.

[0095] In the embodiments of this application, the description relating to the accompanying drawings is based on the orientation shown in the accompanying drawings. If the orientation shown in the accompanying drawings changes, the corresponding description will also change accordingly.

[0096] With the continuous development of integrated circuit technology, the number of transistors placed on a chip per unit area in electronic products such as computers or mobile phones is continuously increasing, resulting in the continuous optimization of electronic product performance. On the one hand, the amount of data that can be manipulated by the processor on the chip in a unit of time is constantly increasing, and on the other hand, the memory density on the chip is also constantly increasing, thereby meeting people's demands for data processing in the information age. However, because the logical units in the processor and the memory cells in memory differ in structure and technology, the degree of improvement in processor and memory performance differs. Specifically, the memory density and read / write speed cannot keep up with the operating speed of the processor, resulting in a "storage wall," which ultimately limits the overall performance improvement of electronic products.

[0097] To address the above problems, various types of memory have emerged. Among these various types of memory, gain cell memory is widely used, and the main target application scenario for gain cell memory is high-speed and high-density memory. Gain cell memory with a 2T0C structure can achieve nanosecond-level read / write speeds and millisecond-level storage times. Storage time refers to the time that information stored in memory is retained, that is, the time from when the information is written to when that information is correctly read. However, the storage time of 2T0C gain cell memory is relatively short, and 2T0C gain cell memory needs to be continuously refreshed in practical applications. This results in relatively large dynamic power consumption.

[0098] Based on the above explanation, in order to improve the retention duration of 2T0C structured memory and solve the problem of relatively high power consumption of 2T0C structured gain cell memory, 2T0C structured gain cell memory can now be prepared based on TFTs. On the one hand, the advantage of TFT's ultra-low leakage current can be used, thereby significantly increasing the retention time of 2T0C structured memory and reducing dynamic power consumption; on the other hand, the advantage of the low temperature of the TFT manufacturing process can be used, thereby implementing three-dimensional (3D) memory integration and improving storage density.

[0099] Referring to Figure 2a, which is a schematic diagram of the structure of a memory cell in a 2T0C structure. The memory cell includes a first thin-film transistor Tr0 and a second thin-film transistor Tr1. The gate of the second thin-film transistor Tr1 is electrically connected to the write word line WWL, the source of the second thin-film transistor Tr1 is electrically connected to the write bit line WBL, the drain of the second thin-film transistor Tr1 is electrically connected to the gate of the first thin-film transistor Tr0, and the source of the first thin-film transistor Tr0 is electrically connected to the read word line RWL. The drain of the first thin-film transistor Tr0 is electrically connected to the read bit line RBL.

[0100] Figures 2b and 2c are schematic diagrams of the structures of a first thin-film transistor Tr0 and a second thin-film transistor Tr1 in a storage cell of a TFT-based memory with a 2T0C structure, respectively. Referring to Figures 2b and 2c, both the first thin-film transistor Tr0 and the second thin-film transistor Tr1 include a semiconductor layer 102 disposed on a substrate 101, a source 103 and a drain 104 disposed on and in contact with the semiconductor layer 102, a gate insulating layer 105 disposed on the semiconductor layer 102, and a gate 106 disposed on the gate insulating layer 105. In addition, the interlayer dielectric layer 107 in Figures 2b and 2c is configured to separate different conductive film layers, and signal lines are electrically connected to the corresponding electrodes by using vias. For example, the read word line RWL is electrically connected to the source 103 of the first thin-film transistor Tr0 using vias.

[0101] However, in the first thin-film transistor Tr0 and the second thin-film transistor Tr1 shown in Figures 2b and 2c, the semiconductor layer 102 extends along a plane parallel to the gate 106, and the source 103 and drain 104 are located in the same layer. Thus, the size of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 is relatively large, resulting in low area utilization rates for both transistors. In addition, because the source 103 and drain 104 are located in the same layer, short circuits easily occur between the signal lines electrically connected to the source electrode 103 and the signal lines electrically connected to the drain electrode 104, which does not contribute to routing and increases process difficulty.

[0102] To solve the aforementioned problems, one embodiment of the present application provides a memory. The memory may be used in an electronic device. The electronic device may be a mobile phone, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, mobile phone, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, wearable device, in-vehicle device, smart home device, and / or smart city device, and the specific type of electronic device is not particularly limited in the embodiments of the present application.

[0103] Figure 3 is a schematic diagram of the structure of the electronic device. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identity module (SIM) card interface 195.

[0104] It should be understood that the structure shown in this embodiment of the present application does not constitute a particular limitation on the electronic device 100. In some other embodiments of the present application, the electronic device 100 may include more or fewer components than those shown in the figure, or some components may be combined, or some components may be separated, or different component deployments may be used. The components shown in the figure may be implemented by hardware, software, or a combination of software and hardware.

[0105] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent components or may be integrated into one or more processors.

[0106] The controller may generate operation control signals based on the instruction operation code and time-series signals to complete the control of instruction readout and instruction execution.

[0107] Memory may be further located within the processor 110 and configured to store instructions and data. In some embodiments, the memory within the processor 110 is cache memory. The memory can store instructions or data that have just been used or periodically used by the processor 110. When the processor 110 needs to use an instruction or data again, the processor can retrieve the instruction or data directly from memory. This avoids repeated access, reduces latency for the processor 110, and therefore improves system efficiency.

[0108] In some embodiments, the processor 110 may include one or more interfaces. These interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0109] The I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). The I2S interface can be configured to perform audio communication.

[0110] The PCM interface is configured to perform audio communication, sample analog signals, quantize them, and encode them.

[0111] The UART interface is a universal serial data bus configured to perform asynchronous communication. The bus may also be a bidirectional communication bus. The UART interface converts the data to be transmitted between serial and parallel communication.

[0112] The MIPI interface may be configured to connect the processor 110 to peripheral components such as a display screen 194 or a camera 193. The MIPI interface includes camera serial interface (CSI), display serial interface (DSI), and others.

[0113] The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or a data signal. Alternatively, the GPIO interface may be configured as an I2C interface, I2S interface, UART interface, or MIPI interface.

[0114] The USB interface 130 is an interface that conforms to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, or a USB Type-C interface. The USB interface 130 may be configured to connect to a charger to charge the electronic device 100, or to transmit data between the electronic device 100 and peripheral devices, or to connect to a headset to play audio using the headset.

[0115] It should be understood that the intermodal interface connection relationships shown in this embodiment of the present invention are merely illustrative examples and do not constitute a limitation on the structure of the electronic device 100. In some other embodiments of the present application, the electronic device 100 may, instead, use a different interface connection scheme than those in the embodiments described above, or a combination of multiple interface connection schemes.

[0116] The charging management module 140 is configured to receive a charging input from the charger. The charger may be a wireless charger or a wired charger.

[0117] The power management module 141 is configured to connect to the battery 142, the charge management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charge management module 140 and supplies power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160. The power management module 141 may be further configured to monitor parameters such as battery capacity, battery cycle count, and battery health (leakage or impedance). In some other embodiments, the power management module 141 may be located within the processor 110 instead. In some other embodiments, the power management module 141 and the charge management module 140 may be located within the same component instead.

[0118] The wireless communication function of the electronic device 100 can be implemented by using antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor, and baseband processor.

[0119] Antennas 1 and 2 are configured to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 may be configured to cover one or more communication frequency bands. Different antennas may be further multiplexed to improve antenna utilization. For example, antenna 1 may be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas may be used in combination with tuning switches.

[0120] The mobile communication module 150 can provide wireless communication solutions, including 2G / 3G / 4G / 5G, applicable to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, and low noise amplifier (LNA). The mobile communication module 150 can receive electromagnetic waves through antenna 1, perform processing such as filtering or amplification on the received electromagnetic waves, and transmit the electromagnetic waves to a modem processor for demodulation. The mobile communication module 150 further amplifies the signal modulated by the modem processor and converts the signal into electromagnetic waves for radiation through antenna 1.

[0121] The modem processor may include a modulator and a demodulator. The modulator is configured to modulate a low-frequency baseband signal to be transmitted into a medium-frequency signal. The demodulator is configured to demodulate a received electromagnetic signal into a low-frequency baseband signal. The demodulator then transmits the low-frequency baseband signal obtained through demodulation to a baseband processor for processing. The low-frequency baseband signal is processed by the baseband processor and then transmitted to an application processor. The application processor outputs an audio signal using an audio device (not limited to a speaker or telephone receiver) or displays images or videos using a display screen 194.

[0122] The wireless communication module 160 is applied to the electronic device 100 and may provide wireless communication solutions including wireless local area network (WLAN) (e.g., Wireless Fidelity (Wi-Fi) network), Bluetooth® (Bluetooth, BT), global navigation satellite system (GNSS), frequency modulation (FM), near-field communication (NFC) technology, or infrared (IR) technology. The wireless communication module 160 may be one or more components integrating at least one communication processor module. The wireless communication module 160 receives electromagnetic waves through the antenna 2, performs frequency modulation and filtering on the electromagnetic wave signal, and sends the processed signal to the processor 110. The wireless communication module 160 further receives a signal to be transmitted from the processor 110, performs frequency modulation and amplification on the signal, and converts the signal into an electromagnetic wave for radiation through the antenna 2.

[0123] In some embodiments, antenna 1 of the electronic device 100 is electrically connected to a mobile communication module 150, and antenna 2 is electrically connected to a wireless communication module 160, thereby enabling the electronic device 100 to communicate with a network and other devices using wireless communication technology. Wireless communication technologies include global system for mobile communications (GSM®), general packet radio service (GPRS), and code division multiple access (CDMA).

[0124] The electronic device 100 can embody display functionality through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing and is connected to the display screen 194 and the application processor. The GPU is configured to perform mathematical and geometric calculations and to render images. The processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0125] The display screen 194 is configured to display an image or video. In some embodiments, the electronic device 100 may include one or N display screens 194, where N is a positive integer greater than 1.

[0126] The electronic device 100 can implement a photo-taking function through an ISP, camera 193, video codec, GPU, display screen 194, and application processor.

[0127] The ISP is configured to process the data fed back by camera 193.

[0128] The camera 193 is configured to capture still images or video. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0129] The external memory interface 120 may be configured to connect to an external storage card, such as a microSD card, in order to expand the storage capacity of the electronic device 100. The external storage card communicates with the processor 110 through the external memory interface 120 to implement data storage functions. For example, files such as music and videos are stored on the external storage card.

[0130] The internal memory 121 may be configured to store computer executable program code, which includes instructions. The internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required by at least one function (e.g., an audio playback function or an image display function). The data storage area can store data created during the use of the electronic device 100 (e.g., audio data and an address book). In addition, the internal memory 121 may include high-speed random access memory, or non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or universal flash storage (UFS). The processor 110 executes instructions stored in the internal memory 121 and / or instructions stored in memory located within the processor to perform various functional applications and data processing of the electronic device 100.

[0131] The electronic device 100 can implement audio functions, such as music playback and recording functions, using the audio module 170 and the application processor.

[0132] The audio module 170 is configured to convert digital audio information into analog audio signals for output, and is also configured to convert analog audio input into digital audio signals. The audio module 170 may be further configured to encode and decode audio signals.

[0133] Button 190 includes power buttons, volume buttons, etc. Button 190 may be a mechanical button or a touch button. Electronic device 100 can receive button inputs and generate button signal inputs related to user settings and function control of electronic device 100.

[0134] Motor 191 may generate vibration prompts. Motor 191 may be configured to provide incoming vibration prompts and touch vibration feedback.

[0135] Indicator 192 may be an indicator light, and may be configured to show charging status and power changes, or may be configured to show messages, missed calls, and notifications.

[0136] The SIM card interface 195 is configured to connect to a SIM card. The SIM card may be inserted into or removed from the SIM card interface 195 to achieve contact with or separation from the electronic device 100. The electronic device 100 may support one or N SIM card interfaces, where N is a positive integer greater than 1.

[0137] Based on this, the electronic device 100 may further include a circuit board, such as a printed circuit board (PCB). The processor 110 and internal memory 121 may be arranged on the circuit board, and the processor 110 and internal memory 121 are electrically connected to the circuit board.

[0138] The memory provided in this embodiment of the present application may be used as internal memory 121 in an electronic device 100, or as memory in a processor 110 of the electronic device 100.

[0139] The memory provided in this embodiment of the present application may be off-chip memory or on-chip memory (which may also be referred to as embedded memory).

[0140] In addition, the memory provided in this embodiment of the present application may be memory prepared based on a back-end of line (BEOL) process.

[0141] Referring to Figure 4, the memory 200 includes at least one layer of storage array 201 disposed on the substrate 101. Figure 4 is a schematic diagram using an example in which the memory 200 includes two layers of storage array 201. If the memory 200 includes multiple layers of storage array 201, the storage arrays 201 may be stacked sequentially along the vertical direction, as shown in Figure 4.

[0142] Furthermore, if the memory 200 includes multiple layers of storage arrays 201, it may also be referred to as a three-dimensional integrated memory.

[0143] In addition, the number of layers in the memory array 201 may be stacked as needed. A larger number of stacked layers in the memory array 201 indicates a higher storage density for the memory 200.

[0144] If the memory 200 includes a multi-layer storage array 201, in some embodiments, referring to Figure 4, the memory 200 further includes a sixth dielectric layer 202 positioned between two adjacent layers of the storage array 201, and the two adjacent layers of the storage array 201 are separated by the use of the sixth dielectric layer 202.

[0145] The material of the sixth dielectric layer 202 may be one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide), and Si3N4 (silicon nitride).

[0146] The sixth dielectric layer 202 may be a single layer or a multilayer structure. The material of the single layer and the material of each layer in the multilayer structure may be one or more of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4.

[0147] Referring to Figures 5 and 6a, each layer of the storage array 201 includes multiple storage cells 201A arranged in an array, a write word line (WWL), a write bit line (WBL), a read word line (RWL), and a read bit line (RBL).

[0148] Referring to Figures 6a, 6b, 6c, 6d, and 6e, the memory cell 201A includes a stacked first thin-film transistor Tr0 and a second thin-film transistor Tr1.

[0149] The first thin-film transistor Tr0 includes a gate 106a, which includes a gate base 1061a located at the top and a gate body 1062a extending from the gate base 1061a to the bottom. The first thin-film transistor Tr0 further includes a first electrode 109a, a second electrode 108a, a first dielectric layer 113a, a second dielectric layer 112a, and a semiconductor layer 102a. The first electrode 109a is located at the bottom, and the second electrode 108a is located between the first electrode 109a and the gate base 1061a. The first dielectric layer 113a is positioned between the second electrode 108a and the first electrode 109a, and the first dielectric layer 113a is configured to separate the first electrode 109a from the second electrode 108a. The semiconductor layer 102a is positioned along the side surface of the gate body 1062a, and the second dielectric layer 112a separates the semiconductor layer 102a from the gate 106a. The first electrode 109a and the second electrode 108a are electrically connected to the semiconductor layer 102a, respectively.

[0150] As shown in Figures 6a, 6b, 6c, and 6d, the second dielectric layer 112a covers the surface of the gate base 1061a and the surface of the gate body 1062a. The second dielectric layer 112a surrounds the outside of the gate body 1062a on the first electrode 109a, the semiconductor layer 102a surrounds the outside of the second dielectric layer 112a, and the second electrode 108a is located outside the semiconductor layer 102a and is electrically connected to the semiconductor layer 102a. The second electrode 108a is on the first electrode 109a and is separated by the first dielectric layer 113a, and the first electrode 109a is electrically connected to the semiconductor layer 102a.

[0151] The second thin-film transistor Tr1 includes a gate 106b, which includes a gate base 1061b located at the top and a gate body 1062b extending from the gate base 1061b to the bottom. The second thin-film transistor Tr1 further includes a first electrode 109b, a second electrode 108b, a first dielectric layer 113b, a second dielectric layer 112b, and a semiconductor layer 102b. The first electrode 109b is located at the bottom, and the second electrode 108b is located between the first electrode 109a and the gate base 1061a. The first dielectric layer 113b is positioned between the second electrode 108b and the first electrode 109b, and the first dielectric layer 113b is configured to separate the first electrode 109b from the second electrode 108b. The second dielectric layer 112b covers the surface of the gate base 1061b and the surface of the gate body 1062b. The semiconductor layer 102b is positioned along the side surface of the gate body 1062b, and the second dielectric layer 112b separates the semiconductor layer 102b from the gate 106b. The first electrode 109b and the second electrode 108b are electrically connected to the semiconductor layer 102b, respectively.

[0152] As shown in Figures 6a, 6b, 6c, and 6d, the second dielectric layer 112b surrounds the outside of the gate body 1062b on the first electrode 109b, the semiconductor layer 102b surrounds the outside of the second dielectric layer 112b, and the second electrode 108b is located outside the semiconductor layer 102b and electrically connected to the semiconductor layer 102b. The second electrode 108b lies on the first electrode 109b and is separated by the first dielectric layer 113b, and the first electrode 109b is electrically connected to the semiconductor layer 102b.

[0153] The gate 106b (gate, G) of the second thin-film transistor Tr1 is electrically connected to the write word line WWL, and the second electrode 108b is electrically connected to the write bit line WBL. The first electrode 109a and the second electrode 108a of the first thin-film transistor Tr0 are electrically connected to the read word line RWL and the read bit line RBL, respectively. The first electrode 109b of the second thin-film transistor Tr1 is adjacent to the gate 106a of the first thin-film transistor Tr0, and the first electrode 109b of the second thin-film transistor Tr1 is electrically connected to the gate 106a of the first thin-film transistor Tr0.

[0154] Figure 6b is a schematic cross-sectional view along the first direction X in Figure 6a, and Figure 6c is a schematic cross-sectional view along the second direction Y in Figure 6a. Figure 6d is a schematic cross-sectional view along direction AA in Figure 6b or Figure 6c, and Figure 6e is another schematic cross-sectional view along direction AA in Figure 6b or Figure 6c.

[0155] The memory 200 provided in this embodiment of the present application may be understood to be a memory with a gain cell structure based on a 2T0C structure.

[0156] In some embodiments, the first electrode 109b of the second thin-film transistor Tr1 is in direct contact with the gate 106a of the first thin-film transistor Tr0. In some other embodiments, referring to Figures 6a, 6b, and 6c, both the first electrode 109b of the second thin-film transistor Tr1 and the gate 106a of the first thin-film transistor Tr0 are in contact with the connecting electrode 111, and the first electrode 109b of the second thin-film transistor Tr1 is electrically connected to the gate 106a of the first thin-film transistor Tr0 by using the connecting electrode 111.

[0157] The second thin-film transistor Tr1 is a write transistor, and the first thin-film transistor Tr0 is a read transistor.

[0158] The structures of the second thin-film transistor Tr1 and the first thin-film transistor Tr0 may be the same or different. In some embodiments, it should be understood that the projection of the second thin-film transistor Tr1 onto the substrate overlaps with the projection of the first thin-film transistor Tr0 onto the substrate.

[0159] The write word line WWL may be manufactured in synchronization with the gate 106b of the second thin-film transistor Tr1, and the write bit line WBL may be manufactured in synchronization with the second electrode 108b of the second thin-film transistor Tr1.

[0160] The second electrode 108a of the first thin-film transistor Tr0 may be electrically connected to the readout word line RWL, and the first electrode 109a may be electrically connected to the readout bit line RBL. In this case, the second electrode 108a and the readout word line RWL of the first thin-film transistor Tr0 may be manufactured synchronously, and the first electrode 109a and the readout bit line RBL of the first thin-film transistor Tr0 may be manufactured synchronously. Alternatively, the second electrode 108a of the first thin-film transistor Tr0 may be electrically connected to the readout bit line RBL, and the first electrode 109a may be electrically connected to the readout word line RWL. In this case, the second electrode 108a and the readout bit line RBL of the first thin-film transistor Tr0 may be manufactured synchronously, and the first electrode 109a and the readout word line RWL of the first thin-film transistor Tr0 may be manufactured synchronously.

[0161] In this embodiment of the present application, for the first thin-film transistor Tr0, the second electrode 108a may be the source (S) 103 and the first electrode 109a may be the drain (D) 104; or the second electrode 108a may be the drain 104 and the first electrode 109a may be the source 103. For the second thin-film transistor Tr1, the second electrode 108b may be the source 103 and the first electrode 109b may be the drain 104; or the second electrode 108b may be the drain 104 and the first electrode 109b may be the source 103.

[0162] Furthermore, both the first thin-film transistor Tr0 and the second thin-film transistor Tr1 may be N-type transistors or P-type transistors. Of course, one of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 may be an N-type transistor and the other a P-type transistor.

[0163] In some embodiments, a plurality of first thin-film transistors Tr0 included in each layer of the storage array 201 may be manufactured synchronously, and / or a plurality of second thin-film transistors Tr1 included in each layer of the storage array 201 may be manufactured synchronously.

[0164] Referring to Figure 5, the following describes the write and read operations of memory 200, using one memory cell 201A as an example.

[0165] Write operation process: In the write operation process, the voltages on the read word line RWL and the read bit line RBL are 0, and the first thin-film transistor Tr0 is not operating. The write word line WWL provides a first switch signal, which controls the second thin-film transistor Tr1 to be turned on. When the first logic information is written, and the first logic information is, for example, "0", the write bit line WBL provides a first level signal, which is written to node N using the second thin-film transistor Tr1, and the first level signal can be controlled to turn on the first thin-film transistor Tr0. When the second logic information is written, and the second logic information is, for example, "1", the write bit line WBL provides a second level signal, which is written to node N using the second thin-film transistor Tr1, where the second level signal can be controlled to turn off the first thin-film transistor Tr0.

[0166] It should be understood that after the write operation is complete, the voltages on the read word line RWL and the read bit line RBL are 0, and the first thin-film transistor Tr0 is not operating. The write word line WWL provides a second switch signal, which controls the second thin-film transistor Tr1 to be turned off. In this case, the potential stored by node N is not affected by the external environment.

[0167] Read operation process: The write word line WWL provides a second switch signal, which controls the second thin-film transistor Tr1 to be turned off. The read word line RWL provides a third level signal, and the logical information stored in the memory cell 201A is determined based on the current on the read bit line RBL. When node N stores a first level signal, the first level signal can be controlled to turn on the first thin-film transistor Tr0. Therefore, when the read word line RWL provides a third level signal, the read word line RWL charges the read bit line RBL by using the first thin-film transistor Tr0, causing the voltage on the read bit line RBL to rise. In this way, when a relatively large current is detected on the read bit line RBL, the logical information "0" stored in the memory cell 201A can be read out. If node N stores a second-level signal, the second-level signal can be controlled to turn off the first thin-film transistor Tr0. Therefore, when the read word line RWL provides a third-level signal, the read word line RWL does not charge the read bit line RBL using the first thin-film transistor Tr0, and the read bit line RBL maintains a voltage of 0V. In this way, when a relatively small current is detected on the read bit line RBL, the logical information "1" stored in the memory cell 201A can be read out.

[0168] For multiple second thin-film transistors Tr1, in some embodiments, referring to Figures 5, 6a, and 6b, the gates 106b of the second thin-film transistors Tr1 in multiple storage cells 201A sequentially arranged in each layer of the storage array 201 along a first direction X are electrically connected to the same write word line WWL. Referring to Figures 5, 6a, and 6c, the second electrodes 108b of the second thin-film transistors Tr1 in multiple storage cells 201A sequentially arranged in each layer of the storage array 201A along a second direction Y are electrically connected to the same write bit line WBL. Here, the first direction X intersects the second direction Y.

[0169] In some examples, the first direction X and the second direction Y are orthogonal. For simplicity of description, the following examples will use the case where the first direction X is the row direction and the second direction Y is the column direction.

[0170] In each layer of the memory array 201, the gate 106b of the second thin-film transistor Tr1 in multiple memory cells 201A sequentially arranged along a first direction X is electrically connected to the same write word line WWL, and the second electrode 108b of the second thin-film transistor Tr1 in multiple memory cells 201A sequentially arranged along a second direction Y is electrically connected to the same write bit line WBL. Therefore, in the write operation process, a first switch signal may be provided to each row of multiple write word lines WWL, thereby turning on each row of multiple rows of the second thin-film transistor Tr1. When the first switch signal is provided to the write word line WWL of the current row, logical information is simultaneously written to multiple memory cells 201A electrically connected to the write word line WWL of the current row by using multiple write bit lines WBL. This allows logical information to be written to the memory cells 201A row by row, thereby enabling rapid writing of multiple memory cells 201A in the memory array 201.

[0171] For example, multiple first thin-film transistors Tr0 can be connected in the following four ways:

[0172] When the first electrode 109a of the first thin-film transistor Tr0 is electrically connected to the read bit line RBL and the second electrode 108a is electrically connected to the read word line RWL, the first or second embodiment described below may be used.

[0173] First aspect: Referring to Figures 5, 6a, and 6b, the second electrode 108a of the first thin-film transistor Tr0 in a plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a first direction X is electrically connected to the same read word line RWL; referring to Figures 5, 6a, and 6c, the first electrode 109a of the first thin-film transistor Tr in a plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a second direction Y is electrically connected to the same read bit line RBL. Here, the first direction X intersects the second direction Y.

[0174] In each layer of the memory array 201, the second electrode 108a of the first thin-film transistor Tr0 in multiple memory cells 201A sequentially arranged along a first direction X is electrically connected to the same read word line RWL, and the first electrode 109a of the first thin-film transistor Tr0 in multiple memory cells 201A sequentially arranged along a second direction Y is electrically connected to the same read bit line RBL. Therefore, in the read operation process, a third-level signal may be provided to multiple read word lines RWL row by row. When a third-level signal is provided to the read word line RWL of the current row, the current on each read bit line RBL is detected. In this way, the logical information stored in multiple memory cells 201A electrically connected to the read word line RWL of the current row can be read simultaneously. This allows the logical information stored in the memory cells 201A to be read row by row, thereby enabling rapid reading of multiple memory cells 201A within the memory array 201.

[0175] Second aspect: The second electrode 108a of the first thin-film transistor Tr0 of a plurality of storage cells 201A arranged sequentially in each layer of the storage array 201 along a second direction Y is electrically connected to the same read word line RWL, and the first electrode 109a of the first thin-film transistor Tr0 of a plurality of storage cells 201A arranged sequentially in each layer of the storage array 201 along a first direction X is electrically connected to the same read bit line RBL. Here, the first direction X intersects the second direction Y.

[0176] If the first electrode 109a of the first thin-film transistor Tr0 is electrically connected to the read word line RWL and the second electrode 108a is electrically connected to the read bit line RBL, then the following third or fourth embodiment may be used.

[0177] Third aspect: In a plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a first direction X, the second electrode 108a of the first thin-film transistor Tr0 in each of the plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a second direction Y, the first electrode 109a of the first thin-film transistor Tr0 in each of the plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a second direction Y, the first electrode 109a of the first thin-film transistor Tr0 in each of the same read word line RWL. Here, the first direction X intersects the second direction Y.

[0178] Fourth aspect: In a plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a second direction Y, the second electrode 108a of the first thin-film transistor Tr0 in each of the plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a first direction X, the first electrode 109a of the first thin-film transistor Tr0 in each of the plurality of storage cells 201A sequentially arranged in each layer of the storage array 201 along a first direction X, is electrically connected to the same read word line RWL. Here, the first direction X intersects the second direction Y.

[0179] It should be noted that the second, third, and fourth embodiments have the same technical effects as the first embodiment. For details, please refer to the above description of the technical effects of the first embodiment. Further details will not be explained here.

[0180] Based on the above explanation, for each layer of the memory array 201, the amount of memory cells 201A along the first direction X and / or the second direction Y may be increased to implement a larger memory array.

[0181] Referring to Figure 7, in some embodiments, the memory 200 further includes an integrated circuit 203, and the storage array 201 is arranged on the integrated circuit 203. In this case, the memory 200 is an on-chip memory. In this case, the substrate within the memory 200 is the integrated circuit 203.

[0182] The substrate for the integrated circuit 203 may be a silicon substrate; in other words, the integrated circuit 203 may be an integrated circuit on a silicon substrate.

[0183] Furthermore, the integrated circuit 203 may be a control circuit for the memory array 201, or it may be another functional circuit.

[0184] It should be noted that, since the process temperature for manufacturing thin-film transistors is relatively low, the memory array 201 can be integrated into the back-end line of the integrated circuit 203. In addition, to implement 3D system integration, stacking of multiple layers of the memory array 201 may be carried out on the integrated circuit 203.

[0185] In some examples, a storage cell 201A within a storage array 201 may be electrically connected to an integrated circuit 203. For example, a storage cell 201A within a storage array 201 may be connected to a lower integrated circuit 203 by using interconnection lines.

[0186] Embodiments of the present invention further provide a thin-film transistor 10. This thin-film transistor may be used as the first thin-film transistor Tr0 described above, or as the second thin-film transistor Tr1 described above.

[0187] The structure of the thin-film transistor 10 will be described in detail below.

[0188] Referring to Figures 8a, 8b, and 8c, the thin-film transistor 10 includes a gate 106, a first electrode 109, a second electrode 108, a first dielectric layer 113, a second dielectric layer 112, and a semiconductor layer 102.

[0189] The gate 106 includes a gate base 1061 located at the top and a gate body 1062 extending from the gate base 1061 to the bottom. A first electrode 109 is located at the bottom. A second electrode 108 is located between the first electrode 109 and the gate base 1061. A first dielectric layer 113 is positioned between the second electrode 108 and the first electrode 109, and is configured to isolate the first electrode 109 from the second electrode 108. A second dielectric layer 112 covers the surface of the gate base 1061 and the surface of the gate body 1062. A semiconductor layer 102 is positioned along the side of the gate body 1062, and the second dielectric layer 112 isolates the semiconductor layer 102 from the gate 106. The first electrode 109 and the second electrode 108 are each electrically connected to the semiconductor layer 102.

[0190] Figure 8b is a schematic cross-sectional view along the BB direction of Figure 8a, and Figure 8c is another schematic cross-sectional view along the BB direction of Figure 8a.

[0191] As shown in Figures 8a and 8b, the second dielectric layer 112 surrounds the outside of the gate body 1062 on the first electrode 109, the semiconductor layer 102 surrounds the outside of the second dielectric layer 112, and the second electrode 108 is located outside the semiconductor layer 102 and is electrically connected to the semiconductor layer 102. The second electrode 108 is on the first electrode 109 and is separated by the first dielectric layer 113, and the first electrode 109 is electrically connected to the semiconductor layer 102.

[0192] The gate body 1062 has a surface that contacts the gate base 1061, a surface that is away from the gate base 1061, and a side surface. The surface that contacts the gate base 1061 and the surface that is away from the gate base 1061 are arranged opposite each other.

[0193] In some embodiments, the gate body 1062 and the gate base 1061 are formed integrally. In some other embodiments, the gate body 1062 and the gate base 1061 are manufactured separately.

[0194] In some examples, the gate body 1062 is positioned perpendicular to the gate base 1061.

[0195] The first electrode 109 forms a resistive contact with the semiconductor layer 102, and the second electrode 108 also forms a resistive contact with the semiconductor layer 102. Furthermore, the electrical connection of the first electrode 109 to the semiconductor layer 102 may mean that the first electrode 109 is in direct contact with the semiconductor layer 102, or that the first electrode 109 is not in direct contact with the semiconductor layer 102 but is electrically connected to the semiconductor layer 102 using another medium. Similarly, the electrical connection of the second electrode 108 to the semiconductor layer 102 may mean that the second electrode 108 is in direct contact with the semiconductor layer 102, or that the second electrode 108 is not in direct contact with the semiconductor layer 102 but is electrically connected to the semiconductor layer 102 using another medium.

[0196] The first electrode 109 of the thin-film transistor 10 may be the drain and the second electrode 108 may be the source; or the first electrode 109 of the thin-film transistor 10 may be the source and the second electrode 108 may be the drain.

[0197] Furthermore, the thin-film transistor 10 may be an N-type transistor or a P-type transistor.

[0198] In addition, since the second dielectric layer 112 covers the surface of the gate base 1061 and the surface of the gate body 1062, as shown in Figure 8a, the second dielectric layer 112 includes the first dielectric portion 1121 and the second dielectric portion 1122, the first dielectric portion 1121 covers the surface of the gate base 1061 and the second dielectric portion 1122 covers the surface of the gate body 1062.

[0199] Based on this, in some embodiments, the first dielectric portion 1121 and the second dielectric portion 1122 are manufactured synchronously. In some other embodiments, the first dielectric portion 1121 and the second dielectric portion 1122 may be manufactured separately.

[0200] If the distance between the first electrode 109 and the second electrode 108 is too short, there is a risk that the first electrode 109 and the second electrode 108 may become directly conductive during manufacturing. To avoid direct conduction between the first electrode 109 and the second electrode 108, in some embodiments, the second electrode 108 is positioned close to the gate base 1061.

[0201] It should be understood that the materials of the gate 106, the first electrode 109, and the second electrode 108 are all conductive materials, such as metallic materials. Specifically, the materials of the gate 106, the first electrode 109, and the second electrode 108 may be one or more of the conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0202] For the materials of the first dielectric layer 113 and the second dielectric layer 112, please refer to the material of the sixth dielectric layer 202. Details will not be explained again here. Also, the first dielectric layer 113 and the second dielectric layer 112 may each be single-layer structures or multi-layer laminated structures.

[0203] The material of the semiconductor layer 102 may be one or more of the following semiconductor materials: Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) polycompound, ZnO (zinc oxide), ITO, TiO2 (titanium dioxide), and MoS2 (molybdenum disulfide).

[0204] One embodiment of the present invention provides a thin-film transistor 10. The gate 106 of the thin-film transistor 10 includes a gate base 1061 located at the top and a gate body 1062 extending from the gate base 1061 to the bottom. A semiconductor layer 102 is arranged along the side of the gate body 1062, with a first electrode 109 located at the bottom and a second electrode 108 located between the first electrode 109 and the gate base 1061, and the first electrode 109 and the second electrode 108 are each electrically connected to the semiconductor layer 102. In the prior art, the semiconductor layer 102 is arranged along a plane parallel to the gate 106 (the gate 106 in the prior art is equivalent to the gate base 1061 in this embodiment of the present application), and the second electrode 108 and the first electrode 109 are arranged in the same layer, and as a result the size of the thin-film transistor 10 provided in this embodiment of the present application is relatively small in the plane parallel to the gate base 1061. Therefore, in this embodiment of the present application, the size of the thin-film transistor 10 is reduced and the area utilization rate is improved. In addition, since the second electrode 108 and the first electrode 109 of the thin-film transistor 10 in this embodiment of the present application are located in different layers, short circuits that occur during routing of the signal lines electrically connected to the second electrode 108 and the signal lines electrically connected to the first electrode 109 can be avoided, thereby reducing process difficulties.

[0205] When the structures of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 in the memory 200 are those of the thin-film transistor 10 described above, the size of the first thin-film transistor Tr0 and the second thin-film transistor Tr1 in the memory 200 can be reduced, thereby improving the area utilization rate.

[0206] Regarding the structure of gate 106, the following three implementations can be used as examples.

[0207] First implementation: As shown in Figures 8a, 9, 10, and 11, the boundary of the projection of the gate body 1062 onto the gate base 1061 lies within the boundary of the gate base 1061, i.e., the gate body 1062 is positioned in the intermediate region of the gate base 1061.

[0208] Second implementation: As shown in Figures 12a and 12c, the boundary of the projection of the gate body 1062 onto the gate base 1061 partially overlaps with the boundary of the gate base 1061, i.e., the gate body 1062 is positioned in the edge region of the gate base 1061.

[0209] Third implementation: As shown in Figure 12b, the gate body 1062 has a hollow structure, and the outer boundary of the projection of the gate body 1062 onto the gate base 11061 coincides with the boundary of the gate base 1061.

[0210] Since the gate body 1062 has a hollow structure, it should be understood that the projection of the gate body 1062 onto the gate base 1061 includes two boundaries: an outer boundary and an inner boundary. The boundary closer to the center of the gate base 1061 is called the inner boundary, and the boundary further from the center of the gate base 1061 is called the outer boundary.

[0211] In addition, since the gate body 1062 has a hollow structure, and the outer boundary of the projection of the gate body 1062 on the gate base 1061 coincides with the boundary of the gate base 11061, at least a portion of the region of the second dielectric layer 112 is located within the hollow structure, at least a portion of the region of the semiconductor layer 102 is located within the hollow structure, the second electrode 108 is located within the hollow structure, and at least a portion of the region of the first dielectric layer 113 is located within the hollow structure.

[0212] If the gate body 1062 has a hollow structure, the gate 106 adjusts and controls the current inside the semiconductor layer 102 from the outside of the semiconductor layer 102.

[0213] Regarding the structure of the semiconductor layer 102, the following four implementations can be used as examples.

[0214] First implementation: As shown in Figure 8a, the semiconductor layer 102 is positioned only along the side of the gate body 1062.

[0215] As shown in Figure 8a, the semiconductor layer 102 surrounds only the side surface of the gate body 1062 and is positioned on the first electrode 109.

[0216] The second electrode 108 and the first electrode 109 are electrically connected to or in end contact with the semiconductor layer 102.

[0217] Second implementation: As shown in Figure 12c, the semiconductor layer 102 is positioned along the side of the gate body 1062, and the semiconductor layer 102 further includes an extension that extends along the surface of the gate base 1061. The second dielectric layer 112 separates the semiconductor layer 102 from the gate 106. Also as shown in Figure 12c, the semiconductor layer 102 is positioned along the side of the first dielectric layer 113 and along the side of the second electrode 108, covering the upper surface of the second electrode 108.

[0218] In some examples, as shown in Figure 12c, the semiconductor layer 102 is further positioned on the side surface of the first electrode 109.

[0219] Third implementation: As shown in Figure 9, the semiconductor layer 102 is positioned along the side of the gate body 1062, extending from the side of the gate body 1062 to the side of the gate body 1062 away from the gate base 1061, i.e., located between the gate body 1062 and the first electrode 109. That is, the semiconductor layer 102 further includes an extension located between the gate body 1062 and the first electrode 109. Also, as shown in Figure 9, the semiconductor layer 102 covers the side and bottom surfaces of the second dielectric layer 112.

[0220] In some examples, as shown in Figure 9, the semiconductor layer 102 is placed on the first electrode 109.

[0221] Fourth implementation: As shown in Figures 10, 11, 12a, and 12b, the semiconductor layer 102 is positioned along the side surface of the gate body 1062, and the semiconductor layer 102 further includes an extended portion that extends along the surface of the gate base 1061 and an extended portion located between the gate body 1062 and the first electrode 109. In this case, the semiconductor layer 102 is "Z" shaped. In other words, as shown in Figures 10, 12a, and 12b, the semiconductor layer 102 covers the side, bottom, and top surfaces of the second dielectric layer 112. Alternatively, as shown in Figure 11, the semiconductor layer 102 covers the side and bottom surfaces of the second dielectric layer 112 and further covers the bottom surface of the second electrode 108.

[0222] In some examples, the semiconductor layer 102 is placed on the first electrode 109, as shown in Figures 10, 11, 12a, and 12b.

[0223] In some embodiments, as shown in Figure 8b, the semiconductor layer 102 is arranged around the entire side surface of the gate body 1062. In this case, the semiconductor layer 102 may surround the entire side surface of the gate body 1062, or it may surround only a portion of the side surface of the gate body 1062.

[0224] Since the semiconductor layer 102 is arranged across the entire side surface of the gate body 1062, the area of ​​the semiconductor layer 102 can be increased, and carrier mobility can be improved.

[0225] With respect to the second electrode 108, in some embodiments, as shown in Figures 8a, 9, 10, 12a, and 12b, the second electrode 108 is located on the side of the semiconductor layer 102 away from the second dielectric layer 112.

[0226] If the semiconductor layer 102 further includes an extended portion that extends along the surface of the gate base 1061, it should be understood that when the second electrode 108 is positioned on the side of the semiconductor layer 102 away from the second dielectric layer 112, as shown in Figures 10, 12a, and 12b, the second electrode 108 does not contact the second dielectric layer 112, and the second electrode 108 and the second dielectric layer 112 are separated by the semiconductor layer 102. If the semiconductor layer 102 is positioned along the side of the gate body 1062 and the semiconductor layer 102 does not include an extended portion that extends along the surface of the gate base 1061, then when the second electrode 108 is positioned on the side of the semiconductor layer 102 away from the second dielectric layer 112, as shown in Figures 8a and 9, the second electrode 108 contacts the second dielectric layer 112.

[0227] In some other embodiments, as shown in Figure 11, the second electrode 108 may be located on the side of the semiconductor layer 102 closer to the second dielectric layer 112. In this case, the second electrode 108 is located between the second dielectric layer 112 and the semiconductor layer 102.

[0228] Furthermore, the second electrode 108 may be arranged around the entire side surface of the gate body 1062, or the second electrode 108 may be arranged around the side surface of the gate body 1062, but not around the entire side surface.

[0229] With respect to the first electrode 109, the first electrode 109 is located at the bottom, that is, it is positioned on the side of the second electrode 108 away from the gate base 1061. In some embodiments, as shown in Figures 8a, 9, 10, 11, 12a, and 12b, the first electrode 109 is positioned on the side of the gate body 1062 away from the gate base 1061. In this case, the semiconductor layer 102 is positioned on the first electrode 109. In some other embodiments, as shown in Figure 12c, the first electrode 109 is positioned on the side of the gate body 1062. In this case, the semiconductor layer 102 also extends along the side of the first electrode 109.

[0230] In some embodiments, as shown in Figure 13, the thin-film transistor 10 further includes a fourth dielectric layer 114 disposed between the second electrode 108 and the semiconductor layer 102, and / or a fifth dielectric layer 115 disposed between the first electrode 109 and the semiconductor layer 102.

[0231] For the materials of the fourth dielectric layer 114 and the fifth dielectric layer 115, please refer to the material of the sixth dielectric layer 202. Further details will not be explained here. Also, the fourth dielectric layer 114 and the fifth dielectric layer 115 may be single-layer structures or multi-layer laminated structures.

[0232] The fourth dielectric layer 114 is positioned between the second electrode 108 and the semiconductor layer 102, and it should be noted that the second electrode 108 may or may not be in contact with the semiconductor layer 102. The fifth dielectric layer 115 is positioned between the first electrode 109 and the semiconductor layer 102, and the first electrode 109 may or may not be in contact with the semiconductor layer 102.

[0233] In some embodiments, the thickness of both the fourth dielectric layer 114 and the fifth dielectric layer 115 is in the range of 0.1 nm to 2 nm in order to ensure that the semiconductor layer 102 reliably conducts the first electrode 109 and the second electrode 108 when a voltage is applied to the gate 106.

[0234] For example, the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 may be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, and 2 nm.

[0235] Since the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 are relatively small, ranging from 0.1 nm to 2 nm, even if the fourth dielectric layer 114 is placed between the second electrode 108 and the semiconductor layer 102, and / or the fifth dielectric layer 115 is placed between the first electrode 109 and the semiconductor layer 102, when a voltage is applied to the gate 106, the first electrode 109 and the second electrode 108 can still conduct by using the semiconductor layer 102, and the performance of the thin-film transistor 10 is not affected. In addition, the fourth dielectric layer 114 is placed between the second electrode 108 and the semiconductor layer 102 to avoid the problem of diffusion of the second electrode 108 in the contact region with the semiconductor layer 102 and to reduce the Fermi-level pinning problem of the contact between the second electrode 108 and the semiconductor layer 102. The fifth dielectric layer 115 is positioned between the first electrode 109 and the semiconductor layer 102 to avoid the diffusion problem of the first electrode 109 in the contact region with the semiconductor layer 102 and to reduce the Fermi level pinning problem of the contact between the first electrode 109 and the semiconductor layer 102.

[0236] In some embodiments, the material of the second dielectric layer 112 is a ferroelectric material. In this case, as shown in Figure 14, the thin-film transistor 10 further includes a third dielectric layer 116 disposed between the semiconductor layer 102 and the second dielectric layer 112.

[0237] For the material of the third dielectric layer 116, please refer to the material of the sixth dielectric layer 202. Details will not be explained again here. Also, the third dielectric layer 116 may be a single layer structure or a multilayer laminated structure.

[0238] When the material of the second dielectric layer 112 is a ferroelectric material, it can be understood that the gate 106, the second dielectric layer 112, and the third dielectric layer 116 form a composite gate structure. By using a composite gate structure, the thin-film transistor 10 can achieve the performance of a negative capacitance transistor, and the gate control capability of the thin-film transistor 10 can be improved by using negative capacitance. When the thin-film transistor 10 is used in the memory 200, the performance of the memory 200 can be improved.

[0239] In this embodiment of the present application, it should be noted that the materials of the first dielectric layer 113, the second dielectric layer 112, the third dielectric layer 116, the fourth dielectric layer 114, and the fifth dielectric layer 115 may be the same or different.

[0240] Based on this, if the material of the second dielectric layer 112 is a ferroelectric material and the thin-film transistor 10 includes a third dielectric layer 116, then, as shown in Figure 15, the thin-film transistor 10 further includes a first conductive layer 117 disposed between the second dielectric layer 112 and the third dielectric layer 116.

[0241] For the material of the first conductive layer 117, please refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. Further details will not be explained here.

[0242] The composite gate structure, including gate 106, second dielectric layer 112, first conductive layer 117, and third dielectric layer 116, enables the thin-film transistor 10 to achieve the performance of a negative capacitance transistor, and the gate control capability of the thin-film transistor 10 can be improved by using negative capacitance. When the thin-film transistor 10 is used in the memory 200, the performance of the memory 200 can be improved.

[0243] In some embodiments, as shown in Figure 16, the thin-film transistor 10 further includes a modulated gate electrode 118 positioned between a first electrode 109 and a second electrode 108, the modulated gate electrode 118 being surrounded by a first dielectric layer 113.

[0244] For the material of the modulated gate electrode 118, please refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. Further details will not be explained here.

[0245] It should be noted that the modulated gate electrode 118 is surrounded by the first dielectric layer 113 such that it is separated from the first electrode 109, the second electrode 108, and the semiconductor layer 102. In other words, the modulated gate electrode 118 is electrically insulated from the first electrode 109, the second electrode 108, and the semiconductor layer 102 by using the first dielectric layer 113.

[0246] In this embodiment of the present invention, since the thin-film transistor 10 includes a modulated gate electrode 118, the threshold voltage of the thin-film transistor 10 can be adjusted by using the modulated gate electrode 118.

[0247] When thin-film transistor 10 is used as the first thin-film transistor Tr0 and the second thin-film transistor Tr1 of the memory 200, as shown in Figures 17a, 17b, and 17c, in the memory 200, the first thin-film transistor Tr0 further includes a first modulated gate electrode 118a positioned between the first electrode 109a and the second electrode 108a, the first modulated gate electrode 118a positioned on the semiconductor layer 102a away from the gate body 1062a, the first modulated gate electrode 118a is surrounded by a first dielectric layer 113a, thereby separating the first modulated gate electrode 118a from the first electrode 109a, the second electrode 108a and the semiconductor layer 102a; multiple located in the same layer The first modulated gate electrode 118a of the first thin-film transistor Tr0 are electrically connected together; and / or, the second thin-film transistor Tr1 further includes a second modulated gate electrode 118b positioned between the first electrode 109b and the second electrode 108b, the second modulated gate electrode 118b being positioned on the semiconductor layer 102b side away from the gate body 1062b, the second modulated gate electrode 118b being surrounded by the first dielectric layer 113b, thereby separating the second modulated gate electrode 118b from the first electrode 109b, the second electrode 108b and the semiconductor layer 102b; the second modulated gate electrodes 118b of multiple second thin-film transistors Tr1 located in the same layer are electrically connected together.

[0248] Figures 17b and 17c are both schematic cross-sectional views along the CC direction in Figure 17a.

[0249] The first modulated gate electrodes 118a of multiple first thin-film transistors Tr0 located in the same layer may be electrically connected to each other. That is, all of the first modulated gate electrodes 118a of multiple first thin-film transistors Tr0 located in the same layer may be electrically connected together, or some of the first modulated gate electrodes 118a of multiple first thin-film transistors Tr0 located in the same layer may be electrically connected together. Similarly, the second modulated gate electrodes 118b of multiple second thin-film transistors Tr1 located in the same layer may be electrically connected together. That is, the second modulated gate electrodes 118b of multiple second thin-film transistors Tr1 located in the same layer may be electrically connected together, or some of the second modulated gate electrodes 118b of multiple second thin-film transistors Tr1 located in the same layer may be electrically connected together.

[0250] For example, as shown in Figure 17b, the first modulation gate electrodes 118a of four first thin-film transistors Tr0 located in the same layer are electrically connected together. In this way, joint modulation of the four memory cells 201A can be performed.

[0251] In actual applications, it should be noted that the number of memory cells 201A that are jointly modulated may be selected as needed.

[0252] For the materials of the first modulated gate electrode 118a and the second modulated gate electrode 118b, please refer to the materials of gate 106, the first electrode 109, and the second electrode 108. Further details will not be explained here.

[0253] Since the first thin-film transistor Tr0 includes a first modulated gate electrode 118a, the threshold voltage of the first thin-film transistor Tr0 can be adjusted by using the first modulated gate electrode 118a. Since the second thin-film transistor Tr1 includes a second modulated gate electrode 118b, the threshold voltage of the second thin-film transistor Tr1 can be adjusted by using the second modulated gate electrode 118b. Based on this, the storage performance of the memory 200 can be adjusted more flexibly. For example, for the first thin-film transistor Tr0, a relatively low potential may be set for the first modulated gate electrode 118a, thereby reducing the leakage current of the first electrode 109a and the second electrode 108a of the first thin-film transistor Tr0, thereby achieving longer storage and retention times. Also, a relatively high potential may be set for the second modulated gate electrode 118b of the second thin-film transistor Tr1, thereby increasing the overall current of the second thin-film transistor Tr1, thereby improving the data readout speed.

[0254] One embodiment of the present invention further provides a method for manufacturing a thin-film transistor 10, which can be used to manufacture the aforementioned thin-film transistor 10. Referring to Figure 18, the method for manufacturing the thin-film transistor 10 includes the following:

[0255] S10. A first electrode 109, a first dielectric layer 113, a second electrode 108, and a semiconductor layer 102 are formed on the substrate. The first electrode 109, the first dielectric layer 113, and the second electrode 108 are stacked sequentially, the first dielectric layer 113 separates the first electrode 109 from the second electrode 108, the semiconductor layer 102 is formed on the side surface of the first dielectric layer 113, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0256] It should be noted that the order in which the first electrode 109, the first dielectric layer 113, the second electrode 108, and the semiconductor layer 102 are formed is not limited.

[0257] The first electrode 109 and the second electrode 108 may both be in direct contact with the semiconductor layer 102, or they may each be in contact with the semiconductor layer 102 through a separate dielectric layer.

[0258] For the materials of the first electrode 109, the first dielectric layer 113, the second electrode 108, and the semiconductor layer 102, please refer to the embodiments described above. Further details will not be explained here.

[0259] Furthermore, the first dielectric layer 113 has a surface close to the second electrode 108, a surface close to the first electrode 109, and a side surface. The surface close to the second electrode 108 and the surface close to the first electrode 109 are arranged facing each other.

[0260] Based on this, the first electrode 109 may be formed as a drain and the second electrode 108 as a source; or the first electrode 109 may be formed as a source and the second electrode 1081 as a drain.

[0261] S11. The second dielectric layer 112 and the gate 106 are formed sequentially. Here, the gate 106 includes a gate base 1061 located at the top and a gate body 1062 extending from the gate base 1061 to the bottom, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0262] For the material of the second dielectric layer 112, please refer to the embodiments described above. Further details will not be explained here.

[0263] In addition, please refer to the previously described embodiment for the material of gate 106. Further details will not be explained here.

[0264] The gate base 1061 and the gate body 1062 may be formed simultaneously, or they may be formed separately.

[0265] Based on the foregoing description, in this embodiment of the present application, when the thin film transistor 10 is manufactured, steps S10 and S11 may be sequentially executed, or steps S11 and S10 may be sequentially executed.

[0266] An embodiment of the present invention provides a method for manufacturing a thin film transistor 10. The method for manufacturing the thin film transistor 10 provided in this embodiment of the present application has the same technical effects as the foregoing thin film transistor 10. For details, please refer to the foregoing description. Details will not be described again here.

[0267] The following will describe the specific implementation of the method for manufacturing the thin film transistor 10 using examples.

Example

[0268] Embodiment 1 For example, the manufacturing of the thin film transistor 10 shown in FIG. 8a specifically includes the following steps.

[0269] S100. As shown in FIG. 19, sequentially form a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on the substrate 101.

[0270] The first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 can be sequentially formed using methods such as chemical vapor deposition, physical vapor deposition, sputtering, electroplating, etc.

[0271] S101. As shown in FIG. 19, pattern the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 to form a first electrode 109, a first dielectric layer 113, and a second electrode 108 that are sequentially laminated. Here, the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0272] The first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 can be patterned using dry etching or wet etching.

[0273] Alternatively, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 may be etched separately, or they may be etched simultaneously.

[0274] S102. A semiconductor layer 102 is formed as shown in Figure 19. Here, the semiconductor layer 102 is formed on the sidewall of the groove structure, that is, the semiconductor layer 102 is formed on the side surface of the first dielectric layer 113 and the side surface of the second electrode 108, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0275] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is an entire layer, covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; the semiconductor thin film is then etched. In addition to the semiconductor thin film formed on the side walls of the groove, semiconductor thin films formed on other parts such as the bottom of the groove, the top surface of the second electrode 108, and the outside of the groove are also etched, thereby forming a semiconductor layer 102.

[0276] Epitaxial growth methods include, for example, chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and other processes.

[0277] S103. A second dielectric layer 112 is formed as shown in Figure 19. Here, the second dielectric layer 112 covers the semiconductor layer 102, the second electrode 108, and the first electrode 109.

[0278] It should be noted that step S103 can be implemented in two embodiments. In the first embodiment, the second dielectric layer 112 may be formed directly by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is an entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second embodiment, the seventh dielectric thin film may first be formed using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113; thereafter, the seventh dielectric thin film is etched. In addition to the portions formed on the sides and bottom of the groove, the upper surface of the second electrode 108, and the upper surface of the semiconductor layer 102, all other seventh dielectric thin films are etched to form the second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0279] S104. A gate 106 is formed as shown in Figure 19. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0280] The process for forming the gate 106 may specifically involve first forming a conductive thin film, and then etching the conductive thin film to form the gate 106. [Examples]

[0281] Embodiment 2 For example, the manufacturing method of the thin-film transistor 10 shown in Figure 9 specifically includes the following:

[0282] S110. As shown in Figure 20, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0283] For the specific implementation process of step S110, please refer to step S100 mentioned above. Further details will not be explained here.

[0284] S111. As shown in Figure 20, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113, and a second electrode 108 which are sequentially stacked, and the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0285] For the specific implementation process of step S111, please refer to step S101 mentioned above. Further details will not be explained here.

[0286] S112. A semiconductor layer 102 is formed as shown in Figure 20. Here, the semiconductor layer 102 is formed on the side walls and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the side surfaces of the second electrode 108, and the semiconductor layer 102 further extends from the side surfaces of the first dielectric layer 113 and the side surfaces of the second electrode 108 to the surface of the first electrode 109 on the side closer to the second electrode 108, i.e., the upper surface of the first electrode 109, so that both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0287] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is an entire layer covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; the semiconductor thin film is then etched. In addition to the semiconductor thin film formed on the side walls and bottom of the groove, the semiconductor thin film formed on other parts such as the top surface of the second electrode 108 and the outside of the groove is etched, thereby forming the semiconductor layer 102.

[0288] S113. As shown in FIG. 20, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108.

[0289] For the specific implementation process of step S113, please refer to step S103 described above. Details will not be described again here.

[0290] S114. As shown in FIG. 20, a gate 106 is formed. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061. The gate body 1062 extends into the groove structure, that is, the gate body 1062 extends along the side surfaces of the first dielectric layer 113 and the second electrode 108. The gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109. The second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0291] For the specific implementation process of step S114, please refer to step S104 described above. Details will not be described again here.

Embodiment

[0292] Embodiment 3 For example, the manufacturing of the thin film transistor 10 shown in FIG. 10 specifically includes the following.

[0293] S120. As shown in FIG. 21, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 laminated on the substrate 101 are sequentially formed.

[0294] For the specific implementation process of step S120, please refer to step S100 described above. Details will not be described again here.

[0295] S121. As shown in Figure 21, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108, and the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0296] For the specific implementation process of step S121, please refer to step S101 mentioned above. Further details will not be explained here.

[0297] S122. As shown in Figure 21, a semiconductor layer 102 is formed, where the semiconductor layer 102 is formed on the side walls and bottom of the groove structure, and on the surface of the second electrode 108 away from the first electrode 109, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, and the semiconductor layer 102 further extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the second electrode 108 away from the first electrode 109 (i.e., the top surface of the second electrode 108) and the surface of the first electrode 109 closer to the second electrode 108 (i.e., the top surface of the first electrode 109), so that both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0298] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is an entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the side walls and bottom of the groove, and on the upper surface of the second electrode 108, the semiconductor thin film formed outside the groove is etched, thereby forming a semiconductor layer 102.

[0299] S123. As shown in Figure 21, a second dielectric layer 112 is formed, and the second dielectric layer 112 covers the semiconductor layer 102.

[0300] For the specific implementation process of step S123, please refer to step S103 mentioned above. Further details will not be explained here.

[0301] S124. A gate 106 is formed as shown in Figure 21. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0302] For the specific implementation process of step S124, please refer to step S104 mentioned above. Further details will not be explained here.

[0303] Note that the difference between Embodiment 1, Embodiment 2, and Embodiment 3 lies in the structure of the semiconductor layer 102 that is formed. [Examples]

[0304] Embodiment 4 For example, the manufacturing method of the thin-film transistor 10 shown in Figure 13 specifically includes the following:

[0305] S130. As shown in Figure 22, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0306] For the specific implementation process of step S130, please refer to step S100 mentioned above. Further details will not be explained here.

[0307] S131. As shown in Figure 22, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108, where the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0308] For the specific implementation process of step S131, please refer to step S101 mentioned above. Further details will not be explained here.

[0309] S132. As shown in Figure 22, a fifth dielectric layer 115 is formed at the bottom of the groove structure. That is, the fifth dielectric layer 115 is formed on the upper surface of the first electrode 109. Here, the fifth dielectric layer 115 is in contact with the first electrode 109.

[0310] The process for forming the fifth dielectric layer 115 may specifically involve first forming a fifth dielectric thin film, and then etching the fifth dielectric thin film to form the fifth dielectric layer 115.

[0311] S133. As shown in Figure 22, a fourth dielectric layer 114 is formed on the side of the second electrode 108 away from the first electrode 109. That is, the fourth dielectric layer 114 is formed on the upper surface of the second electrode 108. Here, the fourth dielectric layer 114 is in contact with the second electrode 108.

[0312] The process for forming the fourth dielectric layer 114 may specifically involve first forming a sixth dielectric thin film, and then etching the sixth dielectric thin film to form the fourth dielectric layer 114.

[0313] It should be noted that steps S132 and S133 may be performed step by step. In this case, step S132 may be performed first and then step S133, or step S133 may be performed first and then step S132. Alternatively, steps S132 and S133 may be performed synchronously. That is, the fourth dielectric layer 114 and the fifth dielectric layer 115 are formed simultaneously.

[0314] S134. As shown in Figure 22, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the side walls and bottom of the groove structure, and on the surface of the fourth dielectric layer 114 away from the second electrode 108. That is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113, the side of the second electrode 108, and the side of the fourth dielectric layer 114. The semiconductor layer 102 extends further to the surface of the body layer 114 away from the second electrode 108 (i.e., the upper surface of the fourth dielectric layer 114) and to the surface of the fifth dielectric layer 115 away from the first electrode 109 (i.e., the upper surface of the fifth dielectric layer 115), so that the semiconductor layer 102 is in contact with both the fourth dielectric layer 114 and the fifth dielectric layer 115, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0315] First, a semiconductor thin film may be formed by an epitaxial growth method, and the semiconductor thin film is an entire layer, covering the exposed surfaces of the fourth dielectric layer 114, the fifth dielectric layer 115, the first electrode 109, the first dielectric layer 113, and the second electrode 108; then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the side walls and bottom of the groove, and on the upper surface of the fourth dielectric layer 114, the semiconductor thin film formed outside the groove is etched to form semiconductor layer 102.

[0316] S135. As shown in Figure 22, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0317] For the specific implementation process of step S135, please refer to step S103 mentioned above. Further details will not be explained here.

[0318] S136. A gate 106 is formed as shown in Figure 22. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending within a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113, the side of the second electrode 108, and the side of the fourth dielectric layer 114, the gate base 1061 being formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separating the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0319] For the specific implementation process of step S136, please refer to step S104 mentioned above. Further details will not be explained here.

[0320] Compared to Embodiment 3, Embodiment 4 includes steps S132 and S133.

[0321] In Embodiment 4, both steps S132 and S133 are performed. In some embodiments, either step S132 or step S133 may be performed instead.

[0322] Furthermore, in Embodiment 4, the structure of the semiconductor layer 102 formed in step S134 is the same as the structure of the semiconductor layer 102 formed in Embodiment 3. In some embodiments, the structure of the semiconductor layer 102 formed in step S134 may also be the same as the structure of the semiconductor layer 102 formed in Embodiment 1 or Embodiment 2. [Examples]

[0323] Embodiment 5 For example, the manufacturing method of the thin-film transistor 10 shown in Figure 14 specifically includes the following:

[0324] S140. As shown in Figure 23, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0325] For the specific implementation process of step S140, please refer to step S100 mentioned above. Further details will not be explained here.

[0326] S141. As shown in Figure 23, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108, and the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0327] For the specific implementation process of step S141, please refer to step S101 mentioned above. Further details will not be explained here.

[0328] S142. As shown in Figure 23, a semiconductor layer 102 is formed, which is formed on the side walls and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, and the semiconductor layer 102 extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the first electrode 109 on the side closer to the second electrode 108, i.e., the upper surface of the first electrode 109, so that both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0329] For the specific implementation process of step S142, please refer to step S112 mentioned above. Further details will not be explained here.

[0330] S143. A third dielectric layer 116 is formed as shown in Figure 23. Here, the third dielectric layer 116 is formed on the side walls and bottom of the groove structure.

[0331] It should be noted that step S143 can be implemented in two embodiments. In the first embodiment, the third dielectric layer 116 can be formed directly by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the third dielectric layer 116 is the entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second embodiment, the eighth dielectric thin film may first be formed using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The eighth dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Subsequently, the eighth dielectric thin film is etched. In addition to the portions formed on the sides and bottom of the groove, all other portions of the eighth dielectric thin film are etched to form the third dielectric layer 116.

[0332] S144. As shown in Figure 23, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the third dielectric layer 116, the semiconductor layer 102, and the second electrode 108, and the material of the second dielectric layer 112 is a ferroelectric material.

[0333] For the specific implementation process of step S144, please refer to step S103 mentioned above. Further details will not be explained here.

[0334] S145. A gate 106 is formed as shown in Figure 23. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separating the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0335] For the specific implementation process of step S145, please refer to step S104 mentioned above. Further details will not be explained here.

[0336] In Embodiment 5, step S143 is added compared to Embodiment 2.

[0337] Furthermore, in Embodiment 5, the structure of the semiconductor layer 102 formed in step S142 is the same as the structure of the semiconductor layer 102 formed in Embodiment 2. In some embodiments, the structure of the semiconductor layer 102 formed in step S142 is also the same as the structure of the semiconductor layer 102 formed in Embodiment 1 or Embodiment 3. [Examples]

[0338] Embodiment 6 For example, the manufacturing method of the thin-film transistor 10 shown in Figure 15 specifically includes the following:

[0339] S150. As shown in Figure 24, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0340] For the specific implementation process of step S150, please refer to step S100 mentioned above. Further details will not be explained here.

[0341] S151. As shown in Figure 24, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108. Here, the first electrode 109, the first dielectric layer 113, and the second electrode 108 form a groove structure.

[0342] For the specific implementation process of step S151, please refer to step S101 mentioned above. Further details will not be explained here.

[0343] S152. As shown in Figure 24, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the side walls and bottom of the groove structure, that is, the semiconductor layer 102 is formed on the side surfaces of the first dielectric layer 113 and the side surfaces of the second electrode 108, and the semiconductor layer 102 further extends from the side surfaces of the first dielectric layer 113 and the side surfaces of the second electrode 108 to the surface of the first electrode 109 on the side closer to the second electrode 108, i.e., the upper surface of the first electrode 1109, so that both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0344] For the specific implementation process of step S152, please refer to step S112 mentioned above. Further details will not be explained here.

[0345] S153. As shown in Figure 24, a third dielectric layer 116 is formed, and the third dielectric layer 116 is formed on the side walls and bottom of the groove structure.

[0346] For the specific implementation process of step S153, please refer to step S143 mentioned above. Further details will not be explained here.

[0347] S154. As shown in Figure 24, a first conductive layer 117 is formed, which is formed on the side walls and bottom of the groove structure.

[0348] First, a fourth conductive thin film may be formed. Here, the fourth conductive thin film covers the exposed surfaces of the third dielectric layer 116, the semiconductor layer 102, the second electrode 108, the first dielectric layer 113, and the first electrode 109; then, the fourth conductive thin film is etched. In addition to the portions formed on the sides and bottom of the groove, other portions of the fourth conductive thin film are etched to form the first conductive layer 117.

[0349] S155. As shown in Figure 24, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the first conductive layer 117, the second dielectric layer 116, the semiconductor layer 102, and the second electrode 108, and the material of the second dielectric layer 112 is a ferroelectric material.

[0350] For the specific implementation process of step S155, please refer to step S103 mentioned above. Further details will not be explained here.

[0351] S156. A gate 106 is formed as shown in Figure 24. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0352] For the specific implementation process of step S156, please refer to step S104 mentioned above. Further details will not be explained here.

[0353] In Embodiment 6, step S154 is added compared to Embodiment 5. [Examples]

[0354] Embodiment 7 For example, the manufacturing of the thin-film transistor 10 shown in Figure 12b specifically includes the following:

[0355] S160. As shown in Figure 25, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0356] For the specific implementation process of step S160, please refer to step S100 mentioned above. Further details will not be explained here.

[0357] S161. As shown in Figure 25, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108. Here, the projection boundaries of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 are located within the boundary of the first electrode 109; that is, the first dielectric layer 113 and the second electrode 108 are located in the central region of the first electrode 109.

[0358] For the specific implementation process of step S161, please refer to step S101 mentioned above. Further details will not be explained here.

[0359] S162. As shown in Figure 25, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 covers the exposed surfaces of the second electrode 108 and the first dielectric layer 113 and the upper surface of the first electrode 109. That is, the semiconductor layer 102 covers the upper and side surfaces of the second electrode 108, the side surfaces of the first dielectric layer 113 and the upper surface of the first electrode 109.

[0360] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is an entire layer, covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108, and then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the top and side surfaces of the second electrode 108, the side surfaces of the first dielectric layer 113, and the top surface of the first electrode 109, the semiconductor thin film formed on other parts is etched, thereby forming a semiconductor layer 102.

[0361] S163. As shown in Figure 25, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0362] For the specific implementation process of step S163, please refer to step S103 mentioned above. Further details will not be explained here.

[0363] S164. A gate 106 is formed as shown in Figure 25. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 being arranged around the entire side surface of the first dielectric layer 113 and the second electrode 108, i.e., the gate body 1062 is hollow, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0364] For the specific implementation process of step S164, please refer to step S104 mentioned above. Further details will not be explained here. [Examples]

[0365] Embodiment 8 For example, the manufacturing of the thin-film transistor shown in Figure 12a specifically includes the following steps:

[0366] S170. As shown in Figure 26, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0367] For the specific implementation process of step S170, please refer to step S100 mentioned above. Further details will not be explained here.

[0368] S171. As shown in Figure 26, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108. Here, the projection boundaries of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 partially overlap with the boundary of the first electrode 109, i.e., the first dielectric layer 113 and the second electrode 108 are located in the edge region of the first electrode 109.

[0369] For the specific implementation process of step S171, please refer to step S101 mentioned above. Further details will not be explained here.

[0370] S172. A semiconductor layer 102 is formed as shown in Figure 26. Here, the semiconductor layer 102 is formed on the side surface of the second electrode 108 and the side surface of the first dielectric layer 113, and the semiconductor layer 102 further extends from the side surface of the second electrode 108 and the side surface of the first dielectric layer 113 to the top surface of the second electrode 108 and the top surface of the first electrode 109.

[0371] First, a semiconductor thin film may be formed by an epitaxial growth method. The semiconductor thin film is an entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108. The semiconductor thin film is then etched. In addition to the semiconductor thin films formed on the sides of the second electrode 108 and the first dielectric layer 113, the top surface of the second electrode 108, and the top surface of the first electrode 109, the semiconductor thin films formed on other parts are etched, thereby forming a semiconductor layer 102.

[0372] S173. As shown in Figure 26, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0373] It should be noted that step S173 can be implemented in two embodiments. In the first embodiment, the second dielectric layer 112 can be formed directly by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is an entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second embodiment, first, a seventh dielectric thin film is formed using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Subsequently, the seventh dielectric thin film is etched. In addition to the seventh dielectric thin film formed on the surface of the semiconductor layer 102 away from the first electrode 109, the seventh dielectric thin film formed in a different location is etched to form a second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0374] S174. A gate 106 is formed as shown in Figure 26. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0375] For the specific implementation process of step S174, please refer to step S104 mentioned above. Further details will not be explained here. [Examples]

[0376] Embodiment 9 For example, the manufacturing of the thin-film transistor shown in Figure 12c specifically includes the following:

[0377] S180. As shown in Figure 27, a first conductive thin film 1090, a first dielectric thin film 1130, and a second conductive thin film 1080 are sequentially formed on the substrate 101.

[0378] For the specific implementation process of step S180, please refer to step S100 mentioned above. Further details will not be explained here.

[0379] S181. As shown in Figure 27, the first conductive thin film 1090, the first dielectric thin film 1130, and the second conductive thin film 1080 are patterned to form a sequentially stacked first electrode 109, a first dielectric layer 113, and a second electrode 108, such that the projection boundaries of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 overlap with the boundary of the first electrode 109.

[0380] For the specific implementation process of step S181, please refer to step S101 mentioned above. Further details will not be explained here.

[0381] S182. A semiconductor layer 102 is formed as shown in Figure 27. The semiconductor layer 102 is formed on the side of the first electrode 109, the side of the first dielectric layer 113, and the side of the second electrode 108, and the semiconductor layer 102 further extends from the side of the first electrode 109, the side of the first dielectric layer 113, and the side of the second electrode 108 to the surface on the side of the second electrode 108 away from the first electrode 109, i.e., the top surface of the second electrode 108. First, a semiconductor thin film may be formed using an epitaxial growth method, the semiconductor thin film being an entire layer and covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then the semiconductor thin film is etched. In addition to the semiconductor thin films formed on the left side of the first electrode 109, the left side of the first dielectric layer 113, the left side of the second electrode 108, and the upper surface of the second electrode 108, semiconductor thin films formed on other parts are etched to form the semiconductor layer 102.

[0382] S183. As shown in Figure 27, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0383] It should be noted that step S183 can be implemented in two embodiments. In the first embodiment, the second dielectric layer 112 may be formed directly by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is an entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second embodiment, the seventh dielectric thin film may first be formed using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Subsequently, the seventh dielectric thin film is etched. In addition to the seventh dielectric thin film formed on the side and top surfaces of the semiconductor layer 102, the seventh dielectric thin film formed elsewhere is etched to form a second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0384] S184. A gate 106 is formed as shown in Figure 27. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0385] For the specific implementation process of step S184, please refer to step S104 mentioned above. Further details will not be explained here.

[0386] It should be noted that the difference between Embodiments 7, 8, and 9 and the other embodiments described above lies in the different structures of the laminated first electrode 109, the first dielectric layer 113, and the second electrode 108. [Examples]

[0387] Embodiment 10 For example, the manufacturing method of the thin-film transistor 10 shown in Figure 16 specifically includes the following:

[0388] S190. As shown in Figure 28, a first conductive thin film 1090 and a third dielectric thin film 1131 are sequentially stacked on the substrate 101.

[0389] For the specific implementation process of step S190, please refer to step S100 mentioned above. Further details will not be explained here.

[0390] S191. As shown in Figure 28, a modulated gate electrode 118 is formed on the third dielectric thin film 1131.

[0391] A specific process for forming the modulated gate electrode 118 may involve first forming a fifth conductive thin film, and then patterning the fifth conductive thin film to form the modulated gate electrode 118.

[0392] S192. As shown in Figure 28, a fourth dielectric thin film 1132 is formed on the modulated gate electrode 118. Here, the fourth dielectric thin film 1132 covers the modulated gate electrode 118.

[0393] The fourth dielectric thin film 1132 can be formed using methods such as chemical vapor deposition, physical vapor deposition, sputtering, and electroplating.

[0394] S193. As shown in Figure 28, the fourth dielectric thin film 1132 is subjected to grinding.

[0395] Grinding may be performed on the fourth dielectric thin film 1132 using chemical mechanical polishing techniques.

[0396] Please note that step S193 is an optional step. For example, in some embodiments, step S193 may be omitted.

[0397] S194. As shown in Figure 28, a second conductive thin film 1080 is formed on the fourth dielectric thin film 1132.

[0398] The second conductive thin film 1080 can be formed using methods such as chemical vapor deposition, physical vapor deposition, sputtering, and electroplating.

[0399] S195. As shown in Figure 28, the second conductive thin film 1080 is patterned to form the second electrode 108, the fourth dielectric thin film 1132 and the third dielectric thin film 1131 are patterned to form the first dielectric layer 113, and the first conductive thin film 1090 is patterned to form the first electrode 109. Here, the second electrode 108, the first dielectric layer 113, and the first electrode 109 form a groove structure, and the first dielectric layer 113 surrounds the modulated gate electrode 118, thereby separating the modulated gate electrode 118 from the second electrode 108 and the first electrode 109.

[0400] For the specific implementation process of step S195, please refer to step S101 mentioned above. Further details will not be explained here.

[0401] S196. A semiconductor layer 102 is formed as shown in Figure 28. Here, the semiconductor layer 102 is formed on the side walls and bottom of the groove structure, and on the surface of the second electrode 108 away from the first electrode 109. That is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, and the semiconductor layer 102 extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the second electrode 108 away from the first electrode 109 (i.e., the top surface of the second electrode 108) and the surface of the first electrode 109 closer to the second electrode 108 (i.e., the top surface of the first electrode 109), and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0402] For the specific implementation process of step S196, please refer to step S122 mentioned above. Further details will not be explained here.

[0403] S197. As shown in Figure 28, a second dielectric layer 112 is formed. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0404] For the specific implementation process of step S197, please refer to step S103 mentioned above. Further details will not be explained here.

[0405] S198. A gate 106 is formed as shown in Figure 28. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0406] For the specific implementation process of step S198, please refer to step S104 mentioned above. Further details will not be explained here.

[0407] It should be noted that the main difference between Embodiment 10 and the other embodiments described above is the addition of step S191 in Embodiment 10. [Examples]

[0408] Embodiment 11 For example, the manufacturing of the thin-film transistor 10 shown in Figure 11 specifically includes the following:

[0409] S200. As shown in Figure 29, a first conductive thin film 1090 and a first dielectric thin film 1130 are sequentially stacked on the substrate 101.

[0410] For the specific implementation process of step S200, please refer to step S100 mentioned above. Further details will not be explained here.

[0411] S201. As shown in Figure 29, the first conductive thin film 1090 and the first dielectric thin film 1130 are patterned to form a sequentially stacked first electrode 109 and first dielectric layer 113. Here, the first dielectric layer 113 and the first electrode 109 form a groove structure.

[0412] For the specific implementation process of step S201, please refer to step S101 mentioned above. Further details will not be explained here.

[0413] S202. A semiconductor layer 102 is formed as shown in Figure 29. Here, the semiconductor layer 102 is formed on the side walls and bottom of the groove structure, and on the surface of the first dielectric layer 113 away from the first electrode 109. That is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113, and the semiconductor layer 102 extends from the side of the first dielectric layer 113 to the surface of the first electrode 109 closer to the first dielectric layer 113 (i.e., the top surface of the first electrode 109) and the surface of the first dielectric layer 113 away from the first electrode 109 (i.e., the top surface of the first dielectric layer 113), and the first electrode 109 is electrically connected to the semiconductor layer 102.

[0414] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is an entire layer, covering the exposed surfaces of the first electrode 109 and the first dielectric layer 113, and then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the side walls and bottom of the groove, and on the upper surface of the first dielectric layer 113, the semiconductor thin film formed outside the groove is etched to form the semiconductor layer 102.

[0415] S203. As shown in Figure 29, a second electrode 108 is formed. Here, the second electrode 108 is located on the side of the first dielectric layer 113 away from the first electrode 109. That is, the second electrode 108 is located on the upper surface of the first dielectric layer 113.

[0416] The process for forming the second electrode 108 may specifically involve first forming a second conductive thin film, and then etching the second conductive thin film to form the second electrode 108.

[0417] S204. A second dielectric layer 112 is formed as shown in Figure 29. Here, the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108.

[0418] It should be noted that step S204 can be implemented in two ways. In the first way, the second dielectric layer 112 can be formed directly by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is an entire layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second way, the seventh dielectric thin film may first be formed using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. The seventh dielectric thin film is then etched. In addition to the portions formed on the sides and bottom of the grooves, and on the top and sides of the second electrode 108, all other seventh dielectric thin films are etched to form the second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0419] S205. As shown in Figure 29, a gate 106 is formed, comprising a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into a groove structure, i.e., the gate body 1062 extending along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separating the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0420] For the specific implementation process of step S205, please refer to step S104 mentioned above. Further details will not be explained here.

[0421] The main difference between Embodiment 11 and the other embodiments described above is that the sequence for forming the semiconductor layer 102 and the second electrode 108 in Embodiment 11 differs from that of the other embodiments described above.

[0422] It should be understood that the thin-film transistor 10 provided in the embodiments of this application may be manufactured by using the manufacturing method for the thin-film transistor 10 described above, or by using a different manufacturing method. This is not limited herein.

[0423] One embodiment of the present invention further provides a memory manufacturing method comprising forming at least one layer of a storage array 201 on a substrate 101.

[0424] For example, as shown in Figure 30, manufacturing any layer of the storage array 201 shown in Figure 4 specifically involves the following steps:

[0425] S300. Multiple first signal lines are formed on the substrate 101, arranged in parallel.

[0426] S301. A plurality of first thin-film transistors Tr0 are arranged in an array on the plurality of first signal lines, and a plurality of second signal lines are arranged in parallel, wherein the first electrode 109a of the first thin-film transistor Tr0 is electrically connected to the first signal line, and the second electrode 108a of the first thin-film transistor Tr0 is electrically connected to the second signal line, the first signal line is either a read bit line RBL or a read word line RWL, and the second signal line is the other of the read bit line RBL and the read word line RWL. The first thin-film transistors Tr0 may be manufactured by using the manufacturing method of the thin-film transistor 10 provided in any of the embodiments described above. Here, it can be understood that the plurality of first thin-film transistors Tr0 arranged in an array may be formed synchronously.

[0427] The first signal line may be the read bit line RBL, and the second signal line may be the read word line RWL. In this case, the first electrode 109a of the first thin-film transistor Tr0 is electrically connected to the read bit line RBL, and the second electrode 108a is electrically connected to the read word line RWL. Alternatively, the first signal line may be the read word line RWL, and the second signal line is the read bit line RBL. In this case, the first electrode 109a of the first thin-film transistor Tr0 is electrically connected to the read word line RWL, and the second electrode 108a is electrically connected to the read bit line RBL.

[0428] In some embodiments, it may be understood that the first electrode 109a may be formed in synchronization with the first signal line, and the second electrode 108a may be formed in synchronization with the second signal line.

[0429] S302. Multiple connection electrodes 111 are formed in an array-like arrangement. Here, the gate 106a of one first thin-film transistor Tr0 is electrically connected to one of the connection electrodes 111.

[0430] Please note that step S302 is an optional step. For example, in some embodiments, step S302 may be omitted.

[0431] First, a sixth conductive thin film may be formed, and then the sixth conductive thin film is etched to form a plurality of connecting electrodes 111.

[0432] S303. A plurality of second thin-film transistors Tr1, distributed in an array, and a plurality of parallel write bit lines WBL are formed on the first thin-film transistor Tr0. Here, the second electrode 108b of the second thin-film transistor Tr1 is electrically connected to the write bit line WBL. One second thin-film transistor Tr1 corresponds to one first thin-film transistor Tr0, and the first electrode 109b of the second thin-film transistor Tr1 is electrically connected to the gate 106a of the corresponding first thin-film transistor Tr0. The second thin-film transistors Tr1 can be manufactured by using the manufacturing method of the thin-film transistor 10 provided in any of the embodiments described above. Here, it is understood that the plurality of second thin-film transistors Tr1, distributed in an array, may be formed synchronously.

[0433] When the method for manufacturing any layer of the memory array 201 includes step S302, it should be noted that the first electrode 109b of the second thin-film transistor Tr1 is electrically connected to the gate 106a of the corresponding first thin-film transistor Tr0 by using the connecting electrode 111.

[0434] In some embodiments, the second electrode 108b of the second thin-film transistor Tr1 may be formed in synchronization with the write bit line WBL.

[0435] S304. Multiple write word lines WWL are formed on the second thin-film transistor Tr1, arranged in parallel. Here, the gate 106b of the second thin-film transistor Tr1 is electrically connected to the write word lines WWL.

[0436] In some embodiments, the write word line WWL may be formed in synchronization with the gate 106b of the second thin-film transistor Tr1.

[0437] Based on the above description, if the memory 200 includes a multi-layer storage array 201 arranged on the substrate 101, steps S300 to S304 may be repeated when the memory 200 is manufactured to form the multi-layer storage array 201.

[0438] Furthermore, a sixth dielectric layer 202 may be formed after the first layer of the memory array 201 has been manufactured and before the second layer of the memory array 201 has been formed. In this case, the sixth dielectric layer 202 is used as the substrate for the second layer of the memory array 201. Similarly, the sixth dielectric layer 202 may also be formed before the third layer, the fourth layer, and so on of the memory array 201 have been manufactured. The foregoing description is merely a specific implementation of the present application and is not intended to limit the scope of protection of the present application. Any modifications or substitutions that are readily conceivable by a person skilled in the art within the scope of the art disclosed herein shall fall within the scope of protection of the present application. Accordingly, the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

1. It is a thin-film transistor: A gate comprising a gate base located at the top and a gate body extending from the gate base to the bottom; The first electrode located at the bottom; A second electrode located between the first electrode and the gate base; A first dielectric layer disposed between the second electrode and the first electrode, wherein the first dielectric layer is configured to separate the second electrode from the first electrode; A semiconductor layer arranged along the side surface of the gate body; It has a second dielectric layer, a portion of which the second dielectric layer is located between the semiconductor layer and the gate and is in contact with the semiconductor layer and the gate, and a portion of which the second dielectric layer is located between the second electrode and the gate base and is in contact with the second electrode and the gate base. The second electrode is located between the first dielectric layer and the second dielectric layer. The semiconductor layer does not have an extended portion located between the second dielectric layer and the second electrode below the gate base. The first electrode and the second electrode are each electrically connected to the semiconductor layer. Thin-film transistor.

2. The thin-film transistor according to claim 1, wherein the semiconductor layer further includes an extended portion located between the gate body and the first electrode.

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