Array antenna device

Abstract

Provided is an array antenna device that can be used in a 300 GHz band. An array antenna device 100 comprises: a first layer 10 in which a plurality of antenna elements 11 are arranged in a grid shape; and a second layer 20 stacked on the first layer 10. The second layer 20 includes: a plurality of mixers 21 that are arranged in a plurality of grid regions 30 overlapping the plurality of antenna elements 11 in plan view, that each include an LO signal terminal 23, an IF signal terminal 24, and an RF signal terminal 22, with the RF signal terminals 22 electrically connected to the plurality of antenna elements 11; a plurality of LO signal lines 25 which are provided to respective columns of the plurality of mixers 21 and to each of which the LO signal terminals of mixers 21 of the same column are commonly connected; and a plurality of IF signal lines 27 that are provided to respective rows of the plurality of mixers 21 and to each of which the IF signal terminals of mixers 21 of the same row are commonly connected.

Description

Technical Field

[0001] The present invention relates to a wireless device provided with an array antenna, and particularly to an array antenna device suitable for a transceiver using the 300 GHz band.

Background Art

[0002] FIG. 12 is a graph showing the relationship between the frequency band and the S / N ratio for each received radio wave power. The horizontal axis of the graph is the frequency band, and the vertical axis is the S / N ratio. In the graph, the relationships between the frequency band and the S / N ratio when the received power Pr is 0.1 μW (equivalent to -40 dBm), 1 μW (equivalent to -30 dBm), and 10 μW (equivalent to -20 dBm) are plotted. As can be seen from this graph, the S / N ratio decreases as the frequency band increases regardless of the magnitude of Pr.

[0003] In the graph, auxiliary lines indicating the S / N ratio required for BER (bit error rate) <10 -3 for each modulation method of QPSK (quadrature phase shift keying), 16QAM (16 - quadrature amplitude modulation), and 64QAM (64 - quadrature amplitude modulation) are drawn. According to this, if the frequency band is 25 GHz, communication is possible with any of the modulation methods of QPSK, 16QAM, and 64QAM as long as Pr is 0.1 μW or more. However, when the frequency band reaches 50 GHz, if Pr is 0.1 μW, the S / N ratio becomes too small and communication by QPSK becomes difficult. Also, if stable QPSK communication is to be performed in a higher frequency band of about 100 GHz, a received power of 1 μW or more is required.

[0004] The sixth-generation mobile communication system (6G) aims to achieve data rates of 100 Gb / s or more by using the 300 GHz band, which is even higher than the fifth-generation mobile communication system (5G). Therefore, in next-generation mobile communication systems that will become increasingly high-frequency and have higher data rates, it is necessary to increase the output power of the transmitter in order to maintain high received power. Until now, approaches to increase the output power of transceivers using the 300 GHz band have included increasing the antenna gain using lenses or horns, or increasing the output power of a single transceiver by power coupling multiple RF signals using a rat-race type power coupler (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International release 2020 / 110814 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] When evaluating received power from the perspective of EIRP (Equivalent Isotropic Radiated Power), the received power Pr = EIRP·Ar / 4πd, where d is the distance from the transmitter to the receiver and Ar is the antenna area of ​​the receiver. 2 This can be expressed as follows: In other words, the magnitude of the received power is determined by the antenna area Ar of the receiver, regardless of the frequency band, and the larger the antenna area, the greater the antenna gain can be, and the greater the received power can be.

[0007] To increase antenna gain, it is effective to employ an array antenna with multiple antenna elements arranged in a single plane. Furthermore, by using a phased array antenna, beamforming techniques such as adjusting the signal phase of individual antenna elements to transmit radio waves in a specific direction or receive radio waves from a specific direction, as well as beam sweeping to freely change the direction of the beam, become available. This widens the beam control angle compared to using lenses or horns, and makes beamforming itself easier.

[0008] In array antennas, antenna elements are arranged at half-wavelength pitches of radio waves. In the 300 GHz band, antenna elements need to be arranged at approximately 500 μm pitches. Therefore, if an array antenna with antenna elements arranged in a two-dimensional grid is to be used in a transceiver operating in the 300 GHz band, the transceiver circuit must be packed into an area of ​​approximately 500 μm square. Although transistor sizes can be reduced through the miniaturization of semiconductor processes, passive elements such as inductance and capacitance elements are difficult to miniaturize, making it difficult to pack a circuit like the one disclosed in Patent Document 1 into such a narrow area. Thus, employing an array antenna in a transceiver operating in the 300 GHz band is difficult due to the constraints on the circuit arrangement area.

[0009] In view of the above problems, the present invention aims to provide an array antenna device capable of utilizing the 300 GHz band. [Means for solving the problem]

[0010] An array antenna device according to one aspect of the present invention comprises a first layer on which a plurality of antenna elements are arranged in a grid, and a second layer stacked on the first layer, wherein the second layer is characterized by comprising a plurality of mixers arranged in a plurality of grid regions that overlap with the plurality of antenna elements in a plan view, each mixer having an LO signal terminal, an IF signal terminal, and an RF signal terminal, the RF signal terminal of which is electrically connected to the plurality of antenna elements, a plurality of LO signal lines provided for each row of the plurality of mixers, the LO signal terminals of the mixers in the same row being commonly connected, and a plurality of IF signal lines provided for each row of the plurality of mixers, the IF signal terminals of the mixers in the same row being commonly connected. [Effects of the Invention]

[0011] According to the present invention, it becomes possible to transmit and receive radio waves in the 300 GHz band using an array antenna. This makes it possible to easily increase the antenna gain in the 300 GHz band. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic plan view of an array antenna device according to the first embodiment of the present invention. [Figure 2] This is a circuit diagram of a mixerless transmitter, as an example. [Figure 3] This is a schematic plan view of an array antenna device according to a second embodiment of the present invention. [Figure 4] This is a circuit diagram of a mixer-first configuration receiver, as an example. [Figure 5] This is a schematic plan view of an array antenna device according to a third embodiment of the present invention. [Figure 6] This is a schematic plan view of an array antenna device according to a fourth embodiment of the present invention. [Figure 7] This is a schematic plan view of an array antenna device according to a fifth embodiment of the present invention. [Figure 8] This is a schematic plan view of an array antenna device according to a sixth embodiment of the present invention. [Figure 9] It is a schematic plan view of an array antenna device according to the seventh embodiment of the present invention. [Figure 10] It is a schematic plan view of an example of a semiconductor substrate for a transmitter corresponding to a scalable configuration. [Figure 11] It is a schematic plan view of an example of a semiconductor substrate for a receiver corresponding to a scalable configuration. [Figure 12] It is a graph showing the relationship between the frequency band and the S / N ratio for each received radio wave power.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, a more detailed description than necessary may be omitted. For example, detailed descriptions of well-known matters and duplicate descriptions of substantially the same configurations may be omitted. This is to avoid making the following description unnecessarily redundant and to facilitate the understanding of those skilled in the art. The inventor provides the accompanying drawings and the following description for those skilled in the art to fully understand the present invention, and does not intend to limit the subject matter described in the claims thereby. Also, the dimensions of each member depicted in the drawings and the detailed shapes of the details may be different from the actual ones.

[0014] (First Embodiment) FIG. 1 is a schematic plan view of an array antenna device according to the first embodiment of the present invention. The array antenna device 100 according to the present embodiment is a 300 GHz band silicon CMOS transmitter in which a printed circuit board 10 and a semiconductor substrate 20 are laminated. In FIG. 1, for convenience, the plan views of the printed circuit board 10 and the semiconductor substrate 20 are drawn side by side horizontally, but in reality, these are laminated by flip chip bonding.

[0015] On the printed circuit board 10, antenna elements 11 such as rectangular microstrip patch antennas are arranged in a 4×4 grid pattern vertically and horizontally. Considering that the desired RF frequency of the array antenna device 100 is 252 to 296 GHz (wavelength approximately 1000 to 1200 μm), as an example, the sum of the lengths of two sides of the antenna element 11 is 300 to 350 μm with a slight margin from a quarter wavelength of the RF signal, and the arrangement pitch in the row direction and column direction of the antenna element 11 (corresponding to the horizontal direction and vertical direction in FIG. 1) is 600 to 700 μm with a slight margin from a half wavelength of the RF signal.

[0016] On the semiconductor substrate 20, a transmission circuit 201 is mounted. The transmission circuit 201 is an aggregate of individual transmitters that transmit RF signals (radio frequency signals) from the individual antenna elements 11. The individual transmitter is a mixer-last configuration transmitter in which a mixer that up-converts an IF signal (intermediate frequency signal) with a LO signal (local oscillation frequency signal) to generate an RF signal is arranged at the final stage. Such a mixer-last configuration is adopted in a 300 GHz band silicon CMOS transmitter where a power amplifier cannot be arranged at the final stage.

[0017] FIG. 2 is a circuit diagram of a mixer-last configuration transmitter according to an example. The transmitter includes a mixer 21, a LO signal generator 31, and an IF signal amplifier 41. The RF signal terminal 22 of the mixer 21 is connected to the antenna element 11, the LO signal terminal 23 is connected to the LO signal generator 31, and the IF signal terminal 24 is connected to the IF signal amplifier 41.

[0018] More specifically, the LO signal generator 31 comprises a balun 32, a preamplifier 33, and a 9x multiplier 34. The balun 32 converts the unbalanced LO source signal supplied from an oscillator (not shown) into a balanced signal. For example, the frequency of the LO source signal is 25 GHz. The preamplifier 33 amplifies the balanced signal output from the balun 32. The 9x multiplier 34 multiplies the frequency of the preamplifier's output signal by 9 to output a 225 GHz LO signal. The output signal of the 9x multiplier 34 is input to the mixer 21 via the LO signal terminal 23 of the mixer 21. The IF signal amplifier 41 consists of multiple linked amplifiers and amplifies an externally input balanced IF signal of approximately 50 GHz. The output signal of the IF signal amplifier 41 is input to the mixer 21 via the IF signal terminal 24 of the mixer 21. A 275 GHz RF signal is generated at the RF signal terminal 22 of the mixer 21.

[0019] Alternatively, the frequency of the LO source signal may be set to 75 GHz, and the 9-frequency multiplier 34 may be replaced with a tripler that triples the frequency of the input signal.

[0020] Returning to Figure 1, the mixers 21 of the individual transmitters described above are arranged in a grid pattern in a 4x4 grid region 30 on the semiconductor substrate 20. Each mixer 21 consists of one or more transistors and one or more passive elements. The length of one side of each grid region 30 is 600-700 μm, the same as the arrangement pitch of the antenna elements 11, and in a plan view, one antenna element 11 fits in one grid region 30. That is, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, each mixer 21 is positioned directly below each antenna element 11 in a plan view. The RF signal terminal 22 of each mixer 21 on the semiconductor substrate 20 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via bumps (not shown).

[0021] LO signal lines 25 are wired to each row of mixers 21 arranged in a grid. In this embodiment, there are a total of four LO signal lines 25. These LO signal lines 25 are arranged at equal intervals, i.e., the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixers 21. The LO signal terminals 23 of the four mixers 21 in the same row are commonly connected to each LO signal line 25.

[0022] An LO phase shifter 26 is connected to the end of each LO signal line 25. Furthermore, the aforementioned LO signal generator 31 is connected to each LO phase shifter 26. Each LO phase shifter 26 receives an LO signal from the LO signal generator 31, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 25. The amount of phase adjustment by each LO phase shifter 26 is controlled by the controller 29. In this way, LO signals with the same phase are input to the mixers 21 in the same row, and the phase of the LO signal can be adjusted independently of the mixers 21 in other rows for each row of mixer 21. As a result, beam sweeping in the row direction of the antenna element 11 arrangement is possible by adjusting the phase of the LO signal on each LO signal line 25.

[0023] An IF signal line 27 is wired to each row of the mixer 21, which is arranged in a grid. In this embodiment, there are a total of four IF signal lines 27. These IF signal lines 27 are arranged at equal intervals, i.e., at the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixer 21. The IF signal terminals 24 of the four mixers 21 in the same row are commonly connected to each IF signal line 27.

[0024] An IF phase shifter 28 is connected to the end of each IF signal line 27. Furthermore, the aforementioned IF signal amplifier 41 is connected to each IF phase shifter 28. Each IF phase shifter 28 receives the IF signal amplified by the IF signal amplifier 41, adjusts its phase, and supplies the phase-adjusted IF signal to each IF signal line 27. The amount of phase adjustment by each IF phase shifter 28 is controlled by the controller 29. In this way, IF signals with the same phase are input to the mixers 21 in the same row, and the phase of the IF signal can be adjusted independently of the mixers 21 in other rows for each row of mixer 21. As a result, beam sweeping in the column direction of the array of antenna elements 11 is possible by adjusting the phase of the IF signal on each IF signal line 27.

[0025] As mentioned above, each grid region 30 is a narrow region with sides of 600-700 μm, so it is not possible to place many circuit elements there. For this reason, circuits of a certain size, such as the LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, and controller 29, are all placed outside the grid region 30. For example, as shown in Figure 1, the LO phase shifter 26 and the LO signal generator 31 connected to it, which are connected to the ends of the LO signal lines 25 extending in the column direction of the grid region 30, are placed in the empty space in the column direction of the grid region 30. The IF phase shifter 28 and the IF signal amplifier 41 connected to it, which are connected to the ends of the IF signal lines 27 extending in the row direction of the grid region 30, are placed in the empty space in the row direction of the grid region 30. The controller 29 is placed in the remaining empty space.

[0026] As described above, this embodiment allows for increased transmission power by employing an array antenna in a 300GHz silicon CMOS transmitter. Furthermore, the phases of the LO signal and IF signal can be adjusted to sweep the transmitted RF signal in two dimensions, vertically and horizontally. In addition, by arranging the mixer 21, LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, and controller 29 on the same layer of the semiconductor substrate 20, heat generated from various circuit elements is less likely to accumulate compared to when they are stacked, making heat dissipation easier. This prevents performance degradation of the transmission circuit 201 due to heat generation from the semiconductor substrate 20.

[0027] In the example in Figure 1, an LO signal generator 31 is provided on a one-to-one basis for each LO phase shifter 26. However, the LO signal may be distributed and supplied from one LO signal generator 31 to multiple LO phase shifters 26. Also, in the example in Figure 1, an IF signal amplifier 41 is provided on a one-to-one basis for each IF phase shifter 28. However, the IF signal may be distributed and supplied from one IF signal amplifier 41 to multiple IF phase shifters 28. Furthermore, the connection order of the IF phase shifter 28 and the IF signal amplifier 41 may be reversed so that the IF signal, phase-adjusted by the IF phase shifter 28, is amplified by the IF signal amplifier 41 and supplied to the IF signal line 27. In other words, the IF phase shifter 28 may be directly connected to the IF signal line 27 or connected via the IF signal amplifier 41.

[0028] The amount of circuitry that can be packed into the grid region 30 depends on the size of the standard cell, which is determined by the arrangement pitch of the antenna elements 11. If there is still room in the grid region 30, in addition to the mixer 21, other components such as the 9-multiplier 34 (or triplar or other multipliers depending on the case) of the LO signal generator 31, the final stage amplifier constituting the IF signal amplifier 41, and the buffer circuit (not shown) connected to the mixer 21 may also be placed in the grid region 30. By placing the circuit elements connected to the mixer 21 as close to the mixer 21 as possible, the wiring distance from the circuit elements to the mixer 21 can be minimized, thereby suppressing signal attenuation input to the mixer 21 and improving the noise figure of the transmitter.

[0029] (Second embodiment) Figure 3 is a schematic plan view of an array antenna device according to a second embodiment of the present invention. The array antenna device 200 according to this embodiment is a 300 GHz band silicon CMOS receiver formed by stacking a printed circuit board 10 and a semiconductor substrate 20. For convenience, Figure 3 shows the plan views of the printed circuit board 10 and the semiconductor substrate 20 side by side, but in reality, they are stacked by flip-chip bonding.

[0030] On the printed circuit board 10, antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid. Considering that the desired RF frequency of the array antenna device 200 is 252-296 GHz (wavelength approximately 1000-1200 μm), as an example, the sum of the lengths of two sides of the antenna elements 11 is 300-350 μm, with a slight margin over one-quarter wavelength of the RF signal, and the arrangement pitch of the antenna elements 11 in the row and column directions (corresponding to the horizontal and vertical directions in Figure 3) is 600-700 μm, with a slight margin over half wavelength of the RF signal.

[0031] A receiving circuit 202 is mounted on the semiconductor substrate 20. The receiving circuit 202 is a collection of individual receivers that process the RF signals received by each antenna element 11. These individual receivers are mixer-first receivers in which a mixer is placed in the first stage to down-convert the RF signal with an LO signal and generate an IF signal. Such a mixer-first configuration is adopted in 300GHz band silicon CMOS receivers where a low-noise amplifier cannot be placed in the first stage.

[0032] Figure 4 is a circuit diagram of a mixer-first configuration receiver as an example. The receiver comprises a mixer 21, an LO signal generator 31, and an IF signal amplifier 42. The RF signal terminal 22 of the mixer 21 is connected to the antenna element 11, the LO signal terminal 23 is connected to the LO signal generator 31, and the IF signal terminal 24 is connected to the IF signal amplifier 42.

[0033] More specifically, the LO signal generator 31 comprises a balun 32, a preamplifier 33, and a 9x multiplier 34. The balun 32 converts the unbalanced LO signal input from an oscillator (not shown) into a balanced signal. For example, the frequency of the RF signal at the RF signal terminal 22 of the mixer 21 is 275 GHz, and the frequency of the LO signal is 25 GHz. The preamplifier 33 amplifies the balanced signal output from the balun 32. The 9x multiplier 34 multiplies the frequency of the preamplifier's output signal by 9 to output a 225 GHz LO signal. The output signal of the 9x multiplier 34 is input to the mixer 21 via the LO signal terminal 23 of the mixer 21. The IF signal amplifier 42 consists of multiple amplifiers linked together and amplifies the approximately 50 GHz balanced IF signal output from the IF signal terminal 24 of the mixer 21.

[0034] Alternatively, the frequency of the LO source signal may be set to 75 GHz, and the 9-frequency multiplier 34 may be replaced with a tripler that triples the frequency of the input signal.

[0035] Returning to Figure 3, the individual receiver mixers 21 described above are arranged in a grid pattern in a 4x4 grid region 30 on the semiconductor substrate 20. Each mixer 21 consists of one or more transistors and one or more passive elements. The length of one side of each grid region 30 is 600-700 μm, the same as the arrangement pitch of the antenna elements 11, and in a plan view, one antenna element 11 fits in one grid region 30. That is, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, each mixer 21 is positioned directly below each antenna element 11 in a plan view. The RF signal terminal 22 of each mixer 21 on the semiconductor substrate 20 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via bumps (not shown).

[0036] LO signal lines 25 are wired to each row of mixers 21 arranged in a grid. In this embodiment, there are a total of four LO signal lines 25. These LO signal lines 25 are arranged at equal intervals, i.e., the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixers 21. The LO signal terminals 23 of the four mixers 21 in the same row are commonly connected to each LO signal line 25.

[0037] An LO phase shifter 26 is connected to the end of each LO signal line 25. Furthermore, the aforementioned LO signal generator 31 is connected to each LO phase shifter 26. Each LO phase shifter 26 receives an LO signal from the LO signal generator 31, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 25. The amount of phase adjustment by each LO phase shifter 26 is controlled by the controller 29. In this way, LO signals with the same phase are input to the mixers 21 in the same row, and the phase of the LO signal can be adjusted independently of the mixers 21 in other rows for each row of mixer 21. As a result, beam sweeping in the row direction of the antenna element 11 arrangement is possible by adjusting the phase of the LO signal on each LO signal line 25.

[0038] An IF signal line 27 is wired to each row of the mixer 21, which is arranged in a grid. In this embodiment, there are a total of four IF signal lines 27. These IF signal lines 27 are arranged at equal intervals, i.e., at the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixer 21. The IF signal terminals 24 of the four mixers 21 in the same row are commonly connected to each IF signal line 27.

[0039] An IF phase shifter 28 is connected to the end of each IF signal line 27. 28The aforementioned IF signal amplifier 42 is connected to it. The IF phase shifter 28 and the IF signal amplifier 42 connected to it are arranged in the empty area in the row direction of the grid area 30. Each IF phase shifter 28 receives an IF signal from the IF signal line 27 and adjusts its phase. The IF signal amplifier 42 amplifies the IF signal whose phase has been adjusted by the IF phase shifter 28. After each phase of the IF signal is amplified by the IF signal amplifier 42, it is power coupled to become the received IF signal. The amount of phase adjustment by each IF phase shifter 28 is controlled by the controller 29. In this way, IF signals with the same phase are output from the mixers 21 in the same row, and the phase of the IF signal can be adjusted independently of the mixers 21 in other rows for each row of mixer 21. This makes it possible to perform a beam sweep in the column direction of the array of antenna elements 11 by adjusting the phase of the IF signal on each IF signal line 27.

[0040] As mentioned above, each grid region 30 is a narrow region with sides of 600-700 μm, so it is not possible to place many circuit elements there. For this reason, circuits of a certain size, such as the LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, and controller 29, are all placed outside the grid region 30. For example, as shown in Figure 3, the LO phase shifter 26 and the LO signal generator 31 connected to it, which are connected to the ends of the LO signal lines 25 extending in the column direction of the grid region 30, are placed in the empty space in the column direction of the grid region 30. The IF phase shifter 28 and the IF signal amplifier 42 connected to it, which are connected to the ends of the IF signal lines 27 extending in the row direction of the grid region 30, are placed in the empty space in the row direction of the grid region 30. The controller 29 is placed in the remaining empty space.

[0041] As described above, this embodiment allows for increased received power by employing an array antenna in a 300GHz silicon CMOS receiver. Furthermore, the phases of the LO signal and IF signal can be adjusted to sweep the received RF signal in two dimensions, vertically and horizontally. In addition, by arranging the mixer 21, LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 42, and controller 29 on the same layer of the semiconductor substrate 20, heat generated from various circuit elements is less likely to accumulate compared to when they are stacked, making heat dissipation easier. This prevents performance degradation of the receiving circuit 202 due to heat generation from the semiconductor substrate 20.

[0042] In the example in Figure 3, an LO signal generator 31 is provided one-to-one with the LO phase shifter 26, but the LO signal may be distributed and supplied from one LO signal generator 31 to multiple LO phase shifters 26. Also, in the example in Figure 3, an IF signal amplifier 42 is provided one-to-one with the IF phase shifter 28, but the output signals of multiple IF phase shifters 28 may be power coupled and then the coupled IF signal may be input to a single IF signal amplifier 42. Furthermore, the connection order of the IF phase shifter 28 and the IF signal amplifier 42 may be reversed so that the IF signal from the IF signal line 27 is amplified by the IF signal amplifier 42 and then phase-adjusted by the IF phase shifter 28. In other words, even if the IF phase shifter 28 is directly connected to the IF signal line 27, the IF signal amplifier 42 It doesn't matter if the connection is made via [a different method].

[0043] The amount of circuitry that can be packed into the grid region 30 depends on the size of the standard cell, which is determined by the arrangement pitch of the antenna elements 11. If there is still room in the grid region 30, in addition to the mixer 21, other components such as the 9-multiplier 34 (or triplar or other multipliers depending on the case) of the LO signal generator 31, the first-stage amplifier constituting the IF signal amplifier 42, and a buffer circuit (not shown) connected to the mixer 21 may also be placed in the grid region 30. By placing circuit elements that supply signals directly to the mixer 21, or receive signals directly from the mixer 21, as close to the mixer 21 as possible, the wiring distance from these circuit elements to the mixer 21 can be minimized, thereby suppressing attenuation of signals input to or output from the mixer 21 and improving the noise figure of the receiver.

[0044] (Third embodiment) Figure 5 is a schematic plan view of an array antenna device according to a third embodiment of the present invention. The array antenna device 300 according to this embodiment is a 300 GHz band transmitter formed by laminating a printed circuit board 10 and an optoelectronic substrate 50. In Figure 5, for convenience, the plan views of the printed circuit board 10 and the optoelectronic substrate 50 are shown side by side, but in reality, they are laminated by flip-chip bonding. The following description will omit explanations of points that are the same as in the first embodiment and will only explain the differences.

[0045] On the printed circuit board 10, antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid. Considering that the desired RF frequency of the array antenna device 300 is 252-296 GHz (wavelength approximately 1000-1200 μm), as an example, the sum of the lengths of two sides of the antenna elements 11 is 300-350 μm, with a slight margin over one-quarter wavelength of the RF signal, and the arrangement pitch of the antenna elements 11 in the row and column directions (corresponding to the horizontal and vertical directions in Figure 5) is 600-700 μm, with a slight margin over one-half wavelength of the RF signal.

[0046] A photoelectric conversion circuit 203 is mounted on the photoelectric substrate 50. Specifically, mixers 51 are arranged in a grid pattern in a 4x4 grid region 30 on the photoelectric substrate 50. The mixer 51 is a single-travel carrier photodiode (UTC-PD). When two optical signals with a frequency difference are input to the UTC-PD, a terahertz wave is generated as a beat signal of those optical signals. For example, by inputting two optical signals with a frequency difference of about 300 GHz (LO signal and IF signal, described later) to the mixer 51, electromagnetic waves in the 300 GHz band are generated in the mixer 51 and 300 GHz radio waves are output from the antenna element 11.

[0047] The length of one side of each grid region 30 is 600-700 μm, the same as the arrangement pitch of the antenna elements 11, and in a plan view, one antenna element 11 fits within one grid region 30. That is, if the printed circuit board 10 is the upper layer and the optoelectronic substrate 50 is the lower layer, in a plan view, each mixer 51 is positioned directly below each antenna element 11. The RF signal terminals (not shown) of each mixer 51 on the optoelectronic substrate 50 are electrically connected to the corresponding antenna elements 11 on the printed circuit board 10 via bumps (not shown).

[0048] LO signal lines 55 are wired to each row of mixers 51 arranged in a grid. The LO signal lines 55 are optical waveguides, and in this embodiment there are a total of four. These LO signal lines 55 are arranged at equal intervals, i.e., the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixers 51. The LO signal terminals (not shown) of the four mixers 51 in the same row are commonly connected to each LO signal line 55.

[0049] An LO phase shifter 56 is connected to the end of each LO signal line 55. The LO phase shifter 56 is an optical phase shifter that adjusts the phase of the input optical signal. Each LO phase shifter 56 receives an LO signal, which is an optical signal, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 55. As an example, the LO signal is near-infrared light with a wavelength of about 1.5 μm. The amount of phase adjustment by each LO phase shifter 56 is controlled by a controller 59. In this way, LO signals with the same phase are input to the mixers 51 in the same row, and the phase of the LO signal can be adjusted independently of the mixers 51 in other rows for each row of mixer 51. As a result, beam sweeping in the row direction of the antenna element 11 array is possible by adjusting the phase of the LO signal on each LO signal line 55.

[0050] An IF signal line 57 is wired to each row of mixers 51 arranged in a grid. The IF signal line 57 is an optical waveguide, and in this embodiment there are a total of four of them. These IF signal lines 57 are arranged at equal intervals, i.e., the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixers 51. Each IF signal line 57 is commonly connected to the IF signal terminals (not shown) of the four mixers 51 in the same row.

[0051] An IF phase shifter 58 is connected to the end of each IF signal line 57. The IF phase shifter 58 is an optical phase shifter that adjusts the phase of the input optical signal. Each IF phase shifter 28 receives an IF signal, which is an optical signal, adjusts its phase, and supplies the phase-adjusted IF signal to each IF signal line 57. For example, the IF signal is near-infrared light with a wavelength of about 1.5 μm, and the frequency difference with the LO signal is about 300 GHz. The amount of phase adjustment by each IF phase shifter 58 is controlled by the controller 59. In this way, IF signals with the same phase are input to the mixers 51 in the same row, and the phase of the IF signal can be adjusted independently of the mixers 51 in other rows for each row of mixer 51. This makes it possible to perform beam sweeping in the column direction of the array of antenna elements 11 by adjusting the phase of the IF signal on each IF signal line 57.

[0052] As mentioned above, each grid region 30 is a narrow region with sides of 600-700 μm, so it is not possible to place many circuit elements. For this reason, the LO phase shifter 56, IF phase shifter 58, and controller 59 are all placed outside the grid region 30. For example, as shown in Figure 5, the LO phase shifter 26 connected to the end of the LO signal line 55 extending in the column direction of the grid region 30 is placed in the empty space in the column direction of the grid region 30, the IF phase shifter 58 connected to the end of the IF signal line 57 extending in the row direction of the grid region 30 is placed in the empty space in the row direction of the grid region 30, and the controller 59 is placed in the remaining empty space.

[0053] As described above, according to this embodiment, the transmission power can be increased by employing an array antenna in the 300GHz band transmitter as the wireless interface of the optical communication device. Furthermore, the phase of the LO signal and IF signal can be adjusted to sweep the transmitted RF signal in two dimensions, vertically and horizontally.

[0054] (Fourth embodiment) It is also possible to integrate the transmitter according to the first embodiment and the receiver according to the second embodiment. Figure 6 is a schematic plan view of an array antenna device according to the fourth embodiment of the present invention. The array antenna device 400 according to this embodiment is a 300 GHz band silicon CMOS transceiver formed by stacking a printed circuit board 10 and a semiconductor substrate 20. In Figure 6, for convenience, the plan views of the printed circuit board 10 and the semiconductor substrate 20 are shown side by side, but in reality, they are stacked by flip-chip bonding.

[0055] On the printed circuit board 10, antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid. Considering that the desired RF frequency of the array antenna device 400 is 252-296 GHz (wavelength approximately 1000-1200 μm), as an example, the sum of the lengths of two sides of the antenna elements 11 is 300-350 μm, with a slight margin over one-quarter wavelength of the RF signal; the arrangement pitch of the antenna elements 11 in the row direction (horizontal direction in Figure 6) is 600-700 μm, with a slight margin over one-half wavelength of the RF signal; and the arrangement pitch in the column direction (vertical direction in Figure 6) is 300-350 μm, with a slight margin over one-quarter wavelength of the RF signal. In other words, the arrangement pitch of the antenna elements 11 in the column direction is half that of the first and second embodiments.

[0056] A transceiver circuit 204 is mounted on the semiconductor substrate 20. The transceiver circuit 204 is a collection of individual mixer-first transmitters that transmit RF signals (radio frequency signals) from individual antenna elements 11, and individual mixer-first receivers that process the RF signals received by each antenna element 11. The mixer-first transmitters and mixer-first receivers are described with reference to Figures 2 and 4.

[0057] On the semiconductor substrate 20, the individual transmitter and receiver mixers 21 described above are arranged in a grid pattern within a 4x4 grid region 30. Each mixer 21 consists of one or more transistors and one or more passive elements. The lengths of the vertical and horizontal sides of each grid region 30 are 300-350 μm vertically and 600-700 μm horizontally, respectively, which are the same as the arrangement pitch of the antenna elements 11 in the column and row directions, and in a plan view, one antenna element 11 fits within one grid region 30. That is, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, each mixer 21 is positioned directly below each antenna element 11 in a plan view. The RF signal terminal 22 of each mixer 21 on the semiconductor substrate 20 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via bumps (not shown).

[0058] LO signal lines 25 are wired to each row of mixers 21 arranged in a grid. In this embodiment, there are a total of four LO signal lines 25. These LO signal lines 25 are arranged at equal intervals, i.e., the same pitch as the arrangement pitch of the antenna elements 11, traversing multiple grid regions 30 along the arrangement of the rows of mixers 21. The LO signal terminals 23 of the four mixers 21 in the same row are commonly connected to each LO signal line 25.

[0059] An LO phase shifter 26 is connected to the end of each LO signal line 25. Furthermore, the aforementioned LO signal generator 31 is connected to each LO phase shifter 26. Each LO phase shifter 26 receives an LO signal from the LO signal generator 31, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 25. The amount of phase adjustment by each LO phase shifter 26 is controlled by the controller 29. In this way, LO signals with the same phase are input to the mixers 21 in the same row, and the phase of the LO signal can be adjusted independently of the mixers 21 in other rows for each row of mixer 21. As a result, beam sweeping in the row direction of the antenna element 11 arrangement is possible by adjusting the phase of the LO signal on each LO signal line 25.

[0060] An IF signal line 27 is wired to each row of the mixer 21, which is arranged in a grid. In this embodiment, there are a total of four IF signal lines 27. These IF signal lines 27 are arranged at equal intervals, i.e., the same pitch as the arrangement pitch of the antenna elements 11 in the column direction, traversing multiple grid regions 30 along the arrangement of the rows of mixer 21. The IF signal terminals 24 of the four mixers 21 in the same row are commonly connected to each IF signal line 27.

[0061] An IF phase shifter 28 is connected to the end of each IF signal line 27. Furthermore, the aforementioned IF signal amplifiers 41 and 42 are alternately connected to each IF phase shifter 28. IF phase shifter 28 and the IF signal amplifiers connected thereto 41The IF signal amplifier 42 is located in the empty space in the row direction of the grid region 30. That is, the circuit elements of the individual transmitter and receiver are arranged alternately in the column direction of the antenna elements 11 which are arranged in a grid. Each IF phase shifter 28 of the transmitter receives the IF signal amplified by the IF signal amplifier 41, adjusts its phase, and supplies the phase-adjusted IF signal to each IF signal line 27. Each IF phase shifter 28 of the receiver receives the IF signal from the IF signal line 27 and adjusts its phase. The IF signal amplifier 42 of the receiver amplifies the IF signal that has been phase-adjusted by the IF phase shifter 28, and the IF signal of each phase is amplified by the IF signal amplifier 42 and then power-coupled to become the received IF signal. The amount of phase adjustment by each IF phase shifter 28 is controlled by the controller 29. In this way, for the transmitter, IF signals of the same phase are input to the mixer 21 of the same row, and for the receiver, IF signals of the same phase are output from the mixer 21 of the same row, and the phase of the IF signal can be adjusted independently of the mixer 21 of other rows for each row of the mixer 21. This allows for beam sweeping in the column direction of the antenna element array 11 during both transmission and reception by adjusting the phase of the IF signal on each IF signal line 27.

[0062] As described above, each grid region 30 is a narrow region measuring 300-350 μm vertically and 600-700 μm horizontally, so it is not possible to place many circuit elements there. Therefore, circuits of a certain size, such as the LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, IF signal amplifier 42, and controller 29, are all placed outside the grid region 30. For example, as shown in Figure 6, the LO phase shifter 26 and the LO signal generator 31 connected to it, which are connected to the ends of the LO signal lines 25 extending in the column direction of the grid region 30, are placed in the empty space in the column direction of the grid region 30. The IF phase shifter 28 and the IF signal amplifiers 41 and 42 connected to it, which are connected to the ends of the IF signal lines 27 extending in the row direction of the grid region 30, are placed in the empty space in the row direction of the grid region 30, and the controller 29 is placed in the remaining empty space.

[0063] As described above, this embodiment allows for increased transmit and receive power by employing an array antenna in a 300GHz silicon CMOS transceiver. Furthermore, the phases of the LO signal and IF signal can be adjusted to sweep the transmit RF signal and receive RF signal in two dimensions, vertically and horizontally. In addition, by arranging the mixer 21, LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, IF signal amplifier 42, and controller 29 on the same layer of the semiconductor substrate 20, heat generated from various circuit elements is less likely to accumulate compared to when they are stacked, making heat dissipation easier. This prevents performance degradation of the transmit / receive circuit 204 due to heat generation from the semiconductor substrate 20.

[0064] In the example in Figure 6, an LO signal generator 31 is provided on a one-to-one basis for each LO phase shifter 26. However, the LO signal may be distributed and supplied from one LO signal generator 31 to multiple LO phase shifters 26. Also, in the example in Figure 6, an IF signal amplifier 41 is provided on a one-to-one basis for each IF phase shifter 28. However, the IF signal may be distributed and supplied from one IF signal amplifier 41 to multiple IF phase shifters 28. Furthermore, in the example in Figure 6, an IF signal amplifier 42 is provided on a one-to-one basis for each IF phase shifter 28. However, the output signals of multiple IF phase shifters 28 may be power coupled, and the coupled IF signal may be input to one IF signal amplifier 42. Alternatively, the connection order of the IF phase shifter 28 and the IF signal amplifier 41 may be reversed so that the IF signal, phase-adjusted by the IF phase shifter 28, is amplified by the IF signal amplifier 41 and supplied to the IF signal line 27. In other words, the transmitter's IF phase shifter 28 may be directly connected to the IF signal line 27 or connected via the IF signal amplifier 41. Alternatively, the connection order of the IF phase shifter 28 and the IF signal amplifier 42 may be reversed so that the IF signal from the IF signal line 27 is amplified by the IF signal amplifier 42 and then phase-adjusted by the IF phase shifter 28. In other words, the receiver's IF phase shifter 28 may be directly connected to the IF signal line 27 or connected via the IF signal amplifier 41.

[0065] The amount of circuitry that can be packed into the grid region 30 depends on the size of the standard cell, which is determined by the arrangement pitch of the antenna elements 11. If there is still room in the grid region 30, in addition to the mixer 21, other components such as the 9-multiplier 34 (or triplar or other multipliers depending on the case) of the LO signal generator 31, the final stage amplifier constituting the IF signal amplifier 41, the first stage amplifier constituting the IF signal amplifier 42, and a buffer circuit (not shown) connected to the mixer 21 may also be placed in the grid region 30. By placing circuit elements that supply signals directly to the mixer 21, or receive signals directly from the mixer 21, as close to the mixer 21 as possible, the wiring distance from these circuit elements to the mixer 21 can be minimized, thereby suppressing attenuation of signals input to or output from the mixer 21 and improving the noise figure of the transmitter and receiver.

[0066] In the above configuration, the receiving antenna elements 11, for example, the odd-numbered rows of antenna elements 11 in the antenna array, are not used during transmission, and the transmitting antenna elements 11, for example, the even-numbered rows of antenna elements 11 in the antenna array, are not used during reception, resulting in poor utilization efficiency of the antenna elements 11. Therefore, in order to enable transmission and reception using all antenna elements 11, the arrangement pitch in the column direction of the antenna elements 11 may be double the above pitch, that is, 600 to 700 μm, which allows for a small margin of half a wavelength of the RF signal, similar to the first and second embodiments. In this case, the arrangement pitch of each transmitting and receiving antenna element 11 will be equivalent to one wavelength, but by configuring the circuit so that during transmission the receiving antenna element 11 transmits an RF signal with an intermediate phase between the RF signals transmitted from the transmitting antenna elements 11 on both sides, and during reception the transmitting antenna element 11 receives an RF signal with an intermediate phase between the RF signals received by the receiving antenna elements 11 on both sides, the transmitting and receiving antenna elements 11 are effectively arranged at a pitch equivalent to half a wavelength.

[0067] (Fifth embodiment) The semiconductor substrate 20 of the array antenna device 100 according to the first embodiment may be made of a compound semiconductor or bipolar CMOS (BiCMOS). Figure 7 is a schematic plan view of the array antenna device according to the fifth embodiment of the present invention. In the antenna device 100A according to this embodiment, the semiconductor substrate 20 is a compound semiconductor substrate such as GaAs, InP, InGaAlP, or a SiGe-BiCMOS substrate. Because compound semiconductors and BiCMOS have excellent high-frequency characteristics, it becomes possible to provide a power amplifier 61 that amplifies the 300 GHz RF signal output from the mixer 21 after the mixer 21, that is, between the antenna element 11 and the mixer 21. The power amplifier 61 after the mixer 21 is placed in the grid region 30 together with the mixer 21.

[0068] In the case of an array antenna device 100 composed of silicon CMOS as shown in Figure 1, the output power per mixer 21 is relatively small, so many antenna elements 11 must be used to secure the required transmission power. For this reason, many mixer-less transmitters as shown in Figure 2 are required, which increases power consumption. Furthermore, if there is an upper limit on the power consumption of the semiconductor substrate 20, the number of transmitters that can be driven is limited, which may result in insufficient transmission power. On the other hand, although compound semiconductors and BiCMOS have higher manufacturing costs than silicon CMOS, a power amplifier 61 can be placed after the mixer 21 to increase the transmission power per antenna element 11, thus reducing the number of transmitters required to secure the necessary transmission power. In other words, compound semiconductors and BiCMOS can obtain high transmission power with a smaller circuit size compared to silicon CMOS, thus overcoming the problem of increased manufacturing costs.

[0069] (Sixth embodiment) The semiconductor substrate 20 of the array antenna device 200 according to the second embodiment may be made of a compound semiconductor or bipolar CMOS (BiCMOS). Figure 8 is a schematic plan view of the array antenna device according to the sixth embodiment of the present invention. In the antenna device 200A according to this embodiment, the semiconductor substrate 20 is a compound semiconductor substrate such as GaAs, InP, InGaAlP, or a SiGe-BiCMOS substrate. Because compound semiconductors and BiCMOS have excellent high-frequency characteristics, it is possible to provide a low-noise amplifier 62 that amplifies the weak 300 GHz RF signal received by the antenna element 11 in front of the mixer 21, that is, between the antenna element 11 and the mixer 21. The low-noise amplifier 62 in front of the mixer 21 is placed in the grid region 30 together with the mixer 21.

[0070] In the case of an array antenna device 200 composed of silicon CMOS as shown in Figure 2, the power of the RF signal input to each mixer 21 is relatively small, so many antenna elements 11 must be used to secure the required receiving power. For this reason, many mixer-first receivers as shown in Figure 4 are required, which increases power consumption. Also, if there is an upper limit on the power consumption of the semiconductor substrate 20, the number of receivers that can be driven is limited, which may result in insufficient receiving power. On the other hand, although compound semiconductors and BiCMOS have higher manufacturing costs than silicon CMOS, a low-noise amplifier 62 can be placed in front of the mixer 21 to increase the power of the RF signal input to the mixer 21, thus reducing the number of receivers required to secure the necessary receiving power. In other words, compound semiconductors and BiCMOS can obtain greater receiving power with a smaller circuit size compared to silicon CMOS, thus overcoming the problem of increased manufacturing costs.

[0071] (Seventh Embodiment) The semiconductor substrate 20 of the array antenna device 400 according to the fourth embodiment may be made of a compound semiconductor or bipolar CMOS (BiCMOS). Figure 9 is a schematic plan view of the array antenna device according to the seventh embodiment of the present invention. In the antenna device 400A according to this embodiment, the semiconductor substrate 20 is a compound semiconductor substrate such as GaAs, InP, InGaAlP, or a SiGe-BiCMOS substrate. Compound semiconductors and BiCMOS have excellent high-frequency characteristics, so for the transmitter, it is possible to provide a power amplifier 61 that amplifies the 300 GHz RF signal output from the mixer 21 after the mixer 21, i.e., between the antenna element 11 and the mixer 21, and for the receiver, it is possible to provide a low-noise amplifier 62 that amplifies the weak 300 GHz RF signal received by the antenna element 11 before the mixer 21, i.e., between the antenna element 11 and the mixer 21. The power amplifier 61 located downstream of the mixer 21 and the low-noise amplifier 62 located upstream of the mixer 21 are placed together with the mixer 21 in the grid region 30.

[0072] In the case of an array antenna device 400 composed of silicon CMOS as shown in Figure 6, the output power per mixer 21 is relatively small, and the power of the RF signal input to each mixer 21 is also relatively small. Therefore, many antenna elements 11 must be used to secure the necessary transmission and reception power. For this reason, many mixer-last configuration transmitters and mixer-first configuration receivers, as shown in Figures 2 and 4, are required, which increases power consumption. Furthermore, if there is an upper limit on the power consumption of the semiconductor substrate 20, the number of transmitters and receivers that can be driven is limited, which may result in insufficient transmission and reception power. On the other hand, although compound semiconductors and BiCMOS have higher manufacturing costs than silicon CMOS, a power amplifier 61 can be placed after the mixer 21 to increase the transmission power per antenna element 11, and a low-noise amplifier 62 can be placed before the mixer 21 to increase the power of the RF signal input to the mixer 21. As a result, fewer transmitters and receivers are needed to secure the necessary transmission and reception power. In other words, compound semiconductors and BiCMOS can achieve greater transmit and receive power with smaller circuit sizes compared to silicon CMOS, thus overcoming the problem of increased manufacturing costs.

[0073] ≪Variations≫ Mixer 21 or mixer 51 does not need to be positioned directly below the antenna element 11; it can be placed anywhere in the grid region 30. In this sense, mixers 21 or mixer 51 do not need to be arranged at equal intervals; for example, they may be arranged in a staggered pattern.

[0074] The LO signal lines 25 or 55 do not need to be spaced equally apart. For example, two LO signal lines 25 or 55 may be placed between the first and second columns of mixer 21 or mixer 51, and the remaining two LO signal lines 25 or 55 may be placed between the third and fourth columns of mixer 21 or mixer 51. Similarly, the IF signal lines 27 or 57 do not need to be spaced equally apart. For example, two IF signal lines 27 or 57 may be placed between the first and second rows of mixer 21 or mixer 51, and the remaining two IF signal lines 27 or 57 may be placed between the third and fourth rows of mixer 21 or mixer 51. This ensures that there is enough circuit space for four grid areas 30 (two vertically and two horizontally), allowing circuit elements other than mixer 21 or mixer 51 to be placed in the grid area 30.

[0075] The antenna element 11 may be mounted on the redistribution layer (RDL) of the semiconductor substrate 20 instead of the printed circuit board 10. This allows the array antenna device to be realized on a single chip.

[0076] It goes without saying that the antenna elements 11 are not limited to a total of 16 (4x4). The antenna gain can be increased by increasing the number of antenna elements 11. For example, by using 32x32 (1024) antenna elements 11, the antenna gain is 64 times greater than when there are 16 antenna elements 11, according to a simple calculation. When the number of antenna elements 11 is large, the length of the LO signal line 25 or LO signal line 55 and the IF signal line 27 or IF signal line 57 increases, which may cause significant signal attenuation at the end of the signal line. Therefore, a buffer circuit may be provided at an appropriate point in the middle of the signal line to ensure that a signal of a certain magnitude or greater is transmitted to the end. Also, the LO phase shifter 26 may be connected directly to the LO signal line 25 or connected via a buffer circuit.

[0077] If it is sufficient for the RF signal to be swept in only one direction, the phase shift amount of either the LO phase shifter or the IF phase shifter may be fixed to a fixed value. Alternatively, either the LO phase shifter or the IF phase shifter may be omitted, and a signal of the same phase or a predetermined phase difference may be connected to the signal line on which the phase shifter is omitted.

[0078] If sweeping the RF signal is unnecessary and beamforming in a specific direction is sufficient, the controller can be omitted and the phase values ​​of the LO phase shifter and IF phase shifter can be fixed. Alternatively, the LO phase shifter and IF phase shifter can also be omitted, and the LO signal and IF signal, which are in phase or have a predetermined phase difference, can be connected to the LO signal line and IF signal line.

[0079] By connecting the circuit elements of the LO phase shifter 26, IF phase shifter 28, LO phase shifter 56, and IF phase shifter 58 in series in each of the above embodiments, an array antenna device can be configured scalably. Figure 10 is a schematic plan view of an example of a semiconductor substrate for a transmitter that corresponds to a scalable configuration. For convenience, in Figure 10, the mixer 21 and the power amplifier 61 in the case of a compound semiconductor, as shown in Figures 1 and 7, are referred to as "mixer array" and are not shown, and the controller 29 is also not shown. In the semiconductor substrate 20, multiple LO phase shifters 26 are connected in series in the row direction at the same pitch as the row arrangement pitch of the mixers in the mixer array (not shown). The first stage LO phase shifter 26 (the leftmost LO phase shifter 26 in the example of Figure 10) receives an LO signal from an LO signal generator (not shown). The LO phase shifter 26 includes a phase shifter 261, a frequency multiplier 262, and a buffer circuit 263. The LO signal input to the LO phase shifter 26 is phase-adjusted by the phase shifter 261 and split into two. One is amplified twice via a buffer circuit (not shown) and input to the frequency multiplier 262, and the other is amplified twice again via a buffer circuit (not shown) and input to the next stage LO phase shifter 26. The amount of phase adjustment by the phase shifter 261 is controlled by a controller (not shown). The LO signal input to the frequency multiplier 262 has its frequency multiplied and is supplied to the LO signal line 25 via the buffer circuit 263. In addition, on the semiconductor substrate 20, multiple IF phase shifters 28 are arranged in a column direction at the same pitch as the column arrangement pitch of the mixers (not shown) in the mixer array and connected in series. The first-stage IF phase shifter 28 (the uppermost IF phase shifter 28 in the example of Figure 10) receives an IF signal and an LO signal from an LO signal generator (not shown). The IF phase shifter 28 has a phase shifter 281 and a mixer 282. The LO signal input to the IF phase shifter 28 is phase-adjusted by the phase shifter 281 and split into two. One is amplified twice via a buffer circuit (not shown) and input to the mixer 282, and the other is amplified twice via a buffer circuit (not shown) and input to the next-stage IF phase shifter 28. Similarly, the IF signal input to the IF phase shifter 28 is split into two. One is amplified twice via a buffer circuit (not shown) and input to the mixer 282, and the other is amplified twice via a buffer circuit (not shown) and input to the next-stage IF phase shifter 28.In mixer 282, the IF signal and the phase-adjusted LO signal are mixed to generate a phase-adjusted IF signal. This phase-adjusted IF signal is amplified by the IF signal amplifier 41 and supplied to the IF signal line 27.

[0080] Figure 11 is a schematic plan view of an example of a receiving semiconductor substrate compatible with a scalable configuration. For convenience, in Figure 11, the mixer 21 and the low-noise amplifier 62 in the case of compound semiconductors, as shown in Figures 3 and 8, are omitted from the illustration and labeled as "mixer array," and the controller 29 is also omitted from the illustration. In the semiconductor substrate 20, multiple LO phase shifters 26 are connected in series in the row direction at the same pitch as the row direction arrangement pitch of the mixers (not shown) in the mixer array. The configuration of the LO phase shifters 26 is as described with reference to Figure 10. In the semiconductor substrate 20, multiple IF phase shifters 28 are connected in series in the column direction at the same pitch as the column direction arrangement pitch of the mixers (not shown) in the mixer array. The first-stage IF phase shifter 28 (the uppermost IF phase shifter 28 in the example of Figure 11) receives the IF signal amplified from the IF signal amplifier 42, as well as the LO signal from the LO signal generator (not shown), and further receives the IF signal output from the next-stage IF phase shifter 28. The IF phase shifter 28 has a phase shifter 281, a mixer 282, and a power coupler 283. The LO signal input to the IF phase shifter 28 is phase-adjusted by the phase shifter 281 and split into two. One is amplified twice via a buffer circuit (not shown) and input to the mixer 282, and the other is amplified twice again via a buffer circuit (not shown) and input to the next-stage IF phase shifter 28. The IF signal input to the IF phase shifter 28 is also input to the mixer 282, where the IF signal and the phase-adjusted LO signal are mixed to generate a phase-adjusted IF signal. The power coupler 283 receives the phase-adjusted IF signal and the IF signal output from the next-stage IF phase shifter 28 as inputs, and these IF signals are power-coupled and output. That is, the IF signal output from the last-stage IF phase shifter 28 is successively input to the preceding IF phase shifter 28 and power-coupled cumulatively, and the received IF signal is output from the first-stage IF phase shifter 28.

[0081] In Figures 10 and 11, the LO signal, whose phase has been adjusted by the phase shifter 261 or phase shifter 281, is split into two, with one input to the next-stage phase shifter 261 or phase shifter 281. However, the LO signal before phase adjustment may be split into two, with one input to its own phase shifter 261 or phase shifter 281 and the other to the next-stage phase shifter 261 or phase shifter 281. Furthermore, following the above modifications, the transceiver-integrated array antenna device shown in Figures 6 and 9 can be configured scalably.

[0082] As described above, embodiments have been explained as examples of the technology in the present invention. For this purpose, accompanying drawings and a detailed description have been provided. Therefore, among the components described in the accompanying drawings and detailed description, there may be not only components that are essential for solving the problem, but also components that are not essential for solving the problem, in order to illustrate the above technology. For this reason, the mere fact that these non-essential components are described in the accompanying drawings and detailed description should not be immediately assumed to be essential. Furthermore, since the above embodiments are for the purpose of illustrating the technology in the present invention, various changes, substitutions, additions, omissions, etc., can be made within the scope of the claims or equivalents. [Industrial applicability]

[0083] The array antenna device according to the present invention can be widely used not only in the 300 GHz band but also in wireless communication devices and wireless sensors that use the terahertz band of 100 GHz or higher. [Explanation of symbols]

[0084] 100, 200, 300, 400, 100A, 200A, 400A Array Antenna Devices 10 Printed circuit board (first layer) 11 Antenna elements 20 Semiconductor substrate (second layer) 30 grid areas 21 Mixer 22 RF signal end 23 LO signal end 24 IF signal end 25 LO signal line 26 LO phase shifter 27 IF signal line 28 IF phase shifter 29 Controllers 50. Optoelectronic substrate (second layer) 51 Mixer 55 LO signal line 56 LO phase shifter 57 IF signal line 58 IF phase shifter 59 Controllers

Claims

1. The first layer has multiple antenna elements arranged in a grid, The first layer comprises a second layer laminated on top of the first layer, The aforementioned second layer, A plurality of mixers are arranged in multiple grid regions that overlap with the plurality of antenna elements in a plan view, and each mixer has an LO signal terminal, an IF signal terminal, and an RF signal terminal, the RF signal terminal of which is electrically connected to the plurality of antenna elements. A plurality of LO signal lines are provided for each row of the plurality of mixers, and the LO signal terminals of the mixers in the same row are commonly connected to each other. Each row of the plurality of mixers has a plurality of IF signal lines, to which the IF signal terminals of the mixers in the same row are commonly connected. An array antenna device characterized by the following features.

2. The second layer has a plurality of phase shifters connected to at least one of the plurality of LO signal lines and the plurality of IF signal lines, The array antenna device according to claim 1, wherein the plurality of phase shifters are arranged outside the plurality of grid regions.

3. The second layer has a controller that controls the signal phase adjustment by the phase shifter, The array antenna device according to claim 2, wherein the controller is located outside the plurality of grid regions.

4. The array antenna device according to claim 2, wherein the plurality of phase shifters are connected in series.

5. The array antenna device according to claim 4, wherein the plurality of phase shifters are arranged at the same arrangement pitch as the plurality of mixers.

6. The array antenna device according to any one of claims 1 to 5, wherein the plurality of LO signal lines are arranged in parallel at equal intervals.

7. The array antenna device according to any one of claims 1 to 5, wherein the plurality of IF signal lines are arranged in parallel at equal intervals.

8. The first layer is a printed circuit board, The array antenna device according to any one of claims 1 to 5, wherein the second layer is a semiconductor substrate.

9. The semiconductor substrate is a compound semiconductor substrate or BiCMOS, The array antenna device according to claim 8, wherein an amplifier is provided between the antenna element and the mixer, and the amplifier is located in the grid region.

10. The array antenna device according to claim 8, wherein the array antenna device is a device that integrates transmission and reception.

11. The semiconductor substrate is a compound semiconductor substrate or BiCMOS, The array antenna device according to claim 10, wherein an amplifier is provided between the antenna element and the mixer, and the amplifier is located in the grid region.

12. The first layer is a printed circuit board, The second layer is a photoelectric substrate, The mixer is a single-travel carrier photodiode, The array antenna device according to any one of claims 1 to 5, wherein the signal connected to the LO signal line and the signal connected to the IF signal line are optical signals.

Images