Multilayer wiring board

Abstract

To provide a multilayer wiring board which is excellent in insulation reliability.SOLUTION: A multilayer wiring board 12 has two or more layers 126 laminated with each other, wherein each of the two or more layers 126 includes: an insulating resin layer 1263 that has a first surface S1 and a second surface S2 as a back face of the first surface S1 and is provided with a groove part opened in the first surface S1; a conductor layer 1262 including a wiring part 1262W embedded with the groove part in the insulating resin layer 1263; a first metal-containing layer 1261a which does not cover the side face of the wiring part 1262W and covers the surface on the first surface S1 side of the wiring part 1262W; and a second metal-containing layer 1261b which includes a part interposed between the first metal-containing layer 1261a and the wiring part 1262W and a part covering side face of the wiring part 1262W, and is made of a metal material different from a material of the first metal-containing layer 1261a.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a multilayer wiring board.

Background Art

[0002] In recent years, as semiconductor devices have become faster and more highly integrated, there has also been a demand for a wiring board for a flip chip - ball grid array (FC - BGA) that mounts a semiconductor chip, that is, for an FC - BGA board, to reduce the pitch of bonding terminals used for bonding with a semiconductor chip and to make the wiring in the board finer. On the other hand, for bonding between the FC - BGA board and the motherboard, bonding by bonding terminals arranged at substantially the same pitch as in the past is required. Under these requirements, a technique of providing a multilayer wiring board including fine wiring, also called an interposer, between the FC - BGA board and the semiconductor chip has been adopted.

[0003] One of them is silicon interposer technology. This silicon interposer technology is to manufacture an interposer by forming a multilayer wiring structure in which each layer includes fine wiring on a silicon wafer using semiconductor circuit manufacturing technology.

[0004] Also, a method has been developed in which the above - mentioned multilayer wiring structure is not formed on a silicon wafer but directly incorporated into the FC - BGA board. This method is to form the above - mentioned multilayer wiring structure using chemical mechanical polishing (CMP) or the like in the manufacture of an FC - BGA board whose core layer is made of, for example, a glass epoxy board. This is disclosed in Patent Document 1.

[0005] Furthermore, there is also a method (hereinafter referred to as a transfer method) in which an interposer is formed on a support such as a glass substrate, the interposer is bonded to the FC - BGA board, and then the support is peeled off from the interposer to provide the above - mentioned multilayer wiring structure on the FC - BGA board. This is disclosed in Patent Document 2.

Prior Art Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2014-225671 [Patent Document 2] International Publication No. 2018 / 047861 [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention aims to provide a multilayer wiring board with excellent insulation reliability. [Means for solving the problem]

[0008] According to one aspect of the present invention, the present invention comprises two or more layers laminated together, each of which is an insulating resin layer having a first surface and a second surface which is its back surface, and includes an insulating resin layer having a groove opening on the first surface, a conductor layer including a wiring portion that fills the groove in the insulating resin layer, a first metal-containing layer that covers the surface of the wiring portion on the first surface side without covering the side surface of the wiring portion, and a second metal-containing layer that includes a portion interposed between the first metal-containing layer and the wiring portion and a portion that covers the side surface of the wiring portion, and is made of a metal material different from the material of the first metal-containing layer. Furthermore, the second metal-containing layer is made of copper, and the insulating resin layer and the second metal-containing layer are in contact on the side surface of the wiring portion. A multilayer wiring board is provided.

[0009] According to yet another aspect of the present invention, a multilayer wiring board is provided in which each of the two or more adjacent layers is in contact with the insulating resin layers.

[0010] According to yet another aspect of the present invention, a multilayer wiring board is provided which is formed integrally in the thickness direction, the insulating resin layer is further provided with a first recess opening on the first surface and a second recess opening on the second surface and communicating with one or more of the first recesses, the conductor layer further includes a land portion that fills the first recess of the insulating resin layer and a via portion that protrudes from the first surface at the position of the land portion, the via portion fills a recess of another insulating resin layer adjacent to the first surface on the first surface side, and the first metal-containing layer further covers the surface of the land portion on the first surface side and the surface of the via portion without covering the side surface of the land portion.

[0011] Here, the statement that the insulating resin layer is "formed integrally in the thickness direction" means that this insulating resin layer does not have any interfaces intersecting its thickness direction internally, i.e., it has a single-layer structure. Even if multiple stacked insulating layers are made of the same material, their interfaces can be confirmed by observing their cross-sections with an electron microscope such as a scanning electron microscope.

[0012] According to yet another aspect of the present invention, a multilayer wiring board according to any of the above aspects is provided, wherein the insulating resin layer is made of a non-photosensitive resin.

[0013] According to yet another aspect of the present invention, the first metal-containing layer is titanium Includes A multilayer wiring board according to any of the above embodiments is provided.

[0014] According to yet another aspect of the present invention, a multilayer wiring substrate is provided in which the portion of the second metal-containing layer that covers the side surface of the wiring portion has an arithmetic mean roughness Ra of 10 nm or less.

[0015] According to yet another aspect of the present invention, a composite wiring board is provided comprising a first wiring board and a second wiring board bonded to the first wiring board, wherein the first and second wiring boards are electrically connected to each other via bonding electrodes interposed between them, and the second wiring board is a multilayer wiring board according to any of the above aspects.

[0016] According to yet another aspect of the present invention, a composite wiring board is provided wherein the first wiring board is a wiring board for a flip-chip ball grid array, and the second wiring board is an interposer.

[0017] According to yet another aspect of the present invention, a packaged device is provided comprising a composite wiring board according to any of the above aspects and a functional device mounted on the side of the second wiring board opposite to the first wiring board.

[0018] Here, "functional device" refers to a device that operates by being supplied with at least one of power and / or an electrical signal, a device that outputs at least one of power and / or an electrical signal in response to an external stimulus, or a device that operates by being supplied with at least one of power and / or an electrical signal and also outputs at least one of power and / or an electrical signal in response to an external stimulus. Functional devices are in the form of chips, such as semiconductor chips or chips on which circuits and elements are formed on substrates made of materials other than semiconductors, such as glass substrates. Functional devices can include, for example, one or more large-scale integrated circuits (LSIs), memories, image sensors, light-emitting elements, and MEMS (Micro Electro Mechanical Systems). MEMS are, for example, one or more pressure sensors, acceleration sensors, gyroscopes, tilt sensors, microphones, and acoustic sensors. For example, a functional device is a semiconductor chip including an LSI.

[0019] According to still another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board including forming two or more stacked layers, wherein forming each of the two or more layers includes forming a recess in an insulating resin layer, forming a dummy layer having a groove and a through hole communicating with one or more of the recesses on the insulating resin layer, forming a first metal-containing layer covering the upper surface of the dummy layer and the inner surfaces of the recess, the groove, and the through hole, forming a second metal-containing layer made of a metal material different from that of the first metal-containing layer on the first metal-containing layer, forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole, polishing the conductor layer so that a portion located outside the recess, the groove, or the through hole is removed, and obtaining portions of the conductor layer that fill the recess, the through hole, and the groove as a via portion, a land portion, and a wiring portion, respectively, then removing the dummy layer, removing an exposed portion of the first metal-containing layer, and providing an insulating resin layer covering the conductor layer and filling a gap between the land portion and the wiring portion.

[0020] According to still another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein the dummy layer is made of a photosensitive resin.

[0021] According to still another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any one of the above aspects, wherein the insulating resin layer is made of a non-photosensitive resin.

Advantages of the Invention

[0022] According to the present invention, there is provided a multilayer wiring board having excellent insulation reliability.

Brief Description of the Drawings

[0023] [Figure 1] A cross-sectional view schematically showing a packaged device according to an embodiment of the present invention. [Figure 2] A cross-sectional view schematically showing a multilayer wiring board included in the packaged device shown in FIG. 1. [Figure 3] A cross-sectional view showing an enlarged part of the multilayer wiring board shown in FIG. 2. [Figure 4] A cross-sectional view showing an enlarged part of a multilayer wiring board according to another embodiment of the present invention. [Figure 5] A cross-sectional view schematically showing a step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 6] A cross-sectional view schematically showing another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 7] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 8] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 9] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 10] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 11] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [[ID=2,7]] [Figure 12] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 13] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 14] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 15] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 16] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 17] A cross-sectional view schematically showing still another step in the manufacturing method of a multilayer wiring board according to an embodiment of the present invention. [Figure 18] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 19] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 20] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 21] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 22] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 23] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 24] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 25] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 26] A schematic cross-sectional view showing yet another step in the manufacturing method of a multilayer wiring board according to one embodiment of the present invention. [Figure 27] A schematic cross-sectional view showing one step in the manufacturing method of a packaged device according to one embodiment of the present invention. [Figure 28] A schematic cross-sectional view showing other steps in the manufacturing method of a packaged device according to one embodiment of the present invention. [Figure 29] A schematic cross-sectional view showing yet another step in the manufacturing method of a packaged device according to one embodiment of the present invention. [Figure 30] A schematic cross-sectional view showing a multilayer wiring board related to a comparative example. [Figure 31] Figure 30 is a cross-sectional view showing a magnified portion of the multilayer wiring board. [Modes for carrying out the invention]

[0024] Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below are more specific to any of the above embodiments. The embodiments shown below are examples that embody the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited to the material, shape, structure, and arrangement of the components described below. Various modifications can be made to the technical idea of ​​the present invention within the technical scope defined by the claims described in the patent claims.

[0025] In the drawings referenced in the following description, components with similar or identical functions are given the same reference numerals. It should be noted that the drawings are schematic, and the relationships between dimensions in the thickness direction and dimensions perpendicular to the thickness direction (i.e., in-plane direction), as well as the relationships between dimensions in the thickness direction of multiple layers, may differ from reality. Therefore, specific dimensions should be determined by referring to the following description. It should also be noted that the dimensional relationships between two or more components may differ across multiple drawings. Furthermore, it should be noted that in some drawings, the same structure is depicted upside down compared to other drawings.

[0026] In this disclosure, "upper surface" and "lower surface" refer to the two main surfaces of a plate-like member or a layer contained therein, namely the surface perpendicular to the thickness direction and having the largest area, and its back surface, which are shown at the top and bottom in the drawings, respectively. "Side surface" refers to a surface that is perpendicular to or inclined to the above-mentioned main surface.

[0027] Furthermore, in this disclosure, the phrase "AA on BB" is used independently of the direction of gravity. The state specified by the phrase "AA on BB" includes the state in which AA is in contact with BB. The phrase "AA on BB" does not exclude the presence of one or more other components between AA and BB.

[0028] <Structure> Figure 1 is a schematic cross-sectional view showing a packaged device according to one embodiment of the present invention.

[0029] The packaged device 1 shown in Figure 1 includes a composite wiring board 10, a functional device 20, a sealing resin layer 30, and a bonding electrode 40.

[0030] The functional device 20 is, for example, a semiconductor chip, or a chip on which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, the functional device 20 is assumed to be a semiconductor chip. That is, in this case, the packaging device 1 is a semiconductor package.

[0031] Packaged device 1 includes multiple functional devices 20. Packaged device 1 may include only one functional device 20.

[0032] The functional device 20 is bonded to the composite wiring board 10 via bonding electrodes 40. Here, the functional device 20 is bonded to the composite wiring board 10 by flip-chip bonding. One or more of the functional devices 20 may be bonded to the composite wiring board 10 by other bonding methods such as wire bonding.

[0033] The bonding electrodes 40 are arranged at a narrow pitch between the functional device 20 and the composite wiring board 10. The bonding electrodes 40 are made of, for example, solder. When the functional device 20 is bonded to the composite wiring board 10 by wire bonding, for example, gold wire can be used to electrically connect the functional device 20 and the composite wiring board.

[0034] The sealing resin layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10, and a portion that at least partially covers the side surface of the functional device 20. The sealing resin layer 30 fixes the functional device 20 to the composite wiring board 10.

[0035] The composite wiring board 10 includes an FC-BGA substrate 11, a multilayer wiring board 12, a sealing resin layer 13, and bonding electrodes 14.

[0036] The FC-BGA board 11 is an example of a first wiring board. The FC-BGA board 11 is bonded to, for example, a motherboard (not shown).

[0037] The FC-BGA substrate 11 includes a core layer 111, an insulating layer 112, a conductor layer 113, an insulating layer 114, and a bonding conductor 115.

[0038] The core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate made by impregnating a woven or nonwoven fabric with a thermosetting insulating resin. As the woven or nonwoven fabric, for example, glass fiber, carbon fiber, or aramid fiber can be used. As the insulating resin, for example, epoxy resin can be used.

[0039] The core layer 111 is provided with through holes. A portion of the conductor layer 113 covers the side walls of the through holes. Here, a portion of the conductor layer 113 covers the side walls of the through holes provided in the core layer 111 such that the through holes have side walls made of conductors. These through holes with conductor side walls may be filled with an insulator.

[0040] The remaining conductor layer 113 and the insulating layer 112 form a multilayer wiring structure on both main surfaces of the core layer 111. Each multilayer wiring structure includes alternately stacked conductor layers 113 and insulating layers 112.

[0041] Each insulating layer 112 in the multilayer wiring structure is, for example, an insulating resin layer. Through holes are provided in the insulating layer 112.

[0042] The conductive layer 113 is made of a metal or alloy such as copper. The conductive layer 113 may have a single-layer structure or a multi-layer structure.

[0043] Each conductor layer 113 in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with an insulating layer 112 in between further includes via portions that cover the side walls of through holes provided in the insulating layer 112.

[0044] The insulating layer 114 is provided on the multilayer wiring structure described above. The insulating layer 114 is, for example, an insulating resin layer such as solder resist. The insulating layer 114 is provided with through holes that communicate with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

[0045] The joining conductor 115 is a metal bump provided on the portion of the conductor layer 113 that is exposed at the location of the through-hole in the insulating layer 114. The joining conductor is also called a joining terminal. The joining conductor 115 is made of, for example, solder.

[0046] The multilayer wiring board 12 is a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via bonding electrodes 40 and to the FC-BGA substrate 11 via bonding electrodes 14. In other words, the multilayer wiring board 12 is an interposer that mediates the bonding between the functional device 20 and the FC-BGA substrate 11. The thickness of the multilayer wiring board 12 is, for example, in the range of 10 μm to 300 μm. The multilayer wiring board 12 will be described in detail later.

[0047] The bonding electrodes 14 are arranged between the multilayer wiring board 12 and the functional device 20. The pitch of the bonding electrodes 14 is wider than that of the bonding electrodes 40 and narrower than that of the bonding conductors 115 located on the underside of the FC-BGA substrate 11. The bonding electrodes 14 are made of, for example, solder.

[0048] The sealing resin layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring board 12. The sealing resin layer is also called the underfill layer. The sealing resin layer 13 fixes the second wiring board 12 to the FC-BGA substrate 11.

[0049] The multilayer wiring board 12 will be described in more detail with reference to Figures 2 and 3. Figure 2 is a schematic cross-sectional view showing the multilayer wiring board 12 contained in the packaged device 1 shown in Figure 1. Figure 3 is an enlarged cross-sectional view showing a portion of the multilayer wiring board 12 shown in Figure 2.

[0050] The multilayer wiring board 12 shown in Figures 2 and 3 includes, as shown in Figure 2, two or more layers 126, an insulating resin layer 124, an insulating resin layer 123, a conductor layer 122, an adhesion layer 127a, a seed layer 127b, a conductor layer 129, an insulating resin layer 130, and a surface treatment layer 131.

[0051] Two or more layers 126 are stacked on top of each other. In this case, two layers 126 are stacked. The number of layers 126 may be three or more.

[0052] Each of these layers 126 includes an insulating resin layer 1263, a conductive layer 1262, a first metal-containing layer 1261a, and a second metal-containing layer 1261b.

[0053] The insulating resin layer 1263 is formed integrally, for example, in the thickness direction. Preferably, the insulating resin layer 1263 is made of an insulating resin that does not contain fillers.

[0054] As shown in Figures 2 and 3, the insulating resin layer 1263 has a first surface S1 and a second surface S2 which is its back surface. The insulating resin layer 1263 is provided with a plurality of first recesses R1, a plurality of grooves G, and a plurality of second recesses R2.

[0055] The first recess R1 is open on the first surface S1. The first recess R1 is a land recess that is embedded in the land portion 1262L, which will be described later.

[0056] The first recesses R1 have equal depths. The depth of the first recesses R1 is less than the thickness of the insulating resin layer 1263.

[0057] One or more of the first recesses R1 are in communication with one of the grooves G. In addition, one or more of the first recesses R1 are in communication with a second recess R2 in the insulating resin layer 1263 on which the first recesses R1 are provided.

[0058] The first recess R1 has an opening, side walls, and a bottom surface. The bottom surface of the first recess R1 is a plane perpendicular to the thickness direction. In one example, the first recess R1 has a circular bottom surface, and the bottom surface of the first recess R1 that communicates with the second recess R2 has a circular opening.

[0059] The first recess R1 has a shape in which the dimension perpendicular to the thickness direction gradually increases from the opening towards the bottom surface. That is, the cross section perpendicular to the thickness direction of the first recess R1 is inversely tapered. In one example, the first recess R1 has a frustoconical shape. The cross section parallel to the thickness direction of the first recess R1 may be rectangular. That is, the first recess R1 may have a prism or cylindrical shape with its height direction parallel to the thickness direction.

[0060] The groove G is open on the first surface S1. The groove G is embedded in the wiring section 1262W, which will be described later. The depth of the groove G is equal to the depth of the first recess R1.

[0061] The groove G has an opening, side walls, and a bottom surface. The bottom surface of the groove G is a plane perpendicular to the thickness direction.

[0062] The groove G has a shape in which its width gradually widens from the opening towards the bottom surface. That is, in this case, the groove G has an inverse tapered cross-section perpendicular to the longitudinal direction. The groove G may also have a rectangular cross-section perpendicular to the longitudinal direction.

[0063] The second recess R2 is open on the second surface S2. The second recess R2 is a via recess embedded in the via section 1262V, which will be described later.

[0064] The second recess R2 is in communication with one or more of the first recess R1. Specifically, each of the second recess R2 is in communication with any of the first recess R1.

[0065] The second recess R2 has an opening and a side wall. The second recess R2 communicates with the first recess R1 at its bottom. The orthogonal projection of the second recess R2 onto a plane perpendicular to the thickness direction is surrounded by the contour of the orthogonal projection of the bottom surface of the first recess R1, which communicates with the second recess R2, onto the plane beyond it.

[0066] The second recess R2 has a shape in which the dimension perpendicular to the thickness direction gradually increases from the opening to the bottom. That is, the second recess R2 has an inverse tapered cross-section perpendicular to the thickness direction. For example, the second recess R2 has a frustoconical shape. The second recess R2 may also have a rectangular cross-section parallel to the thickness direction. That is, the second recess R2 may have a prism or cylindrical shape with its height direction parallel to the thickness direction. The first recess R1, groove G, and second recess R2 will be explained in more detail later.

[0067] The conductor layer 1262 includes land portions 1262L and wiring portions 1262W that embed the first recess R1 and groove G of the insulating resin layer 1263, respectively, and via portions 1262V that protrude from the first surface S1 at the position of the land portion 1262L. In each conductor layer 1262, each via portion 1262V is formed integrally with one of the land portions 1262L included in that conductor layer 1262. The via portion 1262V of each conductor layer 1262 embeds the second recess R2 of the insulating resin layer 1263, in which the first recess R1 and groove G are embedded by the land portion 1262L and wiring portion 1262W of that conductor layer 1262, and the other insulating resin layer adjacent to it on the first surface S1 side.

[0068] The conductive layer 1262 is made of a metal or alloy such as copper. The conductive layer 1262 may have a single-layer structure or a multi-layer structure. For example, the conductive layer 1262 is made of copper.

[0069] As shown in Figures 2 and 3, the first metal-containing layer 1261a covers the first surface S1 side of the wiring portion 1262W without covering the sides of the wiring portion 1262W. Furthermore, the first metal-containing layer 1261a covers the first surface S1 side of the land portion 1262L without covering the sides of the land portion 1262L. Also, the first metal-containing layer 1261a covers the side and bottom surfaces of the via portion 1262V in Figure 2.

[0070] The first metal-containing layer 1261a is an adhesion layer or seed adhesion layer that improves the adhesion of the second metal-containing layer 1261b to the dummy layer 125 and the insulating resin layer 124, which will be described later, and makes it difficult for the second metal-containing layer 1261b to peel off. The first metal-containing layer 1261a is also a barrier layer that makes it difficult for metal to diffuse from the conductor layer 1262 to the insulating resin layer 1263. For example, the first metal-containing layer 1261a is a titanium-containing layer such as a titanium oxide layer.

[0071] The second metal-containing layer 1261b includes a portion interposed between the first metal-containing layer 1261a and the wiring portion 1262W, and a portion covering the side surface of the wiring portion 1262W. Furthermore, the second metal-containing layer 1261b includes a portion interposed between the first metal-containing layer 1261a and the land portion 1262L, and a portion covering the side surface of the land portion 1262L. In addition, the second metal-containing layer 1261b includes a portion interposed between the first metal-containing layer 1261a and the via portion 1262V. The second metal-containing layer 1261b is a seed layer that plays the role of a power supply layer in the electroplating film formation of the conductor layer 1262.

[0072] The second metal-containing layer 1261b is made of a different metal material than the first metal-containing layer 1261a. The second metal-containing layer 1261b may be made of the same material as the conductive layer 1262. Alternatively, the second metal-containing layer 1261b may be made of a metal material with a lower ionization tendency compared to the conductive layer 1262. The second metal-containing layer 1261b may contain copper, for example. When the second metal-containing layer 1261b contains copper, delamination is less likely to occur between the insulating resin layer 1263 and the second metal-containing layer 1261b. Even if the two layers stacked on top of each other are made of the same material, the interface between them can be confirmed by observing a cross-section parallel to the stacking direction, for example, with a scanning electron microscope.

[0073] In the second metal-containing layer 1261b, the portion covering the side surface of the wiring portion 1262W preferably has an arithmetic mean roughness Ra of 10 nm or less. When the arithmetic mean roughness Ra of the above portion is 10 nm or less, the distance electrons travel through the surface of the above portion is small, and therefore high transmission characteristics can be achieved. The arithmetic mean roughness Ra is obtained by a method compliant with JIS B 0601:2013.

[0074] As shown in Figure 2, the insulating resin layer 124 is provided on one main surface of the multilayer wiring structure consisting of layer 126. The material of the insulating resin layer 124 may be the same as or different from the material of the insulating resin layer 1263.

[0075] The insulating resin layer 124 has through holes at the location of via portions 1262V of the insulating resin layer 1263 included in the adjacent layer 126. The through holes in the insulating resin layer 124 are filled by the via portions 1262V of the insulating resin layer 1263 included in the adjacent layer 126.

[0076] The through-holes in the insulating resin layer 124 are recesses that open on the layer 126 side. Here, the dimensions perpendicular to the thickness direction gradually increase from bottom to top. That is, the recesses in the insulating resin layer 124 have an inverse tapered cross-section perpendicular to the thickness direction. For example, these through-holes have a frustoconical shape. These through-holes may also have a rectangular cross-section parallel to the thickness direction. That is, these through-holes may have a prism or cylindrical shape with a height direction parallel to the thickness direction.

[0077] The insulating resin layer 123 is provided on the insulating resin layer 124. The material of the insulating resin layer 123 may be the same as or different from the material of the insulating resin layers 124 and 1263. The insulating resin layer 123 has through holes at the same locations as the through holes in the insulating resin layer 124.

[0078] The conductor layer 122 fills the through-holes in the insulating resin layer 123. The conductor layer 122 is an electrode for bonding the multilayer wiring board 12 and the functional device 20. The conductor layer 122 is made of, for example, copper.

[0079] The conductor layer 129 fills the second recess R2 of the insulating resin layer 1263 contained in the layer 126 located above it, and covers the opening of the second recess R2 and the surrounding area of ​​the second surface S2 of the insulating resin layer 1263. The conductor layer 129 is made of a metal such as copper or an alloy.

[0080] The adhesion layer 127a includes a portion that covers the inner surface of the second recess R2 of the insulating resin layer 1263 contained in the upper layer 126, and a portion that covers the area around the opening of the second recess R2 on the second surface S2 of the insulating resin layer 1263. The adhesion layer 127a is a layer that improves the adhesion of the seed layer 127b to the insulating resin layer 1263, making it less likely for the seed layer 127b to peel off.

[0081] The seed layer 127b is provided on the adhesion layer 127a. The seed layer 127b plays the role of a power supply layer in the electroplating film formation of the conductor layer 129.

[0082] The insulating resin layer 130 is provided on top of the insulating resin layer 1263 and the conductor layer 129, which are contained in the layer 126 located above it. The insulating resin layer 130 has through holes at the location of the conductor layer 129.

[0083] The surface treatment layer 131 is provided on the portion of the conductor layer 129 that is exposed within the through-holes of the insulating resin layer 130. The surface treatment layer 131 is provided to prevent oxidation of the surface of the conductor layer 129 and to improve its wettability to solder.

[0084] As shown in Figure 2, in each of the two or more adjacent layers 126, for example, the insulating resin layers 1263 are in contact with each other.

[0085] In Figure 3, length t1 is the distance between the first surface S1 of one adjacent layer 126 and the bottom surface of the groove G contained in the other layer 126. Length t2 is the depth of the groove G in layer 126. Length t3 is the distance between the bottom surface of the groove G contained in layer 126 and the second surface S2 of this layer 126. Length t4 is the width of the bottom surface of the groove G contained in layer 126. Length t5 is the distance between the bottom surfaces of adjacent grooves G in the width direction of the groove G.

[0086] Figure 4 is an enlarged cross-sectional view showing a portion of a multilayer wiring board 12 according to another embodiment of the present invention. The multilayer wiring board 12 according to this embodiment is the same as the multilayer wiring board 12 described above, except that the width D1 shown in Figure 4 is smaller than the width D2 shown in Figure 4. Width D1 is the width of the portion of the first metal-containing layer 1261a that covers the surface of the wiring portion 1262W on the first surface S1 side. In other words, width D1 is the width of the first metal-containing layer 1261a in a direction perpendicular to the length direction of the wiring portion 1262W and perpendicular to the thickness direction of the wiring portion 1262W. Width D2 is the width of the region of the surface of the second metal-containing layer 1261b that faces the plane including the first surface S1.

[0087] When the width D1 is smaller than the width D2, the contact area between the insulating resin layer 1263 and the second metal-containing layer 1261b is larger, making it less likely for delamination to occur between the insulating resin layer 1263 and the second metal-containing layer 1261b.

[0088] <Manufacturing method> The multilayer wiring board 12 included in this packaged device 1 can be manufactured, for example, by the following method.

[0089] Figures 5 to 26 are schematic cross-sectional views illustrating a method for manufacturing a multilayer wiring board according to one embodiment of the present invention.

[0090] In this method, first, a release layer 3 is formed on one side of the support 2, as shown in Figure 5.

[0091] Since light may be irradiated onto the release layer 3 through the support 2, it is advantageous for the support 2 to be translucent. For example, a glass plate can be used as the support 2. A rectangular glass plate is suitable for large-scale applications. Furthermore, glass plates can achieve excellent flatness and high rigidity. Therefore, a glass plate as the support 2 is suitable for forming fine patterns on it.

[0092] Furthermore, glass plates have a low coefficient of thermal expansion (CTE) and are less prone to distortion, making them excellent for ensuring pattern placement accuracy and flatness. When using a glass plate as the support 2, a thicker glass plate is preferable from the viewpoint of suppressing warping during the manufacturing process, for example, 0.5 mm or more, preferably 1.2 mm or more.

[0093] The CTE of the glass plate is preferably 3 ppm to 16 ppm, and more preferably about 10 ppm from the viewpoint of consistency with the CTE of the FC-BGA substrate 11 and the functional device 20.

[0094] Examples of glass used include quartz glass, borosilicate glass, alkali-free glass, soda-lime glass, or sapphire glass.

[0095] On the other hand, if the support 2 does not require light transmittance when peeling it off, such as by using a heat-foaming resin for the release layer 3, then a material with low distortion, such as metal or ceramics, can be used for the support 2.

[0096] As an example, the release layer 3 is made of a resin that absorbs ultraviolet light (UV light) and can be peeled off, and the support 2 is a glass plate.

[0097] The release layer 3 may be a resin that becomes removable by absorbing light such as UV light, generating heat or undergoing a change in quality, or a resin that becomes removable by foaming due to heat. The material of the release layer 3 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, as well as inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. The release layer 3 may further contain additives such as photodegradation accelerators, light absorbers, sensitizers, and fillers.

[0098] The release layer 3 may have a single-layer structure or a multilayer structure. Furthermore, for example, a protective layer may be provided on the release layer 3 for the purpose of protecting the multilayer wiring structure formed on the support 2, and a further layer may be provided between the support 2 and the release layer 3 to improve their adhesion. Additionally, a laser light reflective layer or a metal layer may be further provided between the release layer 3 and the multilayer wiring structure.

[0099] Furthermore, if the release layer 3 is made of a resin that can be peeled off by light such as UV light, for example, laser light, then if the support 2 is translucent, the release layer 3 may be irradiated with light through the support 2.

[0100] Next, in a vacuum, the adhesion layer 4a and seed layer 4b are formed as shown in Figure 6. The adhesion layer 4a is a layer that improves the adhesion of the seed layer 4b to the release layer 3 and prevents the seed layer 4b from peeling off in subsequent processes. The seed layer 4b also plays a role as a power supply layer in the electroplating process for forming the conductor layer 122.

[0101] The adhesion layer 4a and seed layer 4b can be formed, for example, by sputtering or vapor deposition. Suitable materials for the adhesion layer 4a and seed layer 4b include, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), ZnO, PZT (Lead Zirconate Titanate), TiN, Cu3N4, Cu alloys, or combinations thereof. Here, as an example, considering electrical properties, ease of manufacture, and cost, a titanium layer and a copper layer are used for the adhesion layer 4a and seed layer 4b, respectively, and these are formed by sputtering.

[0102] The total film thickness of the adhesion layer 4a and the seed layer 4b is preferably 1 μm or less. Here, as an example, a titanium layer with a thickness of 50 nm is formed as the adhesion layer 4a, and a copper layer with a thickness of 300 nm is formed as the seed layer 4b.

[0103] Next, as shown in Figure 7, a resist layer 121 is formed on the seed layer 4b. The resist layer 121 is made of a photosensitive resin. As the photosensitive resin, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified version thereof can be used. The photosensitive resin may be in liquid form or in film form.

[0104] When a liquid photosensitive resin is used as the material for the resist layer 121, the resist layer 121 can be formed on the seed layer 4b by any of the following methods: slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like resist is used as the resist layer 121, the resist layer 121 can be provided on the seed layer 4b by any of the following methods: lamination, vacuum lamination, vacuum pressing, etc.

[0105] Next, through-holes are formed in the resist layer 121 by photolithography. The planar shape of the through-holes is set according to the pitch and shape of the bonding electrodes of the functional device 20. Here, as an example, the through-holes are assumed to have a circular opening with a diameter of 25 μm and a pitch of 55 μm. Here, planar view means observing the object in the thickness direction, that is, observing the orthogonal projection of the object onto a plane perpendicular to the thickness direction.

[0106] The thickness of the resist layer 121 is set according to the thickness of the conductive layer 122 to be formed next. Here, as an example, the thickness of the resist layer 121 is set to 8 μm.

[0107] Furthermore, after forming these through holes, plasma treatment may be performed to remove residues from the developing process.

[0108] Next, as shown in Figure 8, a conductive layer 122 is formed on the seed layer 4b by electroplating. The conductive layer 122 constitutes an electrode for bonding with the functional device 20. Examples of electroplating methods for forming the conductive layer 122 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. Among these, electrolytic copper plating is preferable because it is simple, inexpensive, and can achieve good electrical conductivity.

[0109] As described above, the conductive layer 122 serves as an electrode for bonding with the functional device 20. Therefore, the thickness of the conductive layer 122 is preferably 1 μm or more from the viewpoint of solder bonding, and preferably 30 μm or less from the viewpoint of productivity.

[0110] Next, as shown in Figure 9, the resist layer 121 is removed. The resist layer 121 can be removed, for example, by dry etching, or by dissolving or peeling it off by immersion in an alkaline solution or solvent.

[0111] Next, as shown in Figure 10, an insulating resin layer 123 is formed so as to embed the conductive layer 122. The material of the insulating resin layer 123 may be a photosensitive resin or a non-photosensitive resin. The material of the insulating resin layer 123 may be the same as or different from the material of the insulating resin layers 124, 130, and 1263 described later.

[0112] Next, as shown in Figure 11, the upper surface of the conductor layer 122 is exposed by physical polishing, or by physical polishing and chemical mechanical polishing (CMP). Note that the structure obtained in this way can also be obtained by the damascene method.

[0113] Next, as shown in Figure 12, an insulating resin layer 124 having through holes at the position of the conductor layer 122 is provided on the conductor layer 122 and the insulating resin layer 123. The through holes in the insulating resin layer 124 are second recesses R2 that open on the second surface of the insulating resin layer 124, in this case, on the upper surface of the insulating resin layer 124. The second recess R2 may be formed to have a rectangular cross-section, but it is preferable to form it in a forward tapered shape. Forming it in a forward tapered shape makes it easier to form the first metal-containing layer 1261a and the second metal-containing layer 1261b without creating discontinuities within the second recess R2.

[0114] The insulating resin layer 124 is made of, for example, a photosensitive resin. As this photosensitive resin, for example, the same material as described above for the resist layer 121 can be used. Furthermore, the insulating resin layer 124 having through holes can be formed, for example, by the same method as described above for the resist layer 121.

[0115] Alternatively, the insulating resin layer 124 is made of a non-photosensitive resin. Examples of non-photosensitive resins include polyimide resin, benzocyclobutene resin, epoxy resin, or modified versions thereof. Non-photosensitive resins such as polyimide offer excellent insulating and mechanical properties, as well as high heat resistance. Furthermore, inorganic particles such as silica, alumina, and zirconia may be added to the non-photosensitive resin as fillers. Here, as an example, a non-photosensitive polyimide resin is used as the non-photosensitive resin.

[0116] The non-photosensitive resin may be in liquid form or in film form.

[0117] When using a liquid non-photosensitive resin, the insulating resin layer 124 can be formed by a method selected from, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.

[0118] If a film-like non-photosensitive resin is provided as the insulating resin layer 124, lamination, vacuum lamination, vacuum pressing, etc., can be applied.

[0119] Here, as an example, a photosensitive epoxy resin is applied to the conductive layer 122 and the insulating resin layer 123 by spin coating. The photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little during curing, which is advantageous for subsequent fine pattern formation. Also, as an example, the insulating resin layer 124 is formed to a thickness of 2 μm.

[0120] Furthermore, after forming the insulating resin layer 124, the surface may be subjected to physical polishing, or to physical polishing and polishing such as CMP, in order to flatten it. If a non-photosensitive resin is used as the material for the insulating resin layer 124, through holes can be formed, for example, by laser irradiation.

[0121] Next, as shown in Figure 13, a dummy layer 125 is formed on the insulating resin layer 124 and the conductor layer 122, having grooves G' and through holes R1', one or more of which communicate with the second recess R2. The grooves G' and through holes R1' of the dummy layer 125 correspond to the grooves G and the first recess R1 of the insulating resin layer 1263, respectively.

[0122] The dummy layer 125 is made of a photosensitive resin. For example, the same material as described above for the resist layer 121 can be used as this photosensitive resin. Furthermore, the dummy layer 125 having grooves G' and through holes R1' can be formed, for example, by the same method as described above for the resist layer 121.

[0123] The through-hole R1' in the dummy layer 125 is formed such that its opening diameter on its upper surface is larger than that of the through-hole in the insulating resin layer 124. Furthermore, the through-hole R1' is formed in a forward tapered shape. The groove G' is also formed such that its cross-section perpendicular to its length has a forward tapered shape.

[0124] The grooves G' and through holes R1' may be formed to have a rectangular cross-section, but forming them in a forward tapered shape makes it easier to form the first metal-containing layer 1261a and the second metal-containing layer 1261b without creating discontinuities within the grooves G' and through holes R1'.

[0125] Next, in a vacuum, as shown in Figure 14, a first metal-containing layer 1261a is formed that covers the upper surface of the dummy layer 125, the inner surface of the second recess R2, the inner surface of the groove G', and the inner surface of the through hole R1'. Subsequently, a second metal-containing layer 1261b, made of a different metal material than the first metal-containing layer 1261a, is formed on the first metal-containing layer 1261a.

[0126] The first metal-containing layer 1261a and the second metal-containing layer 1261b are a seed adhesion layer (or adhesion layer) and a seed layer, respectively. The first metal-containing layer 1261a and the second metal-containing layer 1261b can be made from the same materials as described above for the adhesion layer 4a and the seed layer 4b, respectively. Furthermore, the first metal-containing layer 1261a and the second metal-containing layer 1261b can be formed from the same materials as described above for the adhesion layer 4a and the seed layer 4b, respectively.

[0127] The material of the second metal-containing layer 1261b is preferably the same as the material of the conductor layer 1262, or a metallic material with a lower ionization tendency than the material of the conductor layer 1262. When the material of the second metal-containing layer 1261b has a lower ionization tendency than the material of the conductor layer 1262, the second metal-containing layer 1261b is more likely to prevent the diffusion of metal from the conductor layer 1262 to the insulating resin layer 1263.

[0128] The sum of the thicknesses of the first metal-containing layer 1261a and the second metal-containing layer 1261b is preferably 1 μm or less. In this case, it is preferable as a power supply layer for electroplating.

[0129] The thickness of the first metal-containing layer 1261a is preferably in the range of 10 nm to 100 nm, and more preferably in the range of 30 nm to 80 nm.

[0130] The thickness of the second metal-containing layer 1261b is preferably in the range of 40 nm to 400 nm, and more preferably in the range of 100 nm to 350 nm.

[0131] Here, as an example, considering electrical properties, ease of manufacturing, and cost, and furthermore, in order to improve the adhesion between the insulating resin layer 1263 and the second metal-containing layer 1261b, and to prevent the diffusion of the conductor layer 1262 material, such as copper, a titanium-containing layer is adopted as the first metal-containing layer 1261a. Also, considering electrical properties, ease of manufacturing, and cost, a copper-containing layer is adopted as the second metal-containing layer 1261b. The first metal-containing layer 1261a and the second metal-containing layer 1261b are formed sequentially by sputtering. The thickness of the first metal-containing layer 1261a is 50 nm, and the thickness of the second metal-containing layer 1261b is 300 nm.

[0132] Furthermore, the material of the first metal-containing layer 1261a may be other than titanium, as long as it has the same function as the material of the second metal-containing layer 1261b, such as preventing the diffusion of copper. In addition, a layer made of a metal material different from both the material of the first metal-containing layer 1261a and the material of the second metal-containing layer 1261b may be provided between the first metal-containing layer 1261a and the second metal-containing layer 1261b.

[0133] Next, as shown in Figure 15, a conductive layer 1262' is formed on the second metal-containing layer 1261b. The conductive layer 1262' is formed to fill the second recess R2, groove G', and through hole R1'. The same material as described above for the conductive layer 122 can be used for the conductive layer 1262'. The conductive layer 1262' can also be formed in the same manner as described above for the conductive layer 122. Here, as an example, the conductive layer 1262 is assumed to be a copper layer formed by electroplating.

[0134] Next, as shown in Figure 16, the conductive layer 1262', the first metal-containing layer 1261a, and the second metal-containing layer 1261b are subjected to physical polishing and polishing such as CMP to remove the portions of the conductive layer 1262', the first metal-containing layer 1261a, and the second metal-containing layer 1261b that are located outside the second recess R2, groove G', or through hole R1'. In addition, the portion near the upper surface of the dummy layer 125 may also be removed during this polishing process.

[0135] Of the conductive layer 1262' shown in Figure 15, the portion remaining after the polishing described above is the conductive layer 1262 shown in Figure 16. In this manner, the portion of the conductor layer 1262 in which the second recess R2 is embedded, the portion in which the through hole R1' is embedded, and the portion in which the groove G' is embedded are obtained as via portion 1262V, land portion 1262L, and wiring portion 1262W, respectively.

[0136] Next, the dummy layer 125 is removed, as shown in Figure 17. The dummy layer 125 can be removed by dry etching or by immersion in an alkaline solution or solvent.

[0137] Next, as shown in Figure 18, the exposed portion of the first metal-containing layer 1261a in the structure shown in Figure 17 is removed with an etching agent. By removing the exposed portion of the first metal-containing layer 1261a, the second metal-containing layer 1261b, which covers the side surface of the land portion 1262L and the side surface of the wiring portion 1262W, is exposed.

[0138] As the etching agent, a chemical solution is used that selectively etches the first metal-containing layer 1261a against the second metal-containing layer 1261b. This etching maintains the smoothness of the portion of the second metal-containing layer 1261b that covers the sides of the wiring portion 1262W and the land portion 1262L.

[0139] For example, after etching, the portion of the second metal-containing layer 1261b that covers the sides of the wiring portion 1262W and the land portion 1262L has an arithmetic mean roughness Ra of 10 nm or less.

[0140] Note that the width D1, as explained with reference to Figure 4, may be smaller than the width D2. When widths D1 and D2 are approximately the same, if the adhesion between the insulating resin layer 1263 and the second metal-containing layer 1261b is insufficient, the contact area between the insulating resin layer 1263 and the second metal-containing layer 1261b can be increased by making the width D1 smaller than the width D2. This improves the adhesion between the insulating resin layer 1263 and the second metal-containing layer 1261b.

[0141] Furthermore, in order to improve the adhesion between the wiring section 1262W, the first metal-containing layer 1261a, and the second metal-containing layer 1261b and the insulating resin layer 1263, the exposed portion of the first metal-containing layer 1261a may be removed, and then the wiring section 1262W, the first metal-containing layer 1261a, and the second metal-containing layer 1261b may be treated with a silane coupling agent.

[0142] Next, as shown in Figure 19, an insulating resin layer 1263 is provided that covers the conductor layer 1262 and fills the gap between the land portion 1262L and the wiring portion 1262W. A through hole is formed in the insulating resin layer 1263 as the second recess R2. The lower and upper surfaces of the insulating resin layer 1263 are the first surface S1 and the second surface S2, respectively. The recess in the insulating resin layer 1263 that is filled by the land portion 1262L is the first recess R1 described above. The recess in the insulating resin layer 1263 that is filled by the wiring portion 1262W is the groove G described above.

[0143] The insulating resin layer 1263 is made of a photosensitive resin or a non-photosensitive resin. For example, the same materials as those described above for the resist layer 121 and the insulating resin layer 124 can be used as the photosensitive or non-photosensitive resin. Furthermore, the insulating resin layer 1263 having the first recess R1, the second recess R2 and the groove G can be formed, for example, by the same method as described above for the resist layer 121 and the insulating resin layer 124.

[0144] The thickness of the insulating resin layer 1263 is, for example, in the range of 1.5 μm to 2 μm. Here, as an example, the insulating resin layer 1263 is formed to a thickness of 2 μm.

[0145] In this way, a layer 126 is obtained that includes a first metal-containing layer 1261a, a second metal-containing layer 1261b, a conductor layer 1262, and an insulating resin layer 1263.

[0146] Next, the sequence consisting of the steps described with reference to Figures 13 to 19 is repeated. This yields the multilayer wiring structure shown in Figure 20. That is, a multilayer wiring structure containing two layers 126 is obtained. If the above sequence is repeated two or more times, the number of layers 126 in the multilayer wiring structure can be made three or more.

[0147] Next, as shown in Figure 21, an adhesion layer 127a is formed that covers the upper surface of the insulating resin layer 1263 contained in the upper layer 126 and the inner surface of its second recess R2. Subsequently, a seed layer 127b made of a metal material different from the material of the adhesion layer 127a is formed on the adhesion layer 127a. Preferably, the seed layer 127b is made of the same material as the conductor layer 129 or a metal material with a lower ionization tendency compared to the material of the conductor layer 129.

[0148] The same materials as those described above for the adhesion layer 4a and seed layer 4b can be used for the adhesion layer 127a and seed layer 127b, respectively. Furthermore, the adhesion layer 127a and seed layer 127b can be formed using the same method as described above for the adhesion layer 4a and seed layer 4b, respectively.

[0149] Next, a resist layer 128 having through holes is formed on the seed layer 127b. Each of the through holes in the resist layer 128 communicates with a second recess R2 provided in the insulating resin layer 1263 contained in the upper layer 126.

[0150] The resist layer 128 is made of a photosensitive resin. The same material as described above for the resist layer 121 can be used for the resist layer 128. Furthermore, the resist layer 128 can be formed by the same method as described above for the resist layer 121.

[0151] Next, as shown in Figure 22, a conductor layer 129 is formed on the seed layer 127b. The same material as described above for the conductor layer 122 can be used for the conductor layer 129. The conductor layer 129 can be formed in the same manner as described above for the conductor layer 122.

[0152] Next, as shown in Figure 23, the resist layer 128 is removed. The resist layer 128 can be removed in the same manner as described above for the resist layer 121.

[0153] Next, as shown in Figure 24, the exposed portions of the adhesion layer 127a and seed layer 127b are removed. The adhesion layer 127a and seed layer 127b can be removed, for example, by immersion in a chemical solution. As the chemical solution, for example, a solution containing hydrogen peroxide can be used.

[0154] Next, as shown in Figure 25, an insulating resin layer 130 is formed on the insulating resin layer 1263 and the conductor layer 129. The insulating resin layer 130 has through holes at the positions of the conductor layer 129. The insulating resin layer 130 can be formed, for example, by providing solder resist on the insulating resin layer 1263 and the conductor layer 129, and then subjecting it to exposure and development. The insulating layer obtained from the solder resist is also called the solder resist layer.

[0155] For solder resist materials, insulating resins such as epoxy resin and acrylic resin can be used. Here, as an example, a photosensitive epoxy resin containing fillers will be used as the solder resist.

[0156] Next, as shown in Figure 26, a surface treatment layer 131 is provided on the conductive layer 129. The surface treatment layer 131 is provided for the purpose of preventing oxidation of the surface of the conductive layer 129 and improving its wettability to solder. Here, as an example, an electroless Ni / Pd / Au plating layer is formed as the surface treatment layer 131.

[0157] As the surface treatment layer 131, an OSP (Organic Solderability Preservative) film, i.e., a surface treatment layer made of a water-soluble preflux, may be formed. Alternatively, as the surface treatment layer 131, an electroless tin plating or an electroless Ni / Au plating layer may be formed.

[0158] Next, a bonding conductor 132 is formed on the surface treatment layer 131. The bonding conductor 132 is, for example, a metal bump such as a solder bump. The bonding conductor 132 can be formed by, for example, placing solder material such as solder balls on the surface treatment layer 131, melting them, and then cooling them to fix them to the surface treatment layer 131.

[0159] In this way, a multilayer wiring board 12 supported by the support 2, i.e., a multilayer wiring board with a support, is obtained.

[0160] Using the multilayer wiring board with support obtained in this way, the packaged device 1 shown in Figure 1 can be manufactured, for example, by the following method.

[0161] Figure 27 is a schematic cross-sectional view showing one step in the manufacturing method of a packaged device according to one embodiment of the present invention. Figure 28 is a schematic cross-sectional view showing another step in the manufacturing method of a packaged device according to one embodiment of the present invention. Figure 29 is a schematic cross-sectional view showing yet another step in the manufacturing method of a packaged device according to one embodiment of the present invention.

[0162] First, as shown in Figure 27, the multilayer wiring board 12 supported by the support 2 and the FC-BGA board 11 are joined together. Next, the joint between them is sealed with a sealing resin layer 13.

[0163] As the material for the sealing resin layer 13, for example, a mixture of resin and filler can be used. As the resin, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins can be used. As the filler, for example, one of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide, or two or more of these can be used. The sealing resin layer 13 can be formed, for example, by filling a liquid material between the FC-BGA substrate 11 and the multilayer wiring substrate 12.

[0164] In this way, a composite wiring board 10 including the FC-BGA substrate 11 and the multilayer wiring board 12 is obtained. At this point, the support 2 remains on the multilayer wiring board 12.

[0165] Next, as shown in Figure 28, the release layer 3 is irradiated with laser light 50 from the support 2 side, and as shown in Figure 29, the support 2 and the composite wiring board 10 are separated from each other. As described above, the material of the release layer 3 is a resin that absorbs ultraviolet light (UV light) and can be peeled off, so it is possible to peel the support 2 from the composite wiring board 10 by irradiation with laser light 50. If the release layer 3 remains on the composite wiring board 10, it is removed by etching, for example. The adhesion layer 4a and seed layer 4b are also removed by etching, for example.

[0166] Subsequently, the functional device 20 shown in Figure 1 is bonded to the composite wiring board 10. Prior to bonding the functional device 20, surface treatment layers such as an electroless Ni / Pd / Au plating layer, an OSP film, an electroless tin plating layer, and an electroless Ni / Au plating layer may be provided on the conductive layer 122 exposed on the surface for the purpose of preventing oxidation and improving wettability to solder.

[0167] Next, these joints are sealed with a sealing resin layer 30. For example, the material used for the sealing resin layer 30 can be one of those exemplified for the sealing resin layer 13. The sealing resin layer 30 can be formed, for example, by the same method as described above for the sealing resin layer 13. As described above, the packaged device 1 shown in Figure 1 is completed.

[0168] In the method described above, the functional device 20 is bonded to the multilayer wiring board 12 after it has been bonded to the FC-BGA board 11. Alternatively, the functional device 20 may be bonded to the multilayer wiring board 12 first, and then the multilayer wiring board 12 may be bonded to the FC-BGA board 11.

[0169] <Effects> Interposers obtained through silicon interposer technology, so-called silicon interposers, are manufactured using silicon wafers and semiconductor front-end processing equipment. Silicon wafers have limitations in shape and size, and the number of interposers that can be manufactured from a single wafer is not necessarily large. Furthermore, the manufacturing equipment is expensive. Therefore, silicon interposers are expensive. In addition, because silicon wafers are semiconductors, there is a problem that the transmission characteristics deteriorate when silicon interposers are used.

[0170] Silicon wafers are not required for the manufacture of the multilayer wiring board 12 described above. Furthermore, in the multilayer wiring board 12, many of the insulating layers can be made of insulating resin layers. Therefore, the multilayer wiring board 12 described above can be manufactured with inexpensive materials and equipment, enabling cost reduction and achieving excellent transmission characteristics.

[0171] The method of directly fabricating a multilayer wiring structure containing a conductor layer with a fine wiring pattern onto an FC-BGA substrate results in less degradation of transmission characteristics compared to silicon interposers. However, this method has challenges, including the manufacturing yield of the FC-BGA substrate itself and the difficulty of forming a multilayer wiring structure containing a conductor layer with a fine wiring pattern on a core layer such as a glass epoxy substrate, resulting in an overall low manufacturing yield. Furthermore, it is difficult to achieve high symmetry with respect to a plane that bisects the thickness of the FC-BGA substrate. Therefore, such FC-BGA substrates are prone to warping and distortion during heating.

[0172] In the manufacturing of the composite wiring board 10 and packaged device 1 described above, a multilayer wiring board 12 is manufactured separately from the FC-BGA substrate 11, and these are joined together. The multilayer wiring structure, which includes a conductor layer 1262 having a fine wiring pattern, is not fabricated on the FC-BGA substrate 11, but on the multilayer wiring board 12. Therefore, the composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

[0173] Furthermore, in the manufacturing of the composite wiring board 10, the multilayer wiring structure including the conductor layer 1262 having a fine wiring pattern is formed on a support 2 rather than on a core layer such as a glass epoxy substrate. Since a support 2 with excellent smoothness can be used, the fine patterns formed on it can be formed with high shape accuracy. For these reasons as well, the composite wiring board 10 and the packaged device 1 can be manufactured with a high yield.

[0174] Furthermore, in the above-described composite wiring board 10 and packaged device 1, it is easy to achieve high symmetry with respect to a plane that bisects the thickness of the FC-BGA substrate 11, and it is also easy to achieve high symmetry with respect to a plane that bisects the thickness of the multilayer wiring board 12. Therefore, the above-described composite wiring board 10 and packaged device Option 1 is less prone to warping or distortion when heated.

[0175] Another method for forming fine wiring is the semi-additive method. In the semi-additive method, first, a substrate layer is prepared, and a first metal-containing layer and a second metal-containing layer are formed on the substrate layer. Next, a resist layer is formed in a pattern on the second metal-containing layer, and a conductor layer including the wiring portion is formed on the second metal-containing layer by electrolytic copper plating. Next, the resist is removed, and then the unnecessary first and second metal-containing layers are further removed. Specifically, after removing the resist, the parts of the first and second metal-containing layers that are not covered by the conductor layer are removed by etching. After that, the substrate layer and the conductor layer are covered with an insulating resin layer. In this way, fine wiring is formed on the substrate layer.

[0176] In this method, when etching away unwanted layers, the surface of the conductive layer is also etched. As a result, the surface of the conductive layer becomes rough. In this case, the arithmetic mean roughness Ra of the conductive layer surface is about 100 nm. When the surface of the conductive layer is rough in this way, especially when the surface of the wiring is rough, the distance that electrons travel across the surface is large, making it impossible to achieve high transmission characteristics.

[0177] On the other hand, according to the manufacturing method of the multilayer wiring board 12 described above, the side surface of the wiring portion 1262W is covered by the second metal-containing layer 1261b. Furthermore, according to the method described above, the top surface of the wiring portion and the portion of the second metal-containing layer 1261b that covers the side surface of the wiring portion 1262W are hardly etched. Therefore, the top surface of the wiring portion 1262W and the surface of the above portion of the second metal-containing layer 1261b are smooth. When the top surface of the wiring portion 1262W and the surface of the above portion are smooth, the distance that electrons travel through the surface of the top surface of the wiring portion 1262W and the surface of the above portion of the second metal-containing layer 1261b is small, making it possible to achieve high transmission characteristics.

[0178] Furthermore, in the manufacturing method of the multilayer wiring board 12 described above, if the step described with reference to Figure 18, namely the removal of the exposed portion of the first metal-containing layer 1261a, is omitted, the insulating resin layer 1263 will be in contact with the first metal-containing layer 1261a. For example, when a titanium layer and a copper layer are used as the first metal-containing layer 1261a and the second metal-containing layer 1261b, respectively, delamination may occur between the insulating resin layer 1263 and the titanium layer.

[0179] In contrast, according to the manufacturing method of the multilayer wiring board 12 described above, the insulating resin layer 1263 is in contact with the second metal-containing layer 1261b. When a titanium layer and a copper layer are used as the first metal-containing layer 1261a and the second metal-containing layer 1261b, respectively, delamination between the insulating resin layer 1263 and the copper layer is less likely to occur.

[0180] Furthermore, in the multilayer wiring board 12 described above, as shown in Figures 2 to 4, the first metal-containing layer 1261a covers the first surface S1 side of the wiring portion 1262W. Therefore, in two adjacent layers 126, diffusion of metal from the wiring portion 1262W contained in one layer 126 to the insulating resin layer 1263 contained in the other layer 126 is unlikely to occur. Thus, the multilayer wiring board 12 described above can achieve excellent insulation reliability.

[0181] Furthermore, in the multilayer wiring board 12 described above, as shown in Figures 2 to 4, the first metal-containing layer 1261a covers the first surface S1 side of the wiring portion 1262W without covering the sides of the wiring portion 1262W. For this reason, for example, if a material with lower conductivity than the material of the wiring portion 1262W is used as the material of the first metal-containing layer 1261a, the multilayer wiring board 12 described above can achieve a lower wiring resistivity than a multilayer wiring board equipped with a first metal-containing layer 1261a that further covers the sides of the wiring portion 1262W. [Examples]

[0182] Next, we will explain the effects and advantages of using the multilayer wiring board 12 and its manufacturing method described above.

[0183] (Examples) The multilayer wiring board 12, described with reference to Figures 2 and 3, was manufactured by the method described with reference to Figures 5 to 26. The lengths t1 and t3 of the multilayer wiring board 12 were set to 5 μm, and the lengths t2, t4, and t5 were set to 2 μm. The wiring length was also set to 2 mm.

[0184] (Comparative example) Figure 30 is a schematic cross-sectional view of the multilayer wiring board 12'. Figure 31 is an enlarged cross-sectional view of a portion of the multilayer wiring board 12' shown in Figure 30.

[0185] The multilayer wiring board 12' shown in Figures 30 and 31 is the same as the multilayer wiring board 12 in the embodiment, except for the following points.

[0186] In other words, the multilayer wiring board 12' includes layer 126' instead of layer 126. Each layer 126' includes an insulating resin layer 1263, a first metal-containing layer 1261a', a second metal-containing layer 1261b', and a conductor layer 1262'. Because the conventional semi-additive method was used to form the first metal-containing layer 1261a', the second metal-containing layer 1261b', and the conductor layer 1262', the sides of the wiring portion 1262W' are not covered by the second metal-containing layer 1261b'. Also, the cross-section of the wiring portion 1262W has a substantially rectangular shape. Except for these points, the multilayer wiring board 12' according to the comparative example is the same as the multilayer wiring board 12 according to the embodiment.

[0187] In Figure 31, length t1' is the distance between the first surface S1 of one layer 126' and the bottom surface of the groove contained in the other layer 126'. Length t2' is the depth of the groove in layer 126'. Length t3' is the shortest distance between the bottom surface of the groove contained in layer 126' and the second surface S2 of this layer 126'. Length t4' is the width of the bottom surface of the groove contained in layer 126'. Length t5' is the distance between the bottom surfaces of adjacent grooves in the width direction of the groove.

[0188] The lengths t1' and t3' of the multilayer wiring board 12' were set to 5 μm, and the lengths t2', t4', and t5' were set to 2 μm. The wiring length was also set to 2 mm.

[0189] (Confirmation of effects and benefits) The following evaluations were performed on the multilayer wiring board 12 according to the example and the multilayer wiring board 12' according to the comparative example.

[0190] (Evaluation method) S-parameters were measured using a microwave network analyzer measurement system. The transmission characteristic (S21) was measured as an S-parameter.

[0191] (Evaluation results) The multilayer wiring board 12 according to the embodiment showed an S21 of -1.3 dB at 10 GHz. On the other hand, the multilayer wiring board 12' according to the comparative example showed an S21 of -2 dB at 10 GHz. Thus, the multilayer wiring board 12 according to the embodiment showed high electrical characteristics. The invention described in the original claims is listed below. [1] It comprises two or more layers stacked on top of each other, and each of the two or more layers is An insulating resin layer having a first surface and a second surface which is its back surface, wherein the insulating resin layer has a groove that opens on the first surface, A conductor layer including a wiring portion in which the groove portion of the insulating resin layer is embedded, A first metal-containing layer that covers the first surface of the wiring portion without covering the side surface of the wiring portion, A second metal-containing layer comprising a portion interposed between the first metal-containing layer and the wiring portion, and a portion covering the side surface of the wiring portion, and made of a metal material different from the material of the first metal-containing layer. A multilayer wiring board containing this material. [2] The multilayer wiring board according to item 1, wherein each of the two or more adjacent layers is in contact with the insulating resin layers. [3] The insulating resin layer is integrally formed in the thickness direction, The insulating resin layer is further provided with a first recess that opens on the first surface, and a second recess that opens on the second surface and communicates with one or more of the first recesses. The conductor layer further includes a land portion that fills the first recess of the insulating resin layer, and a via portion that protrudes from the first surface at the position of the land portion. The via portion fills in a recess in another insulating resin layer adjacent to it on the first surface side. The multilayer wiring board according to claim 1 or 2, wherein the first metal-containing layer further covers the first surface side of the land portion and the side of the via portion without covering the side surface of the land portion. [4] The multilayer wiring board according to any one of claims 1 to 3, wherein the insulating resin layer is made of a non-photosensitive resin. [5] A multilayer wiring substrate according to any one of claims 1 to 4, wherein the first metal-containing layer contains titanium and the second metal-containing layer contains copper. [6] The multilayer wiring substrate according to any one of items 1 to 5, wherein the portion of the second metal-containing layer that covers the side surface of the wiring portion has an arithmetic mean roughness Ra of 10 nm or less. [7] A composite wiring board comprising a first wiring board and a second wiring board bonded to the first wiring board, wherein the first and second wiring boards are electrically connected to each other via bonding electrodes interposed between them, and the second wiring board is a multilayer wiring board as described in any one of claims 1 to 6. [8] The composite wiring board according to item 7, wherein the first wiring board is a wiring board for a flip-chip ball grid array, and the second wiring board is an interposer. [9] A composite wiring board as described in item 7 or 8, A functional device mounted on the side of the second wiring board opposite to the first wiring board and A packaged device equipped with the following features.

[10] The process involves forming two or more stacked layers, and the formation of each of the two or more layers is as follows: Forming recesses in the insulating resin layer, A dummy layer having grooves and one or more through holes communicating with the recesses is formed on the insulating resin layer. A first metal-containing layer is formed to cover the upper surface of the dummy layer and the inner surfaces of the recess, groove and through hole. A second metal-containing layer made of a different metal material than the first metal-containing layer is formed on the first metal-containing layer. A conductive layer is formed on the dummy layer so as to fill the recess, groove and through hole, The conductor layer is polished so that the portions located outside the recesses, grooves, or through holes are removed, thereby obtaining the portions of the conductor layer in which the recesses, through holes, and grooves are filled as via portions, land portions, and wiring portions, respectively. Subsequently, the dummy layer is removed, To remove the exposed portion of the first metal-containing layer, An insulating resin layer is provided that covers the conductor layer and fills the gap between the land portion and the wiring portion. A method for manufacturing a multilayer wiring board that includes [the specified component].

[11] The method for manufacturing a multilayer wiring board according to item 10, wherein the dummy layer is made of a photosensitive resin.

[12] The method for manufacturing a multilayer wiring board according to item 10 or 11, wherein the insulating resin layer is made of a non-photosensitive resin. [Explanation of symbols]

[0192] 1...Packaging device, 2...Support, 3...Release layer, 4a...Adhesion layer, 4b...Seed layer, 10...Composite wiring board, 11...FC-BGA substrate, 12...Multilayer wiring board, 12'...Multilayer wiring board, 13...Sealing resin layer, 14...Bonding electrode, 20...Functional device, 30...Sealing resin layer, 40...Bonding electrode, 50...Laser light, 111...Core layer, 112...Insulating layer, 113...Conducting layer, 114...Insulating layer, 115...Bonding conductor, 121...Resist layer, 122...Conducting layer, 123...Insulating resin layer, 124...Insulating resin layer, 125...Dummy layer, 126...Layer, 126'...Layer, 1261a...First metal-containing layer, 1 261a'...First metal-containing layer, 1261b...Second metal-containing layer, 1261b'...Second metal-containing layer, 1262...Conductor layer, 1262'...Conductor layer, 1262L...Land section, 1262L'...Land section, 1262V...Via section, 1262V'...Via section, 1262W...Wiring section, 1262W'...Wiring section, 1263...Insulating resin layer, 127a...Adhesion layer, 127b...Seed layer, 128...Resist layer, 129...Conductor layer, 130...Insulating resin layer, 131...Surface treatment layer, 132...Bonding conductor, G...Groove section, G'...Groove section, R1...First recess, R1'...Through hole, R2...Second recess, S1...First surface, S2...Second surface.

Claims

1. It comprises two or more layers stacked on top of each other, and each of the two or more layers is An insulating resin layer having a first surface and a second surface which is its back surface, wherein the insulating resin layer has a groove that opens on the first surface, A conductor layer including a wiring portion in which the groove portion of the insulating resin layer is embedded, A first metal-containing layer that covers the first surface side of the wiring portion without covering the side surface of the wiring portion, A second metal-containing layer comprising a portion interposed between the first metal-containing layer and the wiring portion, and a portion covering the side surface of the wiring portion, and made of a metal material different from the material of the first metal-containing layer. Includes, The second metal-containing layer is a seed layer made of copper, The insulating resin layer covers the portion of the second metal-containing layer that covers the side surface of the wiring portion without interposing any other layer between the insulating resin layer and the portion of the second metal-containing layer that covers the side surface of the wiring portion.

2. The multilayer wiring board according to claim 1, wherein each of the two or more adjacent layers has the insulating resin layers in contact with each other.

3. The insulating resin layer is integrally formed in the thickness direction, The insulating resin layer is further provided with a first recess that opens on the first surface, and a second recess that opens on the second surface and communicates with one or more of the first recesses. The conductor layer further includes a land portion that fills the first recess of the insulating resin layer, and a via portion that protrudes from the first surface at the position of the land portion. The via portion fills in a recess in another insulating resin layer adjacent to it on the first surface side. The multilayer wiring board according to claim 1 or 2, wherein the first metal-containing layer further covers the first surface side of the land portion and the side of the via portion without covering the side surface of the land portion.

4. The multilayer wiring board according to any one of claims 1 to 3, wherein the insulating resin layer is made of a non-photosensitive resin.

5. The multilayer wiring substrate according to any one of claims 1 to 4, wherein the first metal-containing layer contains titanium.

6. The multilayer wiring substrate according to any one of claims 1 to 5, wherein the portion of the second metal-containing layer that covers the side surface of the wiring portion has an arithmetic mean roughness Ra of 10 nm or less.

7. A composite wiring board comprising a first wiring board and a second wiring board bonded to the first wiring board, wherein the first and second wiring boards are electrically connected to each other via bonding electrodes interposed between them, and the second wiring board is a multilayer wiring board according to any one of claims 1 to 6.

8. The composite wiring board according to claim 7, wherein the first wiring board is a wiring board for a flip-chip ball grid array, and the second wiring board is an interposer.

9. A composite wiring board according to claim 7 or 8, A functional device mounted on the side of the second wiring board opposite to the first wiring board and A packaged device equipped with the following features.

10. The process involves forming two or more stacked layers, and the formation of each of the two or more layers is as follows: Forming recesses in the insulating resin layer, A dummy layer having grooves and one or more through holes communicating with the recesses is formed on the insulating resin layer. A first metal-containing layer is formed to cover the upper surface of the dummy layer and the inner surfaces of the recess, groove and through hole. A second metal-containing layer made of a different metal material than the first metal-containing layer is formed on the first metal-containing layer. A conductive layer is formed on the dummy layer so as to fill the recess, groove and through hole, The conductor layer is polished so that the portions located outside the recesses, grooves, or through holes are removed, thereby obtaining the portions of the conductor layer in which the recesses, through holes, and grooves are filled as via portions, land portions, and wiring portions, respectively. Subsequently, the dummy layer is removed, To remove the exposed portion of the first metal-containing layer, An insulating resin layer is provided that covers the conductor layer and fills the gap between the land portion and the wiring portion. A method for manufacturing a multilayer wiring board that includes [the specified component].

11. The method for manufacturing a multilayer wiring board according to claim 10, wherein the dummy layer is made of a photosensitive resin.

12. The method for manufacturing a multilayer wiring board according to claim 10 or 11, wherein the insulating resin layer is made of a non-photosensitive resin.

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