Wiring boards and semiconductor packages

Abstract

To provide a method for manufacturing a wiring board that has a wiring part and an insulating material layer with sufficient adhesion and heat resistance, and has sufficient insulation reliability.SOLUTION: A method for manufacturing a wiring board includes steps of: (A) forming a first insulating material layer on a support substrate; (B) forming a first opening in the first insulating material layer; (C) forming a seed layer on the first insulating material layer; (D) providing a resist pattern on a surface of the seed layer; (E) forming a wiring part including a pad and wiring; (F) removing the resist pattern; (G) removing the seed layer; (H) executing first surface treatment on a surface of the pad; (I) forming a second insulating material layer; (J) forming a second opening in the second insulating material layer; (K) executing second surface treatment on the surface of the pad; and (L) heating the second insulating material layer to a temperature equal to or more than the glass-transition temperature of the second insulating material layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a wiring board. [Background technology]

[0002] To achieve higher density and performance in semiconductor packages, mounting configurations have been proposed in which chips with different performance characteristics are mixed into a single package, making cost-effective high-density interconnect technology between chips crucial (see, for example, Patent Document 1).

[0003] Package-on-package, which connects different packages by stacking them on top of each other using flip-chip mounting, is widely used in smartphones and tablet devices (see, for example, Non-Patent Documents 1 and 2). Furthermore, as forms for high-density mounting, various packaging technologies have been proposed, including packaging technologies using organic substrates with high-density wiring (organic interposers), fan-out type packaging technologies with through-mold vias (TMVs) (FO-WLP), packaging technologies using silicon or glass interposers, packaging technologies using through-silicon vias (TSVs), and packaging technologies that use chips embedded in the substrate for inter-chip transmission. In particular, with organic interposers and FO-WLP, when semiconductor chips are mounted in parallel, a fine wiring layer is required to achieve high-density conductivity (see, for example, Patent Document 2). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2003-318519 [Patent Document 2] U.S. Patent Application Publication No. 2001 / 0221071 [Non-patent literature]

[0005] [Non-Patent Document 1] Application of Through Mold Via(TMV) as PoP Base Package, Electronic Components and Technology Conference(ECTC),2008 [Non-Patent Document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP(eWLB-PoP)Technology,ECTC,2012 [Overview of the project] [Problems that the invention aims to solve]

[0006] In the technology described in Patent Document 1 above, wiring is formed after desmearing, through the processes of electroless plating, resist patterning, electroplating, resist stripping, seed etching, and insulating material formation. In order to ensure close contact between the wiring and the insulating material, it is necessary to make the wiring surface appropriately rough through etching or the like, and to firmly fix the insulating material to the wiring through the anchoring effect.

[0007] In recent years, there has been a demand for reduced transmission loss in the high-frequency band of wiring boards. As mentioned above, roughening the wiring surface increases transmission loss due to the skin effect. However, if the insulating material layer is formed in the manufacturing method of the wiring board without going through the process of roughening the wiring surface, another problem arises: poor adhesion with the wiring surface leads to a deterioration of electrical insulation. Therefore, the challenge is to manufacture a wiring board that exhibits excellent electrical insulation while ensuring good adhesion between the wiring and the insulating material.

[0008] Furthermore, even when wiring and insulating material are in close contact immediately after the assembly of the wiring board, conducting long-term heat resistance tests such as high-temperature storage tests, moisture resistance tests, reflow resistance tests, and accelerated tests can lead to the formation of a thick oxide layer (e.g., a CuO layer) on the wiring surface, reducing adhesion to the insulating material. As a result, the electrical insulation performance deteriorates. An example of an accelerated test is the HAST (Highly Accelerated Stress Test).

[0009] This disclosure has been made in view of the above-mentioned problems, and aims to provide a method for manufacturing a wiring board in which the wiring portion and the insulating material layer have sufficient adhesion and heat resistance, as well as sufficient insulation reliability. [Means for solving the problem]

[0010] The manufacturing method of the wiring board according to this disclosure includes the following steps. (A) Step of forming a first insulating material layer on a support substrate. (B) Step of forming a first opening in the first insulating material layer (C) A process of forming a seed layer on the surface of the first insulating material layer by electroless plating. (D) Step of providing a resist pattern for wiring formation on the surface of the seed layer. (E) A process of forming a wiring portion including pads and wiring on the surface of the seed layer that is exposed from the resist pattern by electroplating. (F) Step to remove the resist pattern (G) Step of removing the seed layer exposed by removing the resist pattern. (H) Step of applying a first surface treatment to the surface of the wiring section. (I) A step of forming a second insulating material layer so as to cover the wiring section. (J) A step of forming a second opening in the second insulating material layer at a position corresponding to the pad. (K) Process of applying a second surface treatment to the surface of the pad. (L) A step of heating the second insulating material layer to a temperature above the glass transition temperature of the second insulating material layer.

[0011] In step (H) above, the adhesion between the wiring portion and the second insulating material layer can be improved by applying a treatment (first surface treatment) to the surface of the wiring portion that improves adhesion with the second insulating material layer. A specific example of the first surface treatment is a treatment using a surface treatment agent containing an organic component that improves adhesion between the wiring portion made of a metal material and the second insulating material layer. The average roughness Ra of the surface of the wiring portion after the first surface treatment is, for example, 40 to 80 nm. By applying the first surface treatment to the surface of the wiring portion, the adhesion between the wiring portion and the second insulating material layer can be made sufficiently high without making the surface of the wiring portion excessively rough. After step (J), the peel strength of the second insulating material layer against the wiring is, for example, 0.2 to 0.7 kN / m. In addition, the transmission loss can be sufficiently reduced because the surface of the wiring portion is not excessively rough. When forming a fine wiring pattern on the first insulating layer, in step (D) above, for example, a resist pattern having groove-shaped openings with a line width of 0.5 to 20 μm can be formed.

[0012] According to this disclosure, by applying a second surface treatment to the surface of the pad in step (K), excellent conductivity of the pad can be obtained. That is, even if a surface treatment layer is formed on the surface of the pad by the first surface treatment in step (H), and this layer reduces the conductivity of the pad, the conductivity of the pad can be restored by, for example, removing this layer in step (K). Furthermore, according to this disclosure, by performing both steps (H) and (L), the adhesion between the wiring portion and the second insulating material layer can be further improved, and a wiring board with excellent insulation reliability can be manufactured.

[0013] The above manufacturing method may further include a step between step (B) and step (C) for removing residue on the first insulating material layer and / or within the first opening. The process for removing residue may be called desmearing. At least one of the first insulating material layer and the second insulating material layer may contain a photosensitive resin. If the insulating material layer contains a photosensitive resin, the opening can be formed, for example, by a photolithography process.

[0014] It is preferable that the second opening is formed at a position corresponding to the pad. In this case, the manufacturing method may further include a step of performing a second surface treatment on the surface of the pad within the second opening. When a surface treatment agent containing an organic component as described above is used in the step of performing the first surface treatment, the surface treatment agent can be removed from the surface of the pad by the second surface treatment. The second surface treatment is, for example, at least one selected from the group consisting of oxygen plasma treatment, argon plasma treatment, and desmear treatment.

Advantages of the Invention

[0015] According to the present disclosure, there is provided a method for manufacturing a wiring board in which a wiring portion and an insulating material layer have sufficient adhesion and heat resistance and sufficient insulation reliability.

Brief Description of the Drawings

[0016] [Figure 1] FIG. 1(a) is a cross-sectional view schematically showing a state where a first insulating material layer is formed on a support substrate, FIG. 1(b) is a cross-sectional view schematically showing a state where a first opening is provided in the first insulating material layer, FIG. 1(c) is a cross-sectional view schematically showing a state where desmear treatment is performed on the first insulating material layer and the first opening, and FIG. 1(d) is a cross-sectional view schematically showing a state where a seed layer is formed on the first insulating material layer. [Figure 2] FIG. 2(a) is a cross-sectional view schematically showing a state where a resist pattern for forming a wiring portion is formed on the seed layer, FIG. 2(b) is a cross-sectional view schematically showing a state where a wiring portion is formed by electrolytic plating, FIG. 2(c) is a cross-sectional view schematically showing a state where the resist pattern is removed, and FIG. 2(d) is a cross-sectional view schematically showing a state where the seed layer exposed by the removal of the resist pattern is removed. [Figure 3] FIG. 3(a) is a cross-sectional view schematically showing a state where a first surface treatment is performed on the surface of the wiring portion, FIG. 3(b) is a cross-sectional view schematically showing a state where a second insulating material layer having a second opening is formed on the first insulating material layer, and FIG. 3(c) is a cross-sectional view schematically showing a state where a second surface treatment is performed on the surface of the pad. [Figure 4] Figure 4 is a schematic cross-sectional view showing a state in which a sintered layer is formed between the second insulating material layer and the wiring portion by heating the second insulating material layer to a temperature above its glass transition temperature. [Figure 5] Figure 5 is a schematic cross-sectional view showing one embodiment of a wiring board having multiple layers of wiring. [Modes for carrying out the invention]

[0017] The embodiments of this disclosure will be described in detail below with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. Furthermore, unless otherwise specified, positional relationships such as top, bottom, left, and right will be based on the positional relationships shown in the drawings. The dimensional ratios in the drawings are not limited to those shown.

[0018] Where terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "downward" are used in this specification, they are for illustrative purposes only and do not necessarily imply that the relative position is permanent. Furthermore, the term "layer" includes not only structures formed across the entire surface when viewed as a plan view, but also structures formed in only a portion of it. "A or B" may include either A or B, or both.

[0019] In this specification, the term "process" includes not only independent processes but also processes that are not clearly distinguishable from other processes, as long as their intended function is achieved. Furthermore, numerical ranges indicated using "~" represent a range that includes the numbers before and after "~" as the minimum and maximum values, respectively.

[0020] In this specification, the content of each component in a composition refers to the total amount of multiple substances present in the composition, unless otherwise specified, if multiple substances corresponding to each component are present in the composition. Furthermore, unless otherwise specified, the example materials may be used individually or in combination of two or more. Also, in numerical ranges described in stages within this specification, the upper or lower limit of one numerical range may be replaced with the upper or lower limit of another numerical range. Furthermore, in numerical ranges described within this specification, the upper or lower limit of that range may be replaced with the values ​​shown in the examples.

[0021] A method for manufacturing a wiring board according to an embodiment of this disclosure will be described with reference to the drawings. The method for manufacturing a wiring board according to this embodiment includes at least the following steps. (A) Step of forming a first insulating material layer 1 on a support substrate S. (B) Step of forming a first opening H1 in the first insulating material layer 1 (C) A step of forming a seed layer T on the surface of the first insulating material layer 1 by electroless plating. (D) Step of providing a resist pattern R for forming a wiring section on the surface of the seed layer T. (E) A step of forming a wiring portion C including a pad C1 and wiring C2 on the surface of the seed layer T in an area exposed from the resist pattern R by electroplating. (F) Step to remove the resist pattern R (G) Step of removing the seed layer T that is exposed by removing the resist pattern R. (H) Step of applying a first surface treatment to the surface of pad C1 and wiring C2. (I) A step of forming a second insulating material layer 2 so as to cover the pad C1 and the wiring C2. (J) Step of forming a second opening H2 in the second insulating material layer 2. (K) A process of applying a second surface treatment to the surface of the pad C1 inside the second opening H2. (L) A step of heating the second insulating material layer 2 to a temperature above the glass transition temperature of the second insulating material layer 2.

[0022] The wiring board according to this embodiment is suitable for configurations requiring miniaturization and a high pin count, and is particularly suitable for package configurations requiring an interposer for mounting different types of chips. More specifically, the manufacturing method according to this embodiment is suitable for package configurations where the pin spacing is 200 μm or less (for example, 30 to 100 μm for finer configurations) and the number of pins is 500 or more (for example, 1,000 to 10,000 for finer configurations). The following describes each step.

[0023] <Step of forming a first insulating material layer on a support substrate> A first insulating material layer 1 is formed on the support substrate S (Figure 1(a)). The support substrate S is not particularly limited, but can be a silicon plate, glass plate, SUS plate, glass cloth-reinforced substrate, semiconductor element-reinforced encapsulating resin, etc., and a substrate with high rigidity is preferred. As shown in Figure 1(a), the support substrate S may have a conductive layer Sa formed on the surface on which the insulating material layer is formed. The support substrate S may have wiring and / or pads on its surface instead of the conductive layer Sa.

[0024] The thickness of the support substrate S is preferably in the range of 0.2 mm to 2.0 mm. If it is thinner than 0.2 mm, handling becomes difficult, while if it is thicker than 2.0 mm, the material cost tends to be high. The support substrate S may be in the form of a wafer or a panel. The size is not particularly limited, but wafers with a diameter of 200 mm, 300 mm, or 450 mm, or rectangular panels with sides of 300 to 700 mm are preferably used.

[0025] It is preferable to use a photosensitive resin material as the material constituting the first insulating material layer 1. Examples of photosensitive insulating materials include liquid or film forms, and a film-type photosensitive insulating material is preferred from the viewpoint of film thickness flatness and cost. Furthermore, in order to form fine wiring, it is preferable that the photosensitive insulating material contains fillers (fillers) with an average particle size of 500 nm or less (more preferably 50 to 200 nm). The filler content of the photosensitive insulating material is preferably 0 to 70 parts by mass, and more preferably 10 to 50 parts by mass, per 100 parts by mass of the photosensitive insulating material excluding the fillers.

[0026] When using a film-type photosensitive insulating material, it is preferable to carry out the lamination process at the lowest possible temperature, and it is preferable to use a photosensitive insulating film that can be laminated at 40°C to 120°C. Photosensitive insulating films that can be laminated at temperatures below 40°C tend to have strong tack at room temperature (approximately 25°C) and are difficult to handle, while photosensitive insulating films that can be laminated at temperatures above 120°C tend to warp significantly after lamination.

[0027] The thermal expansion coefficient of the first insulating material layer 1 after curing is 80 × 10 from the viewpoint of suppressing warping. -6 It is preferable to have a K value of 70 × 10, which is the value at which high reliability can be obtained. -6 It is more preferable that the temperature is less than or equal to / K. Also, 20 × 10 is preferable in terms of the stress relaxation properties of the insulating material and the ability to obtain a high-resolution pattern. -6 It is preferable that the value is 1 / K or higher.

[0028] The thickness of the first insulating material layer 1 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less. From the viewpoint of insulating reliability, it is preferable that the thickness of the first insulating material layer 1 is within the above range.

[0029] <Step of forming a first opening on the surface of the first insulating material layer> A first opening H1 is formed on the surface of the first insulating material layer 1, extending to the support substrate S or the conductive layer Sa (Figure 1(b)). In this embodiment, the first opening H1 is formed so as to penetrate the first insulating material layer 1 in its thickness direction and is composed of a bottom surface (the surface of the conductive layer Sa) and a side surface (the insulating material layer 1). If the first insulating material layer 1 is made of a photosensitive resin material, the first opening H1 can be formed by a photolithography process (exposure and development).

[0030] Conventional methods such as projection exposure, contact exposure, and direct drawing exposure can be used for exposing the photosensitive resin material. For development, it is preferable to use an alkaline aqueous solution of sodium carbonate or TMAH (tetramethylammonium hydroxide). After forming the first opening H1, the first insulating material layer 1 may be further heat-cured. For example, the heating temperature is 100°C to 200°C, and the heating time is 30 minutes to 3 hours.

[0031] The first opening H1 may be formed in the first insulating material layer 1 by a method other than photolithography (e.g., laser ablation, sandblasting, water blasting, imprinting). For example, if the first insulating material layer 1 is made of a thermosetting resin material, laser ablation is preferred because it can form the first opening H1. As a method of forming the opening by laser ablation, a CO2 laser or UV-YAG laser can be used, but from the viewpoint of cost, the method using a CO2 laser is preferred. The resin residue on the surface of the conductive layer Sa exposed from the first opening H1 may be removed by desmearing. The surface of the first insulating material layer 1 may be roughened by this desmearing treatment. The surface F shown in Figure 1(c) shows a surface that has been subjected to desmearing treatment.

[0032] <Step of forming a seed layer on the surface of the first insulating material layer> A seed layer T is formed on the surface of the first insulating material layer 1 by electroless plating (Figure 1(d)). In this embodiment, first, the surface of the first insulating material layer 1 is washed with a pretreatment solution in order to adsorb palladium, which will serve as a catalyst for electroless copper plating, onto the surface of the first insulating material layer 1. The pretreatment solution may be a commercially available alkaline pretreatment solution containing sodium hydroxide or potassium hydroxide. The concentration of sodium hydroxide or potassium hydroxide is between 1% and 30%. The immersion time in the pretreatment solution is between 1 minute and 60 minutes. The immersion temperature in the pretreatment solution is between 25°C and 80°C. After pretreatment, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess pretreatment solution. Before forming the seed layer T on the surface of the first insulating material layer 1, the surface of the first insulating material layer 1 may be modified by methods such as ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, or plasma treatment.

[0033] After removing the pretreatment solution, the surface of the first insulating material layer 1 is immersed in an acidic aqueous solution to remove alkaline ions. The acidic aqueous solution may be a sulfuric acid aqueous solution, with a concentration of 1% to 20%, and the immersion time is between 1 and 60 minutes. To remove the acidic aqueous solution, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent.

[0034] Next, palladium is attached to the surface of the first insulating material layer 1 after it has been immersed and washed in an acidic aqueous solution. The palladium can be a commercially available palladium-tin colloid solution, an aqueous solution containing palladium ions, a palladium ion suspension, etc., but an aqueous solution containing palladium ions that effectively adsorb to the modified layer is preferred.

[0035] When immersing in an aqueous solution containing palladium ions, the temperature of the aqueous solution should be between 25°C and 80°C, and the immersion time for adsorption should be between 1 minute and 60 minutes. After adsorption of palladium ions, the material may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove any excess palladium ions.

[0036] After palladium ion adsorption, the palladium ions are activated to act as a catalyst. A commercially available activator (activation solution) can be used to activate the palladium ions. The temperature of the activator used for immersion should be between 25°C and 80°C, and the immersion time should be between 1 minute and 60 minutes. After palladium ion activation, the material may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove any excess activator.

[0037] Next, electroless copper plating is applied to the surface of the first insulating material layer 1 to form a seed layer T. This seed layer T serves as a power supply layer for electrolytic plating. Examples of electroless copper plating include electroless pure copper plating (purity of 99% by mass or more) and electroless copper nickel phosphorus plating (nickel content: 1% to 10% by mass, phosphorus content: 1% to 13% by mass), but electroless copper nickel phosphorus plating is preferred from the viewpoint of adhesion. A commercially available electroless copper nickel phosphorus plating solution can be used as the electroless copper nickel phosphorus plating solution; for example, an electroless copper nickel phosphorus plating solution (manufactured by JCU Corporation, product name "AISL-570") can be used. Electroless copper nickel phosphorus plating is carried out in an electroless copper nickel phosphorus plating solution at 60°C to 90°C. The thickness of the seed layer T is preferably 20 nm to 200 nm, more preferably 40 nm to 200 nm, and even more preferably 60 nm to 200 nm.

[0038] After electroless copper plating, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess plating solution. Furthermore, after electroless copper plating, thermal curing (annealing: age-curing treatment by heating) may be performed to improve the adhesion between the seed layer T and the first insulating material layer 1. The thermal curing temperature is preferably 80°C to 200°C. To accelerate the reaction, 120°C to 200°C is more preferable, and 120°C to 180°C is even more preferable. The thermal curing time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and even more preferably 20 minutes to 60 minutes.

[0039] <Process for forming resist patterns for wiring sections> A resist pattern R for forming the wiring section is formed on the seed layer T (Figure 2(a)). The resist pattern R can be a commercially available resist; for example, a negative-type film-type photosensitive resist (Hitachi Chemical Co., Ltd., Photec RY-5107UT) can be used. As shown in Figure 2(a), the resist pattern R has openings R1 and R2. Opening R1 is provided at a position corresponding to opening H1 of the first insulating material layer 1 and is for forming the pad C1. Opening H is formed by the first opening H1 and opening R1. Opening R2 is, for example, a groove-shaped opening with a line width of 0.5 to 20 μm and is for forming the wiring C2.

[0040] The resist pattern R can be formed through the following steps: First, a resist film is deposited using a roll laminator; then, a phototool with the pattern formed on it is placed in close contact with the laminator and exposed using an exposure machine; and finally, the pattern is formed by spray development with an aqueous sodium carbonate solution. A positive-type photosensitive resist may be used instead of a negative-type resist.

[0041] <Process for forming the wiring section> Using the seed layer T as a power supply layer, for example, electrolytic copper plating is performed to form a wiring section C including a pad C1 and wiring C2 (Figure 2(b)). The thickness of the wiring section C is preferably 1 to 10 μm, more preferably 3 to 10 μm, and even more preferably 5 to 10 μm. Note that the wiring section C may also be formed by electrolytic plating other than electrolytic copper plating.

[0042] <Process for removing the resist pattern> After electrolytic copper plating, remove the resist pattern R (Figure 2(c)). The resist pattern R can be removed using a commercially available stripping solution.

[0043] <Process for removing the seed layer> After removing the resist pattern R, the seed layer T is removed (Figure 2(d)). Along with removing the seed layer T, any palladium remaining beneath the seed layer T may also be removed. These removals can be carried out using commercially available removal solutions (etching solutions), and specific examples include acidic etching solutions (JCU Corporation, BB-20, PJ-10, SAC-700W3C).

[0044] <Step of applying a first surface treatment to the surfaces of pad C1 and wiring C2> A surface treatment layer 5 is formed on the surfaces of the pad C1 and the wiring C2 by applying a first surface treatment (Figure 3(a)). The first surface treatment can be carried out using a commercially available surface treatment liquid. As the surface treatment liquid, for example, a liquid containing an organic component that improves the adhesion between the wiring part C and the second insulating material layer 2 formed in a later process (for example, "GliCAP" manufactured by Shikoku Chemicals, Inc.), or a liquid containing an organic component that finely etches the surface of the wiring part C and improves the adhesion between the wiring part C and the second insulating material layer 2 (for example, "Novabond" manufactured by Atotec Japan Co., Ltd. and "CZ8401" and "CZ-8402" manufactured by MEC Corporation) can be used.

[0045] The average surface roughness Ra of the wiring section C (pad C1 and wiring C2) after the first surface treatment is, for example, 40 to 80 nm, but may be 50 to 80 nm or 60 to 80 nm. If the average surface roughness Ra of the wiring section C is 40 nm or more, sufficient adhesion between the wiring section C and the second insulating material layer 2 can be ensured, while if it is 80 nm or less, the transmission loss of the wiring board can be sufficiently reduced.

[0046] <Process for forming the second insulating material layer> A second insulating material layer 2 is formed to cover the wiring section C. The material constituting the second insulating material layer 2 may be the same as or different from that of the first insulating material layer 1.

[0047] <Step of forming a second opening in the second insulating material layer> A second opening H2 is formed in the second insulating material layer 2 (Figure 3(b)). The second opening H2 is located at a position corresponding to the pad C1. The method for forming the second opening H2 may be the same as or different from the method for forming the first opening H1. After this step, the peel strength of the second insulating material layer 2 relative to the wiring C2 is, for example, 0.2 to 0.7 kN / m, and may be 0.4 to 0.65 kN / m or 0.5 to 0.6 kN / m. The peel strength referred to here means the value measured under the conditions of a peel angle of 90° and a peel speed of 10 mm / min. By going through these steps, the wiring board 10 shown in Figure 3(b) is obtained. The wiring board 10 comprises a support substrate S, a pad C1 provided so as to penetrate the first insulating material layer 1 and the second insulating material layer 2, and a wiring layer 8A having wiring C2 embedded in the second insulating material layer 2.

[0048] <Process of applying a second surface treatment to the surface of the pad> The surface treatment layer 5 is removed by applying a second surface treatment to the surface of the pad C1 within the second opening H2 (Figure 3(c)). As described above, the surface treatment layer 5 contains, for example, organic components and may inhibit the conductivity of the pad C1. By removing at least a portion of the surface treatment layer 5, that is, by providing a surface treatment agent removal section 6 on the surface of the pad C1 as shown in Figure 3(c), the decrease in conductivity of the pad C1 caused by the surface treatment layer 5 can be improved. Examples of treatments for removing the surface treatment layer 5 include plasma treatment and desmear treatment (treatment using an alkaline solution). Examples of gases used in plasma treatment include oxygen, argon, nitrogen, and mixtures thereof. Through this process, a wiring board 20 with the configuration shown in Figure 3(c) is obtained. The wiring board 20 differs from the wiring board 10 shown in Figure 3(b) in that a surface treatment agent removal section 6 is provided on the surface of the pad C1.

[0049] <Step of heating the second insulating material layer> By heating the second insulating material layer 2 to a temperature above its glass transition temperature (Tg), a fired layer 7 is formed at the interface between the wiring portion C and the second insulating material layer 2 (Figure 4). This further improves the adhesion between the wiring portion C and the second insulating material layer 2. The fired layer 7 is formed, for example, by the reaction of the surface treatment agent contained in the surface treatment layer 5 with the second insulating material layer 2. The heating temperature is above the glass transition temperature (Tg) of the second insulating material layer 2, for example, 250°C or lower. The heating time is preferably 30 minutes to 3 hours. When the heating temperature is above Tg and the heating time is 30 minutes or longer, the effect of improving the adhesion between the wiring portion C and the second insulating material layer 2 is fully realized. On the other hand, when the heating temperature is 250°C or lower and the heating time is 3 hours or less, the decomposition of the surface treatment agent remaining between the wiring portion C and the second insulating material layer 2 is suppressed, and the excellent adhesion between the wiring portion C and the second insulating material layer 2 can be maintained. Furthermore, the heating temperature being 250°C or lower suppresses warping of the wiring board. Through this process, a wiring board 30 with the configuration shown in Figure 4 is obtained. The wiring board 30 differs from the wiring board 20 shown in Figure 3(c) in that a firing layer 7 is formed at the interface between the wiring section C and the second insulating material layer 2.

[0050] The glass transition temperature of the second insulating material layer referred to here is the midpoint glass transition temperature value obtained when the second insulating material layer after curing is measured using differential scanning calorimetry (DSC, for example, Rigaku Corporation's "Thermo Plus 2"). Specifically, the above glass transition temperature is the midpoint glass transition temperature calculated by measuring the change in heat quantity under the conditions of a heating rate of 10°C / min and a measurement temperature of 30 to 250°C, in accordance with the method compliant with JIS K 7121:1987.

[0051] Although one embodiment of a method for manufacturing a wiring board has been described above, the present invention is not necessarily limited to the above-described embodiment, and modifications may be made as appropriate without departing from the spirit of the invention. For example, the above embodiment illustrates a method for manufacturing a wiring board having a single wiring layer 8A, but a wiring board having multiple wiring layers may also be manufactured. The multilayer wiring board 40 shown in Figure 5 comprises, in addition to the configuration of the wiring board 30, a wiring layer 8B composed of a third insulating material layer 3 and wiring C2 embedded in the third insulating material layer 3. The pad C1 of the multilayer wiring board 40 is provided so as to penetrate the first insulating material layer 1, the second insulating material layer 2, and the third insulating material layer 3. [Examples]

[0052] The present disclosure will be further described in detail by the following examples, but the present invention is not limited to these examples.

[0053] [Example 1] <Preparation of photosensitive resin film> A photosensitive resin composition used for forming an insulating material layer was prepared using the following components. • Photoreactive resin containing carboxyl groups and ethylenically unsaturated groups: Acid-modified cresol novolac type epoxy acrylate (CCR-1219H, manufactured by Nippon Kayaku Co., Ltd., trade name) 50 parts by mass • Photopolymerization initiator components: 2,4,6-trimethylbenzoyl-diphenyl-phosphine oxide (Darocure TPO, manufactured by BASF Japan Ltd., trade name) and 5 parts by mass of ethanol, 1-[9-ethyl-6-(2-methylbenzoyl)-9H-carbazole-3-yl]-,1-(o-acetyloxime) (Irgacure OXE-02, manufactured by BASF Japan Ltd., trade name) • Thermosetting agent component: Biphenol-type epoxy resin (YX-4000, manufactured by Mitsubishi Chemical Corporation, product name) 10 parts by mass • Inorganic filler component: (Average particle size: 50 nm, treated with vinylsilane coupling)

[0054] The inorganic filler component was blended in an amount of 10 parts by volume per 100 parts by volume of resin. The particle size distribution was measured using a dynamic light scattering nanotrac particle size distribution analyzer "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering microtrac particle size distribution analyzer "MT-3100" (manufactured by Nikkiso Co., Ltd.), and it was confirmed that the maximum particle size was 1 μm or less.

[0055] A solution of the photosensitive resin composition with the above composition was applied to the surface of a polyethylene terephthalate film (G2-16, manufactured by Teijin Limited, trade name, thickness: 16 μm). It was then dried at 100°C for approximately 10 minutes using a hot air convection dryer. The resulting photosensitive resin film had a thickness of 10 μm.

[0056] <Formation of wiring layers with fine wiring> A glass cloth-reinforced wiring board (size: 200 mm square, thickness: 1.5 mm) was prepared as the support substrate. A copper layer was formed on the surface of this wiring board, with a thickness of 20 μm.

[0057] ·Process (A) The above-mentioned photosensitive resin film (first insulating material layer) was laminated onto the surface of the copper layer of the wiring board. Specifically, first, the photosensitive resin film was placed on the surface of the copper layer of the wiring board. Then, it was pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). The pressing conditions were: press hot plate temperature 80°C, vacuuming time 20 seconds, lamination pressing time 60 seconds, atmospheric pressure 4kPa or less, and bonding pressure 0.4MPa.

[0058] ·Process (B) By subjecting the insulating material layer after pressing to exposure and development treatments, an opening (first opening) extending to the copper layer of the wiring board was created in the first insulating material layer. Exposure was performed by placing a phototool with a pattern formed on it in close contact with the insulating material layer and using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Therma Precision) at 30 mJ / cm². 2The material was exposed to the following energy. Next, a 1% by mass sodium carbonate aqueous solution at 30°C was spray-developed for 45 seconds to create openings. Then, the surface of the developed insulating material layer was exposed to 2000 mJ / cm² using a mask exposure machine (EXM-1201 exposure machine, manufactured by Oak Manufacturing Co., Ltd.). 2 Post-UV exposure was performed with the specified energy level. Subsequently, thermal curing was carried out in a clean oven at 170°C for 1 hour.

[0059] ·Process (C) A seed layer was formed on the surface of the insulating material layer by electroless copper plating. Specifically, first, as alkaline cleaning, the material was immersed in a 110 mL / L aqueous solution of alkaline cleaner (manufactured by JCU Corporation, product name: EC-B) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as a conditioner, the material was immersed in a mixture of conditioning solution (manufactured by JCU Corporation, product name: PB-200) and EC-B (PB-200 concentration: 70 mL / L, EC-B concentration: 2 mL / L) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as soft etching, the material was immersed in a mixture of soft etching solution (manufactured by JCU Corporation, product name: PB-228) and 98% sulfuric acid (PB-228 concentration: 100 g / L, sulfuric acid concentration: 50 mL / L) at 30°C for 2 minutes, and then immersed in pure water for 1 minute. Next, as a desmat, the material was immersed in 10% sulfuric acid at room temperature for 1 minute. Next, as a catalyst, a mixture of catalyst reagent 1 (manufactured by JCU Corporation, product name: PC-BA), catalyst reagent 2 (manufactured by JCU Corporation, product name: PB-333), and EC-B (PC-BA concentration: 5 g / L, PB-333 concentration: 40 mL / L, EC-B concentration: 9 mL / L) was immersed at 60°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as an accelerator, a mixture of accelerator reagent (manufactured by JCU Corporation, product name: PC-66H) and PC-BA (PC-66H concentration: 10 mL / L, PC-BA concentration: 5 g / L) was immersed at 30°C for 5 minutes, and then immersed in pure water for 1 minute. Next, for electroless copper plating, the samples were immersed in a mixture of electroless copper plating solution (manufactured by JCU Corporation, product names: AISL-570B, AISL-570C, AISL-570MU) and PC-BA (AISL-570B concentration: 70 mL / L, AISL-570C concentration: 24 mL / L, AISL-570MU concentration: 50 mL / L, PC-BA concentration: 13 g / L) at 60°C for 7 minutes, and then immersed in pure water for 1 minute. After that, they were dried on a hot plate at 85°C for 5 minutes. Next, they were heat annealed in an oven at 180°C for 1 hour.

[0060] ·Process (D) Using a vacuum laminator (V-160, manufactured by Nichigo Morton Co., Ltd.), a wiring resist (RY-5107UT, manufactured by Hitachi Chemical Co., Ltd.) was vacuum-laminated onto a 200 mm square substrate with an electroless copper film deposition. The lamination temperature was 110°C, the lamination time was 60 seconds, and the lamination pressure was 0.5 MPa.

[0061] After vacuum lamination, the material was left for one day, and then the resist for wiring formation was exposed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Therma Precision Co., Ltd.). The exposure dose was 140 mJ / cm². 2 The focus was set to -15 μm. After exposure, the material was left for one day, the protective film of the resist for wiring formation was peeled off, and the material was developed using a spray developer (Mikasa Corporation, AD-3000). The developer was a 1.0% sodium carbonate aqueous solution, the development temperature was 30°C, and the spray pressure was 0.14 MPa. This formed the resist pattern for creating the following L / S (line / space) wiring on the seed layer. L / S = 20μm / 20μm (Number of wires: 10) L / S = 15μm / 15μm (Number of wires: 10) L / S = 10μm / 10μm (Number of wires: 10) L / S = 7μm / 7μm (Number of wires: 10) L / S = 5μm / 5μm (Number of wires: 10) L / S = 3μm / 3μm (Number of wires: 10) L / S = 2μm / 2μm (Number of wires: 10)

[0062] ·Process (E) As a cleaner, the sample was immersed in a 100 mL / L aqueous solution of (Okuno Pharmaceutical Co., Ltd., product name: ICP Clean S-135) at 50°C for 1 minute, then in pure water at 50°C for 1 minute, then in pure water at 25°C for 1 minute, and finally in a 10% sulfuric acid aqueous solution at 25°C for 1 minute. Next, to a 7.3 L aqueous solution of 120 g / L copper sulfate pentahydrate and 220 g / L 96% sulfuric acid, 0.25 mL of hydrochloric acid, 10 mL of (Okuno Pharmaceutical Co., Ltd., product name: Toplutina GT-3), and 1 mL of (Okuno Pharmaceutical Co., Ltd., product name: Toplutina GT-2) were added, and the current density was set to 1.5 A / dm² at 25°C. 2 Electroplating was performed under conditions of 10 minutes. After that, it was immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes.

[0063] ·Process (F) The resist used for wiring formation was removed using a spray developer (Mikasa AD-3000). The stripping solution was a 2.38% TMAH aqueous solution, the stripping temperature was 40°C, and the spray pressure was 0.2 MPa.

[0064] ·Process (G) The seed layer, consisting of electroless copper and palladium catalyst, was removed. For etching the electroless copper, the sample was immersed for 1 minute at 35°C in an etching solution (SAC-700W3C, manufactured by JCU Corporation) and an aqueous solution of 98% sulfuric acid, 35% hydrogen peroxide, and copper sulfate pentahydrate (SAC-700W3C concentration: 5 vol%, sulfuric acid concentration: 4 vol%, hydrogen peroxide concentration: 5 vol%, copper sulfate pentahydrate concentration: 30 g / L). Next, to remove the palladium catalyst, the sample was immersed for 1 minute at 50°C in an FL aqueous solution (FL-A 500 mL / L, FL-B 40 mL / L, manufactured by JCU Corporation). After that, it was immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes.

[0065] ·Process (H) The surfaces of the pads and wiring were surface-treated (first surface treatment) with GliCAP (manufactured by Shikoku Kasei Kogyo Co., Ltd.). As acid cleaning, it was immersed in a 3.5% hydrochloric acid aqueous solution at 25°C for 1 minute. Next, it was rinsed with running water in pure water at 25°C for 1 minute. Next, it was immersed in a soft etching solution (manufactured by Shikoku Kasei Co., Ltd., GB-1000) at 30°C for 1 minute. Next, it was rinsed with running water in pure water at 25°C for 1 minute. Next, it was immersed in a surface treatment agent (manufactured by Shikoku Kasei Co., Ltd., GliCAP) at 30°C for 15 minutes. Next, it was rinsed with running water in pure water at 25°C for 1 minute. Then, it was dried on a hot plate at 100°C for 5 minutes.

[0066] · Step (I) A photosensitive resin film (second insulating material layer) was laminated so as to cover the pads and wiring surface-treated through Step (H). Specifically, first, a photosensitive resin film was placed on the first insulating material layer so as to cover the pads and wiring. Next, it was pressed using a press-type vacuum laminator (MVLP-500, manufactured by Naiki Seisakusho Co., Ltd.). The pressing conditions were a press hot plate temperature of 80°C, a vacuum drawing time of 20 seconds, a lamination press time of 60 seconds, an air pressure of 4 kPa or less, and a crimping pressure of 0.4 MPa.

[0067] · Step (J) By performing an exposure treatment and a development treatment on the insulating material layer after pressing, an opening (second opening) reaching the pads was provided in the second insulating material layer. For exposure, a photomask having a pattern formed thereon was closely adhered onto the insulating material layer, and exposure was performed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3 (Ck), manufactured by Summa Precision Co., Ltd.) at an energy amount of 30 mJ / cm 2 Next, spray development was performed for 45 seconds with a 1 mass% sodium carbonate aqueous solution at 30°C to provide an opening. Next, post-UV exposure was performed on the surface of the insulating material layer after development using a mask exposure machine (EXM-1201 type exposure machine, manufactured by Okou Seisakusho Co., Ltd.) at an energy amount of 2000 mJ / cm 2 Then, heat curing was performed at 170°C for 1 hour in a clean oven. The glass transition temperature (Tg) of the second insulating material layer after curing was 160°C.

[0068] [Example 2] A wiring board was obtained in the same manner as in Example 1, except that in step (H), Novabond (manufactured by Atotec Japan Co., Ltd.) was used for surface treatment instead of GliCAP. Specifically, first, it was immersed in a 15 mL / L aqueous solution of Novabond IT stabilizer (manufactured by Atotec Japan Co., Ltd.) at 50°C for 1 minute. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was immersed in a 30 mL / L aqueous solution of Novabond IT (manufactured by Atotec Japan Co., Ltd.) at 50°C for 1 minute. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was immersed in a 20 mL / L aqueous solution of Novabond IT reducer (manufactured by Atotec Japan Co., Ltd.) at 30°C for 5 minutes. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was immersed in a 10 mL / L aqueous solution of Novabond IT protector MK (manufactured by Atotec Japan Co., Ltd.) at 35°C for 1 minute. Next, it was rinsed with pure water at 25°C for 1 minute. After that, it was dried on a hot plate at 100°C for 5 minutes.

[0069] [Example 3] In step (H), a wiring board was obtained in the same manner as in Example 1, except that CZ8401 (manufactured by MEC Corporation) was used for surface treatment instead of GliCAP. Specifically, first, as an acid cleaning, a 5% hydrochloric acid aqueous solution was spray-cleaned at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was spray-treated with CZ8401 treatment solution at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was spray-treated with a 10% sulfuric acid aqueous solution at 25°C for 20 seconds at a water pressure of 0.1 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. After that, it was dried on a hot plate at 100°C for 5 minutes.

[0070] [Example 4] In step (H), a wiring board was obtained in the same manner as in Example 1, except that CZ8402 (manufactured by MEC Corporation) was used for surface treatment instead of GliCAP. Specifically, first, as an acid cleaning, a 5% hydrochloric acid aqueous solution was spray-cleaned at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was spray-treated with CZ8402 treatment solution at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was spray-treated with a 10% sulfuric acid aqueous solution at 25°C for 20 seconds at a water pressure of 0.1 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. After that, it was dried on a hot plate at 100°C for 5 minutes.

[0071] [Comparative Example 1] In step (H), a wiring board was obtained in the same manner as in Example 1, except that a surface treatment agent was not used. Specifically, first, as an acid cleaning, the board was spray-cleaned with a 5% hydrochloric acid aqueous solution at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. After that, it was dried on a hot plate at 100°C for 5 minutes.

[0072] [Comparative Example 2] In step (H), a wiring board was obtained in the same manner as in Example 1, except that CZ8101 (manufactured by MEC Corporation) was used for surface treatment instead of GliCAP. Specifically, first, as an acid cleaning, a 5% hydrochloric acid aqueous solution was spray-cleaned at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was spray-treated with CZ8101 treatment solution at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, it was spray-treated with 10% sulfuric acid aqueous solution at 25°C for 20 seconds at a water pressure of 0.1 MPa. Next, it was rinsed with pure water at 25°C for 1 minute. Next, as a rust prevention treatment, it was immersed in CL-8300 (manufactured by MEC Corporation) treatment solution at 25°C for 30 seconds. Next, it was rinsed with pure water at 25°C for 1 minute. After that, it was dried on a hot plate at 100°C for 5 minutes.

[0073] <Measurement of average surface roughness Ra of the copper layer> The average surface roughness Ra of the copper layer in Example 1 (surface treatment with Glicap), Example 2 (surface treatment with Novabond), Example 3 (surface treatment with CZ-8401), Example 4 (surface treatment with CZ-8402), Comparative Example 1 (no surface treatment agent), and Comparative Example 2 (CZ-8101) was measured using a surface roughness meter (OLS-4000, manufactured by Olympus Corporation). The results are shown in Table 1.

[0074] <Measurement of peel strength at the interface between the copper layer and the insulating material layer> The peel strength of the interface between the copper layer and the insulating material layer in Example 1 (surface treatment with Glicap), Example 2 (surface treatment with Novabond), Example 3 (surface treatment with CZ-8401), Example 4 (surface treatment with CZ-8402), Comparative Example 1 (no surface treatment agent), and Comparative Example 2 (CZ-8101) was measured using a peel strength measuring device (Shimadzu Corporation, ES-Z). The measurement conditions were a peel angle of 90° and a peel speed of 10 mm / min. The results are shown in Table 1.

[0075] <Evaluation of wiring formability> For wiring formation with L / S ratios of 20μm / 20μm, 15μm / 15μm, 10μm / 10μm, 7μm / 7μm, 5μm / 5μm, 3μm / 3μm, and 2μm / 2μm, a rating of "A" was given if 0 out of 10 wires showed signs of bending, peeling, or disconnection; "B" if 1-2 showed such signs; and "C" if 3 or more showed such signs. The results are shown in Table 1.

[0076] [Table 1]

[0077] ·Process (K) Desmear treatment (second surface treatment) was applied to the pad surfaces of the wiring boards according to Examples 1-4 and Comparative Examples 1 and 2. Specifically, first, for swelling treatment, the boards were immersed in 40 mL / L of Swella (Atotech Cleaner Securigant 902) at 70°C for 5 minutes. Then, they were immersed in pure water for 1 minute. Next, to remove the surface treatment agent, the boards were immersed in 40 mL / L of desmear solution (Atotech Compact CP) at 70°C for 3 minutes. Then, they were immersed in pure water for 1 minute. After that, they were dried on a hot plate at 80°C for 5 minutes.

[0078] <Evaluation of surface treatment agent removal capability> The surface treatment agent removal performance of Examples 1-4 and Comparative Examples 1 and 2 was evaluated. For openings of Φ100 μm, Φ50 μm, Φ30 μm, Φ20 μm, and Φ10 μm, the exposed copper surface was measured at 900 cm using a micro-Raman spectrometer (product name: DXR2 Microscope, manufactured by Thermo Fisher Scientific Co., Ltd.). -1 The presence or absence of peaks was examined, and out of 10 pads, those with 0 pads showing peaks (residue) were classified as "A", those with 1-2 pads as "B", and those with 3 or more pads as "C". The results are shown in Table 2.

[0079] [Table 2]

[0080] [Examples 1a-4d and Comparative Examples 1a-2d] ·Process (L) Multiple wiring boards according to Examples 1-4 and Comparative Examples 1 and 2 were prepared and heated at 200°C or 250°C for 30 minutes or 3 hours, respectively, as shown in Table 3.

[0081] <Evaluation of electrical insulation properties> The electrical insulation properties of the wiring boards in Examples 1a-4d and Comparative Examples 1a-2d were evaluated. Wiring with L / S ratios of 20μm / 20μm, 15μm / 15μm, 10μm / 10μm, 7μm / 7μm, 5μm / 5μm, 3μm / 3μm, and 2μm / 2μm was tested using a HAST chamber (EHS-222MD, ESPEC) and an ion migration evaluation system (AM-150-U-5, ESPEC) under the conditions of 130°C, 85% relative humidity, and 3.3V applied voltage. Of the 10 wirings, the electrical resistance value was 1 × 10⁻⁶. 6 When there were 10 wires with an insulation retention time of 200 hours or more in Ω, it was classified as "A", when there were 7 or more, it was classified as "B", and when there were 5 or more, it was classified as "C". The results are shown in Table 3.

[0082] [Table 3]

[0083] <Heat resistance evaluation> The heat resistance of the wiring boards in Examples 1a-4d and Comparative Examples 1a-2d was evaluated. Wiring with L / S ratios of 20 μm / 20 μm, 15 μm / 15 μm, 10 μm / 10 μm, 7 μm / 7 μm, 5 μm / 5 μm, 3 μm / 3 μm, and 2 μm / 2 μm was tested using a HAST chamber (EHS-222MD, ESPEC) at a holding temperature of 130°C, relative humidity of 85%, and holding time of 500 hours. After the heat resistance test, the cross-section of the wiring was observed using a scanning electron microscope (Regulus8230, Hitachi High-Tech Corporation) to check the thickness of copper oxide (CuO) on the wiring surface and whether or not there was delamination between the wiring and the insulating material. A thickness of copper oxide (CuO) of 50 nm or less was classified as "A", 80 nm or less as "B", and 150 nm or less as "C". The evaluation results for the thickness of copper oxide are shown in Table 4. After the heat resistance test, the wires were graded "A" if all 10 wires showed no delamination, "B" if 7 or more showed no delamination, and "C" if 5 or more showed no delamination. The evaluation results for delamination are shown in Table 5.

[0084] [Table 4]

[0085] [Table 5] [Industrial applicability]

[0086] According to this disclosure, a method for manufacturing a wiring board is provided in which the wiring portion and the insulating material layer have sufficient adhesion and heat resistance, as well as sufficient insulation reliability. [Explanation of symbols]

[0087] 1…First insulating material layer, 2…Second insulating material layer, 3…Third insulating material layer, 5…Surface treatment layer, 6…Surface treatment agent removal section, 7…Firing layer, 8A,8B…Wiring layers, 10,20,30…Wiring board, 40…Multilayer wiring board, C…Wiring section, C1…Pad, C2…Wiring, F…Desmeared surface, H…Opening, H1…First opening, H2…Second opening, R…Resist pattern, R1,R2…Opening, S…Support substrate, Sa…Conductive layer, T…Seed layer

Claims

1. A support substrate having a first surface and a second surface, A first insulating material layer formed on the first surface of the support substrate, A first wiring formed on the surface of the first insulating material layer, A second insulating material layer formed to cover the surface of the first insulating material layer and the first wiring, A first firing layer formed between the first wiring and the second insulating material layer, Equipped with, The first fired layer is a layer which has been altered by a reaction between the second insulating material layer and a surface treatment agent containing an organic component that improves the adhesion between the first wiring and the second insulating material layer. The first wiring is a wiring substrate having a surface with an average roughness Ra of 40 to 80 nm.

2. A first opening formed in the first insulating material layer, A second opening is formed in the second insulating material layer and communicates with the first opening, A pad made of conductive material filled in the first opening and the second opening, A second fired layer formed between the pad and the second insulating material layer, Furthermore, The wiring substrate according to claim 1, wherein the second firing layer is a layer obtained by a reaction between the second insulating material layer and a surface treatment agent containing an organic component that improves the adhesion between the pad and the second insulating material layer.

3. A second wiring formed on the surface of the second insulating material layer, A third insulating material layer formed to cover the surface of the second insulating material layer and the second wiring, A third fired layer formed between the second wiring and the third insulating material layer, Furthermore, The wiring substrate according to claim 1 or 2, wherein the third firing layer is a layer formed by the reaction of a surface treatment agent containing an organic component that improves the adhesion between the second wiring and the third insulating material layer with the third insulating material layer.

4. The wiring board according to any one of claims 1 to 3, wherein the width of the first wiring is 0.5 to 20 μm.

5. The wiring board according to any one of claims 1 to 4, further comprising a conductive layer provided between the support substrate and the first insulating material layer.

6. A wiring board according to any one of claims 1 to 5, A semiconductor chip mounted on the aforementioned wiring board, A semiconductor package equipped with the following features.

7. A wiring board according to any one of claims 1 to 5, Multiple semiconductor chips mounted on the aforementioned wiring board, Equipped with, A semiconductor package in which the aforementioned multiple semiconductor chips have different performance characteristics.

8. The semiconductor package according to claim 6 or 7, wherein the semiconductor chip is flip-chip mounted on the wiring substrate.

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