Circuit substrate and semiconductor package

Abstract

This circuit board comprises a ceramic substrate that has silicon nitride as a main component, a conductive part that is formed of a conductive material and is connected to a semiconductor element, and a bonding part that bonds the ceramic substrate and the conductive part, that contains titanium, and that has a plurality of voids arranged along a surface on the bonding part-side of the ceramic substrate, wherein, in a cross-section of the bonding part among the cross-section passing through the ceramic substrate, the bonding part, and the conductive part, the plurality of voids have at least specific voids having a width of at least 0.5 μm, and the total width of the specific voids is at most 54 μm.

Description

Circuit board and semiconductor package

[0001] The present invention relates to a circuit board and a semiconductor package.

[0002] Conventionally, a circuit board including a conductive portion to which a semiconductor element is connected and a ceramic substrate has been known (for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2014-118310

[0004] However, even with the prior art such as Patent Document 1, there is still room for improvement in the technology for suppressing breakage in a circuit board.

[0005] An object of the present invention is to provide a technology for suppressing breakage in a circuit board.

[0006] The present invention has been made to solve at least a part of the above-described problems and can be realized in the following forms.

[0007] (1) According to one aspect of the present invention, a circuit board is provided. The circuit board includes a ceramic substrate mainly composed of silicon nitride, a conductive portion formed of a conductive material and connected to a semiconductor element, and a joint portion that joins the ceramic substrate and the conductive portion and contains titanium, and has a plurality of void portions arranged along the surface of the ceramic substrate on the joint portion side. In a cross section of the joint portion among cross sections passing through the ceramic substrate, the joint portion, and the conductive portion, the plurality of void portions have at least a specific void portion having a width of 0.5 μm or more, and the total width of the specific void portions included in a target region having a width of 120 μm is 54 μm or less.

[0008] In this configuration, the joint connecting the ceramic substrate and the conductive part has multiple voids arranged along the surface of the ceramic substrate facing the joint. In the circuit board, in the cross-section of the joint, the sum of the widths of specific voids with a width of 0.5 μm or more, among the multiple voids included in the target area with a width of 120 μm, is 54 μm or less. That is, the porosity due to the voids arranged along the surface of the ceramic substrate facing the joint is 45% or less. By having an appropriate amount of unbonded area at the joint interface between the ceramic substrate and the joint in this way, stress concentration on the relatively brittle ceramic substrate can be suppressed. As a result, crack propagation in the ceramic substrate due to thermal cycling can be suppressed, and thus damage to the circuit board can be suppressed.

[0009] (2) In the circuit board of the above form, the width of the specific void in the cross section passing through the ceramic substrate, the joint, and the conductive part may be 20 μm or less. With this configuration, the width of the specific void is 20 μm or less. That is, because the width of the specific void is relatively small, it is possible to suppress stress concentration on the ceramic substrate while suppressing a decrease in bonding strength. As a result, it is possible to suppress damage to the circuit board while maintaining a certain level of strength.

[0010] (3) In the circuit board of the above form, the joint portion does not have to contain either aluminum or silver. With this configuration, the joint portion does not contain either aluminum, which has relatively low thermal conductivity, or silver, which is expensive. This makes it possible to suppress the decrease in thermal conductivity of the joint portion and to reduce the manufacturing cost of the circuit board.

[0011] (4) In the circuit board of the above form, the specific void may be located within 2 μm of the ceramic substrate within the joint. With this configuration, the specific void is located relatively close to the ceramic substrate. This further suppresses stress concentration on the ceramic substrate, and thus further suppresses damage to the circuit board.

[0012] (5) In the circuit board of the above form, the ceramic substrate has a pair of main surfaces, the conductive portion has a first conductive portion disposed on one of the pair of main surfaces of the ceramic substrate and a second conductive portion disposed on the other of the pair of main surfaces of the ceramic substrate, the joint portion has a first joint portion that joins the ceramic substrate and the first conductive portion and a second joint portion that joins the ceramic substrate and the second conductive portion, and the thermal conductivity between the first conductive portion and the second conductive portion may be 170 W / (m·K) or more. With this configuration, a circuit board having two conductive portions sandwiched between a ceramic substrate can efficiently transfer heat from, for example, a semiconductor element or electronic component connected to the first conductive portion to the second conductive portion.

[0013] (6) According to another embodiment of the present invention, a semiconductor package is provided. This semiconductor package comprises the circuit board described above and a power semiconductor element connected to the conductive part. With this configuration, the semiconductor package can efficiently dissipate the heat generated by the power semiconductor element, which generates a relatively large amount of heat, through the circuit board.

[0014] Furthermore, the present invention can be realized in various forms, for example, in the form of a method for manufacturing a circuit board and a semiconductor package, an apparatus and system comprising a circuit board and a semiconductor package, a method for controlling such apparatus and system, a computer program that causes such apparatus and system to supply power to electronic equipment and to perform mutual conversion between AC and DC, a server apparatus for distributing the computer program, and a non-temporary storage medium that stores the computer program.

[0015] This is a cross-sectional view of the circuit board of the first embodiment. This is a cross-sectional view of the semiconductor package of the first embodiment. This is an enlarged view of part A in Figure 1. This is an enlarged view of part B in Figure 3. This is a diagram illustrating the results of the evaluation test of the circuit board.

[0016] <First Embodiment> Figure 1 is a cross-sectional view of the circuit board 1 of this embodiment. Figure 2 is a cross-sectional view of the semiconductor package P1 of this embodiment. The circuit board 1 of this embodiment is a substrate on which a power semiconductor element 5 can be mounted, and as shown in Figure 1, comprises a ceramic substrate 10, conductive parts 21, 22, and bonding parts 31, 32. The semiconductor package P1 shown in Figure 2 comprises the circuit board 1 and a power semiconductor element 5 connected to the conductive part 21. The semiconductor package P1 performs various power conversions by switching operation, specifically supplying power to electronic devices and performing mutual conversion between AC and DC. In Figures 1 and 2, the direction along the stacking direction of the ceramic substrate 10, conductive parts 21, 22, and bonding parts 31, 32 is defined as the z-axis direction, the direction perpendicular to the z-axis is defined as the x-axis direction, and the direction perpendicular to the z-axis and x-axis is defined as the y-axis direction. Note that the thickness relationships between the ceramic substrate 10, the conductive parts 21 and 22, and the bonding parts 31 and 32 in Figure 1, and the thickness relationship between the circuit board 1 and the power semiconductor element 5 in Figure 2, are illustrated in a way that differs from the actual thickness relationships for the sake of explanation.

[0017] The ceramic substrate 10 is a flat plate-shaped member whose main component is silicon nitride (Si3N4). Here, "main component is silicon nitride" means that it contains 86 wt% or more of silicon nitride. The ceramic substrate 10 may also contain SiAlON. The ceramic substrate 10 has a pair of main surfaces 10a and 10b. The thickness of the ceramic substrate 10 is, for example, 220 μm or more and 690 μm or less. However, the thickness of the ceramic substrate 10 is not limited to these ranges. In this embodiment, the arithmetic mean roughness Ra of the pair of main surfaces 10a and 10b of the ceramic substrate 10 is 0.24 μm or more and 0.88 μm or less.

[0018] Each of the conductive parts 21 and 22 is formed of a conductive material, and conductive part 21 is connected to the power semiconductor element 5. Conductive part 21 becomes part of the electrical circuit in the semiconductor package P1. Each of the conductive parts 21 and 22 is formed of a metal mainly composed of copper, for example, oxygen-free copper. Here, "metal mainly composed of copper" refers to a metal containing 99 wt% or more of copper. The thickness of each of the conductive parts 21 and 22 is, for example, 200 μm or more and 1500 μm or less. Conductive part 21 is arranged on one of the pair of main surfaces 10a and 10b of the ceramic substrate 10. Conductive part 22 is arranged on the other of the pair of main surfaces 10a and 10b of the ceramic substrate 10. Conductive part 21 corresponds to the "first conductive part" in the claims, and conductive part 22 corresponds to the "second conductive part" in the claims.

[0019] The joints 31 and 32 contain titanium. Neither of the joints 31 and 32 in this embodiment contains aluminum or silver. Here, "neither aluminum nor silver" means that they are not detected in the analysis of the target element by an energy-dispersive X-ray spectrometer (EDS), and specifically, that the content concentration of the target element is less than 1 at%. Joint 31 joins the ceramic substrate 10 and the conductive part 21, and joint 32 joins the ceramic substrate 10 and the conductive part 22. Joint 31 corresponds to the "first joint" in the claims, and joint 32 corresponds to the "second joint" in the claims.

[0020] The thickness of each of the joints 31 and 32 is, for example, 0.3 μm or more and 3 μm or less. The thickness of the joints 31 and 32 can be determined using a scanning electron microscope. For example, to determine the thickness of the joint 31, five locations are randomly selected on the polished surface of a cross section perpendicular to one of the main surfaces 10a of the ceramic substrate 10, and an image of a 120 μm × 90 μm area is taken at a magnification of 2000x. Next, the lengths of 10 line segments drawn perpendicular to a 100 μm line segment drawn at the interface between the ceramic substrate 10 and the joint 31, and at equal intervals, are determined. In this embodiment, the average of these determined values ​​is taken as the thickness of the joint 31. The same procedure is followed for the joint 32. Note that the thickness of the joints 31 and 32 tends to be thicker than the thickness of the metal film produced in the manufacturing method of the circuit board 1 described later. This is because, during the bonding of the ceramic substrate 10 and the conductive parts 21 and 22 via the bonding portions 31 and 32, nitrogen atoms and silicon atoms are supplied from the ceramic substrate 10, and copper atoms are supplied from the conductive parts 21 and 22.

[0021] Figure 3 is an enlarged view of section A in Figure 1. Figure 4 is an enlarged view of section B in Figure 3. Figure 3 is a cross-sectional SEM image of the portion included in section A shown in Figure 1, and is a cross-sectional SEM image of the portion including the ceramic substrate 10, the joint 31, and the conductive portion 21, at a magnification of 1000x. For the sake of explanation, the interface between the joint 31 and the conductive portion 21 is indicated by the dashed line BL in Figures 3 and 4.

[0022] As shown in Figure 3, the joint portion 31 has a plurality of voids 311 arranged along one main surface (the surface on the joint portion 31 side) 10a of the ceramic substrate 10. In the circuit board 1 of this embodiment, the plurality of voids 311 are arranged near the surface 10a of the ceramic substrate 10 on the joint portion 31 side, as shown in Figure 3. Each of the plurality of voids 311 has a void inside. The plurality of voids 311 have at least one specific void 311s with a width W of 0.5 μm or more. In the circuit board 1, in the cross-section of the joint portion 31 of the cross-section passing through the ceramic substrate 10, the joint portion 31, and the conductive portion 21, the total width W of the specific voids 311s included in the target region with a width of 120 μm is 54 μm or less. That is, the porosity in the joint portion 31 can be said to be 45% or less. Here, porosity is the ratio (percentage) of the total width W of specific voids 311s among the multiple voids 311 included in the target area with a width of 120 μm. Specifically, in the cross-sectional SEM image at 1000x magnification shown in Figure 3, the black areas along the surface 10a on the joint 31 side of the ceramic substrate 10 have a width of 0.5 μm or more and are all specific voids 311s. Since the width (length in the x-axis direction) of the cross-sectional SEM image shown in Figure 3 is 120 μm, the total width W (length in the x-axis direction) of the specific voids 311s shown in this cross-sectional SEM image is 54 μm. In the circuit board 1 of this embodiment, the total width W of specific voids 311s with a width W of 0.5 μm or more is 0.6 μm or more. Note that in Figure 3, in order to avoid making the drawing complicated, not all specific voids 311s visible in the cross-sectional SEM image are assigned a number 311s.

[0023] In Figure 3, the joint portion 31 was described, but the joint portion 32 also has a plurality of voids arranged along the other main surface (the surface on the joint portion 32 side) 10b of the ceramic substrate 10. In the joint portion 32, in the cross-section of the joint portion 32 that passes through the ceramic substrate 10, the joint portion 32, and the conductive portion 22, the sum of the widths of specific voids with a width of 0.5 μm or more among the plurality of voids included in the target area with a width of 120 μm is 54 μm or less.

[0024] In the circuit board 1 of this embodiment, as shown in Figure 3, the width W of the specific void portion 311s in the cross-section passing through the ceramic substrate 10, the joint portion 31, and the conductive portion 21 is 20 μm or less. This suppresses stress concentration on the ceramic substrate 10 due to the void portion 311, while also suppressing a decrease in the bonding strength between the ceramic substrate 10 and the conductive portion 21. Therefore, damage to the circuit board 1 can be suppressed while maintaining a certain level of strength.

[0025] In the circuit board 1 of this embodiment, as shown in Figure 4, the range in which the specific void portion 311s exists in the joint portion 31 is within a range where the distance Dsp from one main surface 10a of the ceramic substrate 10 is within 2 μm. That is, the specific void portion 311s is located within a range of 2 μm from the ceramic substrate 10 in the joint portion 31. The distance Dsp is measured using a linear virtual line VL along the stacking direction (z-axis direction) of the ceramic substrate 10 and the conductive portions 21 and 22, as shown in Figure 4. In the cross-section shown in Figure 4, one end VL1 of the virtual line VL is on one main surface 10a of the ceramic substrate 10, and the other end VL2 is on the far end E311 of the specific void portion 311s, which is the position furthest from one main surface 10a of the ceramic substrate 10. The distance Dsp is the distance between the one end VL1 and the other end VL2 of the virtual line VL.

[0026] In the circuit board 1 of this embodiment, the thermal conductivity between the conductive part 21 and the conductive part 22 is 170 W / (m·K) or higher. Specifically, when the relationship between the thickness of the conductive part 21, the thickness of the ceramic substrate 10, and the thickness of the conductive part 22 is, for example, 0.5:0.32:0.5, the thermal conductivity of the circuit board 1 is 170 W / (m·K) or higher. As a result, even if the power semiconductor elements 5 arranged on both sides of the circuit board 1 generate a large amount of heat, the heat can be released to the outside through the ceramic substrate 10.

[0027] Next, the manufacturing method of the circuit board 1 will be described. In the manufacturing method of the circuit board 1, a ceramic substrate 10 is first made. In the manufacturing of the ceramic substrate 10, the raw material powder of the silicon nitride sintered body is weighed. The raw material powder of the silicon nitride sintered body may be oxides, carbonates, hydroxides, nitrides, etc. of each element contained in the silicon nitride sintered body. In addition to silicon nitride, the raw material powder of the silicon nitride sintered body may include, for example, magnesium carbonate, calcium carbonate, yttrium oxide, etc. Ethanol is added to these raw material powders, and a slurry is made by wet mixing and grinding using a ball mill, for example, at 40 rpm to 100 rpm for 6 to 60 hours. The prepared slurry is dried using a water bath or a spray dryer to produce a mixed powder.

[0028] In the fabrication of the ceramic substrate 10, the mixed powder is then filled into a mold and molded by uniaxial pressing at a pressure of, for example, 30 MPa. After that, a molded body is produced by performing CIP (cold isohydrostatic pressing) at a pressure of, for example, 100 MPa to 150 MPa. The fabricated molded body is then placed in a silicon carbide mold coated with BN on the inside and fired in a nitrogen atmosphere of 0.9 MPa at a maximum temperature of 1800°C to 1900°C for 5 to 30 hours to produce a silicon nitride sintered body. The ceramic substrate 10 is manufactured by processing the outer shape of the produced silicon nitride sintered body to a predetermined shape, for example, a flat plate shape and thickness. Processing can be done by cutting, grinding, polishing, etc. At this time, each of the pair of main surfaces 10a and 10b on which the conductive parts 21 and 22 of the ceramic substrate 10 are arranged is polished so that the arithmetic mean roughness Ra is 0.24 μm or more and 0.88 μm or less.

[0029] In the manufacturing method of the circuit board 1, separate from the manufacturing of the ceramic substrate 10, a plate material of a predetermined thickness that will become the conductive parts 21 and 22 is prepared. The plate material that will become the conductive parts 21 and 22 may be formed from a metal containing copper or a metal mainly composed of copper, in addition to oxygen-free copper. Next, a metal film mainly composed of titanium that will become the joint parts 31 and 32 is formed on the surface of each of the two plate materials that will become the conductive parts 21 and 22, or on each of the pair of main surfaces 10a and 10b of the ceramic substrate 10. The metal film can be manufactured by sputtering, vapor deposition, plating, etc. The thickness of the metal film is preferably 3 μm or less. It is desirable to remove organic matter such as oil adhering to the surface of the ceramic substrate 10 and the plate material before forming the metal film. It is thought that by sufficiently removing organic matter from the surface, the gas generated during heat treatment is suppressed and contributes to the diffusion of copper that forms the conductive parts 21 and 22. The process of removing organic matter can be carried out by, for example, degreasing, washing with water, washing with acetone, etc. These steps may be combined, or a surface drying step may be included. Furthermore, if a thin titanium metal foil with a thickness of 3 μm or less is available, the metal foil may be attached to the surfaces of the two plate materials that will form the conductive parts 21 and 22, or to the pair of main surfaces 10a and 10b of the ceramic substrate 10. Even in this case, a step to remove organic matter and a step to dry the surface may be included before attaching the metal foil.

[0030] Next, the plate material that will become the conductive parts 21 and 22 and the ceramic substrate 10 are laminated so that a metal film is sandwiched between the plate material that will become the conductive parts 21 and 22 and the ceramic substrate 10. If metal foil is available, the plate material that will become the conductive part 21, one of the two metal foils, the ceramic substrate 10, the other of the two metal foils, and the plate material that will become the conductive part 22 are laminated in that order. The laminate in which the plate material that will become the conductive parts 21 and 22 and the ceramic substrate 10 are laminated is subjected to HP treatment (hot pressing treatment) or HIP treatment (hot isostatic pressing treatment) to bond the plate material that will become the conductive parts 21 and 22 and the ceramic substrate 10. The conditions for HP treatment are, for example, a pressure of 5 MPa or more and 30 MPa or less, a maximum temperature of 850°C or more and 1050°C or less, and a maximum temperature holding time of 10 minutes or more and 2 hours or less. Note that the manufacturing method of the circuit board 1 is not limited to these methods.

[0031] Next, we will explain the results of the circuit board evaluation test. In this evaluation test, for each of the six types of circuit boards (hereinafter simply referred to as "samples") with different arithmetic mean surface roughness of the ceramic substrate, the relationship between the porosity, the size of specific voids, and the area where specific voids exist, and the mechanical strength, thermal properties, and heat resistance was measured or calculated and evaluated.

[0032] Figure 5 illustrates the results of the circuit board evaluation test. Each of the samples 1 to 6 shown in Figure 5 was manufactured by a method consistent with the manufacturing method of the circuit board 1 of this embodiment. Specifically, for samples 1 to 5, 0.32 mm thick ceramic substrates made of silicon nitride were prepared, each with a different arithmetic mean roughness of the surface due to blast treatment. The arithmetic mean roughness of the surface of the ceramic substrates for each of samples 1 to 5 is shown as "Ra (μm)" in Figure 5. For samples 1 to 5, a titanium film corresponding to the joints 31 and 32 of the circuit board 1 was sputtered onto the prepared ceramic substrate to a thickness of 0.5 μm. Then, a laminate consisting of a 0.5 mm thick copper plate, a ceramic substrate, and another 0.5 mm thick copper plate was bonded by hot pressing through the titanium film. The pressure during the hot pressing process was 10 MPa, the maximum temperature was 1000°C, and the maximum temperature holding time was 0.5 hours. Sample 6 was prepared by applying a brazing material containing Cu, Ag, and Ti (thickness: approximately 30 μm) to both sides (arithmetic mean roughness Ra: 0.44 μm) of a 0.32 mm thick ceramic substrate made of silicon nitride, and then bonding the laminated structure to the substrate by hot pressing, similar to Samples 1 to 5.

[0033] The "porosity (%)" shown in Figure 5 represents the ratio of the total width of specific voids with a width of 0.5 μm or more among multiple voids included in the target area with a width of 120 μm at the joint. The "porosity (%)" was measured using the same method as the method for measuring the porosity in the circuit board 1 of this embodiment.

[0034] The value "W (μm)" shown in Figure 5 indicates the width of a specific void contained in the joint. The value of "W (μm)" is the width of the specific void measured using the cross-sectional SEM images taken for each of the six types of samples. If the cross-sectional SEM image contains multiple specific voids, the width of each of the multiple specific voids was measured, and the largest width among them is shown.

[0035] The "Dsp (μm)" shown in Figure 5 indicates the range in which a specific void exists at the joint. "Dsp (μm)" is the distance from the joint side of the ceramic substrate, measured using cross-sectional SEM images taken for each of the six types of samples. "Dsp (μm)" was measured using the same method as the measurement method for the range in which the specific void 311s exists in the circuit board 1 of this embodiment.

[0036] The value "Sp (kN / m)" shown in Figure 5 represents the peel strength of the sample. For the measurement of "Sp (kN / m)", for each of the six types of samples, first, a slit with a peel width of 5 mm was made in a copper plate bonded to a ceramic substrate, then a portion of the edge of the copper plate was peeled off, and the plate was clamped in a tensile testing machine and pulled vertically to measure the load value when the copper plate was peeled off. Next, the measured load value was divided by the measured peel width and averaged to calculate the value.

[0037] The value "K(W / (m·K))" shown in Figure 5 represents the thermal conductivity of the sample. For the measurement of "K(W / (m·K))", a measurement sample with sides of 10 mm was first prepared for each of the six types of samples. After applying blackbody spray, the thermal diffusivity and specific heat were measured using the flash method. Next, the thermal conductivity was calculated as the product of the thermal diffusivity, specific heat, and density, using the density measured separately. Note that the measurement sample may also be prepared using a semiconductor package from which the semiconductor element has been removed.

[0038] The "Cold and Heat Cycle Test Results" shown in Figure 5 indicate resistance to thermal shock. The cold and heat cycle test was conducted using a thermal shock testing apparatus, where the sample was subjected to a cycle of -40°C for 5 minutes, then maintained at 125°C for 5 minutes, and then cooled to -40°C. A maximum of 1000 cycles of the cold and heat cycle test were performed. After the cold and heat cycle test, SAT inspection (ultrasonic flaw detection) was performed to check for the presence of cracks at the ends of the joints. If the length of the crack was 1 mm or more, it was determined that a crack that would render the product unusable had occurred, and the "Cold and Heat Cycle Test Results" were marked as "Cracks Present". If the length of the crack was less than 1 mm, or if no cracks were found, the "Cold and Heat Cycle Test Results" were marked as "No Cracks".

[0039] As shown in Figure 5, it was confirmed that samples 2 to 6, which had a "porosity (%)" of 45% or less, exhibited greater peel strength ("Sp (kN / m)") compared to sample 1, which had a "porosity (%)" of 50%. In other words, it was confirmed that peel strength improves when the ratio of the total width of specific voids with a width of 0.5 μm or more among the multiple voids included in the target area with a width of 120 μm at the joint is 45% or less.

[0040] Of samples 2 to 6, it was confirmed that for samples 2 to 5, the peel strength ("Sp (kN / m)") increased as the "W (μm)" increased. Specifically, samples 2 to 4, with a "W (μm)" of 7.4 μm or more, showed a higher "Sp (kN / m)" than sample 5, with a "W (μm)" of 6.9 μm. Samples 2 and 3, with a "W (μm)" of 11.0 μm or more, showed a higher "Sp (kN / m)" than sample 4, with a "W (μm)" of 7.4 μm. Furthermore, it was confirmed that sample 2, with a "W (μm)" of 20.0 μm, showed a higher "Sp (kN / m)" than sample 3, with a "W (μm)" of 11.0 μm.

[0041] Of samples 2 to 6, samples 2 to 5 had a "Dsp (μm)" of 2 μm or less, which indicates the range in which a specific void exists at the joint, while sample 6 had a "Dsp (μm)" of 11.0 μm. In other words, the specific voids in each of samples 2 to 5 were located closer to the ceramic substrate than the specific void in sample 6. Of samples 2 to 6, samples 2 to 5 were found to have a higher thermal conductivity ("K (W / (m·K))") compared to sample 6. Furthermore, samples 2 to 5 showed "no cracks" in the thermal cycling test, while sample 6 showed "cracks" in the thermal cycling test. In other words, it was confirmed that when the specific void at the joint of a circuit board is located within 2 μm of the ceramic substrate, the thermal conductivity is improved and the resistance to thermal shock is improved.

[0042] As described above, according to the circuit board 1 of this embodiment, the joint portions 31 and 32 that join the ceramic substrate 10 and the conductive portions 21 and 22 have a plurality of void portions 311 arranged along the surfaces 10a and 10b of the ceramic substrate 10 on the joint portion 31 and 32 side. In the cross-section of the joint portions 31 and 32, the sum of the widths of specific void portions with a width of 0.5 μm or more among the plurality of void portions included in the target area with a width of 120 μm is 54 μm or less. In this way, the circuit board 1 has an appropriate amount of unjointed portions (void portions) at the joint interface between the ceramic substrate 10 and the joint portions 31 and 32, thereby suppressing stress concentration on the relatively brittle ceramic substrate 10. As a result, the propagation of cracks in the ceramic substrate 10 due to thermal cycling can be suppressed, and thus damage to the circuit board 1 can be suppressed.

[0043] Furthermore, according to the circuit board 1 of this embodiment, the width of the specific void is 20 μm or less. That is, since the width W of the specific void 311s is relatively small, it is possible to suppress stress concentration on the ceramic substrate 10 while suppressing a decrease in bonding strength. As a result, it is possible to suppress damage to the circuit board 1 while maintaining a certain level of strength.

[0044] Further, according to the circuit board 1 of the present embodiment, each of the joint portions 31 and 32 does not contain either aluminum with a relatively low thermal conductivity or silver with a high cost. Thereby, it is possible to suppress a decrease in the thermal conductivity of the joint portions 31 and 32 and to reduce the manufacturing cost of the circuit board 1.

[0045] Further, according to the circuit board 1 of the present embodiment, the specific void portion 311s is located relatively close to the ceramic substrate 10. Thereby, since stress concentration on the ceramic substrate 10 can be further suppressed, breakage of the circuit board 1 can be further suppressed.

[0046] Further, according to the circuit board 1 of the present embodiment, the circuit board 1 including the two conductive portions 21 and 22 sandwiching the ceramic substrate 10 has a relatively high thermal conductivity between the two conductive portions 21 and 22, so that heat of the power semiconductor element 5 connected to the conductive portion 21 can be efficiently transmitted to the conductive portion 22.

[0047] Further, according to the semiconductor package P1 of the present embodiment, the semiconductor package P1 can efficiently release heat of the power semiconductor element 5 having a relatively large amount of heat generation by the circuit board 1.

[0048] <Modification Example of the Present Embodiment> The present invention is not limited to the above-described embodiment, and can be implemented in various aspects without departing from the gist thereof. For example, the following modifications are also possible.

[0049] [Modification Example 1] In the above-described embodiment, in the cross section passing through the ceramic substrate, the joint portion, and the conductive portion, the width of the specific void portion is set to 20 μm or less. The width of the specific void portion in the cross section may be larger than 20 μm, but if the width is somewhat smaller, it is possible to suppress stress concentration on the ceramic substrate while suppressing a decrease in the bonding strength.

[0050] [Modification Example 2] In the above-described embodiment, the joint portion does not contain either aluminum or silver. The joint portion may contain at least one of aluminum and silver.

[0051] [Modification 3] In the above embodiment, the specific void was located within 2 μm of the ceramic substrate in the joint. The location of the specific void in the joint is not limited to this. By having the specific void located relatively close to the ceramic substrate, stress concentration on the ceramic substrate can be further suppressed.

[0052] [Modification 4] In the above embodiment, the circuit board is provided with two conductive parts on a single ceramic substrate. The configuration of the circuit board is not limited to this. A configuration in which one conductive part is arranged on a single ceramic substrate is also possible.

[0053] [Modification 5] In the above embodiment, the semiconductor package comprises a circuit board and a power semiconductor element connected to a conductive part. The electronic component connected to the conductive part of the circuit board is not limited to a power semiconductor element.

[0054] The embodiments of this specification have been described above based on the embodiments and modifications described above. The embodiments described above are for the purpose of facilitating understanding of this specification and do not limit it. This specification may be modified and improved without departing from its spirit and the scope of the claims, and equivalents thereof are included in this specification. Furthermore, any technical features that are not described as essential in this specification may be deleted as appropriate.

[0055] <Application Example 1> A circuit board comprising: a ceramic substrate mainly composed of silicon nitride; a conductive portion formed of a conductive material and connected to a semiconductor element; and a joint portion joining the ceramic substrate and the conductive portion, the joint portion containing titanium and having a plurality of voids arranged along the surface of the ceramic substrate on the joint portion side, wherein in the cross-section of the joint portion among the cross-sections passing through the ceramic substrate, the joint portion and the conductive portion, the plurality of voids have at least one specific void portion with a width of 0.5 μm or more, and the total width of the specific voids included in a target area with a width of 120 μm is 54 μm or less. <Application Example 2> The circuit board according to Application Example 1, wherein in the cross-section passing through the ceramic substrate, the joint portion and the conductive portion, the width of the specific void portion is 20 μm or less. <Application Example 3> A circuit board according to Application Example 1 or Application Example 2, characterized in that the joint portion does not contain either aluminum or silver. <Application Example 4> A circuit board according to any one example from Application Example 1 to Application Example 3, characterized in that the specific void portion is located within a range of 2 μm from the ceramic substrate within the joint portion. <Application Example 5> A circuit board according to any one of Application Examples 1 to 4, wherein the ceramic substrate has a pair of main surfaces, the conductive portion has a first conductive portion disposed on one of the pair of main surfaces of the ceramic substrate and a second conductive portion disposed on the other of the pair of main surfaces of the ceramic substrate, the joint portion has a first joint portion that joins the ceramic substrate and the first conductive portion and a second joint portion that joins the ceramic substrate and the second conductive portion, and the thermal conductivity between the first conductive portion and the second conductive portion is 170 W / (m·K) or more. <Application Example 6> A semiconductor package, comprising a circuit board according to any one of Application Examples 1 to 5 and a power semiconductor element connected to the conductive portion.

[0056] 1...Circuit board 5...Power semiconductor element 10...Ceramic substrate 21, 22...Conductive part 31, 32...Bond 311...Void 311s...Specific void Dsp...Distance P1...Semiconductor package W...Width

Claims

1. A circuit board comprising: a ceramic substrate mainly composed of silicon nitride; a conductive portion formed of a conductive material and connected to a semiconductor element; and a joint portion joining the ceramic substrate and the conductive portion, the joint portion containing titanium and having a plurality of voids arranged along the surface of the ceramic substrate on the joint portion side, wherein in the cross-section of the joint portion among the cross-sections passing through the ceramic substrate, the joint portion and the conductive portion, the plurality of voids have at least one specific void portion with a width of 0.5 μm or more, and the total width of the specific voids included in a target region with a width of 120 μm is 54 μm or less.

2. A circuit board according to claim 1, characterized in that, in a cross-section passing through the ceramic substrate, the joint portion, and the conductive portion, the width of the specific void portion is 20 μm or less.

3. A circuit board according to claim 1 or claim 2, characterized in that the joint portion does not contain either aluminum or silver.

4. A circuit board according to claim 1 or claim 2, characterized in that the specific void portion is located within a range of 2 μm from the ceramic substrate within the joint portion.

5. A circuit board according to claim 1 or claim 2, wherein the ceramic substrate has a pair of main surfaces, the conductive portion has a first conductive portion disposed on one of the pair of main surfaces of the ceramic substrate and a second conductive portion disposed on the other of the pair of main surfaces of the ceramic substrate, the joint portion has a first joint portion that joins the ceramic substrate and the first conductive portion and a second joint portion that joins the ceramic substrate and the second conductive portion, and the thermal conductivity between the first conductive portion and the second conductive portion is 170 W / (m·K) or more.

6. A semiconductor package comprising a circuit board according to claim 1 or claim 2, and a power semiconductor element connected to the conductive portion.

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