Semiconductor light-emitting element, light-emitting module, and method for manufacturing a light-emitting module

Abstract

To provide a semiconductor light-emitting element or the like, comprising an electrode with reduced electric resistance.SOLUTION: A semiconductor light-emitting element 10 comprises: a semiconductor laminate 10S; a contact electrode 40 arranged above the semiconductor laminate 10S; and a pad layer 50 that is arranged above the contact electrode 40, and includes Au. The pad layer 50 includes: a first layer 51a arranged above a region where the pad layer 50 and the contact electrode 40 are contacted each other; and a second layer 51b arranged above the first layer 51a, and contacted to the first layer 51a. In a direction parallel to a principal surface of the contact electrode 40, a means particle diameter of Au in the second layer 51b is larger than that of Au in the first layer 51a.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor light-emitting element, a light-emitting module, and a method for manufacturing a light-emitting module. [Background technology]

[0002] Conventionally, semiconductor light-emitting elements such as semiconductor laser elements are known. In such semiconductor light-emitting elements, there is a need for higher efficiency and reduced heat generation. For example, in the semiconductor laser element described in Patent Document 1, Au, which has good conductivity, is used for the pad electrode placed on the P-side electrode. This aims to achieve higher efficiency and reduced heat generation in the semiconductor laser element described in Patent Document 1. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2020 / 110783 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, even when Au is used in the pad electrodes, as in the semiconductor laser element described in Patent Document 1, there is still room for improvement in the electrical resistance of the semiconductor laser element. For example, when the pad electrodes and the submount are joined using AuSn solder, as in the semiconductor laser element described in Patent Document 1, Sn may diffuse from the pad electrodes to the P-side electrodes, potentially increasing the contact resistance between the semiconductor layer and the P-side electrodes.

[0005] This disclosure aims to solve these problems and to provide semiconductor light-emitting elements, etc., equipped with electrodes with reduced electrical resistance. [Means for solving the problem]

[0006] To solve the above problems, one embodiment of a nitride semiconductor light-emitting element according to the present disclosure comprises a semiconductor stack, a contact electrode disposed above the semiconductor stack, and a pad layer disposed above the contact electrode and containing Au, wherein the pad layer has a first layer disposed above the region where the pad layer and the contact electrode are in contact, and a second layer disposed above the first layer and in contact with the first layer, wherein in a direction parallel to the main surface of the contact electrode, the average particle size of Au in the second layer is greater than the average particle size of Au in the first layer.

[0007] One embodiment of the light-emitting module according to the present disclosure comprises a semiconductor light-emitting element and a base to which the semiconductor light-emitting element is bonded, wherein the semiconductor light-emitting element comprises a semiconductor laminate, a contact electrode disposed between the semiconductor laminate and the base, and a bonding layer containing AuSn bonded to the contact electrode and the base, wherein the bonding layer has a first bonding region disposed opposite to the region in contact with the bonding layer and the contact electrode, and the average Sn content in the region of the first bonding region closer to the contact electrode than the center in the thickness direction of the first bonding region is less than the average Sn content in the region of the first bonding region further from the contact electrode than the center.

[0008] One embodiment of a method for manufacturing a light-emitting module according to the present disclosure includes a preparation step of preparing a semiconductor light-emitting element and a base, and a bonding step of bonding the semiconductor light-emitting element to the base using a bonding material containing AuSn, wherein the semiconductor light-emitting element comprises a semiconductor laminate, a contact electrode disposed above the semiconductor laminate, and a pad layer containing Au that is electrically connected to the contact electrode and disposed above the contact electrode, wherein the pad layer includes a first layer disposed above the region in contact with the pad layer and the contact electrode, and a second layer disposed above the first layer and in contact with the first layer, wherein the shape of the crystal grains of Au in the second layer is columnar, and in a direction parallel to the main surface of the contact electrode, the average grain size of the second layer is larger than the average grain size of the first layer, and in the bonding step, the bonding material bonds the base and the pad layer. [Effects of the Invention]

[0009] According to this disclosure, it is possible to provide semiconductor light-emitting elements and the like that which have electrodes with reduced electrical resistance. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic plan view showing the overall configuration of a semiconductor light-emitting element according to Embodiment 1. [Figure 2] Figure 2 is a schematic cross-sectional view showing the overall configuration of the semiconductor light-emitting element according to Embodiment 1. [Figure 3] Figure 3 is a transmission electron microscope (TEM) image showing the shape of the crystal grains in the contact region according to Embodiment 1. [Figure 4] Figure 4 shows the shape of the crystal grains in the contact region according to Embodiment 1. [Figure 5] Figure 5 shows an example of a current supply configuration for a semiconductor light-emitting element according to Embodiment 1. [Figure 6] Figure 6 shows an overview of the current path in the pad layer of a comparative example semiconductor light-emitting device. [Figure 7] Figure 7 is a diagram illustrating the current path in the pad layer according to Embodiment 1. [Figure 8] Figure 8 is a diagram illustrating the method for measuring the average particle size. [Figure 9] Figure 9 is a cross-sectional view showing the first step of the method for manufacturing a semiconductor light-emitting element according to Embodiment 1. [Figure 10] Figure 10 is a cross-sectional view showing the second step of the method for manufacturing a semiconductor light-emitting element according to Embodiment 1. [Figure 11] Figure 11 is a cross-sectional view showing the third step of the method for manufacturing a semiconductor light-emitting element according to Embodiment 1. [Figure 12] Figure 12 is a cross-sectional view showing the fourth step of the method for manufacturing a semiconductor light-emitting element according to Embodiment 1. [Figure 13]FIG. 13 is a cross-sectional view showing the fifth step of the method for manufacturing a semiconductor light-emitting device according to Embodiment 1. [Figure 14] FIG. 14 is a cross-sectional view showing the sixth step of the method for manufacturing a semiconductor light-emitting device according to Embodiment 1. [Figure 15] FIG. 15 is a cross-sectional view showing the seventh step of the method for manufacturing a semiconductor light-emitting device according to Embodiment 1. [Figure 16] FIG. 16 is a cross-sectional view showing the eighth step of the method for manufacturing a semiconductor light-emitting device according to Embodiment 1. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the overall configuration of a light-emitting module according to Embodiment 2. [Figure 18] FIG. 18 is a flowchart showing the process of the method for manufacturing a light-emitting module according to Embodiment 2. [Figure 19] FIG. 19 is a schematic cross-sectional view for explaining the preparation step of the light-emitting module according to Embodiment 2. [Figure 20] FIG. 20 is a graph showing the distribution of Sn intensity obtained by EDX (Energy Dispersive X-ray Spectroscopy) analysis on a straight line along the thickness direction of the first bonding region according to Embodiment 2. [Figure 21] FIG. 21 is a graph showing the distribution of Sn intensity obtained by EDX analysis on a straight line along the thickness direction of the second bonding region according to Embodiment 2. [Figure 22] FIG. 22 is a graph showing the distribution of the average Sn intensity obtained by EDX analysis in a region along the thickness direction of the first bonding region according to Embodiment 2. [Figure 23] FIG. 23 is a graph showing the distribution of the average Sn intensity obtained by EDX analysis in a region along the thickness direction of the second bonding region according to Embodiment 2.

Embodiments for Carrying Out the Invention

[0011] The embodiments of this disclosure will be described below with reference to the drawings. The embodiments described below are all specific examples of this disclosure. Therefore, the numerical values, shapes, materials, components, and their arrangement and connection configurations shown in the following embodiments are examples only and are not intended to limit this disclosure.

[0012] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, the scale and other aspects may not necessarily be consistent across all figures. In addition, the same reference numerals are used for substantially identical components in each figure, and redundant explanations are omitted or simplified.

[0013] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in contact with each other.

[0014] (Embodiment 1) A semiconductor light-emitting element according to Embodiment 1 will be described.

[0015] [1-1. Overall Structure] First, the overall configuration of the semiconductor light-emitting element according to this embodiment will be described using Figures 1 and 2. Figures 1 and 2 are schematic plan and cross-sectional views, respectively, showing the overall configuration of the semiconductor light-emitting element 10 according to this embodiment. Figure 2 shows a cross-section along line II-II in Figure 1. Note that each figure shows mutually orthogonal X, Y, and Z axes. The X, Y, and Z axes are in a right-handed Cartesian coordinate system. The stacking direction of the semiconductor light-emitting element 10 is parallel to the Z-axis direction, and the main emission direction of light (laser light in this embodiment) is parallel to the Y-axis direction.

[0016] As shown in Figure 2, the semiconductor light-emitting element 10 comprises a semiconductor stack 10S and emits light from an end face 10F (see Figure 1) perpendicular to the stacking direction (i.e., the Z-axis direction) of the semiconductor stack 10S. In this embodiment, the semiconductor light-emitting element 10 is a nitride semiconductor laser element having two end faces 10F and 10R that form a resonator. End face 10F is the front end face from which the laser light is emitted, and end face 10R is the rear end face with a higher reflectivity than end face 10F. In this embodiment, the reflectivity of end faces 10F and 10R is 6% and 98%, respectively. The semiconductor light-emitting element 10 also has a waveguide formed between end face 10F and end face 10R. The resonator length of the semiconductor light-emitting element 10 according to this embodiment (i.e., the distance between end face 10F and end face 10R) is approximately 1000 μm. The semiconductor light-emitting element 10 also emits blue-violet light having a peak wavelength in the 405 nm band, for example.

[0017] As shown in Figure 2, the semiconductor light-emitting element 10 comprises a substrate 21, a semiconductor laminate 10S, an insulating layer 30, an adhesion auxiliary layer 32, a contact electrode 40, a pad layer 50, and an N-side electrode 60.

[0018] The substrate 21 is a plate-shaped member that serves as the base for the semiconductor light-emitting element 10. In this embodiment, the substrate 21 is an N-type GaN substrate.

[0019] The semiconductor laminate 10S is a laminate containing a nitride semiconductor. The semiconductor laminate 10S has a plurality of semiconductor layers stacked in the stacking direction (i.e., the Z-axis direction in each figure). In this embodiment, the semiconductor laminate 10S has an N-side semiconductor layer 22, an active layer 23, a P-side semiconductor layer 24, and a contact layer 25.

[0020] The N-side semiconductor layer 22 is an example of a first-conductivity type first semiconductor layer located above the substrate 21 and below the active layer 23. The N-side semiconductor layer 22 includes a nitride semiconductor. In this embodiment, the N-side semiconductor layer 22 includes an N-type cladding layer with a lower refractive index than the active layer 23. The N-side semiconductor layer 22 is, for example, an N-type AlGaN layer. The N-side semiconductor layer 22 may also include layers other than the N-type cladding layer. The N-side semiconductor layer 22 may include, for example, a buffer layer, an optical guide layer, and the like.

[0021] The active layer 23 is a light-emitting layer positioned above the N-side semiconductor layer 22. In this embodiment, the active layer 23 contains a nitride semiconductor and has a quantum well structure. The active layer 23 may have a single quantum well or a plurality of quantum wells. In this embodiment, the active layer 23 has a plurality of barrier layers made of InGaN and a plurality of well layers made of InGaN.

[0022] The P-side semiconductor layer 24 is an example of a second semiconductor layer of second conductivity type, positioned above the active layer 23. The P-side semiconductor layer 24 includes a nitride semiconductor. In this embodiment, the P-side semiconductor layer 24 includes a P-type cladding layer with a lower refractive index than the active layer 23. The P-side semiconductor layer 24 is, for example, a P-type AlGaN layer. The P-side semiconductor layer 24 may also include layers other than the P-type cladding layer. The P-side semiconductor layer 24 may include, for example, an optical guide layer, an electron barrier layer, etc. Furthermore, the P-side semiconductor layer 24 may have a superlattice structure.

[0023] A ridge 24R is formed in the P-side semiconductor layer 24. The ridge 24R is a portion of the P-side semiconductor layer 24 that protrudes in the Z-axis direction and extends in the Y-axis direction. In addition, two grooves 24T are formed in the P-side semiconductor layer 24, arranged along the ridge 24R and extending in the Y-axis direction. In this embodiment, the ridge width (i.e., the dimension of the ridge 24R in the X-axis direction) is approximately 30 μm. The dotted line in Figure 1 corresponds to the position of the side surface (not visible from the top surface) of the groove 24T.

[0024] The contact layer 25 is positioned above the P-side semiconductor layer 24 and is a layer that makes ohmic contact with the contact electrode 40. In this embodiment, the contact layer 25 is a P-type GaN layer.

[0025] The insulating layer 30 is an electrically insulating layer disposed between the semiconductor laminate 10S and the pad layer 50. The insulating layer 30 has an opening (or slit) at a position corresponding to the upper surface of the ridge 24R. In this embodiment, the insulating layer 30 is disposed in the area of ​​the upper surface of the P-side semiconductor layer 24 other than the upper surface of the ridge 24R. The insulating layer 30 may also be disposed in a part of the upper surface of the ridge 24R. The material forming the insulating layer 30 is not particularly limited as long as it is an insulating material. In this embodiment, the insulating layer 30 is made of SiO2.

[0026] The adhesion auxiliary layer 32 is a layer positioned above the insulating layer 30. The adhesion auxiliary layer 32 is positioned between the insulating layer 30 and the pad layer 50 and has the function of improving the adhesion between the pad layer 50 and the insulating layer 30. The adhesion auxiliary layer 32 has an opening (or slit) at a position corresponding to the opening of the insulating layer 30. In this embodiment, in a top view of the substrate 21, the opening of the insulating layer 30 is positioned inside the opening of the adhesion auxiliary layer 32. The adhesion auxiliary layer 32 may contain at least one of Ti and Cr. If the adhesion auxiliary layer 32 contains Ti and the insulating layer 30 is an oxide, the adhesion between the adhesion auxiliary layer 32 and the insulating layer 30 can be further improved. This is because, when the insulating layer 30 is an oxide, if the adhesion auxiliary layer 32, which is made of a metal film, is also a material that easily forms oxides, they bond strongly. In this embodiment, the adhesion auxiliary layer 32 has a laminated structure including a Ti film positioned on the insulating layer 30 and a Pt film positioned on the Ti film.

[0027] The contact electrode 40 is an electrode positioned above the semiconductor laminate 10S. The contact electrode 40 is positioned above the contact layer 25, facing the contact layer 25 and in contact with the contact layer 25. In this embodiment, the contact electrode 40 is positioned above the ridge 24R. The contact electrode 40 is, for example, a monolayer or multilayer film formed of at least one of Ag, Ni, Pd, Cr, and Pt, or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or InGaZnO. x A transparent conductive film made of a transparent metal oxide such as (IGZO) may also be used. In this embodiment, the contact electrode 40 has a Pd layer in contact with the contact layer 25, Pd It has a Pt layer positioned above the layer.

[0028] The pad layer 50 is a conductive layer positioned above the contact electrode 40 and in contact with the contact electrode 40. The pad layer 50 contains Au. In this embodiment, the pad layer 50 is an Au layer with a thickness of approximately 4 μm. The detailed configuration of the pad layer 50 will be described later.

[0029] The N-side electrode 60 is a conductive layer located on the lower surface of the substrate 21 (i.e., the main surface opposite to the main surface on which the semiconductor laminate 10S of the substrate 21 is placed). The N-side electrode 60 is, for example, a single-layer or multi-layer film formed of at least one of Cr, Ti, Ni, Pd, and Pt, and a pad layer made of Au is formed on the N-side electrode 60.

[0030] [1-2. Detailed configuration and effects of the pad layer] Next, the detailed configuration and effects of the pad layer 50 according to this embodiment will be described.

[0031] As shown in Figure 2, the pad layer 50 has a contact area 51 and an outer area 52.

[0032] The contact region 51 is a region of the pad layer 50 located above the region where the pad layer 50 and the contact electrode 40 are in contact. The contact region 51 has a first layer 51a located above the region where the pad layer 50 and the contact electrode 40 are in contact, and a second layer 51b located above the first layer 51a and in contact with the first layer 51a. In this embodiment, the insulating layer 30 is not located in the region between the semiconductor laminate 10S and the pad layer 50, specifically in the region between the semiconductor laminate 10S and the first layer 51a.

[0033] Next, the crystal shapes of the first layer 51a and the second layer 51b will be described using Figures 3 and 4. Figure 3 is a transmission electron microscope (TEM) image showing the crystal shape of the contact region 51 according to this embodiment. In Figure 3, the shape of the crystal grains in a cross-section parallel to the stacking direction of the contact region 51 is shown. Figure 4 is a diagram showing the shape of the crystal grains of the contact region 51 according to this embodiment. Figure 4 shows a schematic diagram (a) of the crystal grain boundaries in a cross-section corresponding to the TEM image shown in Figure 3, and a graph (b) showing the distribution of average grain size in the stacking direction. Graph (b) in Figure 4 shows the average grain size in a direction parallel to the main surface of the contact electrode 40 (i.e., a direction parallel to the XY plane in each figure). Hereinafter, the direction parallel to the main surface of the contact electrode 40 will also be referred to as the "horizontal direction," and the direction perpendicular to it will also be referred to as the "vertical direction."

[0034] In this embodiment, the first layer 51a is an Au layer with a thickness of approximately 0.9 μm, and as shown in schematic diagram (a) of Figures 3 and 4, the Au crystal grains in the first layer 51a are so-called granular, with an aspect ratio of 0.5 or more and 2 or less in the horizontal to vertical direction of grain size. The second layer 51b is an Au layer with a thickness of approximately 0.7 μm, and as shown in schematic diagram (a) of Figures 3 and 4, the Au crystal grains in the second layer 51b are columnar. Each crystal in the second layer 51b extends in the stacking direction (i.e., the Z-axis direction in each figure). In the horizontal direction, the average grain size (i.e., average crystal grain size) of Au in the second layer 51b is the same as that of the first layer 51aThe average particle size of Au is larger than that of the first layer 51a. In this embodiment, in the horizontal direction, the average particle size of Au in the first layer 51a is about 60 nm, and in the second layer 51b, the average particle size of Au is about 150 nm. Here, since the electrical resistivity decreases as the average particle size of Au increases, in the horizontal direction, the electrical resistivity of the second layer 51b is lower than that of the first layer 51a.

[0035] The average particle size of Au in the first layer 51a, when the direction of the particle size is not specified, is approximately 60 nm, and the average particle size of Au in the second layer 51b, when the direction of the particle size is not specified, is approximately 320 nm. Hereafter, when the direction is not specified, the "average value when the direction of the particle size is not specified" will also be simply referred to as "average particle size." The method for measuring the average particle size of Au will be described later. As described above, the average particle size of Au in the second layer 51b is larger than the average particle size in the first layer 51a, so the electrical resistivity of the second layer 51b is lower than that of the first layer 51a.

[0036] The outer region 52 shown in Figure 2 is the region of the pad layer 50 located above the insulating layer 30. In this embodiment, the outer region 52 has a region that is directly connected to (i.e., in contact with) the insulating layer 30 and a region that is connected to the insulating layer 30 via the adhesion auxiliary layer 32. In this embodiment, the shape of the Au crystal grains in the outer region 52 is more random than that of the first layer 51a. The average grain size of Au in the outer region 52 is larger than that of Au in the first layer 51a and smaller than that of Au in the second layer 51b. In this embodiment, the average grain size of Au in the outer region 52 is approximately 100 nm.

[0037] The effects of the pad layer 50 according to this embodiment will be explained in comparison with the comparative example. First, the current supply mode of the semiconductor light-emitting element 10 will be explained using Figure 5. Figure 5 is a diagram showing an example of the current supply mode of the semiconductor light-emitting element 10 according to this embodiment.

[0038] As shown in Figure 5, one example of a current supply method for the semiconductor light-emitting element 10 is to connect a wire 90 to the pad layer 50 by bonding. The wire 90 is a conductive linear member and contains, for example, Au as a conductive material. As shown in Figure 5, the wire 90 is placed in the outer region 52 of the upper surface of the pad layer 50, excluding the area above the ridge 24R of the semiconductor light-emitting element 10. This suppresses damage caused by bonding to the ridge 24R and the layers located above and below the ridge 24R. Furthermore, in this embodiment, the shape of the Au crystal grains in the outer region 52 is more random than that of the first layer 51a, and the average grain size of Au is larger than that of the first layer 51a, so the outer region 52 has lower hardness than the first layer 51a. Therefore, by bonding the wire 90 to the outer region 52, damage caused by bonding to the semiconductor laminate 10S can be suppressed.

[0039] The current path in the semiconductor light-emitting element 10 when using the current supply method shown in Figure 5 will be explained using Figures 6 and 7, in comparison with the comparative example. Figure 6 is a diagram showing the outline of the current path in the pad layer 950 of the semiconductor light-emitting element of the comparative example. Figure 7 is a diagram showing the outline of the current path in the pad layer 50 according to this embodiment. Figures 6 and 7 show the regions corresponding to the dashed lines shown in Figure 5. In Figures 6 and 7, the outline of the electron movement path is shown by dashed arrows.

[0040] The comparative nitride semiconductor light-emitting element shown in Figure 6 differs from the semiconductor light-emitting element 10 according to this embodiment in the configuration of the pad layer 950, but is the same in other configurations. The comparative pad layer 950 has a contact region 951 and an outer region 52. The contact region 951 of the comparative example has a crystal grain shape similar to the first layer 51a of the contact region 51 according to this embodiment. In other words, the crystal grains of Au in the contact region 951 of the comparative example are granular. The average particle size of Au in the contact region 951 of the comparative example is approximately 60 nm.

[0041] Because the average particle size of Au in the contact region 951 of the comparative example semiconductor light-emitting element is small, the electrical resistivity in the contact region 951 is relatively large. Therefore, as shown in Figure 6, in the comparative example semiconductor light-emitting element, electrons move along paths that have a short distance to pass through the contact region 951. In other words, the current path is concentrated in the region near the end of the ridge 24R that is closer to the bonding position of the wire 90. Consequently, in the comparative example semiconductor light-emitting element, there is a bias in the emission intensity distribution in the width direction of the ridge 24R, making degradation more likely to progress near the peak position of the emission intensity of the active layer 23.

[0042] In contrast, the semiconductor light-emitting element 10 according to this embodiment has a second layer 51b in which the contact region 51 of the pad layer 50 is positioned above the first layer 51a. Since the average particle size of Au in the horizontal direction in the second layer 51b is larger than the average particle size of Au in the horizontal direction in the first layer 51a, the electrical resistivity of the second layer 51b in the horizontal direction is smaller than the electrical resistivity of the first layer 51a in the horizontal direction. In other words, with the semiconductor light-emitting element 10 according to this embodiment, the electrical resistance of the electrode including the pad layer 50 can be reduced compared to the electrical resistance of the electrode in the comparative example. As a result, electrons can move more easily in the horizontal direction in the second layer 51b. Therefore, as shown in Figure 7, the current path can be dispersed in the width direction of the ridge 24R. In other words, with the semiconductor light-emitting element 10 according to this embodiment, the light emission intensity distribution in the width direction of the ridge 24R can be made uniform. As a result, the progression of localized degradation of the active layer 23 can be suppressed.

[0043] Furthermore, in this embodiment, since the Au crystal grains in the second layer 51b are columnar and extend in the stacking direction, the electrical resistivity in the stacking direction of the second layer 51b can also be reduced. Therefore, the electrical resistance in the pad layer 50 can be further reduced.

[0044] As described above, the semiconductor light-emitting element 10 according to this embodiment can reduce the electrical resistance of the electrodes.

[0045] [1-3. Method for Measuring Average Grain Size] A method for measuring the average grain size of Au in the pad layer 50 will be described with reference to FIG. 8. FIG. 8 is a diagram for explaining the method for measuring the average grain size. In the present embodiment, after forming a cross section of the pad layer 50 using a focused ion beam (FIB), the intercept method was applied to the observation region observed by a Scanning Ion Microscopy image (SIM image) using a scanning microscope to measure the crystal grain size.

[0046] At this time, as shown in FIG. 8, when there are Ng crystal grains having an average grain size d in a square with a side length of L, the area of the square is L 2 and the area of one crystal grain is π(d / 2) 2 When the observation region is relatively large with respect to the crystal grains, since there are Ng 2 crystal grains in the square, the total area occupied by all the crystal grains is Ng 2 ×π(d / 2) 2 Since the area of the square = the total area occupied by all the crystal grains, L 2 = Ng 2 ×π(d / 2) 2 When this is expressed in terms of d, d = 2L / Ng / (π) 1 / 2 is represented by this relational expression. Using this relational expression, a straight line (dashed line in FIG. 8) was drawn in the observation region L×L, and the average grain size d in the horizontal direction and the stacking direction of the pad layer 50 was obtained by taking the number of grain boundaries intersecting this straight line as the number of crystals Ng. In FIG. 8, since the dashed line intersects six grain boundaries, Ng = 6. When the direction of the average grain size is not specified, the average value can be obtained by taking the geometric mean of the average grain size in the horizontal direction and the average grain size in the stacking direction.

[0047] [1-4. Manufacturing Method] A method for manufacturing the semiconductor light-emitting device 10 according to the present embodiment will be described with reference to FIGS. 2 and 9 to 16. Each of FIGS. 9 to 16 is a cross-sectional view showing each step of the manufacturing method of the semiconductor light-emitting device 10 according to the present embodiment. FIGS. 9 to 16 show the same cross section as FIG. 2.

[0048] First, a substrate 21 is prepared as shown in Figure 9. In this embodiment, a wafer made of N-type GaN (GaN substrate) is prepared as the substrate 21. Next, the N-side semiconductor layer 22, the active layer 23, the P-side semiconductor layer 24, and the contact layer 25 are sequentially stacked on the substrate 21 using epitaxial growth technology by the MOCVD (Metal Organic Chemical Vapor Deposition) method. This allows for the formation of a semiconductor laminate 10S.

[0049] Next, as shown in Figure 10, element isolation grooves 10D are formed to separate the semiconductor light-emitting element 10 into individual components. The element isolation grooves 10D are formed at positions corresponding to both ends of the semiconductor light-emitting element 10 in the X-axis direction. In this embodiment, the element isolation grooves 10D extend from the upper surface of the semiconductor laminate 10S to the interior of the N-side semiconductor layer 22. The method for forming the element isolation grooves 10D is not particularly limited. The element isolation grooves 10D may be formed, for example, using photolithography and etching, or by laser processing.

[0050] Next, as shown in Figure 11, a ridge 24R is formed. In this embodiment, the ridge 24R is formed by forming two grooves 24T in the semiconductor laminate 10S. Each of the two grooves 24T extends from the top surface of the semiconductor laminate 10S into the interior of the P-side semiconductor layer 24. Groove 24T The method of formation is not particularly limited. Groove 24T These are formed, for example, using photolithography and etching techniques.

[0051] Next, as shown in Figure 12, an insulating layer 30 is formed on the upper surface of the semiconductor laminate 10S. In this embodiment, an SiO2 film is formed as the insulating layer 30 using a method such as plasma CVD (Chemical Vapor Deposition). This forms an insulating layer 30 made of amorphous SiO2.

[0052] Next, as shown in Figure 13, the insulating layer 30 located above the ridge 24R is removed using photolithography and etching, and then a contact electrode 40 is formed on the contact layer 25 of the ridge 24R. In this embodiment, a Pd layer and a Pt layer are formed as the contact electrode 40. The contact electrode 40 is formed only above the ridge 24R, for example, using photolithography and vapor deposition.

[0053] Next, as shown in Figure 14, an adhesion auxiliary layer 32 is formed. Specifically, an adhesion auxiliary layer 32 consisting of a Ti film and a Pt film is formed on the insulating layer 30 using photolithography and vapor deposition techniques. Since the insulating layer 30 is amorphous SiO2, the adhesion auxiliary layer 32 has a more random grain shape than the Ti film and Pt film formed on a single crystal.

[0054] Next, as shown in Figure 15, a portion of the pad layer 50 is formed. Specifically, the temperature of the substrate 21 is maintained at approximately 100°C, and an Au film is formed on the contact electrode 40 and the insulating layer 30 by vapor deposition. As a result, a first layer 51a having granular, small crystal grains is formed on the contact electrode 40. On the other hand, a portion of the external region 52 is formed on the insulating layer 30 and the adhesion auxiliary layer 32. Since the insulating layer 30 is amorphous SiO2, the external region 52 formed on the insulating layer 30 has a random crystal grain shape and becomes an Au film with many defects such as intergranular voids. Also, since the adhesion auxiliary layer 32 has a random crystal grain shape similar to the insulating layer 30, the external region 52 formed on the adhesion auxiliary layer 32 also has a random crystal grain shape and becomes an Au film with many defects such as intergranular voids.

[0055] Next, the remaining portion of the pad layer 50 is formed, as shown in Figure 16. Specifically, after forming a portion of the pad layer 50 as shown in Figure 15, the formation is interrupted and the temperature of the substrate 21 is temporarily lowered to approximately 50°C. Subsequently, the formation of the Au film is resumed. At this time, the temperature of the substrate 21 may rise as the Au deposition progresses. As a result, Au grows epitaxially on the first layer 51a. This makes it possible to form a second layer 51b having columnar crystal grains, in which the average grain size of Au in the horizontal direction is larger than the average grain size of Au in the horizontal direction in the first layer 51a. The average grain size of the columnar crystal grains can be made the largest, especially when the contact electrode 40 is Pd.

[0056] Next, as shown in Figure 2, the N-side electrode 60 is formed on the lower surface of the substrate 21. Specifically, the N-side electrode 60 is formed by sequentially forming a Ti film, a Pt film, and an Au film using photolithography and vapor deposition techniques.

[0057] The semiconductor light-emitting element 10 according to this embodiment can be manufactured using the manufacturing method described above.

[0058] (Embodiment 2) A light-emitting module according to Embodiment 2 and a method for manufacturing the same will be described. The light-emitting module according to this embodiment is a module manufactured using a semiconductor light-emitting element according to Embodiment 1.

[0059] [2-1. Overall Structure] The overall configuration of the light-emitting module according to this embodiment will be explained with reference to Figure 17. Figure 17 is a schematic cross-sectional view showing the overall configuration of the light-emitting module 12 according to this embodiment.

[0060] As shown in Figure 17, the light-emitting module 12 comprises a semiconductor light-emitting element 110 and a base 80. The light-emitting module 12 is a module obtained by junction-down mounting the semiconductor light-emitting element 10 according to Embodiment 1 onto the base 80. The manufacturing method of the light-emitting module 12 will be described later.

[0061] The base 80 is a component to which the semiconductor light-emitting element 110 is bonded. In this embodiment, the base 80 is a submount on which the semiconductor light-emitting element 110 is mounted. The base 80 has a rectangular plate shape. As the base 80, for example, a ceramic substrate, polycrystalline substrate, or single-crystal substrate made of alumina, AlN, SiC, diamond, etc., can be used. Note that the base 80 is not limited to a submount. The base 80 may also be a mounting substrate on which the semiconductor light-emitting element 110 is mounted.

[0062] The semiconductor light-emitting element 110 according to this embodiment comprises a substrate 21, a semiconductor laminate 10S, a contact electrode 40, an adhesion auxiliary layer 32, a bonding layer 70, and an N-side electrode 60. The semiconductor light-emitting element 110 differs from the semiconductor light-emitting element 10 according to Embodiment 1 in that it comprises a bonding layer 70 instead of a pad layer 50, but is otherwise identical.

[0063] The contact electrode 40 according to this embodiment is placed between the semiconductor laminate 10S and the base 80. The insulating layer 30 according to this embodiment is placed between the semiconductor laminate 10S and the bonding layer 70.

[0064] The bonding layer 70 is bonded to the contact electrode 40 of the semiconductor light-emitting element 110 and the base 80, and is a layer containing AuSn. The bonding layer 70 has a first bonding region 71 positioned opposite to the area where the bonding layer 70 and the contact electrode 40 are in contact, and a second bonding region 72 positioned opposite to the insulating layer 30. In this embodiment, the adhesion auxiliary layer 32 is positioned between the second bonding region 72 and the insulating layer 30. The bonding layer 70 bonds the contact electrode 40, the insulating layer 30, the adhesion auxiliary layer 32, and the base 80.

[0065] [2-2. Manufacturing method] The manufacturing method of the light-emitting module 12 according to this embodiment will be described with reference to Figures 18 and 19. Figure 18 is a flowchart showing the flow of the manufacturing method of the light-emitting module 12 according to this embodiment. Figure 19 is a schematic cross-sectional view illustrating the preparation process of the light-emitting module 12 according to this embodiment.

[0066] First, as shown in Figure 19, the semiconductor light-emitting element 10 according to Embodiment 1 and the base 80 are prepared (preparation step S10 in Figure 18). In this embodiment, a bonding material 56 is placed on one main surface of the base 80. In this embodiment, the bonding material 56 is a component that bonds the base 80 and the pad layer 50 of the semiconductor light-emitting element 10 in the bonding step S20 described later. In this embodiment, the bonding material 56 is solder containing AuSn.

[0067] Next, as shown in Figure 18, the semiconductor light-emitting element 10 is bonded to the base 80 using a bonding material 56 containing AuSn (bonding step S20). Bonding step S20 includes a placement step S21, a first heating step S22, a first cooling step S23, a second heating step S24, and a second cooling step S25.

[0068] In bonding step S20, first, the semiconductor light-emitting element 10 is placed on the base 80 (placement step S21). Specifically, with the pad layer 50 of the semiconductor light-emitting element 10 shown in Figure 19 facing the bonding material 56 placed on the base 80, the semiconductor light-emitting element 10 is moved toward the base 80, and the pad layer 50 of the semiconductor light-emitting element 10 is brought into contact with the bonding material 56 placed on the base 80.

[0069] After the configuration step S21, as shown in FIG. 18, the base 80 is heated to a first peak temperature T1 higher than the melting point Tm of the bonding material 56 to melt the bonding material 56 (first heating step S22). Specifically, the base 80 is placed on a heater, and the base 80 is heated by raising the temperature of the heater. In this first heating step S22, before the temperature of the base 80 reaches the melting point Tm of the bonding material 56, the application of a load to the semiconductor light emitting element 10 is started, thereby pressing the semiconductor light emitting element 10 against the base 80. As a result, after the bonding material 56 melts, the contact area between the surface of the semiconductor light emitting element 10 facing the bonding material 56 and the bonding material 56 can be increased. In other words, the formation of voids between the semiconductor light emitting element 10 and the bonding material 56 can be suppressed.

[0070] Subsequently, as shown in FIG. 18, after the first heating step S22, the temperature of the base 80 is lowered to a switching temperature Tv which is lower than the melting point Tm of the bonding material 56 (first temperature lowering step S23). In this first temperature lowering step S23, before the temperature of the base 80 reaches the melting point Tm of the bonding material 56, the application of a load to the semiconductor light emitting element 10 is stopped. The temperature at which the application of the load is stopped does not necessarily have to be higher than the melting point Tm, and may be a temperature lower than the melting point Tm.

[0071] After the first temperature lowering step S23, the base 80 is heated to a second peak temperature T2 higher than the melting point Tm of the bonding material 56 to melt the bonding material 56 again (second heating step S24). Here, the first peak temperature T1, the second peak temperature T2, and the melting point Tm of the bonding material 56 satisfy the relationship of Tm < T1 < T2.

[0072] After the second heating step S24, the temperature of the base 80 is lowered to a temperature lower than the melting point Tm of the bonding material 56 (second temperature lowering step S25). Here, the temperature of the base 80 is lowered to the temperature before the first heating step S22 is performed (that is, the standby temperature).

[0073] Second heating step S24 and the second temperature lowering step S25 In this case, a load may or may not be applied to the semiconductor light emitting element 10.

[0074] Through the process described above, a light-emitting module 12 as shown in Figure 17 can be manufactured. In the light-emitting module 12, a bonding layer 70 is formed in which the pad layer 50 of the semiconductor light-emitting element 10 and the bonding material 56 are integrated. Specifically, Sn contained in the bonding material 56 diffuses into the pad layer 50 made of Au, forming a bonding layer 70 containing AuSn.

[0075] [2-3. Effects] The effects of the light-emitting module 12 according to this embodiment will be described.

[0076] As described above, the bonding layer 70 of the light-emitting module 12 according to this embodiment is a layer in which the pad layer 50 of the semiconductor light-emitting element 10 according to Embodiment 1 and the bonding material 56 are integrated. The first bonding region 71 and the second bonding region 72 of the bonding layer 70 correspond to the contact region 51 and the outer region 52 of the pad layer 50, respectively. In other words, the first bonding region 71 is formed from the contact region 51 and a part of the bonding material 56, and the second bonding region 72 is formed from the outer region 52 and another part of the bonding material 56. Due to the difference in the shape of the crystal grains between the contact region 51 and the outer region 52, the distribution of Sn differs between the first bonding region 71 and the second bonding region 72. The distribution of Sn in the first bonding region 71 and the second bonding region 72 will be explained below with reference to Figures 20 to 23. Figures 20 and 21 are graphs showing the distribution of Sn intensity obtained by EDX (Energy Dispersive X-ray Spectroscopy) analysis along a straight line along the thickness direction (i.e., the Z-axis direction in each figure) of the first bonding region 71 and the second bonding region 72 according to this embodiment. Figures 22 and 23 are graphs showing the distribution of average Sn intensity obtained by EDX analysis in the region along the thickness direction of the first bonding region 71 and the second bonding region 72 according to this embodiment. The horizontal axis in each figure indicates the position in the thickness direction. As the value on the horizontal axis increases, the position approaches the base 80, and as the value on the horizontal axis decreases, the position approaches the semiconductor laminate 10S. The average Sn intensity in Figures 22 and 23 is the Sn intensity in the region corresponding to the dashed frame R1 and R2 in Figure 17, respectively. The dashed frame R1 and R2 are regions where the length in the thickness direction and the length in the X-axis direction of the bonding layer 70 are each 5 μm. The Sn strength and average Sn strength in Figures 20 to 23 correspond to the Sn content at each position in the thickness direction of the bonded layer 70 and the average Sn content.

[0077] In this embodiment, in the region of the first bonding region 71 of the bonding layer 70 that corresponds to the second layer 51b of the pad layer 50, the shape of the Au crystal grains is columnar, so Sn easily diffuses in the thickness direction. For this reason, as shown in Figures 20 and 22, the region of the first bonding region 71 that corresponds to the second layer 51b of the pad layer 50 has a high Sn content. By increasing the Sn content in the region of the bonding layer 70 that corresponds to the pad layer 50 in this way, the bonding strength between the bonding layer 70 and the base 80 can be increased. Therefore, the detachment of the semiconductor light-emitting element 110 from the base 80 can be suppressed.

[0078] Furthermore, in the region of the first bonding region 71 of the bonding layer 70 that corresponds to the first layer 51a of the pad layer 50, the Au crystals are granular, and the average particle size is smaller than the average particle size of Au in the second layer 51b, so Sn is less likely to diffuse in this region than in the region corresponding to the second layer 51b. For this reason, as shown in Figures 20 and 22, the Sn content is low in the region of the first bonding region 71 that corresponds to the first layer 51a of the pad layer 50. For this reason, as shown in Figure 20, the Sn content increases in a stepwise manner along a straight line in the thickness direction of the first bonding region 71 as you move away from the contact electrode 40. Also, as shown in Figure 22, in the region along the thickness direction of the first bonding region 71, the first bonding region 71 has a first transition region Rg1 in which the average Sn content gradually increases as you move away from the contact electrode 40. Thus, by the first bonding region 71 becoming a first transition region Rg1 where the average Sn content gradually increases, abrupt changes in the Sn content in the thickness method can be suppressed, and therefore abrupt changes in the thermal expansion coefficient in the region where the Sn content changes can be suppressed. Consequently, failure of the first bonding region 71 due to temperature changes can be suppressed.

[0079] Here, when Sn reaches the contact layer 25 via the contact electrode 40 in contact with the first junction region 71, the contact resistance between the contact layer 25 and the contact electrode 40 increases. In this embodiment, the diffusion of Sn is suppressed by the region of the first junction region 71 that corresponds to the first layer 51a of the pad layer 50, thus suppressing the diffusion of Sn into the contact layer 25. Therefore, the increase in contact resistance between the contact layer 25 and the contact electrode 40 can be suppressed. In other words, the electrical resistance of the electrodes, including the contact electrode 40 and the junction layer 70 of the semiconductor light-emitting element 110, can be reduced.

[0080] As described above, in the light-emitting module 12 according to this embodiment, the average Sn content in the region of the first bonding region 71 that is closer to the contact electrode 40 than the center in the thickness direction of the first bonding region 71 is less than the average Sn content in the region of the first bonding region 71 that is further from the contact electrode 40 than the center. This makes it possible to suppress an increase in contact resistance between the contact layer 25 and the contact electrode 40.

[0081] The second junction region 72 corresponds to the outer region 52 of the pad layer 50, which has many defects such as intergranular voids in Au, and therefore Sn diffuses easily there. As a result, as shown in Figures 21 and 23, a large amount of Sn diffuses to the end of the second junction region 72 that is close to the insulating layer 30. Therefore, the bonding strength between the junction layer 70 and the base 80 can be increased. Consequently, the detachment of the semiconductor light-emitting element 110 from the base 80 can be suppressed.

[0082] Furthermore, as shown in Figure 21, the Sn content in the center of the second bonding region 72 in the thickness direction is less than the Sn content at both ends of the second bonding region 72 in the thickness direction. Thus, the high average Sn content not only at the base 80 side end of the second bonding region 72 in the thickness direction, but also at the insulating layer 30 side end, is presumed to be due to the presence of grain boundaries or defects in the second bonding region 72 that allow Sn to diffuse particularly easily locally. It is thought that Sn rapidly diffuses from the base 80 side end of the second bonding region 72 in the thickness direction to the vicinity of the insulating layer 30 side end via localized grain boundaries or defects, and then diffuses horizontally near the insulating layer 30 side end. Also, since grain boundaries or defects only exist locally in the center of the second bonding region 72 in the thickness direction, it is presumed that the average Sn content in the center of the second bonding region 72 in the thickness direction is not so high.

[0083] Furthermore, as shown in Figure 23, in the region along the thickness direction of the second bonding region 72, the second bonding region 72 has a second transition region Rg2 in which the average Sn content gradually increases as it moves away from the insulating layer 30. In this way, by the second bonding region 72 having a second transition region Rg2 in which the average Sn content gradually increases, abrupt changes in the Sn content in the thickness method can be suppressed, and thus abrupt changes in the coefficient of thermal expansion in the region where the Sn content changes can be suppressed. Therefore, damage to the second bonding region 72 due to temperature changes can be suppressed.

[0084] (Torture, etc.) The semiconductor light-emitting elements and the like related to this disclosure have been described above based on various embodiments, but this disclosure is not limited to the above embodiments.

[0085] The average particle size of the first layer 51a and the second layer 51b of the pad layer 50 of the semiconductor light-emitting element 10 according to Embodiment 1 is not limited to the values ​​described above. In the horizontal direction, the average particle size of Au in the first layer 51a may be 30 nm or more and 80 nm or less, and the average particle size of Au in the second layer 51b may be 120 nm or more and 200 nm or less. When the direction is not specified, the average particle size of Au in the first layer 51a may be 30 nm or more and 80 nm or less, and the average particle size of Au in the second layer 51b may be 240 nm or more and 630 nm or less.

[0086] Furthermore, in the semiconductor light-emitting element 10 according to Embodiment 1, the thicknesses of the first layer 51a and the second layer 51b of the pad layer 50 were approximately the same, but the relative relationship between the thicknesses of the first layer 51a and the second layer 51b is not limited to this. For example, the second layer 51b may be thicker than the first layer 51a. This increases the proportion of the second layer 51b, which has a lower electrical resistivity in the pad layer 50, and thus reduces the electrical resistivity of the pad layer 50.

[0087] Furthermore, although the above embodiments show examples where the semiconductor light-emitting element is a nitride semiconductor laser element, the semiconductor light-emitting element is not limited to a semiconductor laser element. For example, the semiconductor light-emitting element may be a superluminescent diode. In this case, the reflectance of the end face of the semiconductor laminate of the nitride semiconductor light-emitting element with respect to light emitted from the semiconductor laminate may be 0.1% or less. Such reflectance can be achieved, for example, by forming an anti-reflective film made of a dielectric multilayer film on the end face. Alternatively, if the ridge that forms the waveguide is tilted at 5° or more from the normal direction of the front end face and intersects the front end face, the proportion of the component in which the waveguided light reflected from the front end face re-couples with the waveguide and becomes waveguided light can be made to a small value of 0.1% or less. Furthermore, the semiconductor light-emitting element may also be a light-emitting diode.

[0088] Furthermore, this disclosure also includes forms obtained by applying various modifications to each of the above embodiments that a person skilled in the art could conceive, and forms realized by arbitrarily combining the components and functions of each of the above embodiments without departing from the spirit of this disclosure. [Industrial applicability]

[0089] The nitride semiconductor light-emitting element of this disclosure can be applied, for example, as a highly efficient light source for processing machines. [Explanation of symbols]

[0090] 10, 110 Nitride semiconductor light-emitting element 10D sections separation groove 10F, 10R end face 10S semiconductor stack 12 Light-emitting modules 21 circuit boards 22 N-side semiconductor layer 23 Active layer 24 P-side semiconductor layer 24R Ridge 24T groove 25 Contact Layer 30 Insulating layer 32 Adhesion support layer 40 Contact electrodes 50 pad layers 51 Contact Area 51a First layer 51b Second layer 52 External Area 56 Bonding material 60 N side electrode 70 Bonding layer 71 First joint area 72 Second joining area 80 base 90 wires

Claims

1. Semiconductor laminates and A contact electrode positioned above the semiconductor stack, Displaced above the aforementioned contact electrode, a pad layer containing Au is provided. The semiconductor laminate comprises an insulating layer disposed between the pad layer, The aforementioned pad layer is A first layer is disposed above the region where the pad layer and the contact electrode are in contact, It has a second layer positioned above the first layer and in contact with the first layer, In a direction parallel to the main surface of the contact electrode, the average particle size of Au in the second layer is greater than the average particle size of Au in the first layer. In the region between the semiconductor laminate and the pad layer, the insulating layer is not disposed in the region between the semiconductor laminate and the first layer. Semiconductor light-emitting element.

2. The shape of the Au crystal grains in the second layer is columnar. The semiconductor light-emitting element according to claim 1.

3. The pad layer includes an external region located above the insulating layer, The average particle size of Au in the outer region is greater than the average particle size of Au in the single layer. The semiconductor light-emitting element according to claim 1.

4. The electrical resistivity of the second layer is lower than that of the first layer. A semiconductor light-emitting element according to any one of claims 1 to 3.

5. The second layer is thicker than the first layer. A semiconductor light-emitting element according to any one of claims 1 to 4.

6. It is a light-emitting module, Semiconductor light-emitting element and The semiconductor light-emitting element is bonded to a base, The aforementioned semiconductor light-emitting device is Semiconductor laminates and A contact electrode is disposed between the semiconductor laminate and the base, The contact electrode and the base are bonded together, and a bonding layer containing AuSn is bonded to them, The semiconductor laminate and the bonding layer are disposed between the semiconductor laminate and the bonding layer, The aforementioned bonding layer is A first bonding region is positioned opposite the contact electrode, It has a second junction region positioned opposite the insulating layer, The average Sn content at the center of the second bonding region in the thickness direction is less than the average Sn content at both ends of the second bonding region in the thickness direction. Along a straight line in the thickness direction of the first bonding region, the Sn content increases in a stepwise manner as it moves away from the contact electrode. Light-emitting module.

7. It is a light-emitting module, Semiconductor light-emitting element and The semiconductor light-emitting element is bonded to a base, The aforementioned semiconductor light-emitting device is Semiconductor laminates and A contact electrode is disposed between the semiconductor laminate and the base, The contact electrode and the base are bonded together, and a bonding layer containing AuSn is bonded to them, The semiconductor laminate and the bonding layer are disposed between the semiconductor laminate and the bonding layer, The aforementioned bonding layer is A first bonding region is positioned opposite the contact electrode, It has a second junction region positioned opposite the insulating layer, The average Sn content at the center of the second bonding region in the thickness direction is less than the average Sn content at both ends of the second bonding region in the thickness direction. The first junction region has a first transition region in which the average Sn content gradually increases as it moves away from the contact electrode. Light-emitting module.

8. It is a light-emitting module, Semiconductor light-emitting element and The semiconductor light-emitting element is bonded to a base, The aforementioned semiconductor light-emitting device is Semiconductor laminates and A contact electrode is disposed between the semiconductor laminate and the base, The contact electrode and the base are bonded together, and a bonding layer containing AuSn is bonded to them, The semiconductor laminate and the bonding layer are disposed between the semiconductor laminate and the bonding layer, The aforementioned bonding layer is A first bonding region is positioned opposite the contact electrode, It has a second junction region positioned opposite the insulating layer, The average Sn content at the center of the second bonding region in the thickness direction is less than the average Sn content at the end of the second bonding region closer to the insulating layer in the thickness direction. Along a straight line in the thickness direction of the first bonding region, the Sn content increases in a stepwise manner as it moves away from the contact electrode. Light-emitting module.

9. It is a light-emitting module, Semiconductor light-emitting element and The semiconductor light-emitting element is bonded to a base, The aforementioned semiconductor light-emitting device is Semiconductor laminates and A contact electrode is disposed between the semiconductor laminate and the base, The contact electrode and the base are bonded together, and a bonding layer containing AuSn is bonded to them, The semiconductor laminate and the bonding layer are disposed between the semiconductor laminate and the bonding layer, The aforementioned bonding layer is A first bonding region is positioned opposite the contact electrode, It has a second junction region positioned opposite the insulating layer, The average Sn content at the center of the second bonding region in the thickness direction is less than the average Sn content at the end of the second bonding region closer to the insulating layer in the thickness direction. The first junction region has a first transition region in which the average Sn content gradually increases as it moves away from the contact electrode. Light-emitting module.

10. The second junction region has a second transition region in which the average Sn content gradually changes as it moves away from the insulating layer. The light-emitting module according to any one of claims 6 to 9.

11. A method for manufacturing a light-emitting module, Preparation steps for preparing a semiconductor light-emitting element and a base, The process includes a bonding step of bonding the semiconductor light-emitting element to the base using a bonding material containing AuSn, The aforementioned semiconductor light-emitting device is Semiconductor laminates and A contact electrode positioned above the semiconductor stack, A pad layer containing Au is electrically connected to the contact electrode and positioned above the contact electrode, The semiconductor laminate comprises an insulating layer disposed between the pad layer, The pad layer comprises a first layer positioned above the region where the pad layer and the contact electrode are in contact, It includes a second layer positioned above the first layer and in contact with the first layer, The shape of the Au crystal grains in the second layer is columnar, In a direction parallel to the main surface of the contact electrode, the average particle size of the second layer is larger than the average particle size of the first layer. In the joining process, the joining material joins the base and the pad layer, forming a jointed layer in which the pad layer and the joining material are integrated. The aforementioned bonding layer is A first bonding region is positioned opposite the contact electrode, It has a second junction region positioned opposite the insulating layer, The average Sn content at the center of the thickness direction of the second bonding region is: Less than the average Sn content at both ends in the thickness direction of the second bonding region, Along a straight line in the thickness direction of the first bonding region, the Sn content increases in a stepwise manner as it moves away from the contact electrode. A method for manufacturing a light-emitting module.

12. A method for manufacturing a light-emitting module, Preparation steps for preparing a semiconductor light-emitting element and a base, The process includes a bonding step of bonding the semiconductor light-emitting element to the base using a bonding material containing AuSn, The aforementioned semiconductor light-emitting device is Semiconductor laminates and A contact electrode positioned above the semiconductor stack, A pad layer containing Au is electrically connected to the contact electrode and positioned above the contact electrode, The semiconductor laminate comprises an insulating layer disposed between the pad layer, The pad layer comprises a first layer positioned above the region where the pad layer and the contact electrode are in contact, It includes a second layer positioned above the first layer and in contact with the first layer, The shape of the Au crystal grains in the second layer is columnar, In a direction parallel to the main surface of the contact electrode, the average particle size of the second layer is larger than the average particle size of the first layer. In the joining process, the joining material joins the base and the pad layer, forming a jointed layer in which the pad layer and the joining material are integrated. The aforementioned bonding layer is A first bonding region is positioned opposite the contact electrode, It has a second junction region positioned opposite the insulating layer, The average Sn content at the center of the thickness direction of the second bonding region is: Less than the average Sn content at both ends in the thickness direction of the second bonding region, The first junction region has a first transition region in which the average Sn content gradually increases as it moves away from the contact electrode. A method for manufacturing a light-emitting module.

13. In the region between the semiconductor laminate and the pad layer, the insulating layer is not disposed in the region between the semiconductor laminate and the first layer. A method for manufacturing a light-emitting module according to claim 11 or 12.

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