Power supply semiconductor devices and switched-capacitor converters

Abstract

To introduce an appropriate protection technique in a switched capacitor converter.SOLUTION: In a power supply semiconductor device used in a switched capacitor converter having a plurality of power transistors and a plurality of capacitors, a target drive circuit (100A) for a target power transistor (MM), which is one of the plurality of power transistors, supplies a gate signal (GG) to the target power transistor on the basis of a target control signal (CNT_IN). After a gate-source voltage of the target power transistor exceeds a gate threshold voltage, the target drive circuit includes a detection circuit (120) configured to output a detection signal (ERR) according to the drain-source voltage of the target power transistor, and generates a gate signal on the basis of the target control signal and the detection signal.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] This disclosure relates to a power supply semiconductor device and a switched-capacitor converter. [Background technology]

[0002] One type of power supply is a switched-capacitor converter. A switched-capacitor converter has multiple power transistors and multiple capacitors, and generates an output voltage from the input voltage by switching the multiple power transistors. In DC / DC converters that utilize inductors, it is common practice to implement some form of protection when an abnormality such as a ground fault is detected. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2021 / 054027 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In switched-capacitor converters, excessive current can be generated when abnormalities such as output ground faults occur. Since prolonged flow of excessive current is undesirable, the development of appropriate protection technologies for switched-capacitor converters is anticipated.

[0005] This disclosure aims to provide a power supply semiconductor device and a switched-capacitor converter capable of protecting components (such as power transistors) in abnormal conditions where excessive current is generated. [Means for solving the problem]

[0006] The power supply semiconductor device according to this disclosure is a power supply semiconductor device configured to be used in a switched-capacitor converter that has a plurality of power transistors and a plurality of capacitors and generates an output voltage from an input voltage by turning the plurality of power transistors on and off according to a predetermined pattern, and comprises a control block configured to generate a control signal that specifies whether each power transistor is on or off, and a drive block connected to the gate of each power transistor and configured to turn each power transistor on or off by driving the gate of each power transistor based on the control signal, wherein the drive block has a target drive circuit for a target power transistor which is one of the plurality of power transistors, the target drive circuit is connected to the gate of the target power transistor and supplies a gate signal to the target power transistor based on the target control signal which is the control signal for the target power transistor, and the target drive circuit has a detection circuit configured to output a detection signal corresponding to the drain-source voltage of the target power transistor after the gate-source voltage of the target power transistor exceeds the gate threshold voltage of the target power transistor, and generates the gate signal for the target power transistor based on the target control signal and the detection signal. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a power supply semiconductor device and a switched-capacitor converter that can protect components (such as power transistors) in abnormal conditions where excessive current is generated. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram of a power supply device (switched-capacitor converter) according to an embodiment of this disclosure. [Figure 2] Figure 2 is a circuit diagram of a power supply device (switched-capacitor converter) according to an embodiment of the present disclosure. [Figure 3]Figure 3 is a schematic block diagram of a power supply device according to an embodiment of the present disclosure. [Figure 4] Figure 4 is an external perspective view of a power supply IC according to an embodiment of this disclosure. [Figure 5] Figure 5 is an external perspective view of a power supply IC according to an embodiment of this disclosure. [Figure 6] Figure 6 is a schematic block diagram of a power supply IC according to an embodiment of this disclosure. [Figure 7] Figure 7 is a diagram showing the connection relationship between a power supply IC and a plurality of capacitors according to an embodiment of the present disclosure. [Figure 8] Figure 8 shows the relationship between a drive voltage generation block and a plurality of capacitors according to an embodiment of the present disclosure. [Figure 9] Figure 9 is a timing chart of switching control that can be performed by a power supply IC according to an embodiment of the present disclosure. [Figure 10] Figure 10 is a diagram showing the state of each switch element during a certain period (P1) in switching control according to an embodiment of the present disclosure. [Figure 11] Figure 11 shows the state of each switch element during another period (P2) in switching control according to an embodiment of the present disclosure. [Figure 12] Figure 12 is a diagram showing the waveforms of each terminal voltage in switching control according to an embodiment of the present disclosure. [Figure 13] Figure 13 is a diagram showing the external terminal arrangement of a power supply IC according to an embodiment of the present disclosure. [Figure 14] Figure 14 shows the waveform of the drain current of a specific power transistor (assuming no protection operation is performed). [Figure 15] Figure 15 illustrates how a large charge transfer occurs when a specific power transistor is turned on, due to a transition from a normal state to an output ground fault state. [Figure 16] Figure 16 shows the characteristics of a power transistor. [Figure 17]Figure 17 shows an enlarged waveform of the drain current of a specific power transistor when an output ground fault occurs (assuming no protection action is performed). [Figure 18] Figure 18 shows that, according to an embodiment of the present disclosure, a drive circuit is provided for each power transistor. [Figure 19] Figure 19 is a circuit diagram of a drive circuit according to an embodiment of the present disclosure. [Figure 20] Figure 20 is a diagram illustrating the operation of a delay circuit and a selector in a drive circuit according to an embodiment of the present disclosure. [Figure 21] Figure 21 is a timing chart of the drive circuit shown in Figure 19, relating to an embodiment of the present disclosure. [Figure 22] Figure 22 is a diagram illustrating the significance of delay insertion by a delay circuit in a drive circuit according to an embodiment of the present disclosure. [Figure 23] Figure 23 shows an example of a comparator circuit in a drive circuit according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0009] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the referenced drawings, the same parts are denoted by the same reference numerals, and redundant descriptions relating to the same parts are omitted as a general rule. In addition, for the sake of simplification of the description, in this specification, symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, or components may be indicated, and the names of the information, signals, physical quantities, functional parts, circuits, elements, or components corresponding to such symbols or reference numerals may be omitted or abbreviated.

[0010] First, some terms used in the description of the embodiments of this disclosure will be explained. IC is an abbreviation for Integrated Circuit. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or the potential of 0V itself. The reference conductive part may be formed using a conductor such as metal. The potential of 0V is sometimes called the ground potential. In the embodiments of this disclosure, voltages shown without specifying a reference represent the potential as seen from ground.

[0011] Level refers to the level of electric potential. For any signal or voltage of interest, a high level has a higher potential than a low level. For any signal or voltage of interest, being at a high level strictly means that the signal or voltage has a high level, and being at a low level strictly means that the signal or voltage has a low level. The level for a signal is sometimes expressed as the signal level, and the level for a voltage is sometimes expressed as the voltage level.

[0012] For any signal or voltage of interest, the transition from a low level to a high level is called an up edge, and the timing of this transition is called the up edge timing. Up edge may be interpreted as rising edge. Similarly, for any signal or voltage of interest, the transition from a high level to a low level is called a down edge, and the timing of this transition is called the down edge timing. Down edge may be interpreted as falling edge.

[0013] For any transistor configured as a FET (field-effect transistor), including MOSFETs, the "on" state refers to the state where the drain and source of the transistor are conducting, and the "off" state refers to the state where the drain and source of the transistor are not conducting (closed state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, it can be assumed that the back gate is short-circuited to the source in any MOSFET.

[0014] The electrical characteristics of a MOSFET include the gate threshold voltage. For any N-channel and enhancement-type MOSFET transistor, the transistor is ON when its gate potential is higher than its source potential and the magnitude of its gate-source voltage is greater than or equal to its gate threshold voltage; otherwise, the transistor is OFF. For any P-channel and enhancement-type MOSFET transistor, the transistor is ON when its gate potential is lower than its source potential and the magnitude of its gate-source voltage is greater than or equal to its gate threshold voltage; otherwise, the transistor is OFF. For any FET, the gate threshold voltage is defined as the gate-source voltage required to allow a predetermined drain current to flow when a predetermined voltage is applied between the drain and source of the FET under a predetermined ambient temperature environment. The gate-source voltage corresponds to the gate potential as seen from the source potential.

[0015] In the following, the on state and off state of any transistor may simply be referred to as on and off. For any transistor, the switching from the off state to the on state is referred to as turn-on, and the switching from the on state to the off state is referred to as turn-off.

[0016] For any signal that takes on a high or low signal level, the period during which the signal level is high is called the high-level period, and the period during which the signal level is low is called the low-level period. The same applies to any voltage that takes on a high or low voltage level.

[0017] Unless otherwise specified, connections between multiple parts that form a circuit, such as arbitrary circuit elements, wiring (lines), and nodes, can be understood to refer to electrical connections.

[0018] Figure 1 shows a circuit diagram of power supply unit 1 according to an embodiment of this disclosure. Power supply unit 1 is a switched-capacitor converter (hereinafter referred to as SCC). Therefore, power supply unit 1 will be referred to as SCC1 below.

[0019] SCC1 comprises, as its main components, switch elements M1 to M8 and flying capacitors C1 to C3. A voltage source 4 is connected to SCC1. The voltage source 4 generates a DC voltage having a predetermined positive DC voltage value, and this DC voltage is connected to the input voltage V IN This is supplied to SCC1. Figure 1 also shows the load LD of SCC1. Load LD is any load connected to SCC1.

[0020] As shown in FIG. 2, the switch elements M1 to M8 are constituted by power transistors. Therefore, the components M1 to M8 may be referred to as the switch elements M1 to M8, or may be referred to as the power transistors M1 to M8. The power transistors M1 to M8 are each formed by an N-channel type MOSFET. One end of the switch element M1 corresponds to the drain of the power transistor M1, and the other end of the switch element M1 corresponds to the source of the power transistor M1. Similarly, one end of the switch element M2 corresponds to the drain of the power transistor M2, and the other end of the switch element M2 corresponds to the source of the power transistor M2. The same applies to the switch elements M3 to M8.

[0021] The terminal PIN is an input terminal (voltage input terminal) and receives an input voltage V IN The terminal OUT is an output terminal (voltage output terminal), and an output voltage V OUT is applied to the terminal OUT. The output voltage V OUT is the output voltage of SCC1. The voltages applied to the terminals SW1, SW2, SW3, SW6, and SW7 are respectively referred to as voltages V SW1 、V SW2 、V SW3 、V SW6 、V SW7 A switching circuit composed of the power transistors M1 to M8 and the capacitors C1 to C3 is connected to the terminals PIN and OUT, and by turning on and off the power transistors M1 to M8 according to a predetermined pattern, the input voltage V IN is generated from the output voltage V OUT The power transistors M1 to M8 and the capacitors C1 to C3 are connected to each other.

[0022] Specifically, the drain of the power transistor M1 is connected to the terminal PIN. The terminal PIN is connected to the positive output terminal of the voltage source 4 and receives the input voltage V IN from the voltage source 4. Therefore, the input voltage V INThe following are added. The source of power transistor M1, the drain of power transistor M2, and the first terminal of capacitor C1 are commonly connected to terminal SW1. The second terminal of capacitor C1, the source of power transistor M7, and the drain of power transistor M8 are commonly connected to terminal SW7. The source of power transistor M2, the drain of power transistor M3, and the first terminal of capacitor C2 are commonly connected to terminal SW2. The second terminal of capacitor C2, the source of power transistor M6, and the drain of power transistor M5 are commonly connected to terminal SW6. The source of power transistor M3, the drain of power transistor M4, and the first terminal of capacitor C3 are commonly connected to terminal SW3. The second terminal of capacitor C3 is connected to terminal SW7. The source of power transistor M4 and the drains of power transistors M6 and M7 are commonly connected to terminal OUT. The sources of power transistors M5 and M8 are commonly connected to terminal PGND. Terminal PGND is connected to ground. One end of load LD is connected to terminal OUT, and the other end of load LD is connected to terminal PGND.

[0023] Therefore, power transistor M1 conducts or disconnects between terminal PIN and SW1 depending on whether it is turned on or off. Power transistor M2 conducts or disconnects between terminals SW1 and SW2 depending on whether it is turned on or off. Power transistor M3 conducts or disconnects between terminals SW2 and SW3 depending on whether it is turned on or off. Power transistor M4 conducts or disconnects between terminal SW3 and OUT depending on whether it is turned on or off. Power transistor M5 conducts or disconnects between terminal SW6 and PGND depending on whether it is turned on or off. Power transistor M6 conducts or disconnects between terminal OUT and SW6 depending on whether it is turned on or off. Power transistor M7 conducts or disconnects between terminal OUT and SW7 depending on whether it is turned on or off. Power transistor M8 conducts or disconnects between terminal SW7 and PGND depending on whether it is turned on or off.

[0024] Here, it is assumed that SCC1 will function as a voltage divider. Specifically, in SCC1 in Figures 1 and 2, the output voltage V OUT The input voltage is VIN This is 1 / 4 the voltage. Input voltage V IN The value of can be arbitrary, but here, for the sake of detail in the explanation, we will use the input voltage V. IN Let's assume it's 48V. Then, when SCC1 is operating stably, the output voltage V OUT The voltage is 12V. The signals applied to the gates of power transistors M1 to M8 are called gate signals, and the gate signals of power transistors M1 to M8 are referred to as gate signals G1 to G8, respectively.

[0025] Figure 3 is a schematic block diagram of the SCC1. The SCC1 comprises a power supply IC2, which is a semiconductor device for power supply, and a discrete component group 3 consisting of multiple discrete components externally connected to the power supply IC2. Capacitors C1 to C3 are included in the discrete component group 3. The power supply IC2 turns power transistors M1 to M8 on and off according to a predetermined pattern, thereby changing the input voltage V IN Output voltage V OUT This is generated. Power transistors M1 to M8 are built into power supply IC2. However, the power transistors M1 to M8 may be modified so that they are included in discrete component group 3.

[0026] Figures 4 and 5 show external perspective views of the power supply IC 2. The power supply IC 2 is an electronic component comprising a semiconductor chip CP having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip CP, and a plurality of external terminals exposed from the housing CS to the outside of the power supply IC 2. The power supply IC 2 is formed by enclosing the semiconductor chip CP in a housing CS made of resin. Figure 4 is an external perspective view of the power supply IC 2 when observed from the front side of the housing CS. Figure 5 is an external perspective view of the power supply IC 2 when observed from the back side of the housing CS. In Figures 4 and 5, only in Figure 4 is the schematic shape of the semiconductor chip CP shown with a dashed line. A metal pad PAD for heat dissipation is provided on the back side of the housing CS. The terminals PIN, OUT, PGND, SW1, SW2, SW3, SW6, and SW7 shown in Figures 1 and 2 are external terminals provided on the power supply IC 2.

[0027] The types of enclosures for the power supply IC2 and the shapes and number of external terminals shown in Figures 4 and 5 are merely examples, and they can be designed arbitrarily.

[0028] Figure 6 shows a schematic internal block diagram of the power supply IC 2. The power supply IC 2 comprises a control block 10, a drive block 20, a switch block 30, and a drive voltage generation block 40. The switch block 30 has power transistors M1 to M8. The control block 10, drive block 20, switch block 30, and drive voltage generation block 40 are provided on the semiconductor chip CP in the form of a semiconductor integrated circuit.

[0029] The control block 10 generates a control signal CNT that specifies whether power transistors M1 to M8 are on or off, and outputs the generated control signal CNT to the drive block 20. The drive block 20 is connected to the gates of power transistors M1 to M8 and drives the gates of power transistors M1 to M8 based on the control signal CNT, thereby turning power transistors M1 to M8 on or off. That is, the drive block 20 generates and outputs gate signals G1 to G8 based on the control signal CNT, thereby individually turning power transistors M1 to M8 on or off according to the specifications of the control signal CNT. The drive voltage generation block 40 generates a drive voltage, which is the voltage for driving power transistors M1 to M8. The drive block 20 uses the drive voltage to individually turn power transistors M1 to M8 on or off.

[0030] The gate drivers 21-28 shown in Figure 7 are provided on the drive block 20. The terminals BST1-BST4, BST6 and BST7 shown in Figure 7 are external terminals provided on the power supply IC 2. In Figure 7, capacitor C BST1 ~C BST4 , C BST6 and C BST7 This is a bootstrap capacitor included in discrete component group 3.

[0031] Outside of power supply IC2, capacitor C BST1 ~C BST4 , C BST6 and C BST7 The first end of each is connected to terminals BST1-BST4, BST6, and BST7, respectively. Outside the power supply IC2, capacitor C BST1 ~C BST3 , C BST6 and C BST7 The second end of each is connected to terminals SW1~SW3, SW6 and SW7, respectively, and capacitor C BST4 The second end is connected to terminal OUT. The flying capacitors C1 to C3 are also provided outside the power supply IC2, with capacitor C1 connected to terminals SW1 and SW7, capacitor C2 connected to terminals SW2 and SW6, and capacitor C3 connected to terminals SW3 and SW7.

[0032] Gate driver 21 is connected to terminals BST1 and SW1 and the gate of power transistor M1, and generates and outputs gate G1 based on the voltage between terminals BST1 and SW1. Gate driver 22 is connected to terminals BST2 and SW2 and the gate of power transistor M2, and generates and outputs gate G2 based on the voltage between terminals BST2 and SW2. Gate driver 23 is connected to terminals BST3 and SW3 and the gate of power transistor M3, and generates and outputs gate G3 based on the voltage between terminals BST3 and SW3. Gate driver 26 is connected to terminals BST6 and SW6 and the gate of power transistor M6, and generates and outputs gate G6 based on the voltage between terminals BST6 and SW6. Gate driver 27 is connected to terminals BST7 and SW7 and the gate of power transistor M7, and generates and outputs gate G7 based on the voltage between terminals BST7 and SW7.

[0033] The gate driver 24 is connected to terminals BST4 and OUT and the gate of power transistor M4, and generates and outputs gate G4 based on the voltage between terminals BST4 and OUT. The gate driver 25 operates under the internal power supply voltage V REGThe terminal to which the voltage is applied, the terminal PGND, and the gate of power transistor M5 are connected, and the internal power supply voltage V is referenced to the ground potential. REG Based on this, gate G5 is generated and output. The gate driver 28 uses the internal power supply voltage V REG The terminal to which the voltage is applied, the PGND terminal, and the gate of power transistor M8 are connected, and the internal power supply voltage V is referenced to the ground potential. REG Based on this, gate G8 is generated and output.

[0034] As shown in Figure 8, the drive voltage generation block 40 is connected to terminals BST1~BST4, BST6, BST7, SW1~SW3, SW6, SW7 and OUT, and capacitor C BST1 ~C BST4 , C BST6 and C BST7 Together with the bootstrap circuit, the aforementioned drive voltage (voltage for driving power transistors M1 to M8) is generated. Since the bootstrap circuit itself is a well-known technology, a detailed explanation of its internal circuit configuration and operation will be omitted.

[0035] The driving voltage includes the first boot voltage, which is the voltage of terminal BST1 as seen from the potential of terminal SW1; the second boot voltage, which is the voltage of terminal BST2 as seen from the potential of terminal SW2; the third boot voltage, which is the voltage of terminal BST3 as seen from the potential of terminal SW3; the fourth boot voltage, which is the voltage of terminal BST4 as seen from the potential of terminal OUT; the sixth boot voltage, which is the voltage of terminal BST6 as seen from the potential of terminal SW6; and the seventh boot voltage, which is the voltage of terminal BST7 as seen from the potential of terminal SW7. Here, the internal power supply voltage V is also included. REG It is assumed that this includes the internal power supply voltage V. REG The input voltage is V IN or output voltage V OUT This is a positive DC voltage generated based on [the formula / condition].

[0036] The 1st, 2nd, 3rd, 4th, 6th, and 7th boot voltages are greater than the gate threshold voltages of power transistors M1, M2, M3, M4, M6, and M7, respectively. Internal power supply voltage V REGThis is greater than the gate threshold voltages of power transistors M5 and M8. The gate threshold voltage of each power transistor has a positive voltage value (e.g., 0.5V).

[0037] Gate signals G1 to G8 each have either a high-level or low-level signal level. High-level gate signals G1, G2, G3, G4, G6, and G7 have potentials corresponding to terminals BST1, BST2, BST3, BST4, BST6, and BST7, respectively. Low-level gate signals G1, G2, G3, G4, G6, and G7 have potentials corresponding to terminals SW1, SW2, SW3, OUT, SW6, and SW7, respectively. High-level gate signals G5 and G8 have potentials corresponding to the internal power supply voltage V REG It has a potential of the same magnitude. Low-level gate signals G5 and G8 have a potential of the same magnitude as ground.

[0038] Therefore, power transistors M1, M2, M3, M4, M5, M6, M7, and M8 are ON when their gate signals G1, G2, G3, G4, G5, G6, G7, and G8 are at a high level, respectively. Power transistors M1, M2, M3, M4, M5, M6, M7, and M8 are OFF when their gate signals G1, G2, G3, G4, G5, G6, G7, and G8 are at a low level, respectively.

[0039] Figure 9 shows the timing chart of the switching control SC that can be executed by the power supply IC 2. The switching control SC is understood to be realized by the cooperation of the control block 10 and the drive block 20. In the switching control SC, the control block 10 generates control signals CNT1 and CNT2 as control signals CNT (see Figure 6) and outputs them to the drive block 20. In the switching control SC, control signals CNT1 and CNT2 alternately have high-level and low-level signal levels at frequency f SW This is a square wave signal with frequency f. SW This corresponds to the switching frequency of power transistors M1 to M8.

[0040] In other words, in a switching control SC, the control signal CNT1 alternates between high and low levels, and the length of the high-level period and the low-level period of the control signal CNT1 within one cycle of the control signal CNT1 are equal. Therefore, the duty cycle of the control signal CNT1 is 50%. The reciprocal of one cycle of the control signal CNT1 is the frequency f. SW In a switching control SC, the control signal CNT2 alternates between high and low levels. However, the phases of control signals CNT1 and CNT2 are 180° apart. Therefore, in a switching control SC, when control signal CNT1 is high, control signal CNT2 is low, and when control signal CNT1 is low, control signal CNT2 is high. The period when control signal CNT1 is high and control signal CNT2 is low is called period P1, and the period when control signal CNT1 is low and control signal CNT2 is high is called period P2. In a switching control SC, periods P1 and P2 alternate and repeat, and the repetition frequency of periods P1 and P2 is frequency f SW That is the case.

[0041] In the switching control SC, control signal CNT1 functions as a control signal for gate drivers 21, 23, 25, and 27, and control signal CNT2 functions as a control signal for gate drivers 22, 24, 26, and 28.

[0042] During period P1, gate drivers 21, 23, 25, and 27 supply high-level gate signals G1, G3, G5, and G7 respectively to the gates of power transistors M1, M3, M5, and M7 based on a high-level control signal CNT1. During period P1, gate drivers 22, 24, 26, and 28 supply low-level gate signals G2, G4, G6, and G8 respectively to the gates of power transistors M2, M4, M6, and M8 based on a low-level control signal CNT2. Therefore, during period P1, as shown in Figure 10, power transistors M1, M3, M5, and M7 are controlled to the ON state, while power transistors M2, M4, M6, and M8 are controlled to the OFF state.

[0043] During period P2, gate drivers 21, 23, 25, and 27 supply low-level gate signals G1, G3, G5, and G7 respectively to the gates of power transistors M1, M3, M5, and M7 based on the low-level control signal CNT1. During period P2, gate drivers 22, 24, 26, and 28 supply high-level gate signals G2, G4, G6, and G8 respectively to the gates of power transistors M2, M4, M6, and M8 based on the high-level control signal CNT2. Therefore, during period P2, as shown in Figure 11, power transistors M1, M3, M5, and M7 are controlled to the off state, while power transistors M2, M4, M6, and M8 are controlled to the on state.

[0044] Figure 12 shows the voltage waveforms at each terminal of the switching control SC. Figure 12 shows the voltage V in the switching control SC. SW1 and V SW3 The waveform is shown as a rectangular solid line, and the voltage V in the switching control SC SW2 and V SW6 The waveform is shown as a rectangular dashed line. To avoid complexity in the illustration, Figure 12 does not show the voltage V SW7 The waveform is not shown, but the voltage V SW7 The voltage is V SW6 It has an inverted waveform. Figure 12 shows the output voltage V of SCC1. OUT This shows the terminal voltages after stabilization. Output voltage V of SCC1 OUT After stabilization, the output voltage V OUT is voltage (V IN This is essentially equivalent to (×1 / 4).

[0045] During period P1 related to the switching control SC, the voltage V SW1 The input voltage is V IN This is essentially the same as, and the voltage V SW2 and V SW3 is voltage (V IN (×1 / 2) is essentially the same, and the voltage V SW6 This is virtually identical to 0V, and the voltage V is not shown in Figure 12. SW7 is voltage (V INThis is substantially equivalent to ×1 / 4). During the period P2 related to the switching control SC, the voltage V SW1 and V SW2 is voltage (V IN (×3 / 4) is essentially the same, and the voltage V SW3 and V SW6 is voltage (V IN This is substantially the same as (×1 / 4), and the voltage V is not shown in Figure 12. SW7 This is essentially equivalent to 0V.

[0046] Figure 13 shows the arrangement of external terminals when the housing CS of the power supply IC 2 is observed from the back. The back of the housing CS has a roughly square shape, and the four sides of this square are referred to as sides SD1 to SD4. The back of the housing CS is parallel to the mutually orthogonal X and Y axes. Sides SD1 and SD3 are two opposing sides parallel to the X axis, and sides SD2 and SD4 are two opposing sides parallel to the Y axis. The power supply IC 2 is provided with external terminals numbered 1 to 24 (i.e., a total of 24 external terminals).

[0047] External terminals with pin numbers 1 to 6 are provided on edge SD1. Along edge SD1, from the negative side to the positive side of the X-axis, external terminals with pin numbers 1, 2, 3, 4, 5, and 6 are provided in this order. External terminals with pin numbers 7 to 12 are provided on edge SD2. Along edge SD2, from the negative side to the positive side of the Y-axis, external terminals with pin numbers 7, 8, 9, 10, 11, and 12 are provided in this order. External terminals with pin numbers 13 to 18 are provided on edge SD3. Along edge SD3, from the positive side to the negative side of the X-axis, external terminals with pin numbers 13, 14, 15, 16, 17, and 18 are provided in this order. External terminals with pin numbers 19 to 24 are provided on edge SD4. Along edge SD4, external terminals numbered 19, 20, 21, 22, 23, and 24 are provided in this order, starting from the positive side of the Y-axis and moving towards the negative side.

[0048] The external terminals for pins 1, 2, 3, 4, 5, and 6 are terminals PIN, IN, EN, VREG, NC1, and BST2, respectively. The external terminals for pins 7, 8, 9, 10, 11, and 12 are terminals BST3, NC2, RT, GND, EXTVCC, and BST4, respectively. The external terminals for pins 13, 14, 15, 16, 17, and 18 are terminals PG, BST7, NC3, BST6, SW6, and PGND, respectively. The external terminals for pins 19, 20, 21, 22, 23, and 24 are terminals SW7, OUT, SW3, SW2, SW1, and BST1, respectively.

[0049] The functions of the external terminals numbered 1 to 24 that are not shown in Figure 2 or Figure 7 will be explained. Terminal IN is the power input terminal of the internal circuit of power supply IC2. In this embodiment, the input voltage V is connected to terminal IN. IN The following is supplied: The internal circuitry of the power supply IC2 (e.g., control block 10) is driven based on the supply voltage to terminal IN. Terminal EN is the enable terminal. The power supply IC2 operates or stops depending on the voltage applied to terminal EN. The internal power supply voltage V is supplied to terminal VREG. REG The following is added. Terminals NC1 to NC3 are not connected to the semiconductor chip CP and do not affect the operation of the power supply IC2 in any way. Terminal RT is a frequency setting terminal. Outside the power supply IC2, a frequency setting resistor is provided between terminal RT and ground. The control block 10 adjusts the above frequency f according to the value of the frequency setting resistor. SW This is set to a variable value. Terminal GND is the ground terminal and is connected to ground, just like terminal PGND.

[0050] Terminal EXTVCC can be connected to terminal OUT or ground. When terminal EXTVCC is connected to terminal OUT, the output voltage V supplied to terminal EXTVCC is OUT Based on this, the internal power supply voltage V is located within the power supply IC2. REG When terminal EXTVCC is connected to ground, the input voltage V supplied to terminal IN is generated. IN Based on this, the internal power supply voltage V is located within the power supply IC2. REGA signal is generated. Terminal PG is the power good terminal. Terminal PG is connected to an open-drain circuit inside the power supply IC2, and a signal is output from terminal PG depending on whether or not there is a malfunction in the power supply IC2.

[0051] [Short circuit protection] Incidentally, a typical step-down DC / DC converter has a half-bridge circuit consisting of a high-side transistor and a low-side transistor, and the high-side and low-side transistors are alternately turned on and off. This generates a square wave voltage at the connection node between the high-side and low-side transistors. This square wave voltage is rectified and smoothed by an inductor and a capacitor to generate an output voltage at the output terminal. In this type of step-down DC / DC converter, when a ground fault occurs at the output terminal, the current flowing through the half-bridge circuit gradually increases due to the action of the inductor. Therefore, even if ground fault protection is performed with the high-side transistor turned off some time after the ground fault occurs, no problem arises.

[0052] On the other hand, the SCC1 has the characteristic that when an output ground fault occurs, the power transistor current increases rapidly. In the SCC1, an output ground fault means that the output terminal, terminal OUT, is short-circuited to ground. The state in which an output ground fault occurs is called the output ground fault state.

[0053] Figure 14 shows the drain current I of power transistor M1. D The waveform 610 of _M1 is shown (however, waveform 610 is assumed to be the waveform when the protection operation described later does not occur). In Figure 14, time T A1 It is assumed that the transition occurred from a state without an output ground fault to a state with an output ground fault. When an output ground fault occurs, the drain current I is affected when power transistor M1 turns on. D _M1 increases rapidly. The same occurs when a short circuit occurs between the ends of capacitors C1, C2, or C3 (hereinafter referred to as a capacitor short circuit anomaly).

[0054] As shown in Fig. 15, in the normal state where neither the ground short circuit nor the capacitor short circuit abnormality occurs, the voltage V_C1 applied between both ends of the capacitor C1 is the difference between the input voltage V IN (48V) and the output voltage V OUT (12V), which is 36V. In the normal state, assuming that the current flowing through the load LD is zero, even if the power transistors M1 to M8 are switched, no charge transfer occurs through the capacitor C1. Therefore, no current flows through the power transistor M1 (ignoring charge leakage, etc.). After that, when the power transistor M1 is turned on through the occurrence of an output ground short circuit, a potential difference of 12V is additionally applied to the capacitor C1 based on the normal state, so a large charge transfer occurs through the power transistor M1.

[0055] When an abnormality such as an output ground short circuit occurs, it is required to quickly turn off the power transistor for protection. When an abnormality occurs in SCC1, a much larger current than normal flows through the power transistor, and protection is achieved by utilizing this characteristic. Since the currents flowing in the normal and abnormal states are significantly different, it is not necessary to set a fine threshold voltage. For example, in the case of a MOSFET, it is possible to determine that it is normal if the operating region of the MOSFET belongs to the linear region, and abnormal if it belongs to the saturation region.

[0056] Fig. 16 shows the relationship between the drain-source voltage V DS _M1 of the power transistor M1 and the drain current I D _M1 of the power transistor M1. In Fig. 16, it is assumed that the gate-source voltage V GS _M1 of the power transistor M1 is maintained at a constant voltage sufficiently larger than the gate threshold voltage. When the voltage V DS _M1 is relatively small, the power transistor M1 operates in the linear region, and as the voltage V DS _M increases, the drain current I D _M1 increases linearly. However, when the voltage V DS _M1 exceeds a certain value, the power transistor M1 operates in the saturation region, and even if the voltage V DS [[ID=Z8]]_M1 increases, the drain current ID _M1 hardly changes. Alternatively, when the gate signal G1 is at a high level, the drain current I is abnormally large. D When _M1 flows, voltage V DS If _M1 exceeds a certain voltage value, it can be determined that an output short circuit or similar issue has occurred.

[0057] Generally, the delay time of a high-precision comparator is around several tens to 100 nanoseconds. If a high-precision comparator is used to protect against output ground faults, an excessive current will continue to flow for the duration of the high-precision comparator's delay. An increase in the time during which the excessive current flows can increase damage to the components of the SCC1 (e.g., power transistor M1). As mentioned above, considering that fine threshold voltage settings are unnecessary, it is possible to speed up the process by using a low-precision comparator, and the time until protection can be shortened to, for example, several nanoseconds to 10 nanoseconds. Figure 17 shows the time T in Figure 14. A1 After that, the drain current I when power transistor M1 is turned on. D The waveform 610 of _M1 is shown in an enlarged view. When attempting to protect using a high-precision comparator, the delay time t of the high-precision comparator... DLY2 During this time, an excessive current continues to flow, whereas using a low-precision comparator, the time during which the excessive current flows is reduced by the delay time of the low-precision comparator t. DLY1 It is also possible to reduce it to this extent (t DLY1 <t DLY2 ). The low-precision comparator here corresponds to comparator 123 (see Figure 19), which will be described later.

[0058] The behavior of the drain current of power transistor M1 and the protection of power transistor M1 in the event of an output ground fault or a short circuit of capacitors C1, C2, or C3 have been described, but the same applies to any abnormality in which an excessive current flows through any of the power transistors M1 to M8. A circuit capable of performing protective operations against such abnormalities is provided in the drive block 20 (Figure 6). As shown in Figure 18, the drive block 20 is equipped with a drive circuit for each power transistor. In the drive block 20, the drive circuits provided for power transistors M1 to M8 are drive circuits 100[1] to 100[8], respectively. The drive circuits 100[1] to 100[8] may have the same configuration as each other.

[0059] Figure 19 shows the circuit diagram of drive circuit 100A. The configurations of drive circuits 100[1] to 100[8] can be the same as the configuration of drive circuit 100A.

[0060] In Figure 19, transistor MM is a power transistor connected to the drive circuit 100A. The drive circuit 100A is provided with a gate driver 110. The signal applied to the gate of power transistor MM is the gate signal GG. The output terminal of the gate driver 110 is connected to the gate of power transistor MM, and the gate driver 110 outputs the gate signal GG from its own output terminal. The drain of power transistor MM is connected to terminal TD, and the source of power transistor MM is connected to terminal TS.

[0061] When the drive circuit 100A is drive circuits 100[1], 100[2], 100[3], 100[4], 100[5], 100[6], 100[7], and 100[8], the power transistors MM are power transistors M1, M2, M3, M4, M5, M6, M7, and M8 respectively, the gate drivers 110 are gate drivers 21, 22, 23, 24, 25, 26, 27, and 28 respectively (see Figure 7), the gate signals GG are gate signals G1, G2, G3, G4, G5, G6, G7, and G8 respectively (see Figure 7), the terminals TD are terminals PIN, SW1, SW2, SW3, SW6, OUT, OUT, and SW7 respectively (see Figure 2, etc.), and the terminals TS are terminals SW1, SW2, SW3, OUT, PGND, SW6, SW7, and PGND respectively.

[0062] The control signal CNT_IN is input to the drive circuit 100A. The control signal CNT_IN is a control signal for the power transistor MM (a signal that specifies whether the power transistor MM is on or off), and is supplied from the control block 10 (see Figure 6). When the drive circuit 100A is drive circuit 100[1], 100[3], 100[5], or 100[7], the control signal CNT_IN is control signal CNT1 (see Figure 9). When the drive circuit 100A is drive circuit 100[2], 100[4], 100[6], or 100[8], the control signal CNT_IN is control signal CNT2 (see Figure 9).

[0063] In addition to the gate driver 110, the drive circuit 100A is provided with an abnormality detection circuit 120, a latch circuit 130, and a logical AND circuit 140. In the following, the gate-source voltage of the power transistor MM is denoted by the symbol "V". GS Refer to "_MM" and the gate-source voltage V GS _MM, or simply voltage V GS It will be referred to as _MM. The gate threshold voltage of the power transistor MM will be referred to by the symbol "Vth". Furthermore, the voltage at the source of the power transistor MM will be the source voltage V. S This refers to the voltage at the drain of the power transistor MM as the drain voltage V. Dis referred to as. The drive circuit 100A operates based on the source potential of the power transistor MM.

[0064] The abnormality detection circuit 120 includes a delay circuit 121, a selector 122, and a comparator 123. The delay circuit 121 is connected to the gate of the power transistor MM and outputs a signal S121 having a value of "0" or "1" based on the voltage V GS _MM. Fig. 20 shows the relationship between the voltage V GS _MM and the signal S121 (the voltage V P shown in Fig. 20 will be described later). The delay circuit 121 has a function of comparing the voltage V GS _MM with the gate threshold voltage Vth, and outputs, as the signal S121, a signal obtained by delaying the comparison result signal. When the state where the voltage V GS _MM is lower than the gate threshold voltage Vth is maintained, the value of the signal S121 is "0". When the value of the signal S121 is "0" and the state changes from the established state of "V GS [[ID=十六]]_MM < Vth" to the established state of "V GS _MM > Vth", after a predetermined delay time td has elapsed since the transition, the delay circuit 12 determines that the value of the signal S121 is "0". When the value of the signal S121 is "0" and the state changes from the established state of "V GS _MM < Vth" to the established state of "V GS _MM > Vth", after a predetermined delay time td has elapsed since the transition, the delay circuit 121 switches the value of the signal S121 from "0" to "1". Then, when the state returns to the established state of "V GS _MM < Vth", after a predetermined delay time td has elapsed since the return, the delay circuit 121 switches the value of the signal S121 from "1" to "0".

[0065] The selector 122 has a first input terminal connected to the source of the power transistor MM to receive the source voltage V S , a second input terminal connected to the drain of the power transistor MM to receive the drain voltage V D , a control terminal to receive the signal S121, and an output terminal. When the value of the signal S121 is "0", the selector 122 outputs, from the output terminal, the signal at the first input terminal (i.e., the signal having the source voltage V S ), and when the value of the signal S121 is "1", the selector 122 outputs, from the output terminal, the signal at the second input terminal (i.e., the drain voltage V DA signal having the following characteristics is output from the output terminal. The voltage of the signal output from the output terminal of selector 122 is set to voltage V P This is referred to as [this term]. Therefore, as shown in Figure 20, when the value of signal S121 is "0", the source voltage V S Voltage V P The output from selector 122 is as follows, and when the value of signal S121 is "1", the drain voltage V D Voltage V P It is output from selector 122 as follows.

[0066] Comparator 123 is connected to the output terminal of selector 122 and the source of power transistor MM. Comparator 123 controls the voltage V P voltage (V S +V J It compares the voltage (V) and outputs a detection signal ERR according to the comparison result. S +V J ) is the source voltage V S The predetermined determination voltage V J It refers to a voltage that is only slightly higher. Judgment voltage V J It has a predetermined positive voltage value. The detection signal ERR is a binary signal that has a high level or a low level. Comparator 123 has a voltage V P is voltage (V S +V J If the voltage is higher than ), a high-level detection signal ERR is output, and voltage V P is voltage (V S +V J If it is lower than ), it outputs a low-level detection signal ERR. P =V S +V J When this is the case, the detection signal ERR will be either high or low. Here, a high-level detection signal ERR functions as the detection signal ERR for the asserted state, and a low-level detection signal ERR functions as the detection signal ERR for the negated state.

[0067] The comparator 123 may determine whether the power transistor MM is operating in the linear region or the saturation region when the power transistor MM is ON. In this case, when a high-level gate signal GG is supplied to the gate of the power transistor MM, the drain-source voltage of the power transistor MM (i.e., the drain voltage as seen from the source potential) is the determination voltage V if the power transistor MM is operating in the linear region. J If the value is smaller and the power transistor MM is operating in the saturation region, then the determination voltage V J It becomes larger. Then, the comparator 123 outputs a low-level detection signal ERR when it is determined that the power transistor MM is operating in the linear region, and outputs a high-level detection signal ERR when it is determined that the power transistor MM is operating in the saturation region.

[0068] The latch circuit 130 comprises circuits 131 to 133. Circuit 133 is an inverter circuit that receives a detection signal ERR from comparator 123 and outputs an inverted signal of the detection signal ERR. Therefore, the output signal of circuit 133 has a low level if the detection signal ERR is high level, and a high level if the detection signal ERR is low level. Circuits 131 and 132 are both 2-input negative AND circuits. Circuit 131 receives the control signal CNT_IN and the output signal of circuit 132, and outputs a low-level signal only when both the control signal CNT_IN and the output signal of circuit 132 are high level, and outputs a high-level signal otherwise. Circuit 132 receives the output signals of circuit 131 and circuit 133, and outputs a low-level signal only when both the output signals of circuit 131 and circuit 133 are high level, and outputs a high-level signal otherwise. The output signal of circuit 131 is output to circuit 140 as the output signal S130 of the latch circuit 130.

[0069] Circuit 140 is a two-input logical AND gate. Circuit 140 receives the control signal CNT_IN and the output signal S130 of the latch circuit 130. It outputs a high-level signal S140 only when both the control signal CNT_IN and the output signal S130 of the latch circuit 130 are at a high level, and outputs a low-level signal S140 otherwise. Signal S140 is supplied to the gate driver 110.

[0070] When the output signal S140 of circuit 140 is at a high level, the gate driver 110 turns on the power transistor MM by supplying a high-level gate signal GG to the gate of the power transistor MM. When the output signal S140 of circuit 140 is at a low level, the gate driver 110 turns off the power transistor MM by supplying a low-level gate signal GG to the gate of the power transistor MM. The gate signal GG is a voltage signal referenced to the potential of terminal TS. When the gate signal GG is at a high level, the voltage V GS _MM is greater than the gate threshold voltage Vth. When the gate signal GG is at a low level, the voltage V GS _MM is smaller than the gate threshold voltage Vth and can effectively be 0V.

[0071] Figure 21 shows the timing chart of the drive circuit 100A. The operation of the drive circuit 100A will be explained with reference to Figure 21. For any natural number i, time T Bi+1 is time T Bi Assume that this is a later time than time T. B3 Prior to this point, SCC1 was kept in a normal state (see Figure 15), and time T B3 This assumes a transition from a normal state to an output ground fault state. Figure 21 shows, from top to bottom, the control signal CNT_IN, the gate signal GG, and the voltage V. DS The waveforms of _MM, detection signal ERR, and signal S130 are shown. Voltage V DS _MM represents the drain-source voltage of the power transistor MM (i.e., the drain voltage as seen from the source potential).

[0072] The control signal CNT_IN has the frequency f mentioned above. SWIt is a square wave signal having a duty cycle of 50%. Time T B1 An up edge occurs in the control signal CNT_IN at time T. B4 is time T B1 This is a time that is one cycle later than the control signal CNT_IN, and time T B7 is time T B1 This is two cycles after the control signal CNT_IN. Therefore, time T B4 and T B7 In each of these cases, an up edge occurs in the control signal CNT_IN. Time T B2 is time T B1 This is a time that is half a cycle later than the control signal CNT_IN, and time T B6 is time T B4 This is a time that is half a cycle later than the control signal CNT_IN, and time T B9 is time T B7 This is a time that is half a cycle later than the control signal CNT_IN. Therefore, time T B2 , T B6 and T B9 A down edge occurs in the control signal CNT_IN at each of these times. B1 Immediately before, the control signal CNT_IN is low level, and therefore the gate signal GG is low level, so the power transistor MM is off, and "V P =V S Therefore, the detection signal ERR is at a low level (negate state). Thus, at time T B1 Immediately before this point, signal S130 is at a high level.

[0073] The control signal CNT_IN corresponds to the set signal for the latch circuit 130. Time T B1 Even when the up edge of the control signal CNT_IN occurs, signal S130 remains at a high level. Therefore, at time T B1 In response to the up edge of the control signal CNT_IN, an up edge is generated in the gate signal GG. In response to the up edge of the gate signal GG, the power transistor MM turns on, causing a voltage V DS _MM drops to a sufficiently low voltage. Then, at time T B2In response to the down edge of the control signal CNT_IN, a down edge occurs in the gate signal GG, causing the power transistor MM to turn off, resulting in a voltage V DS _MM increases. Under normal conditions, when power transistor MM is on, the drain current flowing through power transistor MM is relatively small, and as a result, "V P <V S +V J Since this condition is maintained, the detection signal ERR is kept at a low level. Because the detection signal ERR is kept at a low level, the output signal S130 of the latch circuit 130 is kept at a high level.

[0074] Time T B3 After an output ground fault occurred at time T B4 An up edge occurs in the control signal CNT_IN at this time. Since the detection signal ERR is low at this stage, time T B4 In response to the up edge of the control signal CNT_IN at time T, an up edge also occurs in the gate signal GG, resulting in the power transistor MM turning on. B4 The time t after the delay time td has elapsed B5 The voltage V input to comparator 123 P Source voltage V S From the drain voltage V D Switches to this. Due to the effect of an output ground fault, time T B4 and T B5 The drain current of the power transistor MM in between is very large, and as a result, "V D >V S +V J “This holds true. Therefore, at time t B5 Voltage V P The drain voltage is V D Switching to this configuration creates an up edge in the detection signal ERR. The power transistor MM operates in the linear region under normal conditions, but may operate in the saturation region under output ground fault conditions.

[0075] The detection signal ERR corresponds to the reset signal for the latch circuit 130. Time t B5The up edge of the detection signal ERR generates a down edge in the output signal S130 of the latch circuit 130. The down edge of signal S130 triggers a down edge in the gate signal GG, causing the power transistor MM to turn off. At time t B5 After the power transistor MM is turned off, the voltage V DS _MM may fluctuate, but time t B5 If there is no charge transfer through terminals TD or TS after the power transistor MM is turned off, the voltage V DS _MM hardly changes.

[0076] Time T B5 After the down edge of the gate signal GG, triggered by the down edge of signal S130, and after the delay time td has elapsed, “V P =V D From the state of "V P =V S As the state switches to ", a down edge occurs in the detection signal ERR (the time at which this down edge occurs is time T B6 (Assuming it is earlier than this). However, since the latch circuit 130 maintains the low level of signal S130, the low level of gate signal GG and the off state of power transistor MM are maintained.

[0077] Then, at time T B6 When a down edge occurs in the control signal CNT_IN, the detection signal ERR at this point is at a low level, and therefore an up edge occurs in signal S130 due to the function of the latch circuit 130. Thus, at the subsequent time T B7 , T B8 and T B9 At time T B4 , T B5 and T B6 The same action as before is repeated.

[0078] Using the drive circuit 100A in Figure 19, when an excessive current flows through the power transistor MM, such as during an output ground fault, the power transistor MM is quickly turned off, thereby protecting the power transistor MM and other components. The comparator 123 may be a low-precision comparator capable of high-speed operation, and the high-speed operation of the comparator 123 can sufficiently shorten the time during which an excessive current flows through the power transistor MM (for example, the delay time t in Figure 17). DLY1 (This can be kept to a reasonable level.) Therefore, it is possible to reduce damage to components (including power transistors MM) or their surrounding parts through which excessive current passes to a level that does not pose a problem.

[0079] The significance of inserting the delay time td will be explained with reference to Figure 22. When the gate signal GG switches from a low level to a high level triggered by the up edge of the control signal CNT_IN, the power transistor MM switches from the off state to the on state. At this time, due to the influence of parasitic inductance related to the power transistor MM, the voltage V DS Ringing occurs in _MM due to switching. After this ringing has completely subsided or is mostly gone, the input voltage V to comparator 123 is set. P Source voltage V S From the drain voltage V S A delay time td is inserted to allow the system to switch to the desired state. This enables appropriate protection that suppresses the effects of ringing. However, if the effects of ringing are minor, the delay time td can be set to zero.

[0080] Figure 23 shows the circuit diagram of comparator 123a, which is an example of comparator 123. Since it is sufficient to distinguish whether the power transistor MM is operating in the linear region or the saturation region, comparator 123a can be constructed using a simple, low-precision comparator.

[0081] Comparator 123a is connected to wirings 171 and 172. When gate driver 110 is gate drivers 21, 22, 23, 24, 26, 27 (see Figure 7), wiring 171 is connected to terminals BST1, BST2, BST3, BST4, BST6, BST7, respectively. When gate driver 110 is gate driver 25 or 28 (see Figure 7), wiring 171 is connected to the internal power supply voltage V REG Wiring 172 is connected to terminal TS, and therefore wiring 172 has a source voltage V S It will be added.

[0082] Comparator 123a includes transistors 161 to 166. Transistors 161 and 165 are P-channel MOSFETs, and transistors 162 to 164 and 166 are N-channel MOSFETs.

[0083] The sources of transistors 161 and 165 are connected to wiring 171. The gates of transistors 161 and 162 are connected to the output terminals of selector 122, with voltage V P The drains of transistors 161 and 162 are connected in common to the gates of transistors 165 and 166. The source of transistor 162 is connected to the drain and gate of transistor 163 and the drain of transistor 164. The sources of transistors 163, 164 and 166 are connected to wiring 172. The back gate of transistor 162 is also connected to wiring 172. The gate of transistor 164 is connected to the drains of transistors 165 and 166, along with node ND. ERR It connects to node ND. ERR The signal in this case is the detection signal ERR.

[0084] Voltage V P The voltage across wiring 172 (i.e., source voltage V) SIf the same conditions are met, the states of transistors 161, 162, 165, and 166 will be in the first state. In the first state, transistor 161 is on and transistor 162 is off, and through the rise in the gate potentials of transistors 165 and 166, transistor 165 becomes off and transistor 166 becomes on. Therefore, in the first state, the detection signal ERR will be at a low level (the level of potential of wiring 172). Voltage V P If the voltage is the same as that of wiring 171, the state of transistors 161, 162, 165, and 166 will be the second state. In the second state, transistor 161 is off and transistor 162 is on, and through the decrease in the gate potentials of transistors 165 and 166, transistor 165 is turned on and transistor 166 is turned off. Therefore, in the second state, the detection signal ERR will be at a high level (the level of the potential of wiring 171).

[0085] Voltage V P The voltage across wiring 172 (i.e., source voltage V) S During the process of rising from ), the state of transistors 161, 162, 165, and 166 switches from the first state to the second state, causing the detection signal ERR to switch from a low level to a high level. The voltage V when the state of transistors 161, 162, 165, and 166 switches from the first state to the second state. P The determination voltage V J This corresponds to the determination voltage V. J This can be higher than the pinch-off voltage of power transistor MM when a high-level gate signal GG is supplied to the gate of power transistor MM. Comparator 123a is voltage V P It can be said that, depending on which of the transistors 161 and 162, which receive the signal at their gates, turns on, a low-level or high-level detection signal ERR is output.

[0086] For convenience, let's refer to one of the power transistors M1 to M8 as the target power transistor, and assume that the target power transistor is power transistor MM. Then, the drive circuit 100A can be said to be a target drive circuit for the target power transistor MM, and the control signal CNT_IN can be said to be a target control signal for the target power transistor MM. The target drive circuit 100A supplies a gate signal GG to the target power transistor MM based on the target control signal CNT_IN. At this time, the abnormality detection circuit 120 detects the gate-source voltage V of the target power transistor MM during the process in which the gate signal GG switches from a low level to a high level. GS After _MM exceeds the gate threshold voltage Vth, the drain-source voltage V of the target power transistor MM DS The system outputs a detection signal ERR corresponding to _MM. Then, the target drive circuit 100A generates a gate signal GG for the target power transistor MM based on the target detection signal CNT_IN and the detection signal ERR.

[0087] In detail, the target drive circuit 100A performs a basic turn-on operation by supplying a high-level gate signal GG to the target power transistor MM in response to a change in the target control signal CNT_IN from a low level to a high level, thereby turning on the target power transistor MM. The supply of a high-level gate signal GG is equivalent to supplying a voltage exceeding the gate threshold voltage Vth between the gate and source of the target power transistor MM. In the timing chart of Figure 21, at time T B1 , T B4 , T B7 The basic turn-on operation is executed when the up edge of the target control signal CNT_IN occurs. The target drive circuit 100A can perform a basic turn-off operation after the basic turn-on operation. The basic turn-off operation is an operation that turns off the target power transistor MM by supplying a low-level gate signal GG to the target power transistor MM in response to a change from a high level to a low level of the target control signal CNT_IN. Supplying a low-level gate signal GG is equivalent to supplying a voltage less than the gate threshold voltage Vth between the gate and source of the target power transistor MM. In the timing chart of Figure 21, at time T B2 The basic turn-off operation is executed when the down edge of the target control signal CNT_IN occurs. On the other hand, the abnormality detection circuit 120, after the basic turn-on operation, checks the drain-source voltage V of the target power transistor MM. DS Set _MM to the voltage to be monitored and monitor it (in other words, the source voltage V) S and drain voltage V D The drain-source voltage V is received by DS _MM is monitored as the target voltage). Then, the abnormality detection circuit 120 monitors the target voltage (V DS When _MM) exceeds a predetermined judgment voltage VJ, an assertion state detection signal ERR (in this case, a high-level detection signal ERR) is output. After the basic turn-on operation, when the target drive circuit 100A receives an assertion state detection signal ERR from the abnormality detection circuit 120, it performs a protection operation that turns off the target power transistor MM regardless of the target control signal CNT_IN. In the timing chart of Figure 21, at time T B5 , T B8 The protection operation involves turning off the target power transistor MM when the up edge of the detection signal ERR occurs.

[0088] The target drive circuit 100A performs a basic turn-on operation, then turns off the target power transistor MM through a protection operation, and then maintains the target power transistor MM in the off state until a change from low level to high level occurs due to the target control signal CNT_IN (for example, at time T in Figure 21). B5 From time TB7 (See the period up to ). Subsequently, when a change from low level to high level occurs in the target control signal CNT_IN, the target drive circuit 100A performs the basic turn-on operation again (for example, at time T in Figure 21). B7 (The basic turn-on operation is performed.)

[0089] Comparator 123 monitors the voltage (V) DS _MM) Determine voltage V J By comparing it with the gate-source voltage V, a signal indicating the comparison result is output as the detection signal ERR. The delay circuit 121 and selector 122 control the gate-source voltage V GS After a predetermined time (td) has elapsed since _MM exceeded the gate threshold voltage Vth, the drain-source voltage V DS A delayed supply circuit is formed that supplies _MM as the monitored voltage to comparator 123. Note that comparator 123 is always connected to terminal TS and the source voltage V S In order to receive, drain voltage V D Voltage V P Supplying this to comparator 123 means the drain-source voltage V DS This is equivalent to supplying _MM to comparator 123.

[0090] Comparator 123 monitors the target voltage (V) when the target power transistor MM is ON. DS _MM) and determination voltage V J Through comparison, it is determined whether the target power transistor MM is operating in the linear region or the saturation region. The comparator 123 may output an assertion state detection signal ERR when it is determined that the target power transistor MM is operating in the saturation region.

[0091] As described above, the drive circuits 100[1] to 100[8] have a common configuration (the same configuration) with respect to each other, and each of the drive circuits 100[1] to 100[8] functions as a target drive circuit 100A for the corresponding power transistor.

[0092] In this embodiment, the configuration is illustrated as an example of when SCC1 functions as a step-down SCC (voltage divider), but SCC1 may also be configured as a step-up SCC (charge pump).

[0093] With respect to any signal or voltage, the relationship between their high and low levels can be the reverse of that described above, without undermining the main point stated above.

[0094] The channel types of the FETs (field-effect transistors) shown in each embodiment are illustrative. Without compromising the main points mentioned above, the channel type of any FET can be changed between P-channel and N-channel types. For example, power transistors M1 to M8 can be formed using P-channel MOSFETs.

[0095] As long as no inconvenience arises, any transistor described above may be any type of transistor. For example, any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, as long as no inconvenience arises. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain and the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to the IGBT category, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the base.

[0096] In this embodiment, an SCC (Swivel Switch Controller) is given as an example, which is configured by connecting eight switch elements (M1-M8) and three flying capacitors (C1-C3) in the connection relationship shown in Figure 1. However, as is well known, the number of switch elements and flying capacitors in an SCC, as well as the connection relationships between multiple switch elements and multiple flying capacitors, can vary, and the present disclosure is not limited to the above-described example. Input voltage (V INInput terminals that receive ) and output voltage (V OUT A switching circuit consisting of multiple switching elements and multiple flying capacitors is connected to the output terminal to which the input voltage (V) is applied, and the multiple switching elements are turned on and off according to a predetermined pattern to change the input voltage (V) IN ) from output voltage (V OUT Multiple switching elements and multiple flying capacitors should be connected to each other so that the following is generated.

[0097] The embodiments of this disclosure can be modified in various ways as appropriate within the scope of the technical idea set forth in the claims. The embodiments described above are merely examples of embodiments of this disclosure, and the meaning of the terms in this disclosure or each constituent element is not limited to those described above. The specific numerical values ​​given in the above description are merely examples and can, of course, be changed to various numerical values.

[0098] <<Note>> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.

[0099] A power supply semiconductor device relating to one aspect of this disclosure has a plurality of power transistors (M1 to M8) and a plurality of capacitors (C1 to C3), and by turning the plurality of power transistors on and off according to a predetermined pattern, the input voltage (V IN ) from output voltage (V OUTA power supply semiconductor device (2) configured for use in a switched-capacitor converter (1) that generates a power transistor, comprising: a control block (10) configured to generate a control signal (CNT) that specifies whether each power transistor is on or off; and a drive block (20) connected to the gate of each power transistor and configured to turn each power transistor on or off by driving the gate of each power transistor based on the control signal, wherein the drive block has a target drive circuit (100A) for a target power transistor (MM) which is one of the plurality of power transistors, the target drive circuit is connected to the gate of the target power transistor and supplies a gate signal (GG) to the target power transistor based on the target control signal (CNT_IN), which is the control signal for the target power transistor, and the target drive circuit controls the gate-source voltage (V) of the target power transistor. GS The system includes a detection circuit (120) configured to output a detection signal (ERR) corresponding to the drain-source voltage of the target power transistor after _MM) exceeds the gate threshold voltage of the target power transistor, and a configuration (first configuration) that generates the gate signal for the target power transistor based on the target control signal and the detection signal.

[0100] When an excessive current flows through a power transistor, such as during an output ground fault, the drain-source voltage of the power transistor is expected to become abnormally large. As in the first configuration, by outputting a detection signal corresponding to the drain-source voltage of the power transistor and generating a gate signal that also takes the detection signal into consideration, it becomes possible to protect the power transistor by turning it off when an excessive current flows.

[0101] In the power supply semiconductor device according to the first configuration described above, the drive control signal has a first level or a second level, and the target drive circuit performs a basic turn-on operation to turn on the target power transistor by supplying a voltage exceeding the gate threshold voltage between the gate and source of the target power transistor in response to a change in the target control signal from the first level to the second level, and after the basic turn-on operation, it is possible to perform a basic turn-off operation to turn off the target power transistor by reducing the gate-source voltage of the target power transistor to less than the gate threshold voltage in response to a change in the target control signal from the second level to the first level, and in the target drive circuit, after the basic turn-on operation, the detection circuit monitors the drain-source voltage of the target power transistor as the target voltage, and outputs the detection signal in an asserted state when the monitored voltage exceeds a predetermined determination voltage, and the target drive circuit performs a protection operation to turn off the target power transistor regardless of the target control signal when the detection signal in an asserted state is output from the detection circuit after the basic turn-on operation (second configuration).

[0102] This allows for the rapid turn-off of the power transistor to provide protection when excessive current flows through it due to an output ground fault or other reasons, causing the drain-source voltage (monitored voltage) of the power transistor to exceed the judgment voltage.

[0103] In the examples shown in Figures 19 to 22, the first level and the second level correspond to the low level and the high level, respectively, but their correspondence may be reversed.

[0104] In the power supply semiconductor device according to the second configuration described above, the target drive circuit may be configured to maintain the target power transistor in an off state (third configuration) after the basic turn-on operation and the protection operation that turns off the target power transistor, and then the target control signal that causes a change from the first level to the second level.

[0105] This prevents excessive current from flowing through the target power transistor for extended periods.

[0106] In the power supply semiconductor device according to the second configuration described above, the target drive circuit may be configured such that, after the basic turn-on operation, the target power transistor is turned off by the protection operation, and then the target power transistor is kept in the off state until a change from the first level to the second level occurs in the target control signal, and thereafter, when a change from the first level to the second level occurs in the target control signal, the basic turn-on operation is executed again (fourth configuration).

[0107] In a power supply semiconductor device relating to any of the second to fourth configurations described above, the detection circuit may also have a configuration (fifth configuration) comprising: a comparator (123) configured to output a signal indicating the comparison result as the detection signal by comparing the monitored voltage with the determination voltage; and a delay supply circuit (121, 122) configured to supply the drain-source voltage of the target power transistor to the comparator as the monitored voltage after a predetermined time has elapsed since the gate-source voltage of the target power transistor exceeded the gate threshold voltage.

[0108] This makes it possible to reduce the ringing effect associated with the switching of the target power transistor in the detection circuit.

[0109] In the power supply semiconductor device according to the fifth configuration described above, the comparator may be configured to determine whether the target power transistor is operating in the linear region or the saturation region when the target power transistor is turned on, and to output the asserted detection signal when it is determined that the target power transistor is operating in the saturation region (sixth configuration).

[0110] Since precise threshold voltage settings are unnecessary for determining whether the target power transistor is operating in the linear or saturation region, the above comparator can be constructed using a low-precision comparator capable of high-speed operation. Therefore, in the event of an output ground fault, the time during which excessive current flows through the target power transistor can be kept sufficiently short. As a result, damage to the components through which the excessive current passes (including the target power transistor) or its surrounding components can be kept to an acceptable level.

[0111] In a power supply semiconductor device relating to any of the above configurations 1 to 6, a drive circuit may be provided in the drive block for each of the power transistors, so that a plurality of drive circuits (100[1] to 100[8]) for the plurality of power transistors are provided in the drive block, the plurality of drive circuits have a common configuration with respect to each other, and each of the plurality of drive circuits functions as the target drive circuit for the corresponding power transistor (configuration 7).

[0112] This allows for the necessary protection to be provided to each power transistor.

[0113] In a power supply semiconductor device relating to any of the above configurations 1 to 7, an input terminal (PIN) configured to receive the input terminal and an output terminal (OUT) configured to receive the output voltage may be provided, and a switching circuit having the plurality of power transistors and the plurality of capacitors may be connected to the input terminal and the output terminal, and the plurality of power transistors and the plurality of capacitors may be connected to each other so that the output voltage is generated from the input voltage by turning the plurality of power transistors on and off according to the predetermined pattern (configuration 8).

[0114] A switched-capacitor converter relating to one aspect of this disclosure has a configuration comprising a power supply semiconductor device having a plurality of power transistors, according to any of the first to eighth configurations described above, and a plurality of capacitors (the ninth configuration). [Explanation of symbols]

[0115] 1. SCC (Switched Capacitor Converter) 2 Power IC 3. Discrete component group 4. Voltage source C1~C3 Capacitors (Flying Capacitors) M1-M8 Power Transistors (Switching Elements) LD load PIN, SW1~SW3, SW6, SW7, OUT, PGND terminals G1-G8 Gate Signals CS cabinet CP semiconductor chip PAD Heat dissipation pad V IN Input Voltage V OUT Output voltage V SW1 ~V SW3 , V SW6 , V SW7 Voltage 10 Control Blocks 20 Drive Block 21-28 Gate Driver 30 Switch Blocks 40 Drive voltage generation block C BST1 ~C BST4 , C BST6 , C BST7 Capacitor (bootstrap capacitor) SD1~SD4 sides IN, EN, VREG, NC1~NC3, BST1~BST4, BST6, BST7 RT, GND EXTVCC, PG terminal 100[1]~100[8] Drive Circuit 100A drive circuit (target drive circuit) CNT, CNT1, CNT2 control signals CNT_IN Control signal (Target control signal) MM power transistor (target power transistor) GG gate signal TD, TS terminals 110 Gate Driver 120 Anomaly detection circuit 121 Delay Circuit 122 Selector 123, 123a Comparator 130 Latch Circuit 131, 132, Negated AND Circuit 133 Inverter Circuit 140 AND gates ERR detection signal 161-166 Transistors ND ERR node

Claims

1. A power supply semiconductor device having a plurality of power transistors and a plurality of capacitors, configured for use in a switched-capacitor converter that generates an output voltage from an input voltage by turning the plurality of power transistors on and off according to a predetermined pattern, A control block configured to generate control signals that specify whether each power transistor is on or off, The system includes a drive block connected to the gate of each power transistor and configured to turn each power transistor on or off by driving the gate of each power transistor based on the control signal, The drive block has a target drive circuit for a target power transistor which is one of the plurality of power transistors, the target drive circuit is connected to the gate of the target power transistor and supplies a gate signal to the target power transistor based on the target control signal which is the control signal for the target power transistor, The target drive circuit has a detection circuit configured to output a detection signal corresponding to the drain-source voltage of the target power transistor, and generates the gate signal for the target power transistor based on the target control signal and the detection signal. The detection circuit has a comparator that outputs the detection signal by comparing the input voltage with a first voltage, and is configured to switch the voltage input to the comparator from a second voltage different from the first voltage to the drain voltage of the target power transistor after a predetermined time has elapsed since the gate-source voltage of the target power transistor exceeded the gate threshold voltage of the target power transistor. , power supply semiconductor device.

2. The aforementioned target control signal has a first level or a second level. The target drive circuit is capable of performing a basic turn-on operation to turn on the target power transistor by supplying a voltage exceeding the gate threshold voltage between the gate and source of the target power transistor in response to a change in the target control signal from the first level to the second level, and after the basic turn-on operation, it is capable of performing a basic turn-off operation to turn off the target power transistor by reducing the gate-source voltage of the target power transistor to less than the gate threshold voltage in response to a change in the target control signal from the second level to the first level. In the aforementioned target drive circuit, after the basic turn-on operation, the detection circuit monitors the drain-source voltage of the target power transistor, and outputs the asserted detection signal when the monitored voltage exceeds a predetermined determination voltage. After the basic turn-on operation, when the detection signal in the asserted state is output from the detection circuit, the target drive circuit performs a protection operation to turn off the target power transistor, regardless of the target control signal. The power supply semiconductor device according to claim 1.

3. The target drive circuit, after the basic turn-on operation, turns off the target power transistor due to the protection operation, and then maintains the target power transistor in the off state until a change from the first level to the second level occurs due to the target control signal. The power supply semiconductor device according to claim 2.

4. The target drive circuit, after the basic turn-on operation and the protection operation, turns off the target power transistor, and then maintains the target power transistor in the off state until a change from the first level to the second level occurs in response to the target control signal. After that, when a change from the first level to the second level occurs in response to the target control signal, it performs the basic turn-on operation again. The power supply semiconductor device according to claim 2.

5. The detection circuit includes a delayed supply circuit configured to supply the drain-source voltage of the target power transistor to the comparator as the monitored voltage after a predetermined time has elapsed since the gate-source voltage of the target power transistor exceeded the gate threshold voltage. A power supply semiconductor device according to any one of claims 2 to 4.

6. The comparator determines whether the target power transistor is operating in the linear region or the saturation region when the target power transistor is turned on, and outputs the detection signal in the asserted state when it is determined that the target power transistor is operating in the saturation region. The power supply semiconductor device according to claim 5.

7. A drive circuit is provided in the drive block for each of the power transistors, so that a plurality of drive circuits for the plurality of power transistors are provided in the drive block. The plurality of drive circuits have a common configuration with respect to each other, and each of the plurality of drive circuits functions as the target drive circuit for the corresponding power transistor. The power supply semiconductor device according to claim 1.

8. An input terminal configured to receive the aforementioned input voltage, It comprises an output terminal configured to receive the aforementioned output voltage, A switching circuit having the plurality of power transistors and the plurality of capacitors is connected to the input terminal and the output terminal, and the plurality of power transistors and the plurality of capacitors are connected to each other so that the output voltage is generated from the input voltage by turning the plurality of power transistors on and off according to the predetermined pattern. The power supply semiconductor device according to claim 1.

9. The detection circuit comprises a selector having a first input terminal for receiving the second voltage, a second input terminal for receiving the drain voltage of the target power transistor, and a selector output terminal connected to the comparator, The selector switches the signal output from the selector output terminal from the first input terminal side to the second input terminal side after the predetermined time has elapsed. The power supply semiconductor device according to claim 1.

10. A power supply semiconductor device according to any one of claims 1 to 4 and 7 to 9, having a plurality of power transistors, Equipped with multiple capacitors, Switched capacitor converter.

11. A power supply semiconductor device having a plurality of power transistors and a plurality of capacitors, configured for use in a switched-capacitor converter that generates an output voltage from an input voltage by turning the plurality of power transistors on and off according to a predetermined pattern, A control block configured to generate control signals that specify whether each power transistor is on or off, The system includes a drive block connected to the gate of each power transistor and configured to turn each power transistor on or off by driving the gate of each power transistor based on the control signal, The drive block has a target drive circuit for a target power transistor which is one of the plurality of power transistors, the target drive circuit is connected to the gate of the target power transistor and supplies a gate signal to the target power transistor based on the target control signal which is the control signal for the target power transistor, The target drive circuit has a detection circuit configured to output a detection signal corresponding to the drain-source voltage of the target power transistor after the gate-source voltage of the target power transistor exceeds the gate threshold voltage of the target power transistor, and generates the gate signal for the target power transistor based on the target control signal and the detection signal. The aforementioned target control signal has a first level or a second level. The target drive circuit is capable of performing a basic turn-on operation to turn on the target power transistor by supplying a voltage exceeding the gate threshold voltage between the gate and source of the target power transistor in response to a change in the target control signal from the first level to the second level, and after the basic turn-on operation, it is capable of performing a basic turn-off operation to turn off the target power transistor by reducing the gate-source voltage of the target power transistor to less than the gate threshold voltage in response to a change in the target control signal from the second level to the first level. In the aforementioned target drive circuit, after the basic turn-on operation, the detection circuit monitors the drain-source voltage of the target power transistor, and outputs the asserted detection signal when the monitored voltage exceeds a predetermined determination voltage. After the basic turn-on operation, when the detection signal in the asserted state is output from the detection circuit, the target drive circuit performs a protection operation to turn off the target power transistor, regardless of the target control signal. The target drive circuit, after the basic turn-on operation and the protection operation, turns off the target power transistor, and then maintains the target power transistor in the off state until a change from the first level to the second level occurs in response to the target control signal. After that, when a change from the first level to the second level occurs in response to the target control signal, it performs the basic turn-on operation again. , power supply semiconductor device.

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