Wafer visual inspection device
The wafer visual inspection device sets a defined outer perimeter inspection area using approximation lines to reliably detect defects on the wafer edges, addressing the challenge of uneven surface conditions and false detections.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TORAY ENG CO LTD
- Filing Date
- 2021-12-24
- Publication Date
- 2026-06-24
AI Technical Summary
Existing wafer inspection technologies struggle to reliably detect defects on the outer edges of wafers due to uneven surface conditions, leading to false defect detection and missed actual defects.
A wafer visual inspection device that sets a defined outer perimeter inspection area by generating approximation lines along and offset from the wafer's edge, allowing consistent defect detection criteria to be applied within this region.
Reliably detects defects like foreign objects and scratches on the wafer's outer edge while preventing false defect detection.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a wafer appearance inspection apparatus that inspects defects such as foreign matter and scratches hidden in a wafer based on an appearance image obtained by imaging the appearance of the wafer to be inspected. For example, it relates to a wafer appearance inspection apparatus that images an appearance image of a semiconductor device or the like formed on the surface of a wafer and compares it with a reference image to determine the quality of the semiconductor device or the like.
Background Art
[0002] A semiconductor device is formed by laminating a large number of semiconductor device circuits (that is, repeated appearance patterns of device chips) on a single semiconductor wafer, and then singulated into individual chip components. The chip components are packaged and shipped as individual electronic components or incorporated into electrical products.
[0003] Before the individual chip components are singulated, an inspection regarding the quality of each chip component is performed by comparing an appearance image (inspection image) obtained by imaging the repeated appearance pattern of the device chips formed on the wafer with a reference image (for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] When performing inspection based on the captured appearance image, in the region inside the outer peripheral portion of the wafer, since the surface state is uniform, the luminance in the appearance image is also uniform. Therefore, defect detection can be relatively easily performed by detecting a dark luminance portion from within a bright luminance region. However, the outer edges of the wafer have uneven surface conditions due to the presence of film edges and beveling, resulting in uneven brightness in the external image. Therefore, inspecting the outer edges was difficult because it was necessary to detect areas with a predetermined brightness within a region where light and dark brightness were mixed. Furthermore, it was easy to falsely detect normal areas as defects (i.e., detect them as pseudo-defects).
[0006] Therefore, the present invention aims to provide a wafer appearance inspection device that can reliably detect defects to be detected, even on the outer periphery of a wafer, and prevent the detection of false defects. [Means for solving the problem]
[0007] To solve the above problems, one aspect of the present invention is: A wafer visual inspection device for inspecting defects present in a wafer, The system includes an inspection unit that inspects an inspection area set on a wafer based on an external image captured of the wafer's exterior. The inspection department, An outer edge position detection unit that detects the position of the outer edge of the wafer included in the external image, An approximation line generation unit performs an approximation line fitting process on the outer edge of an external image to generate a first approximation line at a position along the outer edge, and generates a second approximation line at a position offset by a predetermined dimension inward from the first approximation line on the wafer. In the external image, the region formed by the first approximation line and the second approximation line is set as the outer perimeter inspection area; this is the outer perimeter inspection area setting unit. It includes an outer perimeter inspection unit that inspects the outer perimeter inspection area. It is characterized by the following.
[0008] In this embodiment, a region with a width parallel to the outer edge of the wafer can be set as a single outer perimeter inspection region, and inspection can be performed within that region using the same inspection criteria. [Effects of the Invention]
[0009] Even on the outer edge of the wafer, it is possible to reliably detect defects such as foreign objects and scratches, and to prevent the detection of false defects. [Brief explanation of the drawing]
[0010] [Figure 1] This is a schematic diagram showing the overall configuration of an example of an embodiment of the present invention. [Figure 2] This is a schematic diagram showing the main parts of an example embodiment of the present invention. [Figure 3] This is a schematic diagram showing the main parts of another example of an embodiment of the present invention. [Figure 4] This flowchart shows an example of an inspection flow in an example of an embodiment of the present invention. [Modes for carrying out the invention]
[0011] The embodiments for carrying out the present invention will be described below with reference to the figures. In the following description, the three axes of the Cartesian coordinate system are denoted as X, Y, and Z, the horizontal direction is expressed as the X direction and Y direction, and the direction perpendicular to the XY plane (i.e., the direction of gravity) is expressed as the Z direction. Furthermore, the Z direction is expressed as upward when it is against gravity and downward when it is acting with gravity. The direction of rotation around the Z direction as the central axis is defined as the θ direction.
[0012] Figure 1 is a schematic diagram showing the overall configuration of an example of an embodiment of the present invention. Figure 1 schematically shows the various parts that constitute the wafer appearance inspection apparatus 1 according to the present invention, and shows the imaging of an imaging area F set on the outer periphery of a wafer W.
[0013] The wafer visual inspection device 1 inspects for defects present in the wafer. Specifically, the wafer appearance inspection device 1 acquires an appearance image G of the wafer W, and detects defects by processing the acquired appearance image G. More specifically, the wafer appearance inspection apparatus 1 includes an inspection image acquisition unit 2, an inspection unit 3, a wafer holding unit H, an imaging unit S, a relative movement unit M, a computer CP, a controller CN, and the like.
[0014] Note that, as an example of the wafer W to be inspected in the present invention, a wafer having a substantially circular shape is exemplified. This wafer W has an arc-shaped outer edge portion We at an equal distance from the center Wc, and has a linear outer edge portion Wf called an orientation flat and a recessed portion called a notch in a part of the outer edge portion We. Further, since the wafer W is inspected with the radial direction as the XY direction and the thickness direction as the Z direction, the upper surface side of the wafer W is called the front surface, and the lower surface side is called the back surface.
[0015] The inspection image acquisition unit 2 acquires an appearance image G obtained by imaging the appearance of the wafer W. Specifically, the inspection image acquisition unit 2 sets a range including a region obtained by dividing the surface W1 and / or the outer peripheral portion W2 of the wafer at a predetermined dimension (also referred to as a predetermined pitch) as an imaging region F, and acquires an appearance image G obtained by imaging the imaging region F. More specifically, the inspection image acquisition unit 2 is composed of an imaging unit S, which will be described in detail later, and an input unit of the computer CP.
[0016] FIG. 2 is a schematic diagram showing a main part of an example of an embodiment embodying the present invention. FIG. 2(a) shows an external view obtained by enlarging a part of the outer peripheral portion of the wafer W and an arrangement example of the imaging region F. FIG. 2(b) shows an example of an appearance image G obtained by imaging the imaging region F. Note that, as defects X to be detected on the outer peripheral portion of the wafer W, a crack X1 generated in the arc-shaped outer edge portion We, a scratch X2 generated on the surface, and a foreign matter X3 attached to the surface are exemplified.
[0017] The inspection unit 6 inspects an inspection region set on the wafer W based on the appearance image G obtained by imaging the appearance of the wafer W. This inspection region includes an outer peripheral inspection region R1 and a surface inspection region R2. Specifically, the inspection unit 6 performs predetermined image processing, arithmetic processing, etc. on the appearance image G acquired by the inspection image acquisition unit 2, and detects the defect X existing in the inspection target area. For example, processing is performed on each pixel of the appearance image G, pixels deviating from the reference range (also referred to as a threshold value) are extracted as defect candidates, and based on the area, length, luminance difference from surrounding pixels, etc. of a pixel group in which the pixels regarded as the defect candidates are adjacent to each other, it is determined whether it is a defect X, or the type of the defect X (such as crack, scratch, foreign matter, etc.) is classified, and information regarding the defect X (position, area, length, type, etc.) is output. More specifically, the inspection unit 6 is composed of a processing unit and an image processing unit of a computer CP and an execution program, and includes an outer edge position detection unit 31, an approximate line generation unit 32, an outer peripheral inspection area setting unit 33, an inspection condition setting unit 34, an outer peripheral inspection unit 35, a surface inspection unit 36, etc.
[0018] The outer edge position detection unit 31 detects the position of the outer edge We of the wafer W included in the appearance image G. Specifically, the outer edge position detection unit 31 detects the position of the boundary between the wafer W and the background B included in the appearance image G by image processing or the like. More specifically, the outer edge position detection unit 31 detects a plurality of pixel groups having different luminances from the background B as boundaries T1 to T4, and acquires the positions on the XY coordinates in the appearance image G. Then, taking into account the XY coordinates of the appearance image G, the positions of these boundaries T1 to T4 are output as the position of the outer edge We.
[0019] The approximate line generation unit 32 performs fitting processing of an approximate line with respect to the outer edge We in the appearance image G, generates a first approximate line S1 at a position following the outer edge We, and generates a second approximate line S2 at a position offset by a predetermined dimension inside the wafer W with respect to the first approximate line S1. Further, the approximate line generation unit 32 may generate a third approximate line S3 at a position offset by a predetermined dimension inside the wafer W with respect to the second approximate line S2, and generate a fourth approximate line S4 at a position offset by a predetermined dimension inside the wafer W with respect to the third approximate line S3. Specifically, the approximation line generation unit 32 calculates the curvature of a first approximation line S1 to be fitted to the outer edge We of the wafer W in the appearance image G, based on information such as the size (i.e., diameter) of the wafer W. Then, it calculates the fitting position of the first approximation line S1 so that it lies along the boundary T1 to T4 positions (i.e., coordinates in the XY direction relative to the center W of the wafer W) detected by the outer edge position detection unit 31 using the least squares method, and generates the first approximation line S1. Then, the approximation line generation unit 32 generates a second approximation line S2 at a position offset by a predetermined dimension inward from the first approximation line S1 on the wafer W, based on pre-registered offset dimension values. Furthermore, the approximation line generation unit 32 generates a third approximation line S3 at a position offset by a predetermined dimension inward from the second approximation line S2, based on a pre-registered offset dimension value, and generates a fourth approximation line S4 at a position offset by a predetermined dimension inward from the third approximation line S3. At this time, these second approximation lines S2 to the fourth approximation lines S4 are set as lines parallel to the first approximation line S1 and are generated as concentric approximation curves with respect to the center Wc of the wafer W. Furthermore, the positions offset by a predetermined dimension from each of the aforementioned approximation lines S1, S2, and S3 are predetermined by the operator as offset dimensions, taking into consideration the points where the brightness value of pixels inside the outer edge We of the wafer W in the external image G falls outside a predetermined range, where it changes abruptly, and where a predetermined brightness difference occurs relative to the brightness value of defects that are likely to appear.
[0020] The outer perimeter inspection area setting unit 33 sets the area R1a formed by the first approximation line S1 and the second approximation line S2 in the external image G as the outer perimeter inspection area R1. Specifically, the outer perimeter inspection area setting unit 33 sets the area between the first approximation line S1 and the second approximation line S2 in the external image G as the first outer perimeter inspection area R1a. More specifically, the outer perimeter inspection area setting unit 33 sets the arc-shaped region enclosed by the first approximation line S1, the second approximation line S2, and the edge of the outer perimeter image G as the first outer perimeter inspection area R1a. Furthermore, the outer perimeter inspection area setting unit 33 may set the area between the second approximation line S2 and the third approximation line S3 in the external image G as the second outer perimeter inspection area R1b, and the area between the third approximation line S3 and the fourth approximation line S4 as the third outer perimeter inspection area R1c. In this case, these first to third outer perimeter inspection areas R1a to R1c (i.e., outer perimeter inspection area R1) are set as areas with a width parallel to the outer edge We of the wafer W.
[0021] The inspection condition setting unit 34 sets the inspection conditions for the outer perimeter inspection area R1. Specifically, the inspection condition setting unit 34 sets inspection conditions for detecting defects X present in the outer perimeter inspection area R1. More specifically, the inspection condition setting unit 34 sets inspection conditions according to the observation environment of the appearance image G, the appearance, the characteristics of the defects, etc., including the average brightness in the normal state of the first outer perimeter inspection area R1a, the second outer perimeter inspection area R1b, and the third outer perimeter inspection area R1c, the brightness difference between these and the defects X to be detected (i.e., cracks X1, scratches X2, foreign objects X3, etc.), and inspection parameters such as the area and length of the pixels of the defect candidates to be judged as defects.
[0022] The outer perimeter inspection unit 35 inspects the outer perimeter inspection area R1. Specifically, the outer perimeter inspection unit 35 inspects the first outer perimeter inspection area R1a. Furthermore, the outer perimeter inspection unit 35 may also inspect the second outer perimeter inspection area R1b and the third outer perimeter inspection area R1c. The outer perimeter inspection unit 35 can individually set inspection conditions for the first to third outer perimeter inspection areas R1a to R1c, and inspections are performed under independent inspection conditions. More specifically, the outer perimeter inspection unit 35 performs image processing in each outer perimeter inspection area R1a to R1c, extracts pixels (candidate defects) that have brightness values outside the reference range (also called the threshold) of the average brightness of the inspection area, and detects defects X based on the area and length of the pixel groups adjacent to the candidate defect pixels, the brightness difference with surrounding pixels, etc. Using Figure 2(b) as an example, the outer perimeter inspection unit 35 detects defects X as follows. In the first outer perimeter inspection area R1a, a group of pixels darker than the average brightness extends inward from the outer edge We, thus indicating the presence of a crack X1. In the second outer perimeter inspection area R1b, a group of pixels brighter than the average brightness exists in a predetermined area and length, so it is determined that there is a scratch X2. In the third outer perimeter inspection area R1c, a group of pixels darker than the average brightness exists in a predetermined area, so it is determined that there is a foreign object X3.
[0023] The surface inspection unit 36 inspects the area inside the outer periphery of the wafer W. Specifically, the surface inspection unit 36 inspects whether the circuit patterns of semiconductor devices formed on the surface inspection area R2 (i.e., the flat parts of the front and / or back surfaces of the wafer W) inside the outer peripheral inspection area R1 of the wafer W are formed with a predetermined line width, whether there are any scratches or foreign matter on the circuit patterns, and outputs the location and type of defects. More specifically, the surface inspection unit 36 compares an external image of the surface inspection area R2 captured by image processing with a pre-registered inspection reference image, extracts pixels (candidate defects) that have brightness values outside the reference range (also called a threshold), and detects defects X based on the area and length of the pixel groups adjacent to the candidate defect pixels, the brightness difference with surrounding pixels, etc.
[0024] As described above, a configuration is shown in which a first approximation line S1 is fitted to the outer circumference We of the wafer W, a second approximation line S2 is fitted to the inside of the first approximation line S1 at a predetermined offset position, a third approximation line S3 is fitted further inside, and a fourth approximation line S4 is fitted further inside. The region between the first approximation line S1 and the second approximation line S2 is set as the first outer circumference inspection region R1a, the region between the second approximation line S2 and the third approximation line S3 is set as the second outer circumference inspection region R1b, and the region between the third approximation line S3 and the fourth approximation line S4 is set as the third outer circumference inspection region R1c. However, in realizing the present invention, the configuration is not limited to this one. It may also be a configuration in which an outer perimeter inspection area R1 is first set, and then this outer perimeter inspection area R1 is divided. For example, a first approximation line S1 is fitted to the outer circumference We of the wafer W, and a second approximation line S2 is fitted to the inside of the first approximation line S1 at a predetermined offset position to set an outer circumference inspection area R1. This outer circumference inspection area R1 is then divided and inspected.
[0025] Figure 3 is a schematic diagram showing the main parts of another example of an embodiment of the present invention. Figure 3 shows an example of an external image G obtained by imaging a certain imaging area F.
[0026] In this case, the inspection unit 3 is configured to include an inspection area division unit 37 and an individual inspection condition setting unit 38. Specifically, the inspection unit 3, using Figure 2 as described above, uses an outer edge position detection unit 31 to detect the position of the boundary T (e.g., T1 to T4) between the wafer W and the background B included in the appearance image G by image processing or the like. Then, as shown in Figure 3, the approximation line generation unit 32 fits a first approximation line S1 to the outer periphery We of the wafer W and generates a second approximation line S2 at a position offset by a predetermined dimension inside the first approximation line S1 (in this case, the innermost circumference of the outer periphery inspection area). The positions to be offset by a predetermined dimension inside the approximation line S1 are predetermined by the operator, taking into consideration the locations where the brightness value of pixels inside the outer edge We of the wafer W in the external image G falls outside a predetermined range, where it changes abruptly, and where a predetermined brightness difference occurs relative to the brightness value of defects that are likely to appear.
[0027] The inspection area division unit 37 divides the outer perimeter inspection area R1 into at least two or more divided inspection areas having boundary lines parallel to the first approximation line S1. Specifically, the inspection area division unit 37 sets boundary lines D1 and D2 parallel to the first approximation line S1 in the outer perimeter inspection area R1, and divides the outer perimeter inspection area R1 along these boundary lines D1 and D2 to generate divided inspection areas R1e, R1f, R1g, etc. In other words, divided inspection area R1e is the area sandwiched between the first approximation line S1 and the boundary line D1 parallel to it, divided inspection area R1f is the area sandwiched between boundary line D1 and boundary line D2, and divided inspection area R1g is the area sandwiched between boundary line D2 and the second approximation line S2. The outer perimeter inspection unit 35 then inspects each of these divided inspection areas R1e to R1g. Furthermore, the positions of the boundary lines D1 and D2 that divide the outer perimeter inspection area R1 are set in advance by the operator, taking into consideration, similar to the offset dimensions described above, areas where the brightness value of pixels inside the outer edge We of the wafer W in the external image G falls outside a predetermined range or changes abruptly, and areas where a predetermined brightness difference occurs relative to the brightness value of defects that are likely to appear.
[0028] The individual inspection condition setting unit 38 sets different inspection conditions for each of the divided inspection areas R1e to R1g, which are obtained by dividing the outer perimeter inspection area R1. Specifically, the individual inspection condition setting unit 38 sets inspection conditions according to the location of the divided inspection area R1e to R1g, the observation environment, the appearance, the characteristics of the defect, etc. More specifically, the individual inspection condition setting unit 38 sets inspection conditions that make it easier to find cracks X1 in the divided inspection area R1e, which is set on the outermost edge of the wafer W. On the other hand, for the inner separated inspection areas R1f and R1g, the inspection conditions are set based on the average brightness of these divided inspection areas R1f and R1g in a normal state and the brightness value of the defect X to be detected.
[0029] Furthermore, the acquisition of the external image G by the inspection image acquisition unit 2 and the inspection by the inspection unit 3, as described above, are performed by moving the wafer holding unit H and the imaging unit S relative to each other using the relative movement unit M, thereby sequentially changing the imaging range F relative to the wafer W. Specifically, this may be done by moving the unit relative to each other in one direction while flashing the illumination light L1 like a strobe, or by repeatedly capturing an image and moving to the next imaging position while the unit is stationary.
[0030] The wafer holder H holds the wafer W. Specifically, the wafer holder H supports the lower surface of the wafer W and holds it in a horizontal position. More specifically, the wafer holder H is made up of a flat plate-like member with a holding surface (i.e., the side that contacts the lower surface of the wafer W), and pores and grooves are formed on this holding surface. These pores and grooves are connected to a negative pressure suction means via a switching valve or the like, and when the negative pressure suction means is activated with the wafer W placed on the holding surface, a suction force is generated in the space formed between these pores and grooves and the wafer W. As a result, the wafer W is attracted to the holding surface and held by suction.
[0031] The imaging unit S captures the external appearance of the wafer W and outputs an external image G. Specifically, the imaging unit S includes an imaging camera S1, a lens S2, an illumination unit S3, and the like. The imaging camera S1 captures an image of the imaging area F set on the surface or outer edge (near the outer edge We) of the wafer W, and outputs it externally as an external image G. Specifically, the imaging camera S1 is equipped with an image sensor having a predetermined area (a so-called image area sensor) and outputs the captured image as a video signal or video data to an external source (in this embodiment, a computer CP). Lens S2 is used to form an image of the imaging area F onto the image sensor of the imaging camera S1. The illumination unit S3 irradiates illumination light L1 toward the imaging field of view F so that observation light L2 necessary for imaging is obtained. Specifically, the illumination unit S3 irradiates the imaging area F with a predetermined amount of light. More specifically, the illumination unit S3 can be an LED light, a metal halide lamp, a xenon lamp, a laser diode, etc., and switches on / off or flashes a strobe at a predetermined location or timing based on a signal control from an external source (in this embodiment, a controller CN). The imaging camera S1 and illumination unit S3 are attached to the device frame 1f via connecting fittings (not shown).
[0032] The relative movement unit M moves the wafer holding unit H and the imaging unit S relative to each other. Specifically, the relative movement unit M is configured to include an X-axis slider M1, a Y-axis slider M2, and a rotation mechanism M3. The X-axis slider M1 is mounted on the device frame 1f and moves the Y-axis slider M2 in the X direction at any speed and stops it at any position. Specifically, the X-axis slider consists of a pair of rails extending in the X direction, a slider section that moves along the rails, and a slider drive section that moves and stops the slider section. The Y-axis slider M2 moves the rotation mechanism M3 in the Y direction at an arbitrary speed and stops it at an arbitrary position based on a control signal output from the controller CN. Specifically, the Y-axis slider consists of a pair of rails extending in the Y direction, a slider section that moves along the rails, and a slider drive section that moves and stops the slider section. The slider drive units for the X-axis slider M1 and Y-axis slider M2 can be configured using a combination of a servo motor or pulse motor and a ball screw mechanism, or a linear motor mechanism, which rotate and stop under signal control from the controller CN. The rotation mechanism M3 rotates the mounting base H1 in the θ direction at an arbitrary speed and stops it at an arbitrary angle. Specifically, an example of the rotation mechanism M3 is one that rotates / stops at an arbitrary angle by signal control from an external device such as a direct drive motor. The mounting base H1 of the wafer holding unit H is mounted on the rotating side of the rotation mechanism M3. Because of this configuration, the relative movement unit M can hold the wafer W to be inspected and move the wafer W relative to the imaging unit S in the XYθ directions independently or in combination at a predetermined speed and angle, or to stop it at any position and angle.
[0033] A computer (CP) receives signals and data from an external source, performs predetermined arithmetic and image processing, and outputs signals and data to an external source. Specifically, the computer CP performs the following functions: • Setting and registering the wafer size. • Setting and registering the size of the imaging field of view (F), imaging position, imaging route, etc. • Setting and registering the width of the outer perimeter inspection area R1 (i.e., the offset dimension of the second approximation line S2 relative to the first approximation line S1). • Setting and registering inspection conditions (surface inspection, outer perimeter inspection) • Setting of division conditions for the divided imaging area (number of divisions, offset dimensions, etc.) • Number of registrations More specifically, a computer (CP) consists of an input and output unit, a storage unit (called registers or memory), a control unit and an arithmetic unit (called CPU or MPU), an image processing unit (called GPU), auxiliary storage devices (such as HDDs or SSDs) (i.e., hardware), and its execution program (i.e., software).
[0034] The controller CN inputs and outputs signals and data to external devices (such as the workpiece holding unit H, imaging unit S, relative movement unit M, and computer CP) and performs predetermined control processing. Specifically, the controller CN performs the following functions: • Outputs a signal to the workpiece holding unit H for holding / releasing the wafer W. • Output an imaging trigger to the imaging camera S1. • Output a strobe flash signal to the lighting unit S3. • Drive control of relative movement parts M: A function that monitors the current positions of the X-axis slider M1, Y-axis slider M2, and rotation mechanism M3, outputs drive signals, and controls them. More specifically, the controller CN consists of a part of the computer CP or a dedicated programmable logic controller (i.e., hardware) and its execution program (i.e., software).
[0035] <Operating Modes and Operation Flow> Figure 4 is a flowchart showing an example of an inspection flow in an example of an embodiment of the present invention. Figure 4 shows a configuration in which defects X present in wafer W are inspected based on an appearance image G obtained by capturing the appearance of wafer W using the wafer appearance inspection apparatus 1 described above, as a series of steps in a flow.
[0036] First, the wafer W is placed on the mounting table H1 of the wafer visual inspection device 1 (step s10). Then, the wafer W is aligned by reading the alignment marks formed on the wafer W.
[0037] Next, the relative movement unit M is controlled to move to the imaging position and image the appearance of the wafer W (step s11). Then, the appearance image G is acquired (step s12), and it is determined whether the outer perimeter inspection area R1 is included in the appearance image G (step s13).
[0038] If the outer perimeter inspection area R1 is included in the external image G, the position of the outer edge We of the wafer W is detected (step s14). If the outer perimeter inspection area R1 is not included in the external image G, the surface inspection unit 36 inspects the circuit pattern, etc., on the surface of the wafer W (step s30).
[0039] In the external image G, after detecting the position of the outer edge We of the wafer W, the approximation line generation unit 32 generates the first approximation line S1, the second approximation line S2, etc. (step s15). At this time, You may also generate a third approximation line S3 and a fourth approximation line S4 further inside the second approximation line S2.
[0040] The region R1a, enclosed by the first approximation line S1 and the second approximation line S2, is set as the outer perimeter inspection region R1 (step s16). At this time, the region R1b, enclosed by the second approximation line S2 and the third approximation line S3, or the region Rc, enclosed by the third approximation line S3 and the fourth approximation line S4, may also be set as the outer perimeter inspection region R1.
[0041] Then, it is determined whether or not to divide the outer perimeter inspection area R1 (step s17). If the outer perimeter inspection area R1 is to be divided, the inspection area division unit 37 sets divided inspection areas R1a to R1c etc. for the outer perimeter inspection area R1 (step s18), and each divided inspection area R1a to R1c etc. is inspected by the outer perimeter inspection unit 35 (step s19). On the other hand, if the outer perimeter inspection area R1 is not to be divided, the outer perimeter inspection unit 35 inspects the single outer perimeter inspection area R1 (step s20).
[0042] Then, once the series of examinations (steps s19, s20, s30 described above) are complete, a decision is made on whether to image the next location (step s31).
[0043] If imaging is to be performed at the next location, repeat steps s11 to s31 described above. On the other hand, if imaging is not to be performed at the next location, eject wafer W (step s32) and decide whether to inspect the next wafer W (step 33).
[0044] If the next wafer W is to be inspected, repeat steps s10 to s33 described above. If the next wafer W is not to be inspected, terminate the flow sequence.
[0045] In the above description, an example was given in which the inspection unit 3 is equipped with a surface inspection unit 36, and if the outer peripheral inspection area R1 is not included in the external image G, the surface inspection unit 36 inspects the circuit pattern, etc., on the surface of the wafer W. However, in order to realize the present invention, the surface inspection unit 36 is not an essential component of the inspection unit 3, and the outer peripheral inspection unit 35 may perform inspections specifically for the outer peripheral inspection area R1.
[0046] Because the wafer appearance inspection apparatus 1 according to the present invention has such a configuration, a region with a width parallel to the outer edge We of the wafer W can be set as a single outer peripheral inspection region R1, and inspection can be performed within this region R1 using the same inspection criteria. Therefore, even on the outer peripheral of the wafer W, defects X such as foreign objects and scratches that are to be detected can be reliably detected, and the detection of false defects can be prevented.
[0047] [Other forms / variations] In the above description, an example was given of a configuration in which the first outer perimeter inspection region R1a, which is sandwiched between the first approximation line S1 fitted to the outer edge We of the wafer W and the second approximation line S2 inside it, and the outermost segmented inspection region R1e of the outer perimeter inspection region R1 (i.e., the outermost region that is just inside the outer edge We of the wafer W) are inspected. Such a configuration is preferable because it can detect cracks X1 present in the outer edge We of the wafer W. However, inspection of this region (i.e., detection of crack X1) is not an essential part of applying the present invention. The outermost region may be omitted, and the region (i.e., the second outermost inspection region R1b, the third outermost inspection region R1c, the segmented inspection regions R1f, R1g, etc.) may be set as the outermost inspection region R1 and inspected.
[0048] [Other forms / variations] In the above description, examples of defects X to be detected on the outer periphery of the wafer W were given as cracks X1 on the arc-shaped outer edge We, scratches X2 on the surface, and foreign matter X3 adhering to the surface. The example given was that the approximation line generation unit 32 generates an arc-shaped first approximation line S1 that fits the arc-shaped outer edge We of the wafer W, and the outer periphery inspection area setting unit 33 sets an arc-shaped outer periphery inspection area R1. However, the present invention is not limited to inspecting an outer peripheral inspection area R1 set on such an arc-shaped outer edge We, but can also be applied to inspecting an outer peripheral inspection area that includes a linear outer edge Wf (for example, an orientation flat portion). In this case, the approximation line generation unit 32 performs fitting of an approximation line to the outer edge Wf of the wafer W in the appearance image G, generates a linear first approximation line S1 at a position along the outer edge Wf, and generates a linear second approximation line S2 at a position offset by a predetermined dimension inward from the first approximation line S1 on the wafer W. Then, the outer perimeter inspection area setting unit 33 sets the rectangular area formed by the linear first approximation line S1 and the second approximation line S2 in the appearance image G as the outer perimeter inspection area R1. Then, the outer perimeter inspection unit 35 inspects the rectangular outer perimeter inspection area R1.
[0049] In the above description, the wafer W was given the example of a shape that includes an arc-shaped outer edge We and a straight outer edge Wf, but it may also have a shape that only has an arc-shaped or straight outer edge. Alternatively, even if the shape has an ellipse, polygon, or a curved outer edge that can be fitted with a multidimensional approximation formula, the present invention can be applied to inspect the outer periphery inspection area of the wafer W.
[0050] In the above example, the wafer appearance inspection apparatus is provided with a wafer holding unit H, an imaging unit S, and a relative movement unit M, and the appearance image G of the wafer W is captured while the inspection image acquisition unit 2 acquires the appearance image G. However, the wafer holding unit H, imaging unit S, and relative movement unit M are not essential components for realizing the present invention. The system may also be configured such that an external image G, captured and stored by an external device, is acquired by the inspection image acquisition unit 2 and then inspected by the inspection unit 3 (a so-called offline inspection method). Even with this configuration, the outer peripheral inspection area R1 of the outer edge of the wafer W can be set as described above, and the area within that region can be inspected using the same inspection criteria.
[0051] In the above description, the imaging unit S was illustrated as a configuration in which the imaging camera S1 and the illumination unit S2 are arranged on different optical axes. However, a coaxial incident light system in which the illumination light L1 and the observation light L2 are on the same optical axis is also acceptable. [Explanation of symbols]
[0052] 1. Wafer visual inspection device 2. Image acquisition unit 3. Inspection Department 31 Outer edge position detection unit 32 Approximate line generator 33 Outer Perimeter Inspection Area Setting Unit 34. Inspection Condition Setting Unit 35 Perimeter Inspection Section 36 Surface Inspection Section 37 Inspection area division section 38 Individual Inspection Condition Setting Unit H wafer holding section S Imaging Unit M Moving part CP Computer CN Controller 1f Equipment frame H1 mounting platform S1 Imaging Camera S2 Lens S3 Lighting Section M1 X-axis slider M2 Y-axis slider M3 Rotation Mechanism W wafer We wafer outer edge F Imaging area (field of view) G Exterior Image L1 illumination light L2 Observation Light R testing area R1 Outer perimeter inspection area (R1a~R1c, etc.) R2 Surface Inspection Area T boundary (T1~T4 etc.) X Foreign objects / defects, etc. (X1~X3, etc.)
Claims
1. A wafer visual inspection device for inspecting defects present in a wafer, The system includes an inspection unit that inspects an inspection area set on the wafer based on an external image captured of the wafer's external appearance, The aforementioned inspection unit is An outer edge position detection unit for detecting the position of the outer edge of the wafer included in the aforementioned external image, In the aforementioned external image, an approximation line generation unit performs an approximation line fitting process to the outer edge to generate a first approximation line at a position along the outer edge, and generates a second approximation line at a position offset by a predetermined dimension inward from the first approximation line on the wafer, In the aforementioned external view image, the region formed by the first approximation line and the second approximation line is set as the outer perimeter inspection area, and the outer perimeter inspection area setting unit, It comprises an outer perimeter inspection unit for inspecting the outer perimeter inspection area, The aforementioned outer perimeter inspection unit is, The inspection area division unit divides the outer perimeter inspection area into at least two or more divided inspection areas having a boundary line parallel to the first approximation line, The system includes an individual inspection condition setting unit for setting different inspection conditions for each of the aforementioned divided inspection areas. The outer perimeter inspection unit inspects the divided inspection area as the outer perimeter inspection area. A wafer appearance inspection apparatus characterized by the following.
2. A wafer visual inspection device for inspecting defects present in a wafer, The system includes an inspection unit that inspects an inspection area set on the wafer based on an external image captured of the wafer's external appearance, The aforementioned inspection unit is An outer edge position detection unit for detecting the position of the outer edge of the wafer included in the aforementioned external image, In the aforementioned external image, the approximation line generation unit performs an approximation line fitting process to the outer edge to generate a first approximation line at a position along the outer edge, generates a second approximation line at a position offset by a predetermined dimension inward from the first approximation line, and generates a third approximation line at a position offset by a predetermined dimension inward from the second approximation line. In the aforementioned external view image, the region formed by the second approximation line and the third approximation line is set as the outer perimeter inspection area, and the outer perimeter inspection area setting unit, It comprises an outer perimeter inspection unit for inspecting the outer perimeter inspection area, The aforementioned outer perimeter inspection unit is, The inspection area division unit divides the outer perimeter inspection area into at least two or more divided inspection areas having a boundary line parallel to the first approximation line, The system includes an individual inspection condition setting unit for setting different inspection conditions for each of the aforementioned divided inspection areas. The outer perimeter inspection unit inspects the divided inspection area as the outer perimeter inspection area. A wafer appearance inspection apparatus characterized by the following.
3. The wafer has at least a portion of its outer edge that is arc-shaped. The approximation line generation unit generates the first approximation line and the second approximation line as concentric approximation curves. A wafer appearance inspection apparatus according to claim 1 or claim 2, characterized in that