Semiconductor equipment

Abstract

To improve operational reliability.SOLUTION: According to one embodiment, a first transistor includes a source connected to a first terminal and a gate connected to a first node. A first circuit includes a first comparator and a current limiting circuit. The first comparator includes a non-inverting input terminal connected to the first terminal and an inverting input terminal to which a first voltage is applied. The current limiting circuit includes one end connected to an output terminal of the first comparator and the other end connected to the first node. The second circuit includes a second comparator, second and third transistors, and a third circuit. The second comparator includes a non-inverting input terminal connected to the first terminal and an inverting input terminal to which a second voltage is applied. The second transistor includes a source grounded and a drain connected to the first node. The third transistor includes a source grounded and a drain connected to the output terminal of the first comparator. The third circuit is configured to turn on the second transistor and the third transistor for a first time period on the basis of an output of the second comparator.SELECTED DRAWING: Figure 2

Description

Technical Field

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[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Semiconductor devices for supplying power to a load and having an overcurrent protection function are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve operational reliability.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first transistor, a first circuit, and a second circuit. The first transistor has its source connected to a first terminal and its gate connected to a first node. The first circuit includes a first comparator and a current limiting circuit. The first comparator includes a non-inverting input terminal connected to a first terminal and an inverting input terminal to which a first voltage is applied. One end of the current limiting circuit is connected to the output terminal of the first comparator and the other end is connected to a first node. The second circuit includes a second comparator, a second transistor, a third transistor, and a third circuit. The second comparator includes a non-inverting input terminal connected to a first terminal and an inverting input terminal to which a second voltage is applied. The second transistor has its source grounded and its drain connected to a first node. The third transistor has its source grounded and its drain connected to the output terminal of the first comparator. The third circuit turns on the second and third transistors for a first period based on the output of the second comparator. When a power supply voltage is applied to the drain of the first transistor and the first terminal is short-circuited to the ground voltage, the semiconductor device discharges the first node for a first period by the second transistor, thereby reducing the current flowing through the first transistor and maintaining the voltage at the first terminal above 0V. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a semiconductor device according to the first embodiment, an electronic device powered by the semiconductor device, and a power supply that supplies power to the semiconductor device. [Figure 2] A circuit diagram showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 3] A timing chart showing an example of operation of a semiconductor device according to the first embodiment. [Figure 4] A circuit diagram illustrating an example of the configuration of a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. In the description, components having substantially the same function and configuration will be denoted by the same reference numerals. Furthermore, the embodiments shown below are illustrative of the technical concept. The embodiments do not specify the material, shape, structure, arrangement, etc., of the components. Various modifications can be made to the embodiments.

[0008] [1] First Embodiment A semiconductor device according to the first embodiment will be described.

[0009] [1-1] Composition Figure 1 is a block diagram showing an example configuration of a semiconductor device, an electronic device powered by the semiconductor device, and a power supply that supplies power to the semiconductor device according to the first embodiment. The semiconductor device 1 is a load switch that supplies power to a load and has an overcurrent protection function. The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The semiconductor device 1 is also called, for example, an electronic fuse. The electronic device 2 is an electronic device that receives a power supply voltage from the semiconductor device 1 and performs various functions. The electronic device 2 is, for example, an IC chip. The electronic device 2 is, for example, a control circuit for an industrial robot. The power supply PS is a voltage source that outputs a DC voltage.

[0010] The semiconductor device 1 includes terminals TIN and TOUT. Terminal TIN is an input terminal of the semiconductor device 1. A power supply PS, located outside the semiconductor device 1, is connected to terminal TIN, and a voltage VIN is applied to it. Terminal TOUT is an output terminal of the semiconductor device 1. Power is supplied from terminal TOUT to an external electronic device 2. Specifically, a voltage VOUT is output from terminal TOUT to the electronic device 2. A current IOUT is output from terminal TOUT to the electronic device 2.

[0011] The semiconductor device 1 has an overcurrent protection function. Specifically, when the current IOUT becomes large, it limits the voltage VOUT and current IOUT to protect the semiconductor device 1 and the electronic device 2 from damage due to overcurrent.

[0012] The electronic device 2 includes a resistor RL and a resistor RS, as well as a switch SW1. The resistors RL and RS are resistors that consume power. The resistor RL simulates the power consumption when the electronic device is operating normally. The resistor RS simulates the power consumption when the electronic device has a fault accompanied by a short circuit to the ground voltage. The resistance value of the resistor RL is larger than the resistance value of the resistor RS. The resistance value of the resistor RS is a low value close to 0Ω. One end of the resistor RL is connected to the terminal TOUT. The other end of the resistor RL is grounded. One end of the switch SW1 is connected to the terminal TOUT. One end of the resistor RS is connected to the other end of the switch SW1. The other end of the resistor RS is grounded.

[0013] The state of the electronic device 2 is switched by turning on and off the switch SW1. When the switch SW1 is off, the electronic device 2 is in a normal state where power is consumed by the resistor RL. When the normal-state electronic device 2 is connected, the semiconductor device 1 supplies power. When the switch SW1 is on, the electronic device 2 is in a short-circuit state where power is consumed by the resistor RL and the resistor RS. When the short-circuit-state electronic device 2 is connected and a large current flows, the semiconductor device 1 executes a protection operation.

[0014] FIG. 2 is a circuit diagram showing an example of the configuration of the semiconductor device according to the first embodiment. The semiconductor device 1 further includes a transistor NM1, a short-circuit protection circuit 10, an overcurrent protection circuit 20, and a gate driver 30.

[0015] The transistor NM1 is an N-channel MOSFET. The source of the transistor NM1 is connected to the terminal TOUT. The drain of the transistor NM1 is connected to the terminal TIN. The gate of the transistor NM1 is connected to the node N1. The transistor NM1 supplies power to the electronic device 2 via the terminal TOUT when the transistor NM1 is in the on state. The transistor NM1 does not supply power to the electronic device 2 via the terminal TOUT when the transistor NM1 is in the off state.

[0016] The short-circuit protection circuit 10 protects the semiconductor device 1 from overcurrent due to a short circuit between the terminal TOUT and the ground voltage. The short-circuit protection circuit 10 monitors the voltage VOUT, and when the terminal TOUT is short-circuited to the ground voltage, it discharges the node N1 for a period Td and invalidates the overcurrent protection circuit 20. The period Td will be described later.

[0017] The overcurrent protection circuit 20 protects the semiconductor device 1 from overcurrent. The overcurrent protection circuit 20 monitors the voltage VOUT, and when the current IOUT becomes large, it controls the voltage of the node N1 to limit the magnitude of the current IOUT.

[0018] The gate driver 30 supplies a voltage to the node N1. The gate driver 30 is, for example, a charge pump.

[0019] The short-circuit protection circuit 10 includes a comparator CMP1, inverters INV1 to INV5, resistors R1 and R2, a capacitor C1, a NAND gate ND1, and transistors NM2 and NM3. The transistors NM2 and NM3 are N-channel MOSFETs.

[0020] The non-inverting input terminal of the comparator CMP1 is connected to the terminal TOUT. A voltage VSCP is applied to the inverting input terminal of the comparator CMP1. The voltage VSCP is a voltage that can occur at the terminal TOUT when the terminal TOUT is short-circuited to the ground voltage. The voltage VSCP is lower than the voltage VIN and higher than 0V. The output terminal of the comparator CMP1 is connected to the node N2.

[0021] One end of the resistor R1 is connected to the node N2. The other end of the resistor R1 is connected to the node N3. One electrode of the capacitor C1 is connected to the node N3. The other electrode of the capacitor C1 is grounded. The inverter INV1 inverts the logic level of the node N3 and outputs it to the inverter INV2. The inverter INV2 inverts the output of the inverter INV1 and outputs it to the node N4.

[0022] Inverter INV3 inverts the logic level of node N2 and outputs it to node N5. NAND gate ND1 performs a NAND operation on the logic levels of node N4 and node N5 and outputs the result to node N6.

[0023] Inverter INV4 inverts the logic level of node N6 and outputs it to node N7. The source of transistor NM2 is grounded. The gate of transistor NM2 is connected to node N7. One end of resistor R2 is connected to node N1. The other end of resistor R2 is connected to the drain of transistor NM2.

[0024] Inverter INV5 inverts the logic level of node N6 and outputs it to node N8. The source of transistor NM3 is grounded. The drain of transistor NM3 is connected to node N9. The gate of transistor NM3 is connected to node N8.

[0025] The set of inverters INV1 to INV3, resistor R1, capacitor C1, and NAND gate ND1 is also called the timing generator 11. In other words, the input terminal of the timing generator 11 is connected to node N2. The output terminal of the timing generator 11 is connected to node N6.

[0026] The overcurrent protection circuit 20 includes a comparator CMP2 and a current limiting circuit 21.

[0027] The non-inverting input terminal of comparator CMP2 is connected to terminal TOUT. Voltage VOCL is applied to the inverting input terminal of comparator CMP2. Voltage VOCL is the voltage that can occur at terminal TOUT when the current IOUT is large. Voltage VOCL is lower than voltage VIN and higher than voltage VSCP. The output terminal of comparator CMP2 is connected to node N9.

[0028] One end of the current limiting circuit 21 is connected to node N9. The other end of the current limiting circuit 21 is connected to node N1.

[0029] The overcurrent protection circuit 20 configures negative feedback through a path that includes transistor NM1. Specifically, the negative feedback is configured through the output terminal of comparator CMP2, one end of current limiting circuit 21, the other end of current limiting circuit 21, the gate of transistor NM1, the source of transistor NM1, and the non-inverting input terminal of comparator CMP2. Through this negative feedback, the overcurrent protection circuit 20 controls the voltage at node N1 when the voltage VOUT is lower than the voltage VOCL.

[0030] [1-2] Operation The operation of semiconductor device 1 will be explained. The voltage at node N1 will be called voltage VN1. The voltage at node N2 will be called voltage VN2. The voltage at node N3 will be called voltage VN3. The voltage at node N4 will be called voltage VN4. The voltage at node N5 will be called voltage VN5. The voltage at node N6 will be called voltage VN6. The voltage at node N7 will be called voltage VN7. The voltage at node N8 will be called voltage VN8. The voltage at node N9 will be called voltage VN9.

[0031] Figure 3 is a timing chart showing an example of operation of a semiconductor device according to the first embodiment. Figure 3 shows how the semiconductor device 1, which was supplying power to the electronic device 2, detects a short circuit in the electronic device 2 and performs a protective operation. Figure 3 shows voltages VOUT, VSCP, VOCL, current IOUT, VN2, VN4, VN5, VN6, VN7, and VN8.

[0032] At time t0, electronic device 2 is in its normal state, and semiconductor device 1 is supplying power to electronic device 2. More specifically, in electronic device 2, switch SW1 is in the off state, and resistor RL is consuming power.

[0033] In semiconductor device 1, the gate driver 30 supplies voltage to node N1. Because the voltage at node N1 is sufficiently high, transistor NM1 is in the ON state. When transistor NM1 is ON, it outputs a voltage VOUT to terminal TOUT that is approximately equal in height to the voltage VIN.

[0034] In the short-circuit protection circuit 10, comparator CMP1 compares voltage VOUT and voltage VSCP. At time t0, voltage VOUT is higher than voltage VSCP, so comparator CMP1 outputs a "H" level to node N2. Therefore, voltage VN2 is at a "H" level. Because the "H" level at node N2 was maintained for a long period, voltage VN3 is at a "H" level because capacitor C1 is sufficiently charged. Inverter INV1 inverts the "H" level at node N3, and inverter INV2 inverts that, resulting in voltage VN4 being at a "H" level. Inverter INV3 inverts the "H" level at node N2 and outputs it to node N5, so voltage VN5 is at a "L" level. NAND gate ND1 performs a NAND operation on the "H" level at node N4 and the "L" level at node N5, and outputs a "H" level to node N6.

[0035] Inverter INV4 inverts the "H" level of node N6 and outputs it to node N7, resulting in a voltage VN7 at a "L" level. Because voltage VN7 is at a "L" level, transistor NM2 is in the off state. Therefore, the short-circuit protection circuit 10 does not discharge node N1. Inverter INV5 inverts the "H" level of node N6 and outputs it to node N8, resulting in a voltage VN8 at a "L" level. Because voltage VN8 is at a "L" level, transistor NM3 is in the off state. Therefore, the short-circuit protection circuit 10 does not discharge node N9. In other words, the short-circuit protection circuit 10 does not disable the overcurrent protection circuit 20.

[0036] The overcurrent protection circuit 20 does not control the voltage at node N1 because, at time t0, the voltage VOUT is higher than the voltage VOCL.

[0037] At time t1, electronic device 2 switches from the normal state to a short-circuit state. More specifically, in electronic device 2, switch SW1 switches from the off state to the on state, and resistor RS begins to consume power in addition to resistor RL. Since the resistance value of resistor RS is low, close to 0Ω, after time t1, the current IOUT increases and the voltage VOUT decreases. Time t1 is the moment when the increase in current IOUT and the decrease in voltage VOUT begin, and at this point, voltage VOUT is higher than voltage VSCP, so the voltages VN2, VN4, VN5, VN6, VN7, and VN8 shown in the diagram do not change compared to time t0.

[0038] At time t2, the voltage VOUT falls below the voltage VOCL. As a result, the overcurrent protection circuit 20 starts operating to control the voltage at node N1. However, because the overcurrent protection circuit 20, which uses negative feedback to control the voltage at node N1, takes time from the start of operation until it actually performs the control, it has not yet managed to control the current IOUT. Note that even at this point, the voltage VOUT is still higher than the voltage VSCP, so the voltages VN2, VN4, VN5, VN6, VN7, and VN8 shown in the figure remain unchanged compared to time t0.

[0039] At time t3, voltage VOUT falls below voltage VSCP. This changes the operation of the short-circuit protection circuit 10. Specifically, because voltage VOUT is lower than voltage VSCP, comparator CMP1 outputs an "L" level to node N2. Therefore, voltage VN2 changes to an "L" level. Voltage VN3 remains at an "H" level at time t3 because resistor R1 and capacitor C1 maintain an "H" level. Since voltage VN3 does not change, voltage VN4 also remains at an "H" level. Inverter INV3 inverts the "L" level of node N2 and outputs it to node N5, causing voltage VN5 to change to an "H" level. NAND gate ND1 performs a NAND operation on the "H" level of node N4 and the "H" level of node N5, outputting an "L" level to node N6.

[0040] Inverter INV4 inverts the "L" level of node N6 and outputs it to node N7, changing voltage VN7 to "H" level. Because voltage VN7 has changed to "H" level, transistor NM2 turns on. Node N1 is connected to the ground voltage via the now-on transistor NM2 and resistor R2. Therefore, the short-circuit protection circuit 10 discharges node N1.

[0041] Inverter INV5 inverts the "L" level of node N6 and outputs it to node N8, changing the voltage VN8 to the "H" level. Because the voltage VN8 has changed to the "H" level, transistor NM3 turns on. Through the now-on transistor NM3, node N9 is connected to the ground voltage. Therefore, the short-circuit protection circuit 10 discharges node N9 and disables the overcurrent protection circuit 20 by preventing its negative feedback from functioning. Since the time between time t2 and time t3 is very short, the negative feedback of the overcurrent protection circuit 20 has not been able to function. In other words, the overcurrent protection circuit 20 is disabled by the short-circuit protection circuit 10 without controlling the current IOUT.

[0042] Discharge from node N1 begins at time t3, but because it takes time for the voltage VN1 to decrease and for transistor NM1 to limit the current, the current IOUT continues to increase after time t3 and reaches a peak. After the peak, the current IOUT decreases. The voltage VOUT also continues to decrease after time t3.

[0043] Furthermore, the charge stored in capacitor C1 is discharged to node N2 at the "L" level via resistor R1. In other words, the voltage at node N3 decreases from time t3 onward.

[0044] At time t4, the voltage at node N3 falls below the logic level threshold voltage of inverter INV1. In other words, inverter INV1 determines that voltage VN3 is at the "L" level and outputs an "H" level to inverter INV2. Inverter INV2, having received the "H" level, inverts its logic level and outputs an "L" level to node N4. Since voltage VN5 remains at the "H" level from time t3, the NAND gate ND1 performs a NAND operation on the "L" level at node N4 and the "H" level at node N5, and outputs an "H" level to node N6.

[0045] Inverter INV4 inverts the "H" level at node N6 and outputs it to node N7, changing the voltage VN7 to a "L" level. Because the voltage VN7 has changed to a "L" level, transistor NM2 turns off. Because transistor NM2 is off, the discharge at node N1 stops.

[0046] Inverter INV5 inverts the "H" level at node N6 and outputs it to node N8, changing the voltage VN8 to a "L" level. Because the voltage VN8 has changed to a "L" level, transistor NM3 turns off. Because transistor NM3 is off, the discharge at node N9 stops, and the negative feedback of the overcurrent protection circuit 20 starts functioning again. In other words, the overcurrent protection circuit 20 is activated.

[0047] From time t4 onward, the current IOUT is limited by the overcurrent protection circuit 20, and the voltage VOUT is limited to a positive value corresponding to the current IOUT.

[0048] The period from time t3 to time t4 is called period Td. Period Td is longer than the period from the start of discharge at node N1 until the current IOUT reaches its peak. Period Td is shorter than either the period from the start of discharge at node N1 until the current IOUT drops to 0A, or the period from the start of discharge at node N1 until the voltage VOUT drops to 0V.

[0049] The period Td is determined by the contributions of resistors R2 and R1, and capacitor C1. The contribution of each element will be explained below.

[0050] Resistor R2 contributes to the discharge rate of node N1. When node N1 is discharged, the rate at which the voltage decreases is determined, for example, by the parasitic capacitance of node N1, the resistance value of resistor R2, and the on-resistance of transistor NM2. Specifically, if the sum of the resistance value of resistor R2 and the on-resistance of transistor NM2 is small, the rate at which the voltage of node N1 decreases is fast. If the sum of the resistance value of resistor R2 and the on-resistance of transistor NM2 is large, the rate at which the voltage of node N1 decreases is slow. If the rate at which the voltage of node N1 decreases is too fast, the period Td becomes too short, making it difficult to implement the timing generator 11. If the rate at which the voltage of node N1 decreases is too slow, the current IOUT becomes large, which may damage the semiconductor device 1. Therefore, the size of resistor R2 is determined so as to facilitate the implementation of the timing generator 11 while keeping the current IOUT from becoming too large. Note that if a discharge rate suitable for the implementation of the timing generator 11 can be obtained using only the on-resistance of transistor NM2, resistor R2 may be omitted.

[0051] Once the magnitude of resistor R2 is determined, the required period Td is determined. The resistance value of resistor R1 and the capacitance value of capacitor C1 are determined to correspond to the required period Td. More specifically, the resistance value of resistor R1 and the capacitance value of capacitor C1 are determined so that the rate at which the signal is transmitted from node N2 to node N4 is slower by the period Td compared to the rate at which the signal is transmitted from node N2 to node N5.

[0052] [1-3] Effects The semiconductor device 1 according to the first embodiment described above can improve operational reliability. The effects of the semiconductor device 1 according to the first embodiment will be described in detail below.

[0053] One known method of protection when the output terminal of a load switch is short-circuited to ground voltage is to turn off the load switch. By turning off the load switch and setting the output voltage to 0V and the output current to 0A, the load switch can be protected from overcurrent. However, if, for example, the load connected to the load switch contains inductance, turning off the load switch may result in a negative voltage at the output terminal. When the output terminal voltage becomes negative, the load switch and the electronic equipment connected to the load switch may fail or malfunction. To prevent the output terminal voltage from becoming negative, it is preferable to maintain positive values ​​for both the output terminal voltage and output current even in the event of a short circuit.

[0054] The semiconductor device 1 according to the first embodiment includes a timing generator 11. When the comparator CMP1 detects a short circuit, the timing generator 11 turns transistors NM2 and NM3 from the off state to the on state for a period Td. As transistor NM2 turns on for a period Td, the current IOUT begins to decrease after exceeding its peak, and the discharge of node N1 by transistor NM2 ends when the voltage VOUT is higher than 0V.

[0055] Furthermore, after the period Td has elapsed, the overcurrent protection circuit 20, which had been deactivated by transistor NM3, becomes active and limits the current IOUT to less than or equal to the current IOCL. Along with the current limiting, the voltage VOUT is also limited to a certain positive value.

[0056] Thus, the semiconductor device 1 according to the first embodiment can suppress overcurrent due to a short circuit while maintaining the output terminal voltage and output current at positive values. As a result, the semiconductor device 1 according to the first embodiment can improve operational reliability.

[0057] [2] Second embodiment The configuration of the semiconductor device according to the second embodiment differs from that of the semiconductor device according to the first embodiment in the configuration of the short-circuit protection circuit. The differences between the semiconductor device 1a according to the second embodiment and the first embodiment are described below.

[0058] [2-1] Composition Figure 4 is a circuit diagram illustrating an example of the configuration of a semiconductor device according to the second embodiment. In the semiconductor device 1a according to the second embodiment, the short-circuit protection circuit 10 of the semiconductor device 1 described in the first embodiment is replaced with a short-circuit protection circuit 10a. The short-circuit protection circuit 10a according to the second embodiment differs from the short-circuit protection circuit 10 according to the first embodiment in that it further includes a timing generator 11a including inverters INV6 to INV8, a resistor R3, a capacitor C2, and a NAND gate ND2, and the input terminal of inverter INV5 is connected to the timing generator 11a.

[0059] One end of resistor R3 is connected to node N2. The other end of resistor R3 is connected to one electrode of capacitor C2. The other electrode of capacitor C2 is grounded. Inverter INV6 inverts the logic level of the node to which the other end of resistor R3 and one electrode of capacitor C2 are connected and outputs it to inverter INV7. Inverter INV7 inverts the output of inverter INV6 and outputs it to NAND gate ND2.

[0060] Inverter INV8 inverts the logic level of node N2 and outputs it to NAND gate ND2. NAND gate ND2 performs a NAND operation on the output of inverter INV7 and the output of inverter INV8, and outputs the result to inverter INV5.

[0061] Inverter INV5 inverts the output of NAND gate ND2 and outputs it to node N8.

[0062] The other configurations of the semiconductor device 1a according to the second embodiment are the same as those of the semiconductor device 1 according to the first embodiment.

[0063] [2-2] Operation The operation of the semiconductor device 1a according to the second embodiment will now be described. The operation of the semiconductor device 1a according to the second embodiment differs from the operation of the semiconductor device 1 according to the first embodiment in that the inverter INV5 and the transistor NM3 operate based on the output of the timing generator 11a.

[0064] Similar to the semiconductor device 1 according to the first embodiment, the inverter INV4 and transistor NM2 operate based on the output of the timing generator 11. Based on the output of the timing generator 11, the period Td during which transistor NM2 is ON is determined based on the resistance value of resistor R1 and the capacitance value of capacitor C1.

[0065] The timing generator 11a operates in the same manner as the timing generator 11. Based on the output of the timing generator 11a, the period during which transistor NM3 is ON is called period Td2. Period Td2 is determined based on the resistance value of resistor R3 and the capacitance value of capacitor C2.

[0066] Other operations are the same as those of the semiconductor device 1 according to the first embodiment.

[0067] [2-3] Effects In the semiconductor device 1a according to the second embodiment, the period Td during which transistor NM2 is ON and the period Td2 during which transistor NM3 is ON can be set individually. In other words, the period during which node N1 is discharged and the period during which the overcurrent protection circuit 20 is disabled can be set independently. Even with the timing generator configured in this way, the semiconductor device 1a according to the second embodiment can suppress overcurrent due to short circuits while maintaining the output terminal voltage and output current at positive values, similar to the semiconductor device 1 according to the first embodiment. As a result, the operational reliability of the semiconductor device 1a according to the second embodiment can be improved.

[0068] [3] Variations etc. In the above embodiment, the semiconductor device, which is a load switch with an overcurrent protection function, was described as being configured on a single IC chip. The load switch may be configured by combining multiple components, for example, an IC chip that controls the gate voltage and a transistor package. Even when the load switch is configured by combining multiple components, the same effects as in the embodiment can be obtained.

[0069] In the above embodiment, the control circuit of an industrial robot was used as an example of the electronic device to which the semiconductor device supplies power. The configuration of the electronic device to which the semiconductor device supplies power is not limited to the example shown in the above embodiment. The electronic device to which the semiconductor device supplies power may be, for example, an information processing terminal such as a personal computer or a smartphone.

[0070] In the above embodiment, the case in which one or two inverters are connected in series was described as an example. The number of inverters used in series can be changed as long as the number remains odd or even. For example, a configuration using one inverter may be changed to a configuration using three inverters connected in series. A configuration using two inverters connected in series may be changed to a configuration using four inverters connected in series.

[0071] In this specification, "voltages are approximately equal" means that even if there is a small voltage difference due to the effects of the transistor's on-resistance, leakage current, wiring resistance, etc., the voltages are considered to be approximately equal.

[0072] In this specification, “connected” means electrically connected, and does not exclude, for example, the intervening of another element. Also, “electrically connected” may be via an insulator, as long as it is possible to operate as if electrically connected. Furthermore, in this specification, “on state” means that a voltage equal to or greater than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor. “Off state” means that a voltage less than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor, and does not exclude the flow of a small current, such as the leakage current of the transistor.

[0073] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0074] 1,1a...Semiconductor equipment, 2...Electronic equipment, 10,10a...Short circuit protection circuit, 11,11a...Timing generator, 20...Overcurrent protection circuit, 21...Current limiting circuit, 30...Gate driver, C1,C2...Capacitor, CMP1,CMP2...Comparator, INV1~INV8...Inverter, ND1,ND2...NAND gate, NM1~NM3...Transistor, PS...Power supply, R1~R3,RL,RS...Resistor, SW1...Switch, TIN,TOUT...Terminal.

Claims

1. A first transistor whose source is connected to the first terminal and whose gate is connected to the first node, The first circuit and The second circuit and Includes, The first circuit is, A first comparator including a non-inverting input terminal connected to the first terminal and an inverting input terminal to which a first voltage is applied, A current limiting circuit having one end connected to the output terminal of the first comparator and the other end connected to the first node, Includes, The second circuit is, A second comparator including a non-inverting input terminal connected to the first terminal and an inverting input terminal to which a second voltage is applied, A second transistor whose source is grounded and whose drain is connected to the first node, A third transistor whose source is grounded and whose drain is connected to the output terminal of the first comparator, A third circuit that turns on the second transistor and the third transistor for a first period based on the output of the second comparator, Includes, When the power supply voltage is applied to the drain of the first transistor and the first terminal is short-circuited to the ground voltage, the first node is discharged by the second transistor for a first period, thereby reducing the current flowing through the first transistor and maintaining the voltage at the first terminal above 0V. Semiconductor equipment.

2. The third circuit includes a first resistor, a first capacitor, a first inverter, a second inverter, a third inverter, a first NAND gate, a fourth inverter, and a fifth inverter. One end of the first resistor is connected to the output terminal of the second comparator, and the other end of the first resistor is connected to one electrode of the first capacitor. The other electrode of the first capacitor is grounded. The input terminal of the first inverter is connected to the other terminal of the first resistor. The input terminal of the second inverter is connected to the output terminal of the first inverter. The input terminal of the third inverter is connected to the output terminal of the second comparator. The first NAND gate performs a NAND operation on the output of the second inverter and the output of the third inverter, and outputs the result of the NAND operation. The input terminal of the fourth inverter is connected to the output terminal of the first NAND gate, and the output terminal of the fourth inverter is connected to the gate of the second transistor. The input terminal of the fifth inverter is connected to the output terminal of the first NAND gate, and the output terminal of the fifth inverter is connected to the gate of the third transistor. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1, wherein a third resistor is provided between the drain of the second transistor and the first node.

4. Further including a fourth circuit that supplies voltage to the first node, The semiconductor device according to claim 1.

5. The first voltage is higher than the second voltage. The semiconductor device according to claim 1.

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