A system and method for performing deformation and stress analysis modeling within a virtual manufacturing environment.

The virtual manufacturing environment addresses the complexity of semiconductor manufacturing by enabling deformation and stress analysis directly from voxel-based models, enhancing model construction speed and reducing costs while optimizing the manufacturing process.

JP7883488B2Inactive Publication Date: 2026-07-01COVENTOR INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
COVENTOR INC
Filing Date
2021-10-14
Publication Date
2026-07-01
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

The increasing complexity of semiconductor manufacturing processes, particularly at advanced technology nodes, leads to lengthy and costly trial-and-error experimental runs in traditional physical manufacturing environments, resulting in negative or invalid characterization results.

Method used

A virtual manufacturing environment that enables deformation and stress analysis modeling directly from voxel-based models, allowing for the simulation of process sequences without the need for interface-matched meshes, and performs stress and deformation analysis within the environment.

Benefits of technology

Accelerates the construction of structural models, reduces computational costs, and provides rapid verification of process assumptions by predicting the complete 3D structure of semiconductor devices, thereby optimizing the manufacturing process.

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Abstract

Embodiments of the present invention provide the ability to perform deformation and stress analysis modeling within a virtual manufacturing environment. More particularly, embodiments enable a virtual manufacturing environment in which deformation and stress analysis can be modeled directly from a voxel-based model without the need to generate an interface-matched mesh. The stress field in a semiconductor device structure may be determined at specified points in a process sequence used to manufacture the semiconductor device.
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