Breakdown relaxation for programmable resistive memory elements

Abstract

This invention provides a method for reducing the threshold voltage of a threshold switching selector in a programmable resistive memory cell. [Solution] When the memory system controls the circuit to apply a voltage across the programmable resistive memory cell to lower the threshold voltage of the threshold switching selector in the programmable resistive memory cell, it applies a first control signal to the circuit to establish a first resistance of the transistor in series with the programmable resistive memory cell, word line, and bit line. The memory system applies a second control signal to the circuit to establish a second resistance of the circuit in series with the programmable resistive memory cell, word line, and bit line to read the selected programmable resistive memory. The second resistance is lower than the first resistance.

Description

[Technical Field]

[0001] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants (PDAs), medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery). Non-volatile memory can be made to appear non-volatile for at least a limited time by adding a battery to the power source outside the memory chip.

[0002] Memory cells may reside in a crosspoint memory array. In a memory array with a crosspoint architecture, a set of conductive wires extends across the surface of the substrate, and another set of conductive wires is formed on top of the other set of conductive wires that extends perpendicular to the initial layer. Memory cells are located at the crosspoint junction of the two sets of conductive wires. A crosspoint memory array is sometimes called a crossbar memory array.

[0003] Programmable resistive memory cells are formed from materials that have programmable resistance. In a binary approach, a programmable resistive memory cell can be programmed to one of two resistive states, namely a high-resistance state (HRS) and a low-resistance state (LRS). In some techniques, three or more resistive states may be used. One type of programmable resistive memory cell is a magnetoresistive random-access memory (MRAM) cell. MRAM cells use magnetization to represent stored data, in contrast to some other memory technologies that use electric charge (DRAM) or voltage (SRAM) to store data. Bits of data are written to an MRAM cell by changing the direction of magnetization of the magnetic elements ("free layer") within the MRAM cell, and bits are read out by measuring the resistance of the MRAM cell, such resistance changing with the direction of magnetization. However, crosspoint memory arrays may have other types of memory cells. For example, a crosspoint memory array may have memory cells of other technologies such as ReRam, Phase Change Memory (PCM), or FeRam.

[0004] In a crosspoint memory array, each memory cell may include a threshold switching selector in series with a material having programmable resistance. The threshold switching selector has high resistance in the off or non-conductive state until it is biased to a voltage higher than its threshold voltage (Vt) or a current higher than its threshold current (It), and until its voltage bias drops to a current below Vhold ("Voffset") or a current below the holding current Ihold. After Vt is exceeded, and while Vhold is exceeded across the threshold switching selector, the threshold switching selector has significantly low resistance (in the on or conductive state). The threshold switching selector remains on until its current falls below the holding current Ihold or its voltage falls below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by being turned on before the resistance state of the memory cell is determined. An example of a threshold switching selector is an ovonic threshold switch (OTS). Other examples of threshold switching selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metal (MIMs), or other materials that provide a highly nonlinear dependence of current on the selection voltage. [Brief explanation of the drawing]

[0005] Elements with similar numbering refer to common components in different drawings. [Figure 1] This is a block diagram of one embodiment of a non-volatile memory system connected to a host. [Figure 2] This is a block diagram of one embodiment of a memory die. [Figure 3] This is a block diagram of one embodiment of an integrated memory assembly including a control die and a memory structure die. [Figure 4A] The perspective view shows one embodiment of a part of the memory array that forms a crosspoint architecture. [Figure 4B]Respectively, a side view and a top view of the cross-point structure of FIG. 4A are shown. [Figure 4C] Respectively, a side view and a top view of the cross-point structure of FIG. 4A are shown. [Figure 4D] In a perspective view, an embodiment of a part of a two-level memory array forming a cross-point architecture is shown. [Figure 5] An embodiment of the structure of a MRAM memory cell is shown, where for example, a selected cell is driven by a current source for reading or writing. [Figure 6A] An embodiment for incorporating a threshold switching selector into a MRAM memory array having a cross-point architecture is shown. [Figure 6B] An embodiment for incorporating a threshold switching selector into a MRAM memory array having a cross-point architecture is shown. [Figure 7A] An embodiment of a memory array having a cross-point architecture accessed using a forced voltage approach is shown. [Figure 7B] An embodiment of a memory array having a cross-point architecture in which a current force approach is used is shown. [Figure 8] It is a schematic diagram showing the resistance along the path for supplying voltage to both ends of a programmable resistance memory cell. [Figure 9] It is a graph showing snap-back events for a first fire operation and a normal read operation. [Figure 10] An example of a snap-back current that may occur in response to the threshold switching selector being turned on is shown. [Figure 11] It is a diagram of an embodiment of a circuit for supplying voltage to both ends of a programmable resistance memory cell to lower the threshold voltage of the threshold switching selector. [Figure 12] It is a schematic diagram of an embodiment of a path including a word line, a bit line, and a programmable resistance memory cell 401 in series with some transistors. [Figure 13] This is a schematic diagram of one embodiment of a path including a word line, a bit line, and a programmable resistor memory cell in series with several transistors. [Figure 14] This is a flowchart of one embodiment of a process for mitigating damage to programmable resistive memory cells while lowering the threshold voltage of the memory cell threshold switching selector. [Figure 15] This is a flowchart of one embodiment of a process for mitigating damage to programmable resistive memory cells by lowering the threshold voltage of the memory cell threshold switching selector during the forming process. [Figure 16] This is a flowchart of one embodiment of a process that mitigates damage to programmable resistive memory cells while lowering the threshold voltage of the memory cell threshold switching selector during a forming process that uses a current force approach to provide a forming voltage. [Modes for carrying out the invention]

[0006] Techniques for a memory system and method for reducing the threshold voltage of a threshold switching selector in a programmable resistive memory cell are disclosed. Switching the threshold switching selector to ON can result in a snapback current. Specifically, the voltage across the memory cell rapidly drops from Vth to Vhold (or Voffset) after the threshold switching selector is turned ON, resulting in a snapback current. This snapback current can flow through the programmable resistive memory element and may potentially damage it. Also, large voltage changes can occur rapidly across the programmable resistive memory element, which may also potentially damage it. The techniques described herein mitigate damage to the programmable resistive memory element during operation to reduce the threshold voltage of the threshold switching selector.

[0007] One embodiment of the memory system has a circuit configured to connect to a selected programmable resistive memory cell in a crosspoint array and to apply a voltage to the cell. The circuit includes a transistor configured to connect in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line in the crosspoint array. The memory system applies a first control signal to the circuit to establish a first resistance of the transistor in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line when it controls the circuit to apply a voltage across the selected programmable resistive memory cell to lower the threshold voltage of a threshold switching selector in the programmable resistive memory cell. The memory system senses the selected programmable resistive memory by applying a second control signal to the circuit to establish a second resistance of the circuit in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line. The first resistance is higher than the second resistance. The higher second resistance of the transistor results in a higher voltage across the transistor when the threshold switching selector is switched on, thereby lowering the voltage across the programmable resistive memory element and thereby mitigating damage to the programmable resistive memory element. A lower first resistance used in the sensing operation allows for better sensing of the state of the programmable resistive memory element. The first and second control signals may be decoder address signals having different magnitudes. Therefore, a transistor with tuned resistance may be present in the decoder circuit that can be used to select the memory cell.

[0008] In one embodiment, threshold voltage reduction operation is a first-fire operation. When a threshold switching selector is first turned on during the lifetime of a memory device, the threshold voltage (Vth) is substantially higher than during normal operation, such as reading or writing. The voltage required to turn on the selector during the first use is called the first-fire voltage and is substantially higher than the target voltage range required to turn on the selector during normal operation. This is due to a transformation that occurs in the threshold switching selector during a process called "seasoning" or "forming," which reduces the Vth of the threshold switching selector. Typically, the threshold voltage of a threshold switching selector is reduced over several cycles, which may be called forming operation. The state of the selector can be transformed from an initial amorphous state with an initial threshold voltage (referred to herein as the first-fire voltage Vff) to an operating state with an operating threshold voltage (Vop) lower than the initial threshold voltage. As a result of the transformation, the threshold voltage of the selector is permanently reduced. The transformation results in a structural change that may be due to thermal effects of the selector material.

[0009] In one embodiment, a threshold voltage drop operation occurs during a cold start operation. If the threshold switching selector is not turned on for a considerable period of time after the initial forming operation has been performed, the threshold voltage of the threshold switching selector may drift higher. As used herein, a cold start operation refers to an operation that drops the threshold voltage of the threshold switching selector after the threshold voltage has drifted higher. Thus, a cold start operation can be performed after the initial forming operation has established the threshold voltage of the threshold switching selector at its operating threshold voltage (Vop). As used herein, a cold start operation does not sense the state of the memory cell.

[0010] In one embodiment, the Vth of a threshold switching selector in a crossbar array is gradually reduced over several forming cycles. Gradually reducing the Vth of a threshold switching selector can be referred to as "partially forming" the threshold switching selector, since the Vth of the threshold switching selector is only fully formed after several forming cycles. In one embodiment, the memory cell selected to form the threshold switching selector has a forming voltage applied across the cell. The forming voltage can be gradually reduced during the forming operation. In one embodiment, the resistance of the circuit in series with the memory cell (as well as the word and bit lines) gradually decreases as the forming voltage gradually decreases.

[0011] As described above, the resistance of the circuit in series with the memory cell (as well as the word and bit lines) is lower than that of the first-fire, forming, or cold-start operation during one embodiment of sensing the memory cell. One technique for sensing a programmable resistive memory cell occurs in a globally referenced readout. A globally referenced readout is sometimes called a midpoint readout or midpoint reference readout. A globally referenced readout may use a reference voltage between a low-resistance state (LRS) and a high-resistance state (HRS), where LRS and HRS refer to the voltages that appear across the cell in response to the read current. For example, a midpoint reference may be a reference voltage midway between two voltages corresponding to sensing a cell having either an LRS or an HRS. In a forced-current approach, the state of the memory cell is determined based on whether the sensed voltage Vsense is higher or lower than the midpoint reference voltage VREF.

[0012] Another technique for sensing programmable resistive memory cells is commonly called destructive self-referential readout (SRR). In SRR, the reference is generated based on sensing the cell itself, rather than using an intermediate reference that is independent of the cell's state. In destructive SRR, the state of the memory cell may change (e.g., be destroyed) due to the SRR write operation. One SRR technique involves a first readout (readout 1), followed by a destructive write to a known state (e.g., high-resistance state HRS), and a second readout (readout 2). The results of the two readouts are compared to determine the cell's original state. One technique for the first readout is to apply a readout current through the memory cell, resulting in a voltage across the cell with a magnitude representing the resistance of the memory cell. The voltage is stored and may be adjusted (e.g., by 150mV up or down) for comparison with a voltage sample from the second readout. The voltage adjustment may be about half the signal difference across the MRAM for each state. For example, if the low-resistance state (LRS) of the MRAM is 25kΩ, the high-resistance state is 50kΩ, and the read current is 15μA, the difference from the state change is 375mV, so an adjustment of approximately 182.5mV can be made from the read1 storage voltage of the SRR. Determining the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage from read1 of the SRR is up-adjusted and the write was to HRS, then if the cell was originally in HRS, the second sampled voltage from read2 should be approximately the same as read1 and therefore lower than the first read voltage after up-adjustment. However, if the cell was originally in LRS, the second sampled voltage from read2 should be higher than the up-adjusted voltage from read1 due to the higher read2 voltage resulting from writing bits from low-resistance LRS to HRS.

[0013] In one embodiment, the memory system is used with programmable resistive memory cells located within a crosspoint memory array. In a memory array with a crosspoint architecture, a set of conductive wires extends across the surface of the substrate, and another set of conductive wires is formed on top of the other set of conductive wires, extending across the substrate perpendicular to the other set of conductive wires. Memory cells are located at the crosspoint junctions of the two sets of conductive wires. A crosspoint memory array is sometimes called a crossbar memory array. In one embodiment, each memory cell has a magnetoresistive memory element in series with an OTS, which may be called an MRAM memory cell. However, a crosspoint memory array may have other types of memory cells. For example, a crosspoint memory array may have memory cells of other technologies such as ReRam, Phase Change Memory (PCM), or FeRam. Also, the threshold switching selector does not have to be an OTS, but may be a pair of diodes from anode to cathode.

[0014] In some embodiments, the programmable resistive memory cell comprises magnetoresistive random access memory (MRAM) elements. As used herein, the direction of magnetization is the direction in which the magnetic moment is directed relative to a reference direction set by another element of the MRAM ("reference layer"). In some embodiments, low resistance is referred to as parallel or P-state or LRS, and high resistance is referred to as antiparallel or AP-state or HRS. The MRAM can use the spin-transfer torque effect to change the direction of magnetization from P-state to AP-state and vice versa, which typically requires bipolar (bidirectional write) operation for writing. However, the SRR of the programmable resistive memory cell disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0015] Figure 1 is a block diagram of one embodiment of a non-volatile memory system (or more simply, a “memory system”) 100 connected to a host system 120. The memory system 100 can implement the techniques presented herein for a system for reading programmable resistive memory cells having a threshold switching selector. In one embodiment, the memory cells have programmable resistive memory elements (e.g., MRAM elements) in series with a threshold switching selector such as an OTS. Many types of memory systems can be used with the techniques proposed herein. Exemplary memory systems include dual in-line memory modules (DIMMs), solid-state drives (“SSDs”), memory cards, and embedded memory devices. However, other types of memory systems can also be used.

[0016] The memory system 100 in Figure 1 comprises a memory controller 102, a memory 104 for storing data, and a local memory 140 (e.g., MRAM, ReRAM, DRAM). The local memory 140 is non-volatile and can retain data after power-off. The local memory 140 may be volatile and may not be expected to retain data after power-off. In one embodiment, the local memory 140 is MRAM. In one embodiment, the local memory MRAM does not need to retain data after power-off. However, the local memory MRAM may retain data after power-off. In one embodiment, the memory controller 102 and / or the local memory controller 164 provide access to programmable resistive memory cells in the local memory 140. For example, the memory controller 102 may provide access to a crosspoint array of MRAM cells in the local memory 140. In another embodiment, the memory controller 102 or the interface 126 or both are eliminated, and the memory packages are connected directly to the host 120 via a bus such as DDRn. Alternatively, they are connected to a host memory management unit (MMU). In another example, the memory controller 102 or a portion thereof is moved onto memory 104 for a direct connection of memory 104 to the host, such as by providing parity bits, ECC, and wear levels on memory 104 along with a DDRn interface to / from the host 120 or MMU. The term memory system as used throughout this specification is not limited to memory system 100. For example, local memory 140 or the combination of local memory 140 and local memory controller 164 can be considered a memory system. Similarly, host memory 124 or the combination of host processor 122 and host memory 124 can be considered a memory system.

[0017] The components of the memory system 100 shown in Figure 1 are electrical circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, a refresh logic 172, and a wear level 174. The host interface 152 is connected to and communicates with the host 120. The host interface 152 is also connected to the network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, resulting in a significant improvement over conventional bus and crossbar interconnects. Compared to other designs, the NOC improves the scalability of the system-on-chip (SoC) and the power efficiency of complex SoCs. The wiring and links of the NOC are shared by many signals. A high level of parallelism is achieved because all links within the NOC can operate simultaneously for different data packets. Therefore, as the complexity of the integrated subsystem continues to increase, the NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signaling wiring, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The NOC 154 is connected to and communicates with a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, a refresh logic 172, and a wear level 174. The local memory controller 164 is used to operate and communicate with a local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed memory 140 may be DRAM, SRAM, or another type of volatile memory.

[0018] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding of parity bits provided in or out of memory as part of a codeword used for error correction of data fetched from memory 140 or 104. In one embodiment, the ECC engine 158 is a software-programmed electrical circuit. For example, the ECC engine 158 may be a programmable processor. In other embodiments, the ECC engine 158 is a custom, dedicated hardware circuit without any software. In one embodiment, the functions of the ECC engine 158 are implemented by a processor 156. In one embodiment, local memory 140 has an ECC engine, with or without a wear-level engine. In one embodiment, memory 104 has an ECC engine, with or without a wear-level engine.

[0019] Processor 156 performs various controller memory operations, including memory management processes such as programming, erasing, reading, and wear levels. A separate wear level 174 is shown, but wear level 174 may be implemented by processor 156. Also, refresh logic 172 is shown, but refresh may be implemented by processor 156. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom dedicated hardware circuit without software. Processor 156 also implements a translation module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is internally addressed to the storage system using physical addresses associated with one or more memory dies. However, the host system addresses various memory locations using logical addresses. This allows the host to assign data to contiguous logical addresses, while the storage system can freely store data as desired between locations on one or more memory dies. To implement this system, a memory controller 102 (e.g., a translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One exemplary implementation is to maintain a table (i.e., the L2P table described above) that identifies the current translation between logical and physical addresses. Entries in the L2P table can include an identification of the logical address and its corresponding physical address. Although the term "table" is used to describe a logical-to-physical address table (or L2P table), they do not have to be literally tables. Rather, a logical-to-physical address table (or L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all of the L2P table.In such cases, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables is cached in local high-speed memory 140 (L2P cache).

[0020] The memory interface 160 communicates with the storage 104. In one embodiment, the storage 104 includes a programmable resistive memory cell in a crosspoint array. In one embodiment, the storage 104 includes a NAND memory cell. In one embodiment, the memory interface provides a toggle-mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another part of the controller 102) implements a scheduler and buffers for sending data to and receiving data from one or more memory dies.

[0021] In one embodiment, the local memory 140 has an ECC engine. The local memory 140 may be used to help perform other functions such as wear level. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent No. 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference as a whole. In one embodiment, the local memory 140 is synchronous. In one embodiment, the local memory 140 is asynchronous.

[0022] In one embodiment, the storage 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Therefore, the memory controller 102 is connected to one or more memory dies. In one embodiment, the memory packages may include types of memory such as programmable resistive random access memory (such as ReRAM, MRAM, FeRam, or RRAM) or storage class memory (SCM) based on phase-change memory (PCM). In one embodiment, the memory controller 102 provides access to memory cells in a crosspoint array within the storage 104.

[0023] The memory controller 102 communicates with the host 120 via an interface 152 that implements a protocol such as CXL (Compute Express Link). Alternatively, such a controller can be eliminated, and the memory package can be placed directly on the host bus, such as DDRn or CXL. To cooperate with the memory system 100, the host system 120 includes a host processor 122 connected along a bus 128, host memory 124, and interface 126. The host memory 124 is the host's physical memory and may be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In one embodiment, the host memory 124 includes a crosspoint array of programmable resistive memory cells, each memory cell comprising a programmable resistive memory element and a threshold switching selector in series with the programmable resistive memory element.

[0024] The host 120 is located outside and separate from the memory system 100. In one embodiment, the memory system 100 is incorporated into the host 120. The host memory 124 may be referred to herein as the memory system. The combination of the host processor 122 and the host memory 124 may be referred to herein as the memory system. In one embodiment, such host memory may be a crosspoint memory using MRAM.

[0025] Figure 2 is a block diagram showing an example of a memory die 292 that can implement the technology described herein. In one embodiment, the memory die 292 is contained in local memory 140, and in another embodiment, the memory die 292 is contained in storage 104. In another embodiment, the memory die 292 is contained in host memory 124. The memory die 292 includes a memory structure 202 which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations, including, for example, diagonal patterns, may also be implemented to save space. The memory die 292 includes a row control circuit 220, the output 208 of which is connected to each word line of the memory structure 202. The row control circuit 220 receives a group of M row address signals and one or more various control signals from a system control logic circuit 260, and may typically include circuits such as a row decoder 222, a row driver 224, and a block selection circuit 226 for both read and write operations. The row control circuit 220 may also include read / write circuits. In one embodiment, the row control circuit 220 has a sense amplifier 228, each including a circuit for sensing the state (e.g., voltage) of the word lines of the memory structure 202. In one embodiment, by sensing the word line voltage, the state of a memory cell or bit state in the crosspoint array is directly determined by the sense amplifier, which compares the accessed memory cell voltage with a reference voltage. Alternatively, less directly, the read voltage generated by first accessing the memory cell and forcing a read current through the cell is stored, adjusted up or down by 150mV (or half the voltage difference resulting from changing the bit state), then writing the cell to the AP state, accessing the memory cell again with a read current, and comparing the resulting voltage with the stored voltage adjusted to, for example, 150mV (or half the voltage difference resulting from two different bit states). The memory die 292 also includes a column decoder and control circuit 210, the input / output 206 of which are connected to the respective bit lines of the memory structure 202.Although only a single block is shown for the memory structure 202, the memory die can contain multiple arrays or "tiles" that can be accessed individually. The column control circuit 210 receives a group of N column address signals and one or more different control signals from the system control logic 260 and can typically include circuits such as a column decoder 212, a column decoder and driver 214, a block selection circuit 216, and read / write circuits and I / O multiplexers.

[0026] The system control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, the system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement interfaces such as DDR, DIMM, CXL, and PCIe. In another embodiment, these data and commands are sent and received directly from the memory package to the host without a separate controller, and any required controllers are located within each die or on dies added to the multi-chip memory package. In some embodiments, the system control logic 260 may include a state machine 262 that provides die-level control of memory operation. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is fully implemented in hardware (e.g., electrical circuitry). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor. The system control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include charge pump and regulator circuits for generating regulated voltages, and respective on / off controls for word line bit line selection of the memory cells. In some embodiments, the power control 264 includes one or more current sources. The current sources may be used to provide read current and / or write current. The system control logic 260 includes storage 266 which may be used to store parameters for operating the memory structure 202. The system control logic 260 also includes refresh logic 272 and wear level logic 274.Such system control logic may be instructed by the host 120 or memory controller 102 to refresh logic 272, which may load on-chip stored row and column addresses (pointers) that may be incremented after the refresh. Such address bits may be selected (to refresh the OTS). Alternatively, such addresses may be read, corrected by steering through the ECC engine 269, and then stored in a “spare” position, which may also be incremented against the wear level (so all codewords are periodically read, corrected, and relocated across the chip under the control of the wear level logic 274) so ​​that the use of each bit across the chip is more uniform. Such operation may be controlled more directly by an external controller, for example, a host PCIe, CXL, or DDRn controller located separately from or on the memory die.

[0027] Commands and data are transferred between the memory controller 102 and the memory die 292 via the memory controller interface 268 (also called the “communication interface”). Such an interface may be, for example, PCIe, CXL, or DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. An example of the memory controller interface 268 also includes a toggle-mode interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a toggle-mode interface that connects to the toggle-mode interface of the memory interface 228 / 258 for the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins that connect to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn such as DDR5 or LPDDR5, or a subset of those having smaller page counts and / or relaxed timing.

[0028] The system control logic 260 located within the controller on the memory die in the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 is sometimes referred to as an on-die ECC engine because it resides on the same semiconductor die as the memory cells. That is, the on-die ECC engine 269 can be used to encode data and parity bits to be stored in the memory structure 202, decode the decoded data, and correct errors. The encoded data may be referred to herein as a codeword or ECC codeword. The ECC engine 269 can be used to execute a decoding algorithm and perform error correction. Thus, the ECC engine 269 can decode an ECC codeword. In one embodiment, the ECC engine 269 can decode data more rapidly by decoding directly without iteration. Having the ECC engine 269 on the same die as the memory cells enables faster decoding. The ECC engine 269 can use a wide variety of decoding algorithms, including but not limited to Reed-Solomon, BCH (Bose-Chaudhuri-Hocquenghem), and Low-Density Parity Check (LDPC).

[0029] In some embodiments, all elements of the memory die 292, including the system control logic 260, may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on a different die, for example, on an external controller chip.

[0030] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile or volatile memory cells, where multiple memory levels are formed on a single substrate such as a wafer. The memory structure may include any type of non-volatile or volatile memory monolithically formed at one or more physical levels of memory cells having active regions located on a silicon or silicon-on-insulator (or other type) substrate. In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells.

[0031] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the examples given above. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required for the purposes of the newly claimed embodiments proposed herein. Other examples of technologies suitable for the memory cells of the memory structure 202 include ReRAM memory (resistive random-access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of technologies suitable for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, vertical bit-line arrays, etc.

[0032] An example of a ReRAM or MRAM crosspoint memory includes a programmable resistive switching element in series with an OTS selector arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word line and bit line). Another embodiment of the crosspoint is a PCM in series with the OTS selector. In another embodiment, the memory cell may include a conductive bridge memory element. Conductive bridge memory elements are sometimes called programmable metallization cells. Conductive bridge memory elements can be used as state change elements based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature rises, the mobility of ions also increases, reducing the programming threshold of the conductive bridge memory cell. Thus, conductive bridge memory elements can have a wide programming threshold with respect to temperature.

[0033] Magnetoresistive random-access memory (MRAM) stores data using magnetic memory elements. The elements are formed from two ferromagnetic layers, each capable of maintaining a magnetization separated by a thin insulating layer. In magnetic field-controlled MRAM, one of the two layers is a permanent magnet set to a specific polarity, while the magnetization of the other layer can be altered by applying an external magnetic field to store the memory. Other types of MRAM cells are also possible. Memory devices can be constructed from a grid of MRAM cells or as SOT magnetoresistive memory. Embodiments of MRAM-based memory are described in more detail below.

[0034] Phase-change memory (PCM) utilizes the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the coordination state of germanium atoms using laser pulses (or optical pulses from another source). The memory cell is programmed by current pulses that can change the coordination of the PCM material or switch the PCM material between an amorphous and crystalline state. Note that the use of “pulse” herein does not require a square pulse, but includes (continuous or discontinuous) oscillations or bursts of sound, current, voltage, light, or other waves. The current forced for writing may be driven rapidly to a peak value, for example, and then linearly reduced at an edge rate of, for example, 500 ns. Such peak current force may be limited by zoned voltage compliance that varies depending on the location of the memory cell along the word line or bit line. In one embodiment, the phase-change memory cell has a phase-change memory element in series with a threshold switching selector such as an OTS.

[0035] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather cover many related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0036] The elements in Figure 2 can be grouped into two parts: the memory structure 202 and the peripheral circuitry, which includes all other elements. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die 292 allocated to the memory structure 202. However, this reduces the area of ​​the memory die available for the peripheral circuitry or increases the cost associated with chip area. This can impose very strict constraints on these peripheral elements. For example, the need to fit the sense amplifier circuitry within the available area can be a significant constraint on the sense amplifier design architecture. With respect to the system control logic 260, reduced area availability can limit the available functionality that can be implemented on-chip. Thus, the fundamental trade-off in the design of the memory die 292 is the amount of area allocated to the memory structure 202 versus the amount of area allocated to the peripheral circuitry. Such a trade-off can result in more IR reduction from the use of a larger xy array of memory between the drive circuits on the word and bit lines, which in turn can benefit more from the use of voltage limiting and voltage compliance zoning by memory cell location along the word and bit lines.

[0037] Another area where the memory structure 202 and peripheral circuits often conflict lies in the processing involved in forming these areas, as these areas often involve different processing techniques and involve trade-offs in having different techniques on a single die. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 260 often use PMOS devices. In some cases, the memory structure is based on CMOS devices. The processing operations for manufacturing CMOS dies differ in many ways from the processing operations optimized for NMOS-specific techniques.

[0038] To overcome these limitations, the embodiments described below allow the elements of Figure 2 to be separated onto separately formed dies, which are then joined together. Figure 3 shows an integrated memory assembly 270 having a memory structure die 280 and a control die 290. The memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuit elements, including one or more control circuits, are formed on the control die 290. For example, the memory structure die 280 may be formed solely from memory elements, such as an array of memory cells of an MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuits, even if they include elements such as decoders, current sources, and sense amplifiers, can be moved to the control die. This allows each semiconductor die to be individually optimized according to its technology. This allows for more space for peripheral elements and can incorporate additional capabilities that could not be easily incorporated when limited to the margin of the same die holding the memory cell array. The two dies can then be joined together in a joined multi-die integrated memory assembly, with the array on one die connected to the peripheral elements on the other die. The following focuses on an integrated memory assembly with one memory die and one control die, but other embodiments may use additional dies, such as two memory dies and one control die.

[0039] Similar to the memory die 292 in Figure 2, the memory structure die 280 in Figure 3 includes a memory structure 202 that can include multiple independently accessible arrays or "tiles". The system control logic 260, row control circuit 220, and column control circuit 210 are located within the control die 290. In some embodiments, one or more of the column control circuit 210 and all or part of the row control circuit 220 are located on the memory structure die 280. In some embodiments, some of the circuits within the system control logic 260 are located on the memory structure die 280.

[0040] Figure 3 shows a column control circuit 210 on a control die 290 coupled to a memory structure 202 on a memory structure die 280 via an electrical path 293. For example, the electrical path 293 can provide electrical connections between a column decoder 212, a column driver circuit 214, a block selector 216, and the bit lines of the memory structure 202. The electrical path can extend from the column control circuit 210 in the control die 290 through pads on the control die 290 bonded to corresponding pads on the memory structure die 280 connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in the electrical path 293, which includes a pair of bond pads connected to the column control circuit 210. Similarly, a row control circuit 220, including a row decoder 222, a row driver 224, a block selector 226, and a sense amplifier 228, is coupled to the memory structure 202 via an electrical path 294. Each of the electrical paths 294 may correspond to, for example, a word line. An additional electrical path may be provided between the control die 290 and the memory structure die 280.

[0041] For the purposes of this specification, the term “control circuit” may include one or more of the following: the memory controller 102, the local memory controller 164, the processor 156, the system control logic 260, the column control circuit 210, the row control circuit 220, the host processor 122, the microcontroller, the state machine, and / or other control circuits, or other similar circuits used to control non-volatile memory. A control circuit may include hardware only, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or other type of circuit. Such a control circuit may include a driver such as a direct drive via a connection of nodes through a fully on-transistor (gate-to-power supply) driven to a fixed voltage such as a power supply. Such a control circuit may include a current source driver.

[0042] In this specification, the term “device” may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or combination of memory controller 102 and local memory 140, storage 104, memory die 292, integrated memory assembly 270, and / or control die 290.

[0043] In the following description, the memory structure 202 in Figures 2 and 3 is described in the context of a crosspoint architecture. In a crosspoint architecture, a first set of conductive lines or wirings, such as word lines, runs in a first direction relative to the underlying substrate, and a second set of conductive lines or wirings, such as bit lines, runs in a second direction relative to the underlying substrate. Memory cells are located at the intersections of the word lines and bit lines. Memory cells at these crosspoints can be formed according to any of several techniques, including the techniques described above. The following description mainly focuses on embodiments based on a crosspoint architecture using MRAM memory cells, where each MRAM memory cell is in series with a threshold switching selector, such as an obonic threshold switch (OTS), to constitute selectable memory bits. However, embodiments are not limited to supplying current to a crosspoint architecture having MRAM cells, each having a magnetic memory element in a series OTS selector. For example, a crosspoint memory array may have memory cells of other techniques, such as ReRam, Phase Change Memory (PCM), or FeRam.

[0044] Figure 4A shows a perspective view of one embodiment of a portion of a memory array 402 that forms a crosspoint architecture. The memory array 402 in Figure 4A is an example of an implementation of the memory structure 202 in Figure 2 or Figure 3, and the memory die 292 or memory structure die 280 may contain a plurality of such memory arrays 402. The memory array 402 may be contained in the local memory 140 or the host memory 124. Bit lines BL1-BL5 are arranged in a first direction (represented as extending inwards) with respect to the substrate (not shown) beneath the die, and word lines WL1-WL5 are arranged in a second direction perpendicular to the first direction or diagonally opposite to provide intersections where memory cells are interconnected between WL and BL. Figure 4A is an example of a horizontal crosspoint structure in which both word lines WL1-WL5 and BL1-BL5 extend horizontally with respect to the substrate, and two of them are memory cells indicated by 401, through which the current (I) flows. セル The lines (as shown in the diagram) are oriented to flow vertically. In a memory array with additional layers of memory cells, as described below with respect to Figure 4D, there will be corresponding additional layers of bit lines and word lines. One pattern, for example, from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.

[0045] As shown in Figure 4A, the memory array 402 includes a plurality of memory cells 401. The memory cells 401 may include rewritable memory elements, such as those that can be implemented using ReRAM, MRAM, PCM, or other materials having programmable resistance. The memory cells 401 are sometimes referred to herein as programmable resistive memory cells. One type of programmable resistive memory cell is called an MRAM cell, which is a memory cell containing MRAM memory elements. The memory cell 401 may also include a threshold switching selector as an additional series element within the memory cell 401, such as those that can be implemented using an ovonic threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance for changing the selection voltage. The following description focuses on memory cells consisting of MRAM memory elements coupled in series with an ovonic threshold switch element, but much of the description can be applied more generally. The current in a memory cell at the first memory level is indicated by arrow I セル Although shown as flowing upward as indicated by [the symbol], the current can flow in either direction to read or write the memory cell bit state, as will be explained in more detail below.

[0046] Figures 4B and 4C show the side and top views, respectively, of the crosspoint structure in Figure 4A. The side view in Figure 4B shows one lower wiring or word line WL1 and upper wiring or bit lines BL1~BL n This shows that PCM, ReRAM, FeRaM, or other technologies can be used as memory elements, but at each crosspoint between the upper and lower wirings there is an MRAM memory cell 401. Figure 4C shows the M lower wirings WL1~WL M and N upper wiring BL1~BL NThis is a top view showing the crosspoint structure. In the binary embodiment, the MRAM cell at each crosspoint can be programmed to one of two resistance states, namely high and low. Further details regarding embodiments for MRAM memory cell design and techniques for reading them are given below. In some embodiments, these sets of wiring are arranged contiguously as “tiles,” and such tiles may be paired adjacently in the word line (WL) direction and orthogonal in the bit line direction to generate a module. Such a module may consist of 2x2 tiles such that WL drivers between tiles are “center-driven” between tiles, and the WLs form a combination of 4 tiles running contiguously over transistor drivers at approximately the center of the line. Similarly, BL drivers may be placed between pairs of tiles paired in the BL direction to be center-driven, thereby the transistor drivers and their area being shared between pairs of tiles. Copper or other types of low-resistance vias may decode the transistor drivers / selectors and connect to the WLs or BLs. In addition to the memory elements in the memory cell between the WLs and BLs, series selection elements such as OTS may also be included.

[0047] The crosspoint array in Figure 4A has one layer of word lines and bit lines, and one embodiment shows MRAM or other memory technology for memory cells located at the intersection of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. An example of two layers is shown in Figure 4D.

[0048] Figure 4D shows a perspective view of one embodiment of a two-level memory array forming a crosspoint architecture. Similar to Figure 4A, Figure 4D shows the word line WL described above. 1,1 ~WL 1,4 The first layer 418 of the memory cells 401 of the memory array 403 is shown, connected at the crosspoint of the first layer of bit lines BL1 to BL5. The memory array 403 may be included in the memory structure 202 of Figure 2 or Figure 3. The second layer 420 of the memory cells is above the bit lines BL1 to BL5 and is connected to these bit lines and word line WL2、1 ~WL 2、4 is formed between the second set of. In practice, the BL is shared. In an alternative form, the second layer may include another deck of BLs that is above the BLs shown and below the second deck of WLs. FIG. 4D shows two layers 418 and 420 of memory cells, but this structure can be extended upward through additional alternating layers of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array of FIG. 4D can be biased for read or program operations such that current within each layer flows from the word line layer to the bit line layer or vice versa. The two layers can also be configured such that current flows in the same direction in each layer for a given operation, or can be configured such that current flows in opposite directions depending on the selection of a positive or negative direction driver. The memory cells may be arranged in the same orientation within the first and second layers, enabling the use of current in opposite directions for each layer for read or write. Alternatively, the memory cells are arranged in an inverted or flipped orientation when disposed between the BL and WL in the second layer (enabling the use of current in the same direction as that used for read or write in the memory cells within the first layer). As will be apparent to those skilled in the art, the two layers can be extended to three or more layers.

[0049] The use of a crosspoint architecture enables arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each crosspoint may be resistive memory cells, and the data values ​​are encoded as different resistance levels, either two levels, such as MRAM, or two or more levels, such as other memory element technologies, such as PCM. Depending on the embodiment, the memory cells may be binary values ​​having either a low-resistance state or a high-resistance state, or they may be multilevel cells (MLCs) that may have additional resistance between the low-resistance and high-resistance states. The crosspoint arrays described herein may be used in the memory die 292 in Figure 2, the local memory 140 in Figure 1, and / or the host memory 124 in Figure 1, or in any other configuration where additional memory is useful. The resistive memory cells can be formed according to many of the technologies described above, such as ReRAM, PCM, FeRaM, or MRAM. The following description is presented primarily in relation to memory arrays using a crosspoint architecture with binary-value MRAM memory cells, but much of the description is more generally applicable to other memory elements in memory cells within crosspoint arrays, or to other configurations apparent to those skilled in the art.

[0050] Figure 5 shows the structure of one embodiment of an MRAM cell. The MRAM cell can be used, for example, as a programmable resistive memory cell 401 in Figures 4A to 4D. The MRAM cell includes a lower electrode 501, a spacer 512, a threshold switching selector 502, a spacer 514, a pair of magnetic layers (reference layer 503 and free layer 507) separated by an isolation or tunneling layer of magnesium oxide (MgO) 505 in this example, and an upper electrode 511 separated from the free layer 507 by a spacer 509. The spacer 509 may consist of an MgO capping layer in contact with the free layer 507. The spacer 509 may also include an additional metal layer. In another embodiment, the positions of the reference layer 503 and the free layer 507 are swapped, with the reference layer 503 above the MgO 505 and the free layer 507 below the MgO 505. In another embodiment, the position of the threshold switching selector 502 is between the free layer 507 and the upper electrode 511.

[0051] In some embodiments, the lower electrode 501 is a word line and the upper electrode 511 is a bit line. In other embodiments, the lower electrode 501 is a bit line and the upper electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 503 and the free layer 507. If the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low-resistance state (LRS), and if they have opposite orientations, the memory cell is in an antiparallel (AP) high-resistance state (HRS). Embodiments of the MLC include additional intermediate states. The orientation of the reference layer 503 is fixed and is upward in the example of Figure 5. The reference layer 503 is also known as the fixed layer or pinned layer. The reference layer 503 can consist of multiple ferromagnetic layers antiferromagnetically coupled in a structure commonly called a synthetic antiferromagnet or simply SAF.

[0052] Data is written to an MRAM memory cell by programming the free layer 507 to have the same or opposite orientation as the reference layer 503. An array of MRAM memory cells can be placed in an initial or erased state by setting the cells of the MRAM memory cells to a low-resistance state in which all of their free layers have the same magnetic field orientation as their reference layer. Each memory cell is then selectively programmed (also called "written") by placing its free layer 507 to a high-resistance state by reversing the magnetic field so that it is opposite to the magnetic field of the reference layer 503. The reference layer 503 is formed to maintain its orientation when programming the free layer 507. The reference layer 503 may have a more complex design, including a composite antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the figures and descriptions, and only the fixed magnetic layers that are primarily responsible for the tunnel magnetoresistance within the cell are focused on.

[0053] The threshold switching selector 502 has high resistance (off or non-conductive state) until it is biased to a voltage higher than its threshold voltage or a current higher than its threshold current, and until the voltage bias falls below Vhold (also known as "Voffset") or the current falls below Ihold. After Vt is exceeded and while Vhold is exceeded across the switching selector, the switching selector has low resistance (on or conductive state). The threshold switching selector remains on until its current falls below the holding current Ihold or the voltage falls below the holding voltage Vhold. When this happens, the threshold switching selector returns to the off (higher) resistance state. Thus, to program a memory cell at a crosspoint, the associated threshold switching selector is turned on and activated by applying a voltage or current sufficient to set or reset the memory cell, and to read out a memory cell, the threshold switching selector is activated by being turned on before the resistance state of the memory cell is determined. One example of threshold switching selectors is the ovonic threshold switching material of an ovonic threshold switch (OTS). Examples of threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, GeSe, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, with atomic percentages ranging from a few percent to over 90 percent for each element. In one embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 may also include an additional conductive layer at the interface with the reference layer 503. For example, a spacer 514 is shown between the switching selector 502 and the reference layer 503. The spacer layer 514 at the interface with the reference layer 503 may be a single conductive layer or may consist of multiple conductive layers. The threshold switching selector 502 may also include an additional conductive layer at the interface with the lower electrode 501. For example, spacer 512 is shown between the switching selector 502 and the reference layer 503.The spacer layer 512 at the interface with the lower electrode 501 may be a single conductive layer or may consist of multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, tungsten carbon, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, and tantalum nitride. The threshold voltage switch has a threshold voltage (Vth), above which the resistance of the device changes from substantially insulating or semi-insulating to conductive.

[0054] In one embodiment, a current-force approach is used to access an MRAM cell. The current-force approach can be used to read or write to an MRAM cell. In one embodiment, the current-force approach is used to lower the threshold voltage of a threshold switching selector in a programmable resistor memory cell. In the current-force approach, the access current (e.g., I 読み出し , I 書き込み , I 駆動 A current is driven through the lower electrode 501 by a current driver. The current is supplied by a transistor or resistor-based current source. In one embodiment, the current driver may be part of an address-selected row driver circuit (e.g., array driver 224) for electrode 501. However, alternatively, the current driver may be part of an address-selected column driver circuit (e.g., driver circuit 214) for electrode 501. 選択 ) is supplied to the upper electrode 511. In this specification, "readout current" (I 読み出し ) and "writing current" (I 書き込み The term RA 10Ωμm is used in relation to the access current driven through an MRAM cell (or other programmable resistor cell). The write current can change the state of an MRAM cell. For example, a write current of approximately 30μA over 50ns can switch the MRAM state from state P to state AP. 2It can be used in MRAM cells having a limiting dimension (CD) of approximately 20 nanometers. The read current may be about half the write current when applied over a limited time, such as less than 20 ns. A write current flowing in one direction through the MRAM cell changes an AP-state MRAM cell to a P-state. A write current flowing in another direction through the MRAM cell, such as the read direction, changes a P-state MRAM cell from a P-state to an AP-state. Generally, it is preferable that the read current be set low and the read duration be set short enough so that the state of the MRAM cell is not changed from P-state to AP-state or from AP-state to P-state during reading until the cell state is determined or a voltage level correlated with the memory cell state is captured and stored. Typically, the write current required to switch the MRAM state from P-state to AP-state is greater in absolute value than the write current required to switch the MRAM state from AP-state to P-state, and therefore this may be a preferred direction to read to provide a margin for state changes before the bit state is properly sensed. The magnitude of the current may be adjusted by the write direction, or, if a single magnitude is used, by the current used from P to AP.

[0055] In some embodiments, the read current may be applied in the P2AP direction or in the AP2P direction. In some embodiments, the MRAM cell is read by performing an SRR (self-referential read). In one embodiment, the SRR has a first read (read 1 in the P2AP direction), a first write (read 1 to the AP state), and a second read (read 2 in the P2AP direction). The original state of the cell can then be restored by a second write (Write_Back to the P state for bits that were initially in the P state). Alternatively, in another embodiment, both the SRR read current and the destructive write current are inverted, for example, when the second layer is addressed with memory cells oriented in the same direction as the first layer.

[0056] In one embodiment, the voltage level of the memory cell is sensed by a P2AP read 1 and stored, for example, in a capacitor, or converted to digital bits by an analog-to-digital converter, and the bits are stored in memory, such as SRAM, until after use in read 2. The state stored in the capacitor can be adjusted to, for example, a positive or negative 150mV by forcing a voltage across one terminal of the capacitor connected to the storage capacitor. Alternatively, the digital storage level can be adjusted by digitally adding or subtracting 150mV to the storage bit. 150mV can be adjusted to depend on the typical bit resistance. For example, if the low-resistance state of the bit is 25kΩ and the high-resistance state is 50kΩ, the difference is 25kΩ. If the read current is 15μA, the voltage difference between the states is 25kΩ × 15μA = 375mV, which allows for the selection of, for example, 150mV, although 187.5mV may be more optimal.

[0057] The above describes reading in the P2AP direction and destructive writing to the AP state (accompanied by writing back to the P state after SRR). However, in an alternative embodiment, the first SRR includes a first read (read 1 in the AP2P direction), a destructive write to the P state (write 1), and a second read in the AP2P direction (read 2).

[0058] In one embodiment, the MRAM cell is read by applying, for example, approximately 0V to the upper electrode 501 by turning on a transistor connected between 511 and the power supply, while driving a current of, for example, 15 microamperes (μA) through the lower electrode 511. This read current can flow from the lower electrode 501 to the upper electrode 511. The read may be read 1 in the P2AP direction or read 2. P2AP means that the current flows in the direction of writing bits from P to AP or AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to the upper electrode 511 while driving a write current of, for example, -30μA through the lower electrode 501. This write current flows from the upper electrode 511 to the lower electrode 501. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to the upper electrode 501 while driving a current of 30μA through the lower electrode 511. This write current flows from electrode 501 to electrode 511.

[0059] As an alternative to the approach in Figure 5, a selection voltage can be applied to the lower electrode 501 and an access current can be applied through the upper electrode 511. In one such embodiment, the MRAM cell is read out by applying, for example, 3V to the lower electrode 501 while driving a read current of, for example, -15μA through the upper electrode 511. This read current can flow from the lower electrode 501 to the upper electrode 511.

[0060] In one embodiment, an MRAM cell is written from the AP state to the P state by applying, for example, -3V to the lower electrode 501 while driving a write current of, for example, 30μA through the upper electrode 511. The electron current flows from the lower electrode 501 to the upper electrode 511. In another embodiment, an MRAM cell is written from the P state to the AP state by applying, for example, 0V to the lower electrode 501 while driving a current of, for example, -30μA through the upper electrode 511. The electron current flows from the upper electrode 511 to the lower electrode 501. The direction of the current polarity for switching the magnetization of a bit to the P or AP state can be varied based on the reference layer design and the position of the reference layer relative to the free layer.

[0061] Some biasing techniques can introduce voltage to unselected memory cells in an array, which can induce "leakage" current in these unselected memory cells. While this wasted power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high-resistance and low-resistance states when WL or BL is not address-selected, this overhead leakage still results in increased current and power consumption, and imposes additional design constraints on the memory cell and array design due to a lack of read and write margin. One approach to addressing this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, a selector transistor can be placed in series with each resistive memory cell element in Figures 4A-4D, resulting in memory cell 401 being a composite of a selector transistor and a programmable resistor. Such an architecture is sometimes referred to as 1T1R. However, the use of a selector transistor requires the introduction of additional control lines and cell area to enable the corresponding transistor of the selected memory cell to be turned on. Furthermore, transistors often do not scale in the same way as resistive memory element write currents, and as a result, the use of transistor-based selectors can become a limiting factor in reducing costs, for example, as memory arrays move to smaller sizes. An alternative approach to selecting transistors is the use of a threshold switching selector (e.g., threshold switching selector 502) in series with a programmable resistive element. A two-terminal threshold switching selector does not require the aforementioned additional control lines and additional cell area because it can turn on the corresponding selection transistor of the selected memory cell. In some embodiments, a memory system performs a read as disclosed herein to read a memory cell having a two-terminal threshold switching selector in series with a programmable resistive memory element.

[0062] Figures 6A and 6B illustrate embodiments for incorporating a threshold switching selector into an MRAM memory array having a crosspoint architecture. The examples in Figures 6A and 6B show side views of two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer crosspoint array as shown in Figure 4D. As shown in Figure 6A, the manufacturing process can be made identical for each layer by keeping the orientation of the MRAM layers the same for layer 1 and layer 2 cells. Figure 6B, on the other hand, has an inverted memory cell, which allows the drive circuit to operate similarly, for example, BL to go low to read P2AP for each layer. Figures 6A and 6B show the lower first conductive wire of word line 1 600, the upper first conductive wire of word line 2 620, and the intermediate second conductive wire of bit line 610. In these diagrams, all of these lines are shown running from left to right across the page for ease of presentation, but in a crosspoint array, it is more accurately represented as in the perspective view of Figure 4D, where the word lines or first conductive lines or wires run in one direction parallel to the surface of the underlying substrate, and the bit lines or second conductive lines or wires run in a second direction parallel to the surface of the substrate, approximately perpendicular to the first direction. The MRAM memory cell is also represented in a simplified form showing only the reference layer, free layer, and intermediate tunnel barrier, but in actual implementation forms, it typically includes the additional structures described above with respect to Figure 5.

[0063] The MRAM element 602, which includes a free layer 601, a tunnel barrier 603, and a reference layer 605, is formed on a threshold switching selector 609, where this series combination of the MRAM element 602 and the threshold switching selector 609 together forms a layer 1 cell between the bit line 610 and the word line 1 600. The series coupling of the MRAM element 602 and the threshold switching selector 609 operates mainly as described above when the threshold switching selector 609 is turned on. However, initially, the threshold switching selector 609 has a threshold voltage V thIt must be turned on by applying a voltage exceeding a certain value, and then the bias current or voltage must be maintained at a sufficiently high level above the holding current or holding voltage of the threshold switching selector 609 so that it remains on during subsequent read or write operations.

[0064] On the second layer, the MRAM element 612 includes a free layer 611, a tunnel barrier 613, and a reference layer 615, and is formed above the threshold switching selector 619. Together with the series combination of the MRAM element 612 and the threshold switching selector 619, a layer 2 cell is formed between the bit line 610 and the word line 2 620. The layer 2 cell operates similarly to the layer 1 cell, but here the lower conductor corresponds to the bit line 610 and the upper conductor is the word line, i.e., the word line 2 620. Additional pairs of layers may similarly share another bit line between them having the patterns WL1, BL1, WL2, WL3, BL2, WL4, or they may have separate bit lines with patterns such as WL1, BL1, WL2, BL2, or they may have separate bit lines with patterns such as WL1, BL1, BL2, WL2.

[0065] In the embodiment of Figure 6A, the threshold switching selector 609 / 619 is formed beneath the MRAM elements 602 / 612, but in alternative embodiments, the threshold switching selector can be formed above the MRAM elements for one or both layers. The MRAM memory cells are directional. In Figure 6A, the MRAM elements 602 and 612 have the same orientation, and the free layer 601 / 611 is above the reference layer 605 / 615 (with respect to a substrate not shown). Forming layers between conductive wires having the same structure can have several advantages, particularly with respect to processing, since each of the two layers, as well as subsequent layers in embodiments with more layers, can be formed according to the same processing sequence.

[0066] Figure 6B shows an alternative embodiment arranged similarly to the embodiment in Figure 6A, except that the positions of the reference layer and free layer are reversed in the layer 2 cell. More specifically, between the word line 1 650 and the bit line 660, as in Figure 6A, layer cell 1 includes an MRAM element 1 having a free layer 651 formed on top of a tunnel barrier 653, the tunnel barrier is formed on top of a reference layer 655, and the MRAM element 652 is formed on top of a threshold switching selector 659. The second layer of the embodiment in Figure 6B also has an MRAM element 662 formed on top of a threshold switching selector 669 between the bit line 660 and the word line 2 670, but the MRAM element 662 is reversed compared to Figure 6A, and here it has a reference layer 661 formed on top of the tunnel barrier 663 and a free layer 665 formed below the tunnel barrier 663. Alternatively, the configuration of the MRAM element 662 may be used for layer 1 cell and the configuration of the MRAM cell 652 may be used for layer 2 cell.

[0067] The embodiment in Figure 6B requires a different processing sequence to form the layers, but in some embodiments, it can have advantages. In particular, the orientation of the MRAM structure can make the embodiment in Figure 6B attractive because when writing or reading in the same direction (relative to the reference layer and free layer), the bit lines are biased the same way for both the lower and upper layers, and both word lines are biased the same way. For example, if both the layer 1 and layer 2 memory cells are sensed in the P2AP direction (relative to the reference layer and free layer), the bit line layer 660 is biased in the P2AP direction, and so on, with the bit line 660 being low-biased (e.g., 0V) for both the upper and lower cells, and both word lines 1 650 and 2 670 being biased to a higher voltage level. Similarly, with respect to writing, to write to a high-resistance AP state, the bit line 660 is low-biased (e.g., 0V) for both the upper and lower cells, and both word lines 1 650 and 2 670 are biased to a higher voltage level.

[0068] Reading data from or writing data to an MRAM memory cell involves supplying current to the memory cell. In embodiments where a threshold switching selector is arranged in series with the MRAM elements, the threshold switching selector can be turned on by applying sufficient voltage and current to the series combination of the threshold switching selector and the MRAM elements before current can pass through the MRAM elements.

[0069] Figure 7A shows one embodiment of a memory array 700 having a crosspoint architecture. The memory array 700 may be included in the memory structure 202 of Figure 2 or Figure 3. The array 700 has a set of first conductive wires 706a to 706h and a set of second conductive wires 708a to 708d. In one embodiment, the set of first conductive wires 706a to 706h are word wires, and the set of second conductive wires 708a to 708b are bit wires. For ease of explanation, the set of first conductive wires 706a to 706h may be called word wires, and the set of second conductive wires 708a to 708b may be called bit wires. However, the set of first conductive wires 706a to 706h may be bit wires, and the set of second conductive wires 708a to 708b may be word wires.

[0070] The memory array 700 has several programmable resistive memory cells 401. Each memory cell 401 is connected between one of the first conductive wires 706 and one of the second conductive wires 708 (for example, at the crosspoint between one of the first conductive wires 706 and one of the second conductive wires 708). Each memory cell has a programmable resistive memory element 702 in series with a threshold switching selector 502. In one embodiment, the programmable resistive memory element includes a magnetoresistive random access memory (MRAM) element. The threshold switching selector 502 is configured to become conductive with lower resistance in response to the application of a voltage level exceeding a threshold voltage of the threshold switching selector 502, and remains conductive with lower resistance until the current through the switching selector 502 falls below the selector holding current Ihold. The threshold switching selector 502 may be a two-terminal device. In one embodiment, the threshold switching selector 502 includes an OTS.

[0071] A technique is disclosed for reducing the threshold voltage of a threshold switching selector 502 while adjusting the series resistance to mitigate damage to the programmable resistive memory element 702. The reduction of the threshold voltage of the threshold switching selector 502 may include, but is not limited to, a first-fire operation, a forming operation, or a cold-start operation. For illustrative purposes, a memory cell 401a is selected to reduce the threshold voltage of the threshold switching selector 502. The selected memory cell 401a is located at the intersection of the selected word line 706g and the selected bit line 708b. A selected memory cell means a memory cell selected for a memory operation such as first-fire, forming, cold-start, read, or write. The selected memory cell is connected between the selected word line and the selected bit line. In one embodiment, to reduce the threshold voltage of the threshold switching selector 502 in the selected memory cell 401, a selection voltage, such as near ground, is supplied to the selected bit line (e.g., bit line 708b), and a threshold voltage reduction voltage (Vs) is applied to the selected word line (e.g., word line 706g). A selected word line means that the word line is connected to at least one selected memory cell. Alternatively, a memory cell can be selected by applying a voltage (Vs) to a selected bit line while applying a selection voltage to the selected word line. The threshold voltage drop voltage (Vs) may, but is not limited to, include the first-fire voltage, forming (also called seasoning) voltage, or the voltage for cold-start operation.

[0072] In one approach, word lines not connected to a select memory cell can be driven by a voltage that is approximately half the magnitude of Vs. As shown in Figure 7A, a voltage called the semi-selective voltage (Vs / 2) is applied to each of the word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. The semi-selective voltage (Vs / 2) has a magnitude of approximately half the threshold voltage drop voltage (Vs).

[0073] One approach is that bit lines not connected to a select memory cell can be driven by a voltage that is approximately half the magnitude of Vs. As shown in Figure 7A, a voltage called the semi-selective voltage (Vs / 2) is applied to each of the bit lines 708a, 708c, and 708d. As mentioned above, the semi-selective voltage (Vs / 2) has approximately half the magnitude of Vs.

[0074] Some of the memory cells connected to the selected word line are referred to herein as semi-selected memory cells. The voltage applied to a semi-selected memory cell is approximately half the voltage applied to a selected memory cell. Each semi-selected memory cell 401b connected to the selected word line has Vs applied to the selected word line and Vs / 2 applied to each bit line. Thus, each semi-selected memory cell 401b has Vs / 2 applied across the memory cell.

[0075] Some of the memory cells connected to the selected bit line are referred to herein as semi-selective memory cells. The voltage across these semi-selective memory cells is approximately half the voltage across the selected memory cells. Each semi-selective memory cell 401c connected to the selected bit line has 0V applied to the selected bit line and Vs / 2 applied to the respective word line. Thus, each semi-selective memory cell 401c has Vs / 2 applied across the memory cell.

[0076] Other memory cells are not fully selected, meaning they have approximately 0V across the memory cell. Some of the fully unselected memory cells 401d are shown in Figure 7A. In this example, each fully unselected memory cell 401d has Vs / 2 applied to its word line and Vs / 2 applied to its bit line. The threshold switching selector 502 of the fully unselected memory cells 401d will not turn on even if the threshold voltage of the threshold switching selector 502 is somewhat lower than the target Vth range.

[0077] In the example in Figure 7A, there are more word lines than bit lines in the crosspoint array. In another embodiment, there are more bit lines than word lines in the crosspoint array. In another embodiment, the number of bit lines is equal to the number of word lines in the crosspoint array. In the example in Figure 7A, there are twice as many word lines as bit lines in the crosspoint array; however, different ratios can also be used. This allows for different tile sizes. For example, a tile may have 1024 BL × 2048 WL, which may be configured into a module of 2048 × 4096 cells by centrally driving the WL and BL between four tiles. In one embodiment, reading is performed on a group of memory cells, for example, by selecting one memory cell in each of several tiles. In some embodiments, two or more memory cells may be selected from a tile for reading.

[0078] In one embodiment, the memory system applies a threshold voltage reduction voltage (Vs) to gradually decrease the threshold voltage of the threshold switching selector 502 over several forming cycles. The magnitude of the voltage Vs is reduced for at least some of the forming cycles. In one embodiment, as the voltage Vs decreases, the memory system gradually reduces the resistance of one or more transistors in series with the selected memory cell.

[0079] In some embodiments, a voltage-force technique is used to access memory cells in a crosspoint memory array. In other embodiments, a current-force approach is used to access memory cells in a crosspoint memory array. Figure 7B shows one embodiment of a memory array 700 having a crosspoint architecture in which the current-force approach is used. The memory array 700 and memory cells are the same as those in Figure 7A. A selection voltage (V) close to ground is used to select memory cell 401a. 選択_BL ) is supplied to the selected bit line (e.g., bit line 708b), and the access current (I アクセスThe access current is driven (or forced) to a selected word line (e.g., word line 706g). The access current charges the voltage on the selected word line 706g. There is a limit to the height (e.g., compliance voltage) that the voltage on the selected word line 706g can reach. In one embodiment, V 選択_BL is, I アクセス Assuming that is applied to the selected word line with an appropriate compliance voltage for the BL voltage, it has an appropriate magnitude such that the threshold switching selector 502 in the selected memory cell turns on. For example, V 選択_BL V can be approximately 0V. On the other hand, V unsel_BL The magnitude is such that the threshold switching selector 502 does not turn on in unselected memory cells, for example, when the positive power supply is 3.3V, V unsel_BL The voltage may be approximately 1.65V. Access current (I アクセス The selected word line 706g is driven through at least a portion of the selected word line 706g after the OTS is turned on. This access current may also flow through the selected memory cell 401a and a portion of the selected bit line 708b after the OTS is turned on. Such selected WLs may be driven high by a current source having a compliance voltage of, for example, 3.3V, for example, 15μA for reading or 30μA for writing. To write the opposite polarity, the selected word line is forced to, for example, -30μA and the selected bit line is forced to near 3.3V.

[0080] Word lines and bit lines that are not selected are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, a word line or bit line may be unselected by forcing it to an unselected voltage, such as Vmid, which is about half of the drive compliance voltage, for example, 1.65V, or 3.3V. Unselected voltage V unsel_BL However, this is supplied to unselected bit lines (e.g., bit lines 708a, 708c, 708d). Unselected voltages (V) such as Vmid are supplied. unsel_WL) is provided to unselected word lines (e.g., word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h). アクセス Current can flow in either direction through the selected word lines (and selected bit lines). In one embodiment, current other than leakage current is not forced to flow through the unselected word lines (e.g., 706a, 706b, 706c, 706d, 706e, 706f, and 706h).

[0081] Figure 8 is a schematic diagram showing the resistors along the path supplying voltage across the programmable resistive memory cell 401. The path 800 includes the programmable resistive memory cell 401, bit lines, word lines, and several transistors. The transistors may include transistors in a circuit generally called drivers and / or decoders. For example, transistors may be present in row drivers, row decoders, column drivers, and / or column decoders. Thus, the transistors may include, but are not limited to, decoder transistors including a global word line decoder transistor, a local word line decoder transistor, a global bit line decoder transistor, and / or a local bit line decoder transistor. Therefore, this path 800 includes the series resistance of the programmable resistive memory cell 401, the bit line and word line resistors 802, and the transistor resistor 804. A voltage (V) is applied across the series combination of the programmable resistive memory cell 401, the bit line, the word line, and the transistors. This voltage V may be used to lower the threshold voltage of the threshold switching selector 502 in the memory cell 401. The voltage should be large enough to turn on the threshold switching selector 502. The voltage across the programmable resistive memory element 702 is called V_memory element. The voltage across the threshold switching selector 502 is called V_threshold switching selector. The voltage across the bit line and word line combination is called V_BL / WL. The voltage across the transistor is called V_transistor. In one embodiment, the resistance of the transistor is increased when the threshold voltage of the threshold switching selector 502 is reduced, which increases V_transistor and decreases V_memory element. Decreasing V_memory element when applying a voltage that reduces the threshold voltage of the threshold switching selector 502 mitigates potential damage to the programmable resistive memory element 702.

[0082] Before the threshold switching selector 502 is switched on, its resistance may be much larger than that of other elements in the path, so that the majority of the voltage appears across the threshold switching selector 502. When the threshold switching selector 502 is switched on, its resistance drops significantly. For illustrative purposes, the resistance of the threshold switching selector 502 may be approximately 1 GΩ when off and approximately 100 kΩ when on. The resistance of the programmable resistor memory element 702 may be approximately 70 kΩ when in the AP state. The BL / WL resistance 802 is typically very small compared to the cell resistance 401. For example, the BL / WL resistance 802 may be in the range of 5 to 15 kΩ, but this can vary depending on the location of the memory cells in the array. The transistor resistance 804 can also be very low compared to the cell resistance. For example, the transistor resistance 804 may be in the range of 1 kΩ to 10 kΩ. As will be explained in more detail below, the transistor resistor 804 may be increased to avoid damage to the programmable resistor memory element 702 when the threshold voltage of the threshold switching selector is reduced.

[0083] When the threshold switching selector 502 is switched on, the resistance of the threshold switching selector 502 drops significantly, which can result in a snapback current. This snapback current can damage the programmable resistive memory element 702. In one embodiment, the transistor resistor 804 is adjusted to mitigate damage that may occur to the programmable resistive memory element 702 due to the snapback current. In one embodiment, the memory system increases the resistance of at least one of the transistors to significantly increase the transistor resistor 804, which mitigates damage that may occur to the programmable resistive memory element 702 due to the snapback current. For example, the transistor resistor 804 may be increased to about 200 kΩ, but this is just one example.

[0084] Figure 9 is a graph showing snapback events for first-fire operation and normal read operation. Plot 910 shows the snapback event for first-fire operation. Plot 920 shows the snapback event for normal read operation. Each plot 910, 920 shows the current versus voltage across the threshold switching selector (note that the current is on a logarithmic scale). Plot 910 shows that the threshold switching selector 502 turns on at the "first-fire" voltage Vff. After the threshold switching selector 502 turns on, the voltage across the threshold switching selector 502 drops rapidly to a voltage called Voffset. For example, Voffset may be approximately 1.8V. The current may surge when the threshold switching selector 502 turns on. Plot 920 shows that the threshold switching selector 502 turns on at the "normal operation threshold" voltage Vop. After the threshold switching selector 502 turns on, the voltage across the threshold switching selector 502 drops rapidly to Voffset. In this case as well, the current may surge when the threshold switching selector 502 is turned on.

[0085] Figure 10 shows an example of a snapback current that may occur in response to the threshold switching selector 502 being turned on. Plot 1000 is current versus time. Before the threshold switching selector 502 is turned on at t1, the current is very low. At t1, the threshold switching selector 502 is turned on, resulting in a large current spike. The current decays to a stable level (I_stable) over a period that may depend on the RC time constant of the circuit in the path where the memory cell resides.

[0086] As described above, potential damage to the programmable resistive memory element 702 can be mitigated by adjusting the resistance of the transistor in the path supplying voltage across the memory cell 401. This will be illustrated using the following examples. First, an example without adjusting the transistor's resistance will be described, and then an example with adjusting the transistor's resistance will be described. Referring back to Figure 8, the voltage V can be 4V. The voltage across the threshold switching selector 502 after it is turned on (Voffset) can be 1.8V, leaving approximately 2.2V across the other elements in the path 800. Assuming the resistance of the memory element 702 is 70kΩ, the BL / WL resistance is 5kΩ, and the transistor's resistance is 2kΩ, then V_memory element is approximately 2V, V_BL / WL is approximately 0.14V, and V_transistor is approximately 0.06V. However, assuming the transistor's resistance is increased to approximately 200kΩ, then V_memory element is approximately 0.56V, V_BL / WL is approximately 0.04V, and V_transistor is approximately 1.6V. Therefore, increasing the resistance of the transistor reduces the voltage across the programmable resistive memory element 702 from approximately 2V to approximately 0.56V, which substantially reduces the stress on the programmable resistive memory element 702, thereby mitigating damage to the programmable resistive memory element 702.

[0087] Figure 11 shows one embodiment of a circuit that supplies voltage across a programmable resistive memory cell 401 to lower the threshold voltage of a threshold switching selector 502. The circuit may be used for operations including, but not limited to, first fire, forming, and / or cold start. Figure 11 shows a path including a first CMOS driver 1102, a first conductive wire 1106, a programmable resistive memory cell 401, a second conductive wire 1108, and a second CMOS driver 1104. The memory cell 401 resides within a crosspoint memory array. Either the first conductive wire 1106 or the second conductive wire 1108 may be a word line, and the other conductive wire may be a bit line. The first CMOS driver 1102 includes a first decoder circuit 1132 which may include one or more transistors. The first CMOS driver 1102 may include transistors other than the one or more transistors in the first decoder circuit 1132. The first CMOS driver 1102 selectively drives the first conductive wire 1106. The first CMOS driver 1102 can drive current or voltage to the first conductive wire 1106. The second CMOS driver 1104 includes a second decoder circuit 1134 which may include one or more transistors. The second CMOS driver 1104 may include transistors other than one or more transistors in the second decoder circuit 1134. The second CMOS driver 1104 selectively drives the second conductive wire 1108. The second CMOS driver 1104 can drive current or voltage to the second conductive wire 1108. Voltage V1 may be higher or lower than voltage V2. A resistance control signal is supplied to the first CMOS driver 1102 to control the resistance of the first CMOS driver 1102. In one embodiment, the resistance control signal is a voltage applied to the control gate of a transistor in the first CMOS driver 1102. In one embodiment, the resistance control signal is a voltage applied to the control gate of a transistor in the decoder circuit 1132. The magnitude of the voltage controls the resistance of the transistor. In one embodiment, the magnitude of the resistance control signal is sufficient to turn on the transistor so that it can pass a signal (e.g., current, voltage) and select a line in the array, etc.In one embodiment, the transistor is a decoder transistor that selects a first conductive line from among other similar conductive lines. For example, the decoder transistor may be a local word line decoder transistor that selects a word line in the array. In another example, the decoder transistor may be a local bit line decoder transistor that selects a bit line in the array. However, the transistor does not have to be a local word line (or local bit line) decoder transistor.

[0088] Figure 12 is a schematic diagram of one embodiment of a path including a word line, a bit line, and a programmable resistor memory cell 401 in series with several transistors. This path includes a current source 1202, word line decoder transistors (T3P, T1P), a word line (WL), memory cell 401, a bit line (BL), and bit line decoder transistors (T1N, T3N). The word line decoder transistors (T3P, T1P) are present in one embodiment of decoder circuit 1132, and the bit line decoder transistors (T1N, T3N) are present in one embodiment of decoder circuit 1134. Alternatively, the word line decoder transistors (T3P, T1P) are present in one embodiment of decoder circuit 1134, and the bit line decoder transistors (T1N, T3N) are present in one embodiment of decoder circuit 1132. The path has a positive power supply Vp, such as about 3.3V. The current source 1202 is connected to the power supply (Vp) and supplies a drive current I_Drive that can be used to charge the word line. The maximum possible voltage that the word line can reach is Vp, which is less than the voltage that appears between the current source 1202 and transistors T1, T3P, and T1P. The resistance of one or more of the transistors may be adjusted to mitigate potential damage to the memory element 702 during the operation of lowering the threshold voltage of the threshold switching selector 502. In one embodiment, the magnitude of the control gate voltage to one or more of T3P, T1P, T1N, and / or T3N is used to control the resistance of the corresponding transistors T3P, T1P, T1N, and / or T3N to mitigate potential damage to the memory element 702. During this operation, all transistors in the path are turned on in order to select the memory cell 401 and provide the target voltage across the memory cell 401.

[0089] The current is read out to turn on transistor T1. *It can be enabled by setting it low. The output of T1, which is node VXSP, also drives the non-inverting input (+) of the differential sense amplifier 1206. The differential sense amplifier 1206 may be used to sense the resistance of memory cell 401, but sensing of memory cell 401 is not required for threshold voltage drop operations such as first fire, forming, or cold start. The inverting input (-) of the differential sense amplifier 1206 is supplied with a reference voltage (Vref). For globally referenced readouts, Vref is the global reference voltage. For SRR, Vref is derived from a previous sensing operation by, for example, bumping the voltage from readout 1 by 150mV.

[0090] The P-channel transistor T3P functions as a global WL decoder and the decoder address signal SVXP * The P-channel transistor T1P can be selected when the gate of T3P is low, such as when it is driven by the decoder address signal RDEC. * It acts as a local WL decoder that can be selected when the gate of T1P is low, such as when driven by SVXP. The P-channel transistor T3P can act as a driver for the selected WL. The decoder address signal is SVXP * SVXP * In this example, it is active-low, so when it is low, T3P turns on and Tx turns off. However, SVXP * When it is high, T3P is off and Tx is on, and therefore Vmid is provided to the word line. The decoder address signal is RDEC * And in this example, this is active-low, and RDEC * When it is low, T1P is turned on. In one embodiment, the decoder address signal SVXP * The size of the T3P is used to control the resistance and mitigate potential damage to the memory element 702. Decoder address signal SVXP *The magnitude could be at an appropriate level such that T3P is on (Tx is off and T1P is on) to select the word line (WL). Another option is the decoder address signal RDEC * The purpose is to control the resistance of T1P using its magnitude and mitigate potential damage to the memory element 702. Decoder address signal RDEC * The size is at a suitable level for selecting the word line WL while establishing the desired resistance at T1P.

[0091] Memory cell 401 is connected between WL and BL. The memory cell (or bit) has a threshold switching selector 502 and a memory element 702. The selected WL may be one of N WLs in the array. The BL may be one of M BLs in the array. Memory cell 401 may be located at the crosspoint between WL and BL on a chip having one or more arrays. An N-channel transistor T1N can act as a local decoder driver to BL. BL may be selected when the T1N gate is high, such as when driven by the decoder address signal T1N_S. An N-channel transistor T3N can act as a global decoder, and the global decoder is selected when the T3N gate is high, such as when driven by the decoder address signal T3N_S. The output of T3N is VYS. The driver (YEN) is between VYS and a negative (i.e., negative with respect to Vp) power supply (GND).

[0092] In one embodiment, the magnitude of the decoder address signal T1N_S is used to control the resistance of T1N to mitigate potential damage to the memory element 702. The magnitude of the decoder address signal T1N_S may be at an appropriate level such that T1N is turned on (and T3N is also turned on) to select the bit line (BL). Another option is to use the magnitude of the decoder address signal T3N_S to control the resistance of T3N to mitigate potential damage to the memory element 702. The magnitude of the decoder address signal T3N_S will be at a level suitable for selecting the bit line BL while establishing the desired resistance in T3N.

[0093] In one embodiment, the operation of the path is as follows: Node VXSP, selected WL, selected BL, and VYS can be transistor precharged to Vmid during the standby phase. The desired WL line (one of N) can be selected by turning off the precharge and applying a low voltage to the gates of transistors T3P and T1P (the gate voltage is called the decoder address signal). The BL line can be selected by turning off the precharge and applying a high voltage to the gates of transistors T1N and T3N (the gate voltage is called the decoder address signal). The gate of transistor YEN can be set high to connect node VYS to GND. I_drive is then turned on and the gate of T1 is set low (e.g., readout). * It can be connected to VXSP by (when YEN goes low). Therefore, BL can be rapidly pulled to GND by its active driver when it is turned on by YEN going high. The selected WL and VXSP are ramped toward Vp by I_drive.

[0094] The threshold switching selector 502 turns on when the voltage across the threshold switching selector 502 reaches its current threshold voltage. During first-fire operation, this is Vff (see Figure 9). During forming operation, the threshold voltage of the threshold switching selector 502 can be somewhere between Vop and Vff (see Figure 9). When the threshold switching selector 502 switches on, the voltage across the threshold switching selector 502 drops to Voffset (see Figure 9). Snapback current arises due to the voltage drop on the word line when the threshold switching selector 502 turns on. Furthermore, potentially, when the voltage across the threshold switching selector 502 drops, the voltage across the memory element 702 may rise significantly. However, by establishing one or more of the resistors T3P, T1P, T1N, and / or T3N to a resistance higher than the nominal resistance (the nominal resistance is the resistance used when sensing the memory cell 401 using the sense amplifier 1206), a considerable voltage appears across the transistors T3P, T1P, T1N, and / or T3N after the threshold switching selector 502 is turned on, thereby reducing the voltage across the memory element 702.

[0095] Figure 13 is a schematic diagram of one embodiment of a path including a word line, a bit line, and a programmable resistor memory cell 401 in series with several transistors. The read path includes a current source 1302, word line decoder transistors (T6N, T4N), a word line (WL), memory cell 401, a bit line (BL), and bit line decoder transistors (T4P, T6P). The word line decoder transistors (T6N, T4N) are present in one embodiment of decoder circuit 1132, and the bit line decoder transistors (T4P, T6P) are present in one embodiment of decoder circuit 1134. Alternatively, the word line decoder transistors (T6N, T4N) are present in one embodiment of decoder circuit 1134, and the bit line decoder transistors (T4P, T6P) are present in one embodiment of decoder circuit 1132. The read path has a Vp positive power supply, such as approximately 3.3V, connected to transistor YEP. The current source 1302 is connected to ground and supplies I_Drive to the memory cell (when the threshold switching selector 502 is ON, current flows from the bit line to the word line). The current is read out to turn on transistor T1. * It can be enabled by setting it low. The output of T1, which is node VXSN, also drives the non-inverting input (+) of the differential sense amplifier 1206. The inverting input (-) of the differential sense amplifier 1206 is supplied with a reference voltage (Vref). For globally referenced readouts, Vref is the global reference voltage. For SRR, Vref is derived from a previous sensing operation by, for example, bumping the voltage from readout 1 by 150mV.

[0096] The N-channel transistor T6N functions as a global WL decoder and can be selected when its gate is high, such as when driven by the decoder address signal SVXN. The N-channel transistor T4N functions as a local WL decoder and can be selected when its gate is high, such as when driven by the decoder address signal RDEC. The N-channel transistor T6N can also function as a driver to the selected WL. The decoder address signal is SVXN, which in this example is active high so that when SVXN is high, T6N is on and T5 is off. However, when SVXN is low, T6N is off and T5 is on, thus providing Vmid to the word line. The decoder address signal is RDEC, which in this example is active high so that when RDEC is high, T4N is on.

[0097] Memory cell 401 is similar to the cell described in relation to Figure 12. BL is the decoder address signal T4P_S * The T4P gate may be selected when it is low, such as when driven by [a specific mechanism]. The P-channel transistor T6P can act as a global bit-line decoder, and the decoder address signal T6P_S * This is selected when the T6P gate is low, such as when driven by [a specific mechanism]. The output of T6P is VYS. The driver (YEP) is between VYS and a positive power supply (Vp), which can be approximately 3.3V. The operation of the path is similar to the path described in relation to Figure 12; therefore, a detailed explanation is omitted.

[0098] The resistance of one or more of the transistors in Figure 13 may be adjusted to mitigate potential damage to the memory element 702 during the operation of lowering the threshold voltage of the threshold switching selector 502. In one embodiment, the magnitude of the control gate voltage to one or more of T6N, T4N, T4P, and / or T6P is used to control the resistance of the corresponding transistors T6N, T4N, T4P, and / or T6P to mitigate potential damage to the memory element 702. During this operation, all transistors in the path are turned on to select the memory cell 401 and provide the target voltage across the memory cell 401.

[0099] In one embodiment, the magnitude of the decoder address signal SVXN is used to control the resistance of T6N and mitigate potential damage to the memory element 702. The magnitude of the decoder address signal SVXN may be at an appropriate level such that T6N is on (T5 is off and T4N is on) to select the word line (WL). Another option is to use the magnitude of the decoder address signal RDEC to control the resistance of T4N and mitigate potential damage to the memory element 702. The magnitude of the decoder address signal RDEC is at a level suitable for selecting the word line WL while establishing the target resistance in T4N.

[0100] In one embodiment, the decoder address signal T4P_S * The size of the T4P is used to control the resistance of the T4P and mitigate potential damage to the memory element 702. Decoder address signal T4P_S * The magnitude can be at an appropriate level such that T4P is on (and T6P is also on) to select the bit line (BL). Another option is the decoder address signal T6P_S * The purpose is to control the resistance of T6P using its magnitude and mitigate potential damage to the memory element 702. Decoder address signal T6P_S * The size of this value will be at a level suitable for selecting the bit line BL while establishing the target resistance on T6P.

[0101] Figure 14 is a flowchart of one embodiment of a process 1400 for mitigating damage to a programmable resistive memory cell 401 while lowering the threshold voltage of the threshold switching selector of the memory cell 401. Step 1402 includes establishing the resistance of one or more transistors in series with the memory cell 401 as a first resistance in order to lower the threshold voltage of the threshold switching selector 502 within the programmable resistive memory cell 401.

[0102] Step 1404 includes applying a voltage across the programmable resistive memory cell 401 using a transistor in the first resistor to lower the threshold voltage of the threshold switching selector 502 within the programmable resistive memory cell 401.

[0103] Step 1406 is a decision on whether or not to further reduce the threshold voltage of the threshold switching selector 502. In one embodiment, steps 1402 and 1404 are performed in a cold start operation, and it is not necessary to further reduce the threshold voltage of the threshold switching selector 502 after the first loop. In one embodiment, steps 1402 and 1404 are performed in a first-fire operation, and it is not necessary to further reduce the threshold voltage of the threshold switching selector 502 after the first loop. However, steps 1402 and 1404 may also be performed in a forming operation, and steps 1402 and 1404 may be repeated multiple times. When repeating steps 1402 and 1404, one option is to gradually use lower resistance for the transistor as the voltage applied across the memory cell 401 decreases. When the threshold voltage of the threshold switching selector 502 has been reduced to a desired level (e.g., Vop), the execution of steps 1402 and 1404 may be terminated.

[0104] A dashed line is placed between step 1406 and step 1408 to indicate that a considerable amount of time may elapse between them. For example, if steps 1406 and 1408 are used for first fire and / or forming, a considerable amount of time may elapse between step 1402 and step 1404. However, if steps 1402 and 1404 are used for cold start operations, step 1408 may be executed without a considerable amount of time elapsed.

[0105] Step 1408 includes establishing the resistance of one or more transistors in series with the memory cell 401 as a second resistance for sensing the programmable resistor memory cell 401. The second resistance is lower than the first resistance.

[0106] Step 1410 includes applying a voltage across the programmable resistive memory cell 401 using a transistor in a second resistor in order to sense the programmable resistive memory cell 401. Step 1410 may also include sensing the memory cell 401 using a sense amplifier (e.g., sense amplifier 1206). In one embodiment, sense amplifier 1206 is used to sense a voltage at node VXSP (see Figures 12 and 13).

[0107] Figure 15 is a flowchart of one embodiment of process 1500 for mitigating damage to a programmable resistive memory cell 401 while lowering the threshold voltage of the threshold switching selector of the memory cell 401 during the forming process. The memory cell 401 may reside in a crosspoint array. Process 1500 provides further details of one embodiment of process 1400. Process 1500 can be used to lower the threshold voltage of an obonic threshold switch (OTS). Other types of threshold switching selectors can have their threshold voltages lowered by performing process 1500. The programmable resistive memory cell 401 has a programmable resistive memory element 702 in series with a threshold switching selector 502. Examples of programmable resistive memory elements include, but are not limited to, MRAM, ReRam, Phase Change Memory (PCM), and FeRam. When describing process 1500, refer to the crossbar array 700 in Figure 7A.

[0108] Step 1502 includes setting the initial magnitude of the forming voltage. The forming voltage is applied to the selected memory cell (or multiple memory cells) for forming. In one embodiment, the initial magnitude of the forming voltage is greater than the maximum expected initial threshold voltage (e.g., Vff) of the threshold switching selector 502. An example of the initial magnitude of the forming voltage is about 4.2V, but this magnitude may vary depending on the characteristics of the threshold switching selector 502. Step 1504 includes setting the initial magnitude of the control gate voltage of the decoder transistor for the highest resistance. This highest resistance refers to the highest resistance used in process 1500, and it should be noted that the decoder transistor is turned on at this resistance so that it may be used in the selection of either a word line or a bit line. In one embodiment, the decoder transistor is a "global decoder transistor". In one embodiment, the decoder transistor is a "local decoder transistor". However, the decoder transistor is not limited to being a global or local decoder transistor. In one embodiment, the control gate voltage is the decoder address signal.

[0109] Process 1500 is illustrated using an example of selecting one memory cell 401 in a crosspoint array at a time. Steps 1506-1512 are described in a specific order for convenience of explanation. Steps 1506-1512 may be performed in a different order, and / or some of these steps may be performed simultaneously. Step 1506 includes grounding the selected bit line. For example, 0V is applied to bit line 708b. Step 1508 includes applying a semi-selective voltage Vs / 2 to the semi-selective word lines. For example, Vs / 2 is applied to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. Step 1510 includes applying a semi-selective voltage Vs / 2 to the semi-selective bit lines. For example, Vs / 2 is applied to bit lines 708a, 708c, and 708d. Step 1512 includes applying a forming voltage to the selected word line. In one embodiment, Vs in Figure 7A is the forming voltage. For example, Vs is applied to word line 706g. Step 1512 also includes applying a voltage to the control gate of the decoder transistor to establish the target resistance in the decoder transistor. An exemplary range for the duration of the forming voltage is 10 nanoseconds (ns) to 100 ns. However, the duration of the forming voltage may be longer or shorter than this example range. In one embodiment, the forming voltage is applied to one end of the selected memory cell, and the other end of the selected memory cell is grounded.

[0110] Step 1514 includes a decision on whether to perform additional forming on this cell. In step 1514, the memory system may test the threshold voltage of the memory cell to determine whether the threshold voltage has reached the target level. When testing the Vt of the memory cell, the resistance of the decoder transistor may be established at a lower resistance than that used in step 1512. For example, the resistance of the decoder transistor may be established at the nominal level used when sensing during a read operation. An exemplary range for the target level is between 2V and 3V, but the target level may be below or above this range. It is not necessary to test the threshold voltage with each iteration. Rather, the memory system may apply the forming voltage multiple times between each test of the threshold voltage.

[0111] Step 1516 is an optional reduction of the forming voltage. In one embodiment, the memory system applies a forming voltage to a selected memory cell a predetermined number of times at its current magnitude. The memory system may change the polarity of the forming signal in subsequent applications. For example, in one iteration of steps 1508-1512, the forming voltage may result in a positive voltage from the word line to the bit line, and in another iteration of steps 1508-1512, the forming voltage may result in a negative voltage from the word line to the bit line. Step 1516 may include reducing the magnitude of the forming voltage. As an example, the magnitude of the forming voltage may be reduced by 100mV. The magnitude of the semi-selective voltage is also reduced accordingly, while the semi-selective voltage remains at Vs / 2.

[0112] Step 1518 includes optionally changing the magnitude of the control gate voltage to the decoder transistor in order to reduce the resistance of the decoder transistor. In one embodiment, the resistance of the decoder transistor decreases in response to a decrease in the magnitude of the forming voltage. After step 1518, the memory system repeats steps 1508-1512.

[0113] Figure 16 is a flowchart of one embodiment of process 1600, which mitigates damage to the programmable resistive memory cell 401 while lowering the threshold voltage of the threshold switching selector of the memory cell 401 during a forming process that uses a current-force approach to provide a forming voltage. Process 1600 provides further details of one embodiment of process 1400. Process 1600 can be used to lower the threshold voltage of an obonic threshold switch (OTS). Other types of threshold switching selectors can have their threshold voltages lowered by performing process 1600. The programmable resistive memory cell 401 has a programmable resistive memory element 702 in series with a threshold switching selector 502. Examples of programmable resistive memory elements include, but are not limited to, MRAM, ReRam, Phase Change Memory (PCM), and FeRam. When describing process 1500, refer to the crossbar array 700 in Figure 7B.

[0114] Step 1602 includes setting the initial magnitude of the voltage limit for the forming voltage caused by the current applied to the selected word line. In one embodiment, the initial magnitude of the forming voltage is greater than the maximum expected initial Vth of the threshold switching selector 502. An example of an initial voltage limit for the forming voltage is about 4.2V, but this magnitude may vary depending on the characteristics of the threshold switching selector 502.

[0115] Step 1604 includes setting the initial magnitude of the control gate voltage of the decoder transistor for the highest resistance. Note that this highest resistance refers to the highest resistance used in process 1600, and the decoder transistor is turned on at this resistance so that it can be used in either the word line or the bit line. In one embodiment, the decoder transistor is a "global decoder transistor". In one embodiment, the decoder transistor is a "local decoder transistor". However, the decoder transistor is not limited to being a global or local decoder transistor. In one embodiment, the control gate voltage is the decoder address signal.

[0116] Process 1600 is illustrated using an example of selecting one memory cell 401 in the crossbar array at a time. Steps 1606-1612 are described in a specific order for convenience of explanation. Steps 1606-1612 may be performed in a different order, and / or some of these steps may be performed simultaneously. Step 1606 includes grounding the selected bit line. For example, 0V is applied to bit line 708b. Step 1608 includes applying a semi-selective voltage Vs / 2 to the semi-selective word lines. For example, Vs / 2 is applied to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. Step 1610 includes applying a semi-selective voltage Vs / 2 to the semi-selective bit lines. For example, Vs / 2 is applied to bit lines 708a, 708c, and 708d. Step 1612 includes driving (forcing) current to the selected word line. For example, the current drives word line 706g. Step 1612 also includes applying a voltage to the control gate of the decoder transistor to establish the target resistance in the decoder transistor.

[0117] Step 1614 includes a decision on whether to perform additional forming on this cell. In step 1614, the memory system may test the threshold voltage of the memory cell to determine whether the threshold voltage has reached the target level. When testing the Vt of the memory cell, the resistance of the decoder transistor may be established at a lower resistance than that used in step 1512. An exemplary range for the target level is between 2V and 3V, but the target level may be below or above this range. It is not necessary to test the threshold voltage in every iteration.

[0118] Step 1616 is an optional reduction of the voltage limit. The memory system may change the polarity of the current in the next application. For example, one iteration of steps 1608-1612 may yield a positive voltage from the word line to the bit line, and another iteration of steps 1608-1612 may yield a negative voltage from the word line to the bit line. Step 1616 may include reducing the magnitude of the voltage limit. As an example, the magnitude of the voltage limit may be reduced by 100mV. The magnitude of the semi-selective voltage is also reduced accordingly, while the semi-selective voltage remains Vs / 2.

[0119] Step 1618 includes optionally changing the magnitude of the control gate voltage to the decoder transistor in order to reduce the resistance of the decoder transistor. In one embodiment, the resistance of the decoder transistor is reduced in response to a reduction in the magnitude of the voltage limit. After step 1618, the memory system repeats steps 1608-1612.

[0120] Considering the above, it can be seen that according to one embodiment, the device comprises a circuit configured to connect to a selected programmable resistive memory cell in a crosspoint array and to apply a voltage to the cell. The circuit comprises a plurality of transistors configured to connect in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line in the crosspoint array. The device comprises one or more control circuits that communicate with the circuit. One or more control circuits are configured to apply a first control signal to the circuit to establish a first resistance in the plurality of transistors in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line, when controlling the circuit to apply a voltage across the selected programmable resistive memory cell in order to lower the threshold voltage of a threshold switching selector in the selected programmable resistive memory cell. One or more control circuits are configured to apply a second control signal to the circuit to establish a second resistance in the circuit in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line, in order to sense the selected programmable resistive memory. The second resistance is lower than the first resistance.

[0121] In a further embodiment of the device, the first control signal and the second control signal are decoder address signals having different magnitudes.

[0122] In a further embodiment of the device, one or more control circuits are configured to apply a first control signal to the control gate of a decoder transistor in the circuit in order to select either a selected word line or a selected bit line in order to reduce the threshold voltage of the threshold switching selector in a programmable resistive memory cell during threshold switching selector threshold voltage reduction operation. One or more control circuits are also configured to apply a second control signal to the control gate of a decoder transistor in the circuit in order to select either a selected word line or a selected bit line, and to sense the selected programmable resistive memory cell during readout operation.

[0123] In a further embodiment of the device, one or more control circuits are configured to apply a series of voltages across a selected programmable resistive memory cell to gradually decrease the threshold voltage of a threshold switching selector within the programmable resistive memory cell, including gradually decreasing the resistance of a series of transistors in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line by a series of voltages.

[0124] In a further embodiment of the device, one or more control circuits are configured to apply a first control signal to the circuit to establish a first resistance of a plurality of transistors in first-fire operation.

[0125] In a further embodiment of the device, one or more control circuits are configured to apply a first control signal to the circuit in order to establish a first resistance of a plurality of transistors in a forming operation.

[0126] In a further embodiment of the device, one or more control circuits are configured to apply a first control signal to the circuit in order to establish a first resistance of a plurality of transistors during a cold start operation.

[0127] In a further embodiment of the device, the threshold switching selector comprises an obonic threshold switch (OTS).

[0128] In a further embodiment of the device, the programmable resistive memory elements within the programmable resistive memory cell include magnetoresistive random access memory (MRAM) elements.

[0129] One embodiment includes a method for operating a memory having a crosspoint array. The method includes supplying a first decoder address signal having a first magnitude to the control gate of a transistor in the decoder circuit to cause the decoder circuit to charge the voltage on the first selected conductive line in the crosspoint array while the transistor has a first resistance during a threshold voltage drop operation of a threshold switching selector for a selected programmable resistor memory cell connected to a first selected conductive line. The method also includes supplying a second decoder address signal having a second magnitude to the control gate of a transistor in the decoder circuit to cause the decoder circuit to charge the voltage on the first selected conductive line in the crosspoint array while the transistor has a second resistance during a read operation of a selected programmable resistor memory cell connected to the first selected conductive line. The second resistance is lower than the first resistance.

[0130] One embodiment includes a memory system comprising a crossbar array having a plurality of first conductive wires, a plurality of second conductive wires, and a plurality of programmable resistive memory cells. Each programmable resistive memory cell has a threshold switching selector in series with the programmable resistive memory element. Each programmable resistive memory cell is located at a crosspoint between one of the first conductive wires and one of the second conductive wires. The memory system includes a decoder circuit comprising a transistor having a control gate. The memory system includes one or more control circuits that communicate with the crossbar array and the decoder circuit. One or more control circuits are configured to apply a first voltage to the control gate of a transistor so that the transistor has a first resistance while the threshold switching selector in a selected programmable resistive memory cell connected to a selected first conductive wire is forming, and the transistor supplies a first current to the selected first conductive wire in the crossbar array to charge the voltage on the selected first conductive wire. One or more control circuits are configured to apply a second voltage to the control gate of a transistor so that the transistor has a second resistance while the transistor supplies a second current to the selected first conductive wire in the crossbar array, thereby charging the voltage on the selected first conductive wire, during a read operation of a selected programmable resistor memory cell connected to a selected first conductive wire. The second resistance is smaller than the first resistance.

[0131] For the purposes of this specification, references to “embodiments,” “one embodiment,” “several embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0132] For the purposes of this specification, connections may be direct or indirect (e.g., via one or more other parts). Where it is referred to that one element is connected or coupled to another, that element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is said to be directly connected to another element, there is no intermediary element between that element and the other element. Two devices are “communicating” if they are connected directly or indirectly so that electronic signals can be communicated between them.

[0133] For the purposes of this specification, the term "based on" may be read as "based at least in part on."

[0134] For the purposes of this specification, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, may not imply an ordering of objects, but rather may be used for identifying purposes to distinguish different objects.

[0135] The terms “top” and “bottom,” “upper” and “lower,” and “vertical” and “horizontal,” and their forms, as may be used herein, are for illustrative and illustrative purposes only and do not mean to limit the description of the technique insofar as the items being referenced are interchangeable in position and orientation. Also, as used herein, the terms “substantially” and / or “about” mean that the specified dimensions or parameters may vary within acceptable tolerances for a given application.

[0136] The detailed description above is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosed form to the exact form. Many modifications and variations are possible in light of the above teachings. The embodiments described have been selected to best illustrate the principles of the proposed art and its practical application, thereby enabling other persons skilled in the art to best utilize it in various embodiments and with various modifications suitable for the specific use to be intended. The scope is intended to be defined by the claims appended herein.

Claims

1. It is a device, A circuit configured to connect to a selected programmable resistor memory cell in a crosspoint array and apply a voltage across its terminals, comprising a plurality of transistors configured to be connected in series with the selected programmable resistor memory cell, a selected word line, and a selected bit line in the crosspoint array, One or more control circuits that communicate with the aforementioned circuit, When controlling the circuit to apply a voltage across the selected programmable resistive memory cell in order to lower the threshold voltage of the threshold switching selector in the selected programmable resistive memory cell, a first control signal is applied to the circuit to establish a first resistance of the plurality of transistors in series with the selected programmable resistive memory cell, the selected word line, and the selected bit line, An apparatus comprising one or more control circuits configured to apply a second control signal to a circuit to establish a second resistance in the circuit in series with the selected word line, the selected bit line, and the selected programmable resistive memory cell, such that the second resistance is lower than the first resistance, in order to sense the selected programmable resistive memory cell.

2. The apparatus according to claim 1, wherein the first control signal and the second control signal are decoder address signals having different magnitudes.

3. The one or more control circuits described above The first control signal is applied to the control gate of the decoder transistor in the circuit to select either the selected word line or the selected bit line, thereby lowering the threshold voltage of the threshold switching selector in the programmable resistor memory cell during the threshold switching selector threshold voltage reduction operation. The apparatus according to claim 1, configured to apply the second control signal to the control gate of the decoder transistor in the circuit, to select either the selected word line or the selected bit line, and to sense the selected programmable resistor memory cell in a read operation.

4. The one or more control circuits described above The apparatus according to claim 1, wherein the apparatus is configured to apply a series of voltages across the selected programmable resistive memory cell, including gradually reducing the resistance of the plurality of transistors in series with the selected programmable resistive memory cell, the selected word line, and the selected bit line, in order to gradually reduce the threshold voltage of the threshold switching selector in the programmable resistive memory cell.

5. The apparatus according to claim 1, wherein one or more control circuits are configured to apply a first control signal to the circuit in order to establish the first resistance of the plurality of transistors in first-fire operation.

6. The apparatus according to claim 1, wherein one or more control circuits are configured to apply a first control signal to the circuit in order to establish the first resistance of the plurality of transistors in a forming operation.

7. The apparatus according to claim 1, wherein one or more control circuits are configured to apply the first control signal to the circuit in order to establish the first resistance of the plurality of transistors during a cold start operation.

8. The apparatus according to claim 1, wherein the threshold switching selector comprises an ovonic threshold switch (OTS).

9. The apparatus according to claim 1, wherein the programmable resistive memory element in the programmable resistive memory cell comprises a magnetoresistive random access memory (MRAM) element.

10. A method for operating a memory having a crosspoint array, A first decoder address signal having a first magnitude is supplied to the control gate of a transistor in the decoder circuit, causing the decoder circuit to charge the voltage on the first selected conductive line while the transistor has a first resistance during threshold voltage drop operation of the threshold switching selector of a selected programmable resistor memory cell connected to the first selected conductive line in the crosspoint array, A method comprising supplying a second decoder address signal having a second magnitude to the control gate of the transistor in the decoder circuit, such that the second resistance is lower than the first resistance, to cause the decoder circuit to charge a voltage on the first selected conductive line in the crosspoint array while the transistor has a second resistance during a read operation of the selected programmable resistor memory cell connected to the first selected conductive line.

11. During the threshold voltage reduction operation, further comprising applying a series of forming voltages to the selected programmable resistor memory cell, and applying a series of voltages to the control gate of the transistor in the decoder circuit to cause the decoder circuit to charge the voltage on the first selected conductive line while the transistor has a gradually decreasing resistance due to the series of forming voltages, The method according to claim 10, further comprising:

12. The method according to claim 10, wherein the threshold voltage reduction operation is a first-fire operation.

13. The method according to claim 10, wherein the threshold voltage reduction operation is a forming operation.

14. The method according to claim 10, wherein the threshold voltage reduction operation is a cold start operation.

15. It is a memory system, A crossbar array comprising a plurality of first conductive wires, a plurality of second conductive wires, and a plurality of programmable resistive memory cells, wherein each programmable resistive memory cell has a threshold switching selector in series with a programmable resistive memory element, and each programmable resistive memory cell is positioned at a crosspoint between one of the first conductive wires and one of the second conductive wires. A decoder circuit comprising a transistor having a control gate, The system comprises one or more control circuits that communicate with the crossbar array and the decoder circuit, and the one or more control circuits During the forming operation of the threshold switching selector in a selected programmable resistor memory cell connected to the selected first conductive wire, while the transistor supplies a first current to the selected first conductive wire in the crossbar array to charge the voltage on the selected first conductive wire, a first voltage is applied to the control gate of the transistor so that the transistor has a first resistance, A memory system configured to perform the following during a read operation of the selected programmable resistor memory cell connected to the selected first conductive wire: while the transistor supplies a second current to the selected first conductive wire in the crossbar array to charge the voltage on the selected first conductive wire, a second voltage is applied to the control gate of the transistor so that the transistor has a second resistance, wherein the second resistance is smaller than the first resistance.

16. The forming operation includes a series of gradually decreasing forming voltages applied across the selected programmable resistive memory cell to gradually decrease the threshold voltage of the threshold switching selector within the selected programmable resistive memory cell, The one or more control circuits are configured to change the magnitude of the first voltage applied to the transistor during the forming operation, thereby gradually reducing the resistance of the transistor using a series of gradually decreasing forming voltages. The memory system according to claim 15.

17. The first voltage and the second voltage are decoder address signals having different magnitudes. The memory system according to claim 15.

18. The decoder circuit is a local word line decoder or a local bit line decoder configured to select the selected first conductive line in response to the decoder address signal. The memory system according to claim 17.

19. The memory system according to claim 15, wherein the threshold switching selector comprises an ovonic threshold switch (OTS).

20. The memory system according to claim 15, wherein the programmable resistive memory element includes a magnetoresistive random access memory (MRAM) element.

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