Wiring board and trimming method thereof, and multilayer wiring board

Abstract

Provided is a wiring substrate enabling improvement in mechanical strength, water resistance, moisture resistance, and product yield during and after trimming. This wiring substrate is provided with: a device region in which a main wiring pattern constituted of a metal layer is embedded in an insulating layer; a peripheral region which surrounds the device region and in which a dummy wiring pattern constituted of a metal layer electrically independent of the main wiring pattern is embedded in an insulating layer; and an insulation boundary region which is interposed between the device region and the peripheral region and which is constituted of an insulating layer with no metal layer present therein. The insulation boundary region, in plan view, has a bending, twisting shape that makes it possible to draw a virtual straight line that alternately crosses the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulation boundary region, said virtual line being in parallel with an inscribed line on at least one side of an outer margin of the device region. The device region, in plan view, is completely separated by the insulation boundary region from the virtual straight line.

Description

Technical Field

[0001] The present invention relates to a wiring board, a trimming method thereof, and a multilayer wiring board.

Background Art

[0002] In recent years, in order to increase the mounting density and miniaturize printed wiring boards (wiring boards), the multilayerization of printed wiring boards has been widely carried out. Such multilayer printed wiring boards (multilayer wiring boards) are used in many portable electronic devices for the purpose of weight reduction and miniaturization. And for such multilayer printed wiring boards, further reduction in the thickness of the interlayer insulating layer and further weight reduction as a wiring board are required.

[0003] As a technique to meet such requirements, a method for manufacturing a multilayer printed wiring board using a coreless build-up method has been adopted. The coreless build-up method is a method of alternately laminating (building up) an insulating layer and a wiring layer to form a multilayer without using a so-called core substrate. In the coreless build-up method, it has been proposed to use a carrier-attached metal foil so that the carrier can be easily peeled from the multilayer printed wiring board. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-101137) discloses a method for manufacturing a package substrate for mounting a semiconductor element, which includes attaching an insulating resin layer to the carrier surface of a copper foil with a carrier to form a support, forming a first wiring conductor by processes such as photoresist processing, pattern electrolytic copper plating, and resist removal on the ultra-thin copper layer side of the copper foil with a carrier, then forming a build-up wiring layer, peeling the carrier-attached support substrate, and removing the ultra-thin copper layer.

[0004] Furthermore, in order to miniaturize embedded circuits as shown in Patent Document 1, a carrier-mounted metal foil with a metal layer thickness of 1 μm or less is desired. Therefore, in order to reduce the thickness of the metal layer, it has been proposed to form the metal layer by a vapor phase method such as sputtering. For example, Patent Document 2 (International Publication No. 2017 / 150283) discloses a carrier-mounted copper foil in which a release layer, an anti-reflective layer, and an ultrathin copper layer (e.g., a film thickness of 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent Document 3 (International Publication No. 2017 / 150284) also discloses a carrier-mounted copper foil in which an intermediate layer (e.g., an adhesive metal layer and a release assist layer), a release layer, and an ultrathin copper layer (e.g., a film thickness of 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent documents 2 and 3 teach that interposing an intermediate layer made of a predetermined metal provides excellent stability in the mechanical peel strength of the carrier, and that the anti-reflective layer exhibits a desirable dark color, thereby improving visibility in image inspection (e.g., automated image inspection (AOI)).

[0005] In particular, with the increasing miniaturization and power saving of electronic devices, there is a growing need for higher integration and thinner semiconductor chips and printed circuit boards. To meet these needs, the adoption of FO-WLP (Fan-Out Wafer Level Packaging) and PLP (Panel Level Packaging) has been considered in recent years as next-generation packaging technologies. Furthermore, the adoption of coreless build-up methods is also being considered for FO-WLP and PLP. One such method is called the RDL-First (Redistribution Layer-First) method, in which a wiring layer and, if necessary, a build-up wiring layer are formed on the surface of a coreless support, the chip is mounted and sealed, and then the support is peeled off. For example, Patent Document 4 (Japanese Patent Application Publication No. 2015-35551) discloses a method for manufacturing a semiconductor device, which includes forming a metal delamination layer on the main surface of a support made of glass or a silicon wafer, forming an insulating resin layer thereon, forming a redistribution layer including a build-up layer thereon, mounting and sealing a semiconductor integrated circuit thereon, exposing the delamination layer by removing the support, exposing secondary mounting pads by removing the delamination layer, forming solder bumps on the surface of the secondary mounting pads, and secondary mounting.

[0006] Furthermore, wiring boards having multiple device areas for mounting semiconductor chips and the like are also known. In such wiring boards, multiple divided small boards can be obtained by cutting (trimming) the periphery of each device area. Therefore, a trimmable wiring board comprises, for example, multiple device areas where wiring patterns for mounting semiconductor chips exist, and peripheral areas surrounding these device areas that serve as waste space. In this respect, trimmable wiring boards have the problem that they are prone to cracking, warping, etc., due to the non-uniformity of the wiring pattern density between the device areas and the peripheral areas.

[0007] To address this problem, it is known that the balance of wiring pattern density can be adjusted by providing dummy wiring patterns in the peripheral areas that are to be discarded. For example, Patent Document 5 (JP 2016-72413 A) discloses a semiconductor device comprising a device region formed on a semiconductor substrate and a peripheral region formed to surround the device region, wherein a non-periodic pattern is formed in the peripheral region to surround the device region. Patent Document 6 (JP 2006-332344 A) discloses a semiconductor device comprising a dummy reinforcement pattern in a laminated structure of multiple interlayer insulating films at the periphery of a chip region, wherein the dummy reinforcement pattern is composed of dummy wiring and line-shaped dummy vias. Furthermore, Patent Document 7 (JP 2009-239149 A) ​​discloses a semiconductor wafer having a scribe line region and multiple element formation regions partitioned by the scribe line region, wherein a conductive pattern is provided in the scribe line region. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2005-101137 [Patent Document 2] International Publication No. 2017 / 150283 [Patent Document 3] International Publication No. 2017 / 150284 [Patent Document 4] Japanese Patent Publication No. 2015-35551 [Patent Document 5] Japanese Patent Publication No. 2016-72413 [Patent Document 6] Japanese Patent Publication No. 2006-332344 [Patent Document 7] Japanese Patent Publication No. 2009-239149 [Overview of the project]

[0009] Incidentally, when forming a wiring board (e.g., a redistribution layer) using a carrier-attached metal foil as shown in Patent Documents 2 and 3, a step is performed to peel the wiring board from the carrier. This step includes, for example, attaching a reinforcing sheet (second carrier) to the wiring board, trimming the wiring board, and peeling the trimmed wiring board and reinforcing sheet combination from the carrier. In this regard, when peeling the wiring board from the carrier, it may not be possible to peel the wiring board exactly where it was trimmed, and unintended cracks (such as splits or tears) may occur in the wiring board. Wiring boards in which such cracks have occurred are prone to defects such as dielectric breakdown and corrosion of the wiring portion as etching solution, desmear solution, various plating solutions or their cleaning solutions, or moisture in the air or condensation water derived therefrom enter through the cracks during the manufacturing process. On the other hand, from the viewpoint of improving product yield, it is also desirable to perform an electrical inspection on the device area before peeling the wiring board from the carrier.

[0010] The present inventors have now found that by interposing an insulating boundary region having a winding shape, on which a virtual straight line satisfying predetermined conditions can be drawn between the device region and the surrounding peripheral region of a wiring board to be trimmed, the mechanical strength, water resistance, moisture resistance, and product yield during and after trimming can be improved.

[0011] Therefore, the object of the present invention is to provide a wiring board that can improve mechanical strength, water resistance, moisture resistance, and product yield during and after trimming.

[0012] According to one aspect of the present invention, A device region in which a main wiring pattern composed of a metal layer is embedded in an insulating layer, A peripheral region surrounding the device area, in which a dummy wiring pattern consisting of a metal layer electrically independent of the main wiring pattern is embedded in an insulating layer, An insulating boundary region, which is interposed between the device region and the peripheral region and is composed of an insulating layer, and in which no metal layer exists, A wiring board comprising: When viewed in plan view, the insulating boundary region has a meandering shape such that a virtual straight line that alternately crosses a metal layer constituting the dummy wiring pattern and an insulating layer constituting the insulating boundary region can be drawn parallel to an inscribed line of at least one side of the outer edge of the device region. When viewed in plan view, the device region is completely separated from the insulating boundary region by the virtual straight line, and a wiring board is provided.

[0013] According to another aspect of the present invention, a multilayer wiring board including the wiring board is provided.

[0014] According to still another aspect of the present invention, A step of preparing the wiring board; A step of cutting the wiring board along the virtual straight line and removing the peripheral region; A wiring board trimming method including the above is provided.

Brief Description of Drawings

[0015] [Figure 1] It is a schematic top view conceptually showing an example of the wiring board of the present invention. [Figure 2A] It is an enlarged view of a portion surrounded by a dotted line in the wiring board of FIG. 1, showing an example of the shape of the insulating boundary region. [Figure 2B] Another example of the shape of the insulating boundary region is shown. [Figure 2C] Another example of the shape of the insulating boundary region is shown. [Figure 2D] Another example of the shape of the insulating boundary region is shown. [Figure 2E] Another example of the shape of the insulating boundary region is shown. [Figure 2F] Another example of the shape of the insulating boundary region is shown. [Figure 2G] Another example of the shape of the insulating boundary region is shown. [Figure 2H] Another example of the shape of the insulating boundary region is shown. [Figure 3A]This is a schematic cross-sectional flow diagram showing an example of the circuit board transfer process, corresponding to the first half of the process (steps (i) to (iii)). [Figure 3B] This is a schematic top view flowchart showing the process corresponding to Figure 3A. [Figure 4A] This flowchart shows a schematic cross-sectional view of an example of the circuit board transfer process, corresponding to the later steps (steps (iv) and (v)) following the steps shown in Figure 3A. [Figure 4B] This is a schematic top view flowchart showing the process corresponding to Figure 4A. [Figure 5] This is a schematic diagram showing an example of the shape of the insulating boundary region in a conventional wiring board. [Figure 6] This is a photograph of the surface of the wiring board fabricated in Example 1 after carrier delamination. [Figure 7] Figure 6 is an optical microscope image of the vicinity of the insulating boundary region in the wiring board. [Figure 8] This is an external view photograph of the substrate surface of the wiring board fabricated in Example 2, where delamination occurred in some of the individual pattern ends. [Figure 9] Figure 8 is an optical microscope image of the vicinity of the insulating boundary region in the wiring board. [Modes for carrying out the invention]

[0016] Wiring board and trimming method thereof Figure 1 conceptually illustrates the wiring board of the present invention, while Figure 2A shows an enlarged view of the area enclosed by the dotted line in Figure 1. As shown in Figure 1, the wiring board 10 of the present invention comprises a device region D, a peripheral region P, and an insulating boundary region B. In the device region D, a main wiring pattern composed of a metal layer is embedded in an insulating layer. The peripheral region P is the region surrounding the device region D. In the peripheral region P, a dummy wiring pattern composed of a metal layer electrically independent of the main wiring pattern is embedded in an insulating layer. The insulating boundary region B is interposed between the device region D and the peripheral region P and is composed of an insulating layer, but does not contain a metal layer. As shown in Figures 1 and 2A, the insulating boundary region B has a winding shape such that, when viewed from above, a virtual straight line L can be drawn alternately across the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region B, parallel to the internal line I of at least one side of the outer edge of the device region D. Furthermore, when viewed from above, the device region D is completely separated from the virtual line L by the insulating boundary region B. In this way, by interposing an insulating boundary region B having a curved shape that allows the predetermined virtual line L to be drawn between the device region D and the surrounding peripheral region P in the wiring board 10 to be trimmed, the mechanical strength, water resistance, moisture resistance, and product yield during and after trimming can be improved. It is preferable that the internal tangent line I and the virtual line L are geometrically parallel (perfectly parallel), but it is sufficient if they are substantially parallel (approximately parallel) within the scope of achieving the objectives of the present invention.

[0017] As described above, when forming a wiring board (e.g., a redistribution layer) using a carrier-attached metal foil as shown in Patent Documents 2 and 3, a step is performed to peel the wiring board from the carrier. Here, an example of the step of peeling the wiring board from the carrier is shown in Figures 3A to 4B. In this step, first, a wiring board 110 having a device region D, a peripheral region P, and an insulating boundary region B is formed on a carrier-attached metal foil 100 (e.g., having a carrier, a release layer, and a metal layer in this order) by a known method (e.g., the build-up method described above) (Figures 3A(i) and 3B(i)). Next, a reinforcing sheet 120 (second carrier) is laminated on the wiring board 110 via an adhesive layer or the like (Figures 3A(ii) and 3B(ii)). After that, a cutting tool T is used to make cuts that penetrate the reinforcing sheet 120 and the wiring board 110 (Figure 3A(iii)). At this point, by making an incision line C across the insulating boundary region B, the device region D of the wiring board 110 and the surrounding peripheral region P are separated (Figure 3B(iii)). Then, the separated wiring board 110 (device region D portion) and the reinforcing sheet 120 are peeled off from the carrier-attached metal foil 100 (Figures 4A(iv) and 4B(iv)). In this way, the trimmed wiring board 110 is transferred to the reinforcing sheet 120 (Figures 4A(v) and 4B(v)).

[0018] However, when conventional wiring boards are peeled off from the carrier, it is not possible to peel the wiring board exactly where it was trimmed, which can result in unintended cracks (such as splits or tears) in the wiring board. When such cracks occur in a wiring board, etching solution, desmear solution, various plating solutions or their cleaning solutions, or moisture from the air and condensation water derived therefrom can enter through the cracks during the manufacturing process, making it prone to defects such as dielectric breakdown and corrosion of the wiring. The inventors investigated the cause of this and found that there is a problem with the cutting point that separates the device area D and the surrounding area P. An example of a conventional wiring board is shown in Figure 5. As shown in Figure 5, the conventional wiring board 210 has a linear insulating boundary area B, which is composed of an insulating layer and does not have a metal layer, interposed between the device area D and the surrounding area P. Therefore, the cut line C that separates the device area D and the surrounding area P continuously crosses the insulating layer that constitutes the insulating boundary area B. As a result, it is believed that cracks occur in the wiring board 210 during trimming or carrier delamination due to the low-strength insulating layer constituting the insulating boundary region B. Furthermore, since the combination of metal and insulating material in the wiring board is generally fixed, it is difficult to change the type of insulating material constituting the insulating layer.

[0019] In contrast, the wiring board 10 of the present invention has a winding shape that allows for the drawing of a virtual straight line L that alternately crosses the metal layer constituting the dummy wiring pattern (in the surrounding region P) and the insulating layer constituting the insulating boundary region B within the insulating boundary region B. Therefore, when the wiring board 10 is cut along this virtual straight line L, the cut site will alternately contain insulating layers and metal layers made of a metal with higher strength than the insulating material constituting the insulating layer (in the length, width, and / or thickness directions). As a result, the mechanical strength of the wiring board 10 is greatly improved compared to a conventional wiring board 210 in which the insulating layer is continuously present at the cut site. Furthermore, when viewed from above, the device region D is completely separated from the virtual straight line L by the insulating boundary region B. In other words, even when the wiring board 10 is cut along the virtual straight line L, the device region D is surrounded by the insulating boundary region B. Therefore, the insulating boundary region B effectively prevents etching solutions, desmear solutions, various plating solutions or their cleaning solutions, or moisture from the air or condensation from it from entering the circuit in or near the device region D, thereby improving the water resistance and moisture resistance of the wiring board 10.

[0020] Therefore, it is preferable that the wiring board 10 be cut along a virtual straight line L. That is, according to a preferred embodiment of the present invention, a trimming method for a wiring board 10 is provided, which includes the steps of preparing the wiring board 10 and cutting the wiring board 10 along a virtual straight line L to remove the peripheral region P.

[0021] On the other hand, in order to improve the mechanical strength of the wiring board, it is conceivable to connect the main wiring pattern in the device area and the dummy wiring pattern in the peripheral area so that a high-strength metal layer exists at the cut points. However, in a wiring board with such a configuration, the device area and the peripheral area are not electrically independent, making it difficult to perform electrical inspection on individual device areas before trimming or carrier stripping. In contrast, in the wiring board 10 of the present invention, the main wiring pattern in the device area D and the dummy wiring pattern in the peripheral area P are separated by an insulating boundary area B and are electrically independent. Therefore, for example, electrical inspection can be performed on each device area D even before trimming or carrier stripping is performed on the wiring board 10. As a result, since defective areas in the wiring board 10 can be identified and understood before proceeding to subsequent processes, the process can be made more rational by omitting processing steps in subsequent processes on areas with defects or device areas. Furthermore, since defective products caused by defects in the wiring board 10 do not occur in subsequent processes such as chip bonding, it is possible to improve the final yield of package products, which have been becoming more high-performance and expensive in recent years.

[0022] Preferably, the insulating boundary region B has a winding shape such that, when viewed from above, it is possible to draw virtual straight lines L that alternately cross the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region B, parallel to the internal lines I of each side of the outer edge of the device region D. Preferably, when viewed from above, the device region D is completely separated from the above-mentioned virtual straight lines L across the insulating boundary region B. This further improves the mechanical strength, water resistance, and moisture resistance of the wiring board 10.

[0023] The winding shape of the insulating boundary region B is not limited to the shapes shown in Figures 1 and 2A, but can be any shape, including the shapes shown in Figures 2B to 2H. For example, the winding shape of the insulating boundary region B is preferably configured such that the outer edge shape of the peripheral region P in contact with the insulating boundary region B, and / or the outer edge shape of the device region D in contact with the insulating boundary region B, includes a comb shape (see, for example, Figure 2A), a wave shape consisting of curves (see, for example, Figure 2B), a triangle (see, for example, Figure 2C), a trapezoid (see, for example, Figures 2E and 2H), a spindle shape (see, for example, Figure 2D), a fastener shape (see, for example, Figures 2F and 2G), or a combination thereof, and more preferably includes a comb shape. By doing so, when the wiring board 10 is viewed from above, the boundary between the metal layer constituting the dummy wiring pattern or main wiring pattern and the insulating layer constituting the insulating boundary region B becomes an intricate shape, which makes it possible to further improve the mechanical strength of the wiring board 10 during and after trimming. Furthermore, the number of metal layers constituting the dummy wiring pattern traversed by the virtual straight line L, and the number of insulating layers constituting the insulating boundary region B, are preferably 1 to 3000 per millimeter with respect to the length of the virtual straight line L, and more preferably 4 to 1000 per millimeter.

[0024] From the same viewpoint as above, the winding shape of the insulating boundary region B is preferably a wavy pattern. This wavy pattern is preferably a sine wave (see, for example, Figure 2B), a sawtooth wave, a square wave (see, for example, Figure 2A), a trapezoidal wave (see, for example, Figures 2E and 2H), a triangular wave (see, for example, Figure 2C), or a combination thereof, and more preferably a square wave. The sine wave, sawtooth wave, square wave, trapezoidal wave, and triangular wave may be partially or entirely modified within the scope of achieving the objectives of the present invention. For example, the shapes of the insulating boundary region B shown in Figures 2D, 2F, and 2G are included in these wavy patterns as variations of the square wave or trapezoidal wave. Furthermore, while keeping the width of the insulating boundary region B constant may make design and manufacturing easier, at least a part of it may not be constant within the scope of achieving the objectives of the present invention.

[0025] The width of the insulating boundary region B (i.e., the distance between the device region D and the peripheral region P) is not particularly limited, but is typically 0.1 μm to 2000 μm, more typically 0.5 μm to 1000 μm, and even more preferably 1 μm to 250 μm. Furthermore, the width of the insulating boundary region B is preferably 0.02 to 250 times the thickness t of the wiring substrate, and more preferably 0.10 to 50 times.

[0026] Preferably, the coefficient of thermal expansion of the metal constituting the metal layer of the main wiring pattern in the wiring board 10 is 0.10 to 10 times, more preferably 0.20 to 5 times, even more preferably 0.30 to 3 times, and particularly preferably 0.50 to 2 times. Within this range, it is possible to effectively prevent moisture from entering from the interface between the device area D and the insulating boundary area B, thereby further improving the water resistance and moisture resistance of the wiring board 10.

[0027] The size of the wiring board 10 is not particularly limited. If the board shape is rectangular, it is preferably 1.0 mm square or larger and 150 cm square or smaller, more preferably 3 mm square or larger and 75 cm square or smaller. The number of device areas D on the wiring board 10 is not particularly limited, but is preferably 1 to 5000, more preferably 4 to 2000.

[0028] The wiring board 10 may be manufactured by any method. For example, a carrier-mounted metal foil having a release layer and a metal layer on a carrier can be prepared, and a wiring layer and an insulating layer can be laminated on this carrier-mounted metal foil using a known method to obtain a wiring board 10 having the predetermined device region D, peripheral region P, and insulating boundary region B. Therefore, the wiring board 10 may have a carrier and a release layer on the carrier, and the device region D, peripheral region P, and insulating boundary region B on the release layer. As described above, an electrical inspection can be performed on a wiring board 10 with such a configuration even before trimming or carrier peeling. Furthermore, it is possible to effectively suppress the occurrence of cracks in the wiring board 10 when trimming or carrier peeling is performed, and to effectively prevent desmear liquid, condensation water, or moisture in the air from entering the circuit of the device region D, and furthermore, to prevent short circuits and migrations caused by these.

[0029] The carrier may be composed of glass, ceramics, silicon, resin, or metal, but is preferably a silicon-containing substrate or a glass substrate. Any substrate containing Si as an element can be used as the silicon-containing substrate, such as SiO2 substrates, SiN substrates, Si single-crystal substrates, and Si polycrystalline substrates. More preferably, it is a glass carrier, a single-crystal silicon substrate, or a polycrystalline silicon substrate. When the carrier is a glass carrier, it has advantages such as surface flatness (coplanarity) favorable for microcircuit formation, chemical resistance in desmear and various plating processes during wiring manufacturing, and the ability to use chemical separation methods when peeling the carrier from the wiring substrate. Preferred examples of glass constituting the carrier include quartz glass, borosilicate glass, alkali-free glass, soda-lime glass, aluminosilicate glass, and combinations thereof, more preferably alkali-free glass, soda-lime glass, and combinations thereof, with alkali-free glass being particularly preferred. Alkali-free glass is a type of glass that is primarily composed of silicon dioxide, aluminum oxide, boron oxide, and alkaline earth metal oxides such as calcium oxide and barium oxide, and also contains boric acid, but is substantially free of alkali metals. This alkali-free glass has the advantage of minimizing glass warping in processes involving heating, as its coefficient of thermal expansion is low and stable in the range of 3 ppm / K to 5 ppm / K over a wide temperature range from 0°C to 350°C. The carrier thickness is preferably 100 μm to 2000 μm, more preferably 300 μm to 1800 μm, and even more preferably 400 μm to 1100 μm. When the carrier thickness is within this range, it is possible to achieve thinner wiring and reduced warping that occurs when mounting electronic components, while ensuring appropriate strength that does not hinder handling.

[0030] The surface of the carrier preferably has a maximum height Rz of less than 1.0 μm, more preferably between 0.001 μm and 0.5 μm, even more preferably between 0.001 μm and 0.1 μm, even more preferably between 0.001 μm and 0.08 μm, particularly preferably between 0.001 μm and 0.05 μm, and most preferably between 0.001 μm and 0.02 μm. The smaller the maximum height Rz of the carrier surface, the more desirable it is to obtain a low maximum height Rz at the outermost surface of the metal layer laminated on the carrier (i.e., the surface opposite to the release layer), which makes it suitable for forming highly miniaturized wiring patterns in printed wiring boards manufactured using the wiring board 10, with a line / space (L / S) of 13 μm or less / 13 μm or less (e.g., from 12 μm / 12 μm to 2 μm / 2 μm).

[0031] The release layer is a layer that enables or facilitates the release of carriers. The release layer may be removable by applying physical force, or by using a laser (laser lift-off, LLO). That is, the release layer may be composed of a resin whose interfacial adhesion strength decreases upon laser irradiation after curing, or it may be a layer of silicon or silicon carbide that is modified by laser irradiation. Furthermore, if the release layer can be removed by applying physical force without laser irradiation, it may be either an organic or inorganic release layer. Examples of organic components used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, and carboxylic acids. Examples of nitrogen-containing organic compounds include triazole compounds and imidazole compounds. On the other hand, examples of inorganic components used in the inorganic release layer include metal oxides or metal oxynitrides containing at least one of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, or carbon. Among these, the release layer is preferably a layer mainly containing carbon, from the viewpoint of ease of release and film formation, more preferably a layer mainly composed of carbon or hydrocarbons, and even more preferably a layer made of amorphous carbon, which is a hard carbon film. In this case, the carbon concentration of the release layer (i.e., the carbon-containing layer) measured by XPS is preferably 60 atomic% or more, more preferably 70 atomic% or more, even more preferably 80 atomic% or more, and particularly preferably 85 atomic% or more. The upper limit of the carbon concentration is not particularly limited and may be 100 atomic%, but 98 atomic% or less is practical. The release layer may contain unavoidable impurities (e.g., oxygen, carbon, hydrogen, etc., originating from the surrounding environment such as the atmosphere). In addition, metal atoms of types other than the metal contained in the release layer may be mixed into the release layer due to the film formation method of the layers to be laminated later. When a carbon-containing layer is used as the release layer, the interdiffusion and reactivity with carriers are small, and even when subjected to press processing at temperatures exceeding 300°C, a state in which carriers can be easily peeled off and removed can be maintained. It is preferable for the delamination layer to be formed by a gas-phase method such as sputtering, in terms of suppressing excessive impurities in the delamination layer and enabling continuous production of other layers.When a carbon-containing layer is used as the release layer, its thickness is preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. This thickness is determined by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.

[0032] Alternatively, the release layer may be a metal oxynitride-containing layer instead of such a carbon layer. The surface of the metal oxynitride-containing layer opposite to the carrier (i.e., the metal layer side) preferably contains at least one metal oxynitride selected from the group consisting of TaON, NiON, TiON, NiWON, and MoON. Furthermore, in order to ensure adhesion between the carrier and the metal layer, the carrier-side surface of the metal oxynitride-containing layer preferably contains at least one selected from the group consisting of Cu, Ti, Ta, Cr, Ni, Al, Mo, Zn, W, TiN, and TaN. This suppresses the number of foreign particles on the surface of the metal layer, improves circuit formation, and makes it possible to maintain stable release strength even after heating at high temperatures for a long time. The thickness of the metal oxynitride-containing layer is preferably 5 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 20 nm to 200 nm, and particularly preferably 30 nm to 100 nm. This thickness is determined by analyzing the layer cross-section using an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.

[0033] As long as the wiring board 10 includes a device region D, a peripheral region P, and an insulating boundary region B, it may include layers other than the carrier and the release layer, provided that the original function of the wiring board 10 is not impaired. Examples of such other layers include intermediate layers, anti-reflective layers (etching stopper layers), and ultra-thin copper layers (metal layers), as shown in Patent Document 2 (International Publication No. 2017 / 150283) and Patent Document 3 (International Publication No. 2017 / 150284).

[0034] multilayer wiring board The wiring board 10 of the present invention may be a multilayer wiring board in which wiring layers and insulating layers are layered. That is, according to a preferred embodiment of the present invention, a multilayer wiring board including the above-described wiring board 10 is provided. Such a multilayer wiring board can preferably be manufactured, for example, by alternately laminating wiring layers and insulating layers on the surface of a carrier-attached metal foil using the build-up method described above to form a build-up layer, and then peeling off the carrier-attached metal foil. In this case, it is preferable that the predetermined device region D, peripheral region P, and insulating boundary region B are composed of any or all of the multilayered wiring layers and insulating layers. [Examples]

[0035] The present invention will be further explained by the following examples.

[0036] Example 1 A metal foil with a carrier was prepared, in which a release layer (amorphous carbon layer) and a metal layer (copper layer) were deposited on the carrier by sputtering. A wiring layer and an insulating layer were laminated onto the surface of the copper layer of this metal foil with a carrier to fabricate a wiring board. The specific procedure is as follows.

[0037] (1) Preparation of metal foil with carrier A metal foil with a carrier was prepared by sputtering an amorphous carbon layer (6 nm thick) and a copper layer (300 nm thick) onto a glass sheet (material: soda-lime glass) measuring 350 mm x 350 mm with a thickness of 1.1 mm.

[0038] (2) Fabrication of the wiring board A wiring layer including a main wiring pattern and a dummy wiring pattern was formed by patterning the surface of the copper layer side of a carrier-attached metal foil. Specifically, first, a photosensitive dry film was attached to the surface of the copper layer side of the carrier-attached metal foil, and exposure and development were performed to form a photoresist layer with a predetermined pattern. Next, pattern electrolytic copper plating was performed on the exposed surface of the copper layer (i.e., the part not masked by the photoresist layer) to form an electrolytic copper plating layer, and then the photoresist layer was peeled off. In this way, the copper layer and the electrolytic copper plating layer remained in the shape of the main wiring pattern and dummy wiring pattern, while the copper layer in the parts where these wiring patterns were not to be formed was exposed. Subsequently, by removing the unnecessary parts of the exposed copper layer with an etching solution, a wiring layer was formed in which the main wiring pattern and the dummy wiring pattern were electrically independent of each other. Furthermore, an insulating resin material (photosensitive insulating material, AR-5100 manufactured by Showa Denko Materials Co., Ltd.) was laminated on the wiring layer side of the carrier-attached metal foil, and an insulating layer was formed by performing a heat curing treatment at 230°C for 60 minutes. In this way, a wiring board comprising a device region D, a peripheral region P, and a rectangular wave-shaped insulating boundary region B as shown in Figure 2A was fabricated.

[0039] Example 2 (comparison) As shown in Figure 5, the wiring board was fabricated in the same manner as in Example 1, except that the wiring layer and the insulating layer were formed so that the insulating boundary region B had a linear shape.

[0040] evaluation After peeling off the carriers from the wiring boards prepared in Examples 1 and 2, the condition of the wiring board surface on the side from which the carriers were removed was observed. The carriers were peeled off by laminating a reinforcing sheet (prepreg, FR-4 manufactured by Panasonic Corporation, 200 μm thick) onto the surface of the wiring board opposite to the carriers via an adhesive layer, and then manually peeling the carriers off the wiring board.

[0041] When the surface of the wiring board fabricated in Example 1 was photographed after carrier delamination, the image shown in Figure 6 was obtained. Furthermore, when the area around the insulating boundary region B of the wiring board of Example 1 after carrier delamination was observed with an optical microscope (60x magnification), the image shown in Figure 7 was obtained. Figure 7 also shows the position of the cutting line C for cutting the wiring board. As shown in Figures 6 and 7, no cracks or tears were observed on the surface of the wiring board fabricated in Example 1 after carrier delamination. In addition, no cracks or tears were observed on the surface of the wiring board even after cutting the wiring board along the cutting line C.

[0042] On the other hand, when the surface of the wiring board fabricated in Example 2, where delamination occurred at the pattern boundaries, was photographed, the image shown in Figure 8 was obtained. Furthermore, when the area around the insulating boundary region B of the wiring board of Example 2 after carrier delamination was observed with an optical microscope (60x magnification), the image shown in Figure 9 was obtained. Figure 9 also shows the position of the cutting line C for cutting the wiring board. As shown in Figures 8 and 9, linear cracks were confirmed to be present on the surface of the wiring board fabricated in Example 2 after carrier delamination.

[0043] Based on these results, the wiring board with a curved (rectangular wave) insulating boundary region fabricated in Example 1 was stronger and less prone to cracking than the wiring board with a straight insulating boundary region fabricated in Example 2.

Claims

1. A device region in which a main wiring pattern composed of a metal layer is embedded in an insulating layer, A peripheral region surrounding the device area, in which a dummy wiring pattern consisting of a metal layer electrically independent of the main wiring pattern is embedded in an insulating layer, An insulating boundary region, which is interposed between the device region and the peripheral region and is composed of an insulating layer, and in which no metal layer exists, A wiring board equipped with, The insulating boundary region has a winding shape such that, when viewed from above, it is possible to draw a virtual straight line parallel to the intrinsic line of at least one side of the outer edge of the device region, alternately crossing the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region. When viewed from above, the device region is completely separated from the virtual line by the insulating boundary region. A wiring board configured such that it is cut along the virtual straight line.

2. The wiring board according to claim 1, wherein, when viewed from above, the insulating boundary region has a winding shape such that, for all sides of the outer edge of the device region, it is possible to draw virtual straight lines that alternately cross the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region, parallel to the intrinsic lines of each of those sides, and when viewed from above, the device region is completely separated from the virtual straight lines for all sides by the insulating boundary region.

3. The wiring board according to claim 1 or 2, wherein the winding shape is configured such that the outer edge shape of the peripheral region in contact with the insulating boundary region, and / or the outer edge shape of the device region in contact with the insulating boundary region, includes at least one selected from the group consisting of a comb shape, a curved wave shape, a triangle, a trapezoid, a spindle shape, and a fastener shape.

4. The wiring board according to any one of claims 1 to 3, wherein the aforementioned curved shape includes a wavy pattern.

5. The wiring board according to claim 4, wherein the wave pattern includes at least one shape selected from the group consisting of sine waves, sawtooth waves, square waves, trapezoidal waves, and triangular waves.

6. The wiring board according to any one of claims 1 to 5, wherein the coefficient of linear expansion of the metal constituting the metal layer of the main wiring pattern is 0.10 times or more and 10 times or less the coefficient of linear expansion of the resin constituting the insulating layer of the insulating boundary region.

7. The wiring board according to any one of claims 1 to 6, wherein the wiring board has a carrier and a release layer on the carrier, and the release layer comprises the device region, the peripheral region, and the insulating boundary region.

8. The wiring board according to claim 7, wherein the carrier is a glass carrier.

9. A multilayer wiring board comprising a wiring board according to any one of claims 1 to 8.

10. A step of preparing a wiring board according to any one of claims 1 to 8, The steps include cutting the wiring board along the virtual straight line and removing the surrounding area, A method for trimming a wiring board, including [specific details omitted].

Images