A system and method for tuning to reduce reflected power in multiple conditions.

Abstract

To provide a system and a method for tuning to reduce reflected power in multiple states.SOLUTION: A method includes determining values of one or more parameters of an impedance matching circuit such that reflected power is reduced for multiple states, and such reduction in reflected power extending the life of a radio frequency generator connected to the impedance matching circuit while processing the substrate using the plurality of conditions.SELECTED DRAWING: Figure 5A

Description

Technical Field

[0001] This embodiment relates to a system and method for tuning to reduce reflected power in multiple states.

Background Art

[0002] Generally, a plasma tool includes a high-frequency generator, an impedance matching circuit network, and a plasma chamber. The high-frequency generator supplies power to the plasma chamber via the impedance matching circuit network. When power is supplied, one or more gases are also provided to the plasma chamber to generate plasma therein. The plasma is used for various cleaning operations and other operations performed on the wafer within the plasma chamber.

[0003] However, when power is supplied, the power of the plasma is reflected back toward the RF generator. This reflected power generates a standing wave on the transmission line between the source and the load, and the standing wave can lead to damage to the output drive of the RF generator.

[0004] The embodiments described in this disclosure have arisen from such a background.

Summary of the Invention

[0005] Embodiments of this disclosure provide a system and method for tuning to reduce reflected power in multiple states. It should be understood that this embodiment can be implemented in various forms, such as a process, an apparatus, a system, a device, or a method recorded on a computer-readable medium. Some embodiments are described below.

[0006] During semiconductor plasma processing, the applied radio frequency (RF) power is pulsed at frequencies between 1 Hz and 50 kHz. A tuned matching network is used to couple the RF power to the plasma, ensuring efficient coupling between the RF generator and the plasma. During continuous wave (CW) or single-level pulsation, the matching network is fixed. However, in some examples, two or more levels of pulsation are used, in which case two or more matching network positions, e.g., capacitor values, inductor values, etc., are used. The matching network uses variable reactive components, e.g., capacitors and inductors. These variable reactive components have mechanical parts, which move slower than in multi-level pulsation. The slow response of the mechanical parts makes it difficult to keep up with the multiple power levels of multi-level pulsation. This can be partially mitigated by using frequency tuning between the multiple power levels. However, frequency tuning alone cannot accommodate significantly different power levels. The method and system describe how to optimize the matching network position to maximize matching efficiency across processing for multi-level pulsation. Matching efficiency is improved, and the power reflected towards the RF generator is reduced. The reduction in average reflected RF power towards the RF generator allows for a wider working space.

[0007] In some embodiments, methods are described for tuning to reduce reflected power in multiple states. The method comprises supplying power by an RF generator during a first state of a digital pulse signal to a plasma chamber via an impedance matching circuit. The method further comprises measuring the amount of power reflected to the output of the RF generator during the first state. The method comprises supplying power by an RF generator during a second state of a digital pulse signal to a plasma chamber via an impedance matching circuit. The method further comprises measuring the amount of power reflected to the output of the RF generator during the second state. The method comprises controlling the parameters of the impedance matching circuit to reduce the amount of power measured during the first state to a minimum value and to reduce the amount of power measured during the second state to a minimum value.

[0008] A system for tuning to reduce reflected power in multiple states in various embodiments is described. The system comprises an RF generator configured to supply power during a first state of a digital pulse signal. The system further comprises an impedance matching circuit connected to the RF generator via an RF cable, and a plasma chamber connected to the impedance matching circuit via an RF transmission line. The system comprises a sensor connected to the output of the RF generator. The sensor is configured to measure the amount of power reflected to the output of the RF generator during the first state. The RF generator is configured to supply power to the plasma chamber during a second state of a digital pulse signal via the impedance matching circuit. The sensor is configured to measure the amount of power reflected to the output of the RF generator during the second state. The system comprises a processor connected to the impedance matching circuit to control the parameters of the impedance matching circuit. The parameters are controlled to reduce the amount of power measured during the first state to a minimum and the amount of power measured during the second state to a minimum.

[0009] In various embodiments, a non-temporary computer-readable medium for storing a program causing a computer to execute a method is described. The method comprises the step of supplying power by an RF generator during a first state of a digital pulse signal to a plasma chamber via an impedance matching circuit. The method further comprises the step of receiving a measurement of the amount of power reflected to the output of the RF generator during the first state. The method comprises the step of supplying power by an RF generator during a second state of a digital pulse signal to a plasma chamber via an impedance matching circuit. The method comprises the step of receiving a measurement of the amount of power reflected to the output of the RF generator during the second state. The method comprises the step of controlling the parameters of the impedance matching circuit to reduce the amount of power measured during the first state to a minimum and the amount of power measured during the second state to a minimum.

[0010] Some advantages of the systems and methods described herein for tuning to reduce reflected power in multiple states. For example, if the series circuit of an impedance matching circuit has a value A and / or the shunt circuit of an impedance matching circuit has a value B, the power reflected toward the RF generator is reduced for multiple states S0, S1, S2, S3, etc., compared to the power reflected toward the RF generator for any one state among S0, S1, S2, S3, etc., where the series circuit has a value C and / or the shunt circuit has a value D. Such reduction in reflected power for multiple states extends the lifespan of the RF generator toward which the power is reflected. Furthermore, multiple states can be used to perform various operations on a substrate. For example, during one of the multiple states, a material (such as an oxide) is deposited onto the substrate, and during another of the multiple states, the substrate or material is etched. Another example is that during one of the multiple states, a deposition operation is performed on the substrate, and during another of the multiple states, the substrate is cleaned. As yet another example, during one of multiple states, a deposition operation is performed on the substrate; during another of multiple states, the substrate is cleaned; and during yet another of multiple states, an etching operation is performed on the substrate. If the impedance matching circuit has values ​​A and B and the power is reduced in multiple states, various operations are performed on the substrate while protecting the components of the RF generator.

[0011] Furthermore, reducing reflected power for states S0, S1, S2, S3, etc., improves the efficiency of the impedance matching circuit. The impedance matching circuit allows a higher power to be supplied to the plasma chamber when the series circuit of the impedance matching circuit has a value of A, and / or the shunt circuit of the impedance matching circuit has a value of B. A higher power supply is important for low-amplitude RF signals supplied by the RF generator.

[0012] Another embodiment will become apparent from the following detailed description, which will be based on the attached drawings. [Brief explanation of the drawing]

[0013] The embodiments can be best understood by referring to the following description made in relation to the attached drawings.

[0014] [Figure 1A] A diagram illustrating one embodiment of a system for determining the parameters of a series circuit and a shunt circuit to reduce the power reflected toward an x ​​megahertz (MHz) radio frequency (RF) generator in multiple states S(n-N) to S(n).

[0015] [Figure 1B] A diagram illustrating one embodiment of the system for explaining the reduction of reflected power to the xMHz RF generator and the reduction of reflected power to the yMHz RF generator in states S(nN)~S(n).

[0016] [Figure 1C] A diagram illustrating one embodiment of the system for explaining the reduction of reflected power to the xMHz RF generator, the yMHz RF generator, and the zMHz RF generator in states S(nN)~S(n).

[0017] [Figure 2A] A diagram illustrating two states of an RF signal: a graph of a digital pulse signal and a graph of an RF signal supplied by an RF generator.

[0018] [Figure 2B] A figure showing one embodiment of a graph of an RF signal having three states.

[0019] [Figure 2C] A figure showing one embodiment of a graph of an RF signal having four states.

[0020] [Figure 3A] A diagram illustrating one embodiment of a system for explaining the control of series and shunt circuits of impedance matching circuits in states S(nN)~S(n).

[0021] [Figure 3B] A diagram of an embodiment of a system for explaining the control of a series circuit and a shunt circuit in states S(n-N) to S(n).

[0022] [Figure 3C] A diagram of an embodiment of a system for explaining an impedance matching circuit having any number of series circuits and any number of shunt circuits.

[0023] [Figure 3D] A diagram of an embodiment of a system for explaining an impedance matching circuit that is an L network.

[0024] [Figure 3E] A diagram of an embodiment of a system for explaining an impedance matching circuit that is a Π network.

[0025] [Figure 3F] A diagram of an embodiment of a system for explaining an impedance matching circuit that is a Π network including two L networks.

[0026] [Figure 4] A diagram of an embodiment of a method for explaining the determination of the value of one or more parameters of an impedance matching circuit in which the power reflected toward the RF generator is reduced with respect to states S(n-N) to S(n).

[0027] [Figure 5A] A diagram for explaining a method of determining the capacitance Cseries of the series circuit of an impedance matching circuit and the capacitance Cshunt of the shunt circuit of the impedance matching circuit in order to reduce the reflected power at the output of the RF generator with respect to states S(n-N) to S(n).

[0028] [Figure 5B]A diagram illustrating one embodiment of a graph illustrating the technical advantages of applying a method to tune the system to reduce reflected power in states S(nN)~S(n).

[0029] [Figure 6] A diagram illustrating one embodiment of a machine learning network for determining the values ​​of one or more parameters that result in the minimum value of a variable for a given state S(nN)~S(n). [Modes for carrying out the invention]

[0030] The following embodiments describe tuning systems and methods for reducing reflected power under multiple conditions. It is evident that these embodiments can be implemented without some or all of these specific details. Furthermore, detailed descriptions of well-known processing operations have been omitted to avoid unnecessarily obscuring these embodiments.

[0031] Figure 1A is a diagram of one embodiment of system 100 illustrating the determination of the parameters of a series circuit 102 and a shunt circuit 104 for reducing power reflected toward an x ​​megahertz (MHz) radio frequency (RF) generator. System 100 consists of an x ​​megahertz RF generator, an impedance matching circuit (IMC) 106, a plasma chamber 108, and a host computer. 111 It comprises motor M1, motor M2, driver (DRVR) D1, and driver D2.

[0032] An example of an x ​​megahertz RF generator is a 2 MHz RF generator. The impedance matching circuit 106 comprises one or more series circuits, e.g., series circuit 102, and one or more shunt circuits, e.g., shunt circuit 104. The output of each shunt circuit is connected to ground, e.g., zero potential, non-zero reference potential, etc. Each shunt circuit or each series circuit comprises one or more electrical components, e.g., one or more capacitors, or one or more resistors, or one or more inductors, or a combination of one or more capacitors and one or more resistors, or a combination of one or more resistors and one or more inductors, or a combination of one or more capacitors, one or more resistors, and one or more inductors. Some of the one or more electrical components are connected to each other in series or in parallel. One end of the series circuit 102 is connected to the input 132 of the impedance matching circuit 106, and the other end of the series circuit 102 is connected to the output 134 of the impedance matching circuit 106. Furthermore, one end of the shunt circuit 104 is connected to both the series circuit 102 and the output 134 of the impedance matching circuit 106, and the other end of the shunt circuit 104 is connected to ground.

[0033] The plasma chamber 108 comprises a chuck 110 (for example, an electrostatic chuck (ESC) on which a substrate 112 is placed), an upper electrode 114, and other components (not shown), such as an upper dielectric ring surrounding the upper electrode 114, an upper electrode extension surrounding the upper dielectric ring, a lower dielectric ring surrounding the lower electrode of the chuck 110, a lower electrode extension surrounding the lower dielectric ring, an upper plasma exclusion zone (PEZ) ring, a lower PEZ ring, and the like. An example of the substrate 112 is a wafer on which an integrated circuit has been processed or is to be processed. The upper electrode 114 and the chuck 110 are each made of a metal, such as aluminum, an aluminum alloy, copper, a combination of copper and aluminum, etc.

[0034] host computer 111Examples include desktop computers, laptop computers, tablets, smartphones, etc. Host computer 111 The system comprises one or more processors, for example, processor 116, and one or more memory devices, for example, memory device 118. The processors used herein are application-specific integrated circuits (ASICs), programmable logic devices, microprocessors, or central processing units (CPUs). Furthermore, the memory devices used herein are random-access memory (RAM), read-only memory (ROM), or a combination of RAM and ROM. An example of a motor described herein includes an electromachine that converts electrical energy into mechanical energy. For example, the motor comprises a rotor and a stator. The rotor rotates when current is supplied to the windings of the stator to convert electrical energy into mechanical energy. An example of a driver described herein includes one or more transistors that generate a current signal upon receiving a control signal from processor 116.

[0035] The x megahertz RF generator is connected to an impedance matching circuit 106 via an RF cable 126. Furthermore, the impedance matching circuit 106 is connected to a chuck 110 via an RF transmission line 128. The RF transmission line 128 is an RF cylinder, for example, a tunnel. Inside the cavity of the RF cylinder are an insulator and an RF rod. The RF rod is surrounded by the insulator, which is surrounded by the RF cylinder.

[0036] The x megahertz RF generator comprises a control system 120, a sensor 122, and an RF power supply 124. Examples of the control system described herein include one or more power controllers, one or more automatic frequency controllers (AFTs), or a combination of one or more power controllers and one or more automatic frequency controllers. The control system further comprises a digital signal processor (DSP) connected to one or more power controllers and one or more automatic frequency controllers. Examples of sensors described herein include power sensors or complex voltage and current sensors. Examples of RF power supplies described herein include a driver and an RF oscillator connected to each other. Upon receiving a current signal from the driver, the RF oscillator generates a high-frequency oscillating signal (e.g., a sinusoidal RF signal).

[0037] The sensors described herein are connected to the processor 116 via data cables, such as serial transfer cables, parallel transfer cables, or Universal Serial Bus (USB) cables. Similarly, the control systems described herein (e.g., DSPs of the control systems) are connected to the processor 116 via data cables. The motors described herein are connected to a series circuit or a shunt circuit via one or more connection mechanisms, such as one or more rods, a combination of one or more rods and one or more gears.

[0038] The processor 116 generates a digital pulse signal 130 and provides the digital pulse signal 130 to the control system 120. The digital pulse signal 130 has two or more states (for example, state S(nN) ~ state S(n)), where n is an integer greater than or equal to 1, N is also an integer greater than or equal to 1, and n is greater than N. For example, if S(n) is S2, then S(nN) is S1. Another example is if S(n) is S3, then S(nN) is S1, and there is an intermediate state S2 between the two states S1 and S3.

[0039] The control system 120, for example, a DSP, receives the digital pulse signal 130 and determines whether the digital pulse signal 130 is in state S(nN) or state S(n) based on the logic level of the digital pulse signal 130. For example, state S(nN) has logic level 0, and state S(n) has logic level 1. Another example is that state S0 has logic level L1, state S1 has logic level L2, state S2 has logic level L3, and state S3 has logic level L4. Logic level L4 is greater than logic level L3, logic level L3 is greater than logic level L2, and logic level L2 is greater than logic level L1.

[0040] When the control system 120 determines that the state of the digital pulse signal 130 is S(nN), it identifies the power level and frequency level for state S(nN) and provides these power levels and frequency levels to the RF power supply 124. For example, when the controller for state S(nN) in the power controller receives an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(nN), it identifies the power level for state S(nN) and provides this power level to the RF power supply 124. Furthermore, in this example, when the tuner for state S(nN) in the automatic frequency tuner receives an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(nN), it identifies the frequency level for state S(nN) and provides this frequency level to the RF power supply 124. As an example, the power level and frequency level for state S(nN) are received by the control system 120 from the processor 116. Upon receiving the power level and frequency level for state S(nN), the RF power supply 124 generates an RF signal having the power level and frequency level for state S(nN) and supplies the RF signal for state S(nN) to the impedance matching circuit 106 via the output 136 and RF cable 126. Output 136 is the output of the xMHz RF generator.

[0041] Similarly, when the state of the digital pulse signal 130 is determined to be S(n), the control system 120 identifies the power level and frequency level for state S(n) and provides these power levels and frequency levels to the RF power supply 124. For example, when the controller for state S(n) in the power controller receives an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(n), it identifies the power level for state S(n) and provides this power level to the RF power supply 124. Furthermore, in this example, when the tuner for state S(n) in the automatic frequency tuner receives an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(n), it identifies the frequency level for state S(n) and provides this frequency level to the RF power supply 124. As an example, the power level and frequency level for state S(n) are received by the control system 120 from the processor 116. Upon receiving the power level and frequency level for state S(n), the RF power supply 124 generates an RF signal having the power level and frequency level for state S(n) and transmits the RF signal for state S(n) to the impedance matching circuit 106 via the RF cable 126.

[0042] When an RF signal for state S(nN) is received by the impedance matching circuit 106 from the xMHz RF generator, the impedance matching circuit 106 matches the impedance of a load connected to the output 134 of the impedance matching circuit 106, such as the RF transmission line 128 and the plasma chamber 108, with the impedance of a source connected to the input 132 of the impedance matching circuit 106, such as the RF cable 126 and the x megahertz RF generator. The impedance matching circuit 106 matches the impedances to generate a modulated RF signal for state S(nN) that is provided from the impedance matching circuit 106 to the chuck 110 via the output 134 and the RF transmission line 128.

[0043] Similarly, when the RF signal for state S(n) is received by the impedance matching circuit 106 from the xMHz RF generator, the impedance matching circuit 106 matches the impedance of the load connected to the output 134 of the impedance matching circuit 106 with the impedance of the source connected to the input 132 of the impedance matching circuit 106. The impedance matching circuit 106 matches the impedances to generate a modulated RF signal for state S(n) that is provided from the impedance matching circuit 106 to the chuck 110 via the RF transmission line 128.

[0044] When a modulated RF signal is supplied to the chuck 110, one or more processing gases for processing the substrate 112 are supplied to the plasma chamber 108. Examples of processing gases include oxygen-containing gases and fluorine-containing gases. Examples of fluorine-containing gases include tetrafluoromethane (CF4), sulfur hexafluoride (SF6), and hexafluoroethane (C2F6). When the modulated RF signal is supplied to the chuck 110 and one or more processing gases are supplied to the plasma chamber 108, for example, through one or more holes in the upper electrode 114, the plasma is ignited in the plasma chamber 108 and used to process the substrate 112. Examples of processing the substrate 112 include etching the substrate 112, depositing materials onto the substrate 112, such as oxide layers, metal layers, or copper layers, sputtering the substrate 112, and cleaning the substrate 112, for fabricating one or more integrated circuit chips on the substrate 112.

[0045] During state S(nN), sensor 122 connected to the output 136 of the xMHz RF generator detects the values ​​of variables such as complex voltage and current, complex power, and complex reflected power. Reflected power is the power reflected from the plasma of the plasma chamber 108 towards the output 136 of the xMHz RF generator via the RF transmission line 128, impedance matching circuit 106, and RF cable 126. Similarly, during state S(n), sensor 122 detects the values ​​of variables.

[0046] The values ​​of the variables detected during state S(nN)~S(n) (for example, multiple occurrences of state S(nN)~S(n), state S(nN)) and multiple cycles of S(n), multiple occurrences of state S(nN) and S(n), etc.) are continuously provided from sensor 122 to processor 116 via data cable. The processor 116 determines the values ​​of one or more parameters of one or more electrical components of impedance matching circuit 106 from the variables detected during state S(nN)~S(n), compared with reflected power that is reduced for one of the states S(nN)~S(n) but not for the other states of state S(nN)~S(n), until the reflected power is reduced simultaneously for state S(nN)~S(n). For example, the values ​​of one or more parameters are determined such that the amount of power reflected to the output 136 for all states S(nN)~S(n) is less than the amount of power reflected to the output 136 for any one state of states S(nN)~S(n). To elaborate further, if the capacitance value of the series circuit 102 is C1 and the capacitance value of the shunt circuit 104 is C2, then the amount of power reflected towards the output 136 during state S1 is Pr1. However, if the same values ​​of C1 and C2 are used for state S2, then the amount of power reflected towards the output 136 during state S2 is Pr2, which is substantially larger than Pr1. The same values ​​of C1 and C2 are used due to physical limitations of one or more electrical components, such as capacitors and inductors, whose values ​​cannot be changed as quickly as the changes in states S(nN)~S(n). These components are components of the impedance matching circuit 106. If the values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 106, for example, the value C3 of the parameter of the series circuit 102 and the value C4 of the parameter of the shunt circuit 104, are determined from the variables detected during state S(nN)~S(n) so that the reflected power is simultaneously reduced for state S(nN)~S(n), then the reflected power is the power of quantity Pr3. The value Pr3 is less than the value Pr2 but greater than the value Pr1. In some embodiments, the value Pr3 is less than or equal to the value Pr1. Examples of parameters include inductance and capacitance.

[0047] As another example, if the capacitance of the series circuit 102 is C1 and the capacitance of the shunt circuit 104 is C2, the amount of power reflected towards the output 136 during state S1 is Pr1. The value Pr1 is the minimum value for state S1, which will be detailed later. Furthermore, if the capacitance of the series circuit 102 is C5 and the capacitance of the shunt circuit 104 is C6, the amount of power reflected towards the output 136 during state S2 is Pr4. The value Pr4 is the minimum value for state S2, which will be detailed later. For states S1 and S2, the average of values ​​C1 and C5 is used as the capacitance for the series circuit 102. Furthermore, for states S1 and S2, the average of values ​​C2 and C6 is used. Shunt circuit 104 It is used as capacitance for the following: For the average of values ​​C1 and C5, and the average of values ​​C2 and C6, the power reflected toward the xMHz RF generator is reduced for states S1 and S2.

[0048] As yet another example, if the values ​​of one or more parameters of the impedance matching circuit 106 (e.g., the parameter value C3 of the series circuit 102 and the parameter value C4 of the shunt circuit 104) are determined from variables detected during states S(nN) to S(n) so that the reflected power is simultaneously reduced for states S(nN) to S(n), then the reflected power is a power of quantity Pr3 for state S(nN) and a power of quantity Pr4 for state S(n). The value Pr3 is the minimum value of the reflected power for state S(nN) among the values ​​of the reflected power for state S(nN). Multiple values ​​of the reflected power for state S(nN) are achieved when the frequency of the xMHz RF generator and / or the power of the RF signal supplied by the xMHz RF generator are changed during state S(nN). The value Pr4 is the minimum value of the reflected power for state S(n) among the values ​​of the reflected power for state S(n). Multiple values ​​of reflected power for state S(n) are achieved when the frequency of the xMHz RF generator and / or the power of the RF signal supplied by the xMHz RF generator are changed during state S(n). In various embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n). In some embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n), and both of these minimums are less than a predetermined level of reflected power. In some embodiments, the terms predetermined level and predetermined limit are used interchangeably herein. Value Pr2 is greater than the predetermined level, and value Pr1 is less than the predetermined level.

[0049] During state S(nN)~S(n), processor 116 transmits a control signal to driver D1 indicating the parameter value for state S(nN)~S(n), and continues transmitting until the reflected power decreases by output 136 for state S(nN)~S(n). Upon receiving the control signal, motor M1 rotates to change the parameter value of the series circuit 102 via one or more connection mechanisms that connect motor M1 to the series circuit 102. Similarly, during state S(nN)~S(n), processor 116 transmits a control signal to driver D2 indicating the parameter value for state S(nN)~S(n), and continues transmitting until the reflected power decreases by output 136 for state S(nN)~S(n). Upon receiving the control signal, motor M2 rotates to change the parameter value of the shunt circuit 104 via one or more connection mechanisms that connect motor M2 to the shunt circuit 104.

[0050] Reducing reflected power at output 136 extends the lifespan of the xMHz RF generator. Reflected power can cause damage to components of the xMHz RF generator, such as the control system 120 and the RF power supply 124. Reducing reflected power at output 136 from state S(nN) to S(n) reduces the likelihood of damage to the components of the xMHz RF generator, thereby extending the lifespan of the components.

[0051] In some embodiments, a y-megahertz RF generator or a z-megahertz RF generator is used instead of an x-megahertz RF generator. An example of a y-megahertz RF generator is a 27MHz RF generator, and an example of a z-megahertz RF generator is a 60MHz RF generator. In various embodiments, an akHz RF generator, such as a 400kHz RF generator, is used instead of an x-megahertz RF generator.

[0052] In various embodiments, instead of the digital pulse signal 130 being generated by the processor 116, a digital clock source is used to generate the digital pulse signal 130. The digital clock source is a host computer 111 It is placed inside or outside.

[0053] In some embodiments where the digital pulse signal 130 has more than two states, multiple clock sources are used to generate the digital pulse signal 130. For example, to generate a digital pulse signal 130 with more than two states, clock signals from multiple clock sources are summed by, for example, an adder, a processor 116, etc. The clock signals are out of phase with respect to each other.

[0054] In various embodiments, the control signal is transmitted to the series circuit 102 for control until the reflected power is reduced to output 136 for states S(nN)~S(n), but not to the shunt circuit 104.

[0055] In some embodiments, the sensor described herein is connected to the output of an RF generator and is located outside the RF generator.

[0056] In some embodiments, the terms minuma and minimum are used interchangeably herein.

[0057] Figure 1B is a diagram of one embodiment of System 150 to illustrate the reduction of reflected power to the xMHz RF generator and yMHz RF generator for states S(nN)~S(n). System 150 consists of an xMHz RF generator, a yMHz RF generator, and a host computer. 111 The system comprises an impedance matching circuit 152, a plasma chamber 108, motors M1 and M2, drivers D1 and D2, motor M3, motor M4, driver D3, and driver D4. The impedance matching circuit 152 includes a series circuit 166 and a shunt circuit 168 connected to each other. The impedance matching circuit 152 also includes a series circuit 102 and a shunt circuit 104.

[0058] The output 158 ​​of the yMHz RF generator is connected to the input 160 of the impedance matching circuit 152 via the RF cable 162. The yMHz RF generator is part of the control system 153 The system includes an RF power supply 154 and a sensor 156. The sensor 156 is connected to the output 158 ​​of the yMHz RF generator. Furthermore, the sensor 156 is connected to a processor 116 via a data cable, and the processor 116 controls the control system via the data cable. 153 Connected.

[0059] The processor 116 is connected to the driver D3, which is connected to the motor M3. The motor M3 is connected to the series circuit 166 via one or more connection mechanisms. Furthermore, the processor 116 is connected to the driver D4, which is connected to the motor M4. The motor M4 is connected to the shunt circuit 168 via one or more connection mechanisms.

[0060] One end of the series circuit 166 is connected to the input 160, and the other end of the series circuit 166 is connected to the output 134. Furthermore, one end of the shunt circuit 168 is connected to the series circuit 166 and the output 134 of the impedance matching circuit 152, and the other end of the shunt circuit 168 is connected to ground.

[0061] The processor 116 controls the yMHz RF generator via a data cable. 153 A digital pulse signal 130 is transmitted to the control system. Upon receiving the digital pulse signal 130, the control system 153The control system 120 of the xMHz RF generator provides the power level and frequency level for state S(nN) to the RF power supply 124 of the xMHz RF generator in the manner described above. The RF power supply 154 provides the power level and frequency level for state S(nN) to the RF power supply 154 in the manner described above. The RF power supply 154 generates an RF signal having the power level and frequency level for state S(nN) in the manner that the RF power supply 124 of the xMHz RF generator generates an RF signal having the power level and frequency level for state S(nN). The RF power supply 154 supplies the RF signal to the input 160 of the impedance matching circuit 152 via the RF cable 162.

[0062] Similarly, when the digital pulse signal 130 is received, the control system 153 In the manner described above, the control system 120 of the xMHz RF generator provides the power level and frequency level for state S(n) to the RF power supply 124 of the xMHz RF generator, and provides the power level and frequency level for state S(n) to the RF power supply 154. The RF power supply 154 generates an RF signal having the power level and frequency level for state S(n) in the manner that the RF power supply 124 of the xMHz RF generator generates an RF signal having the power level and frequency level for state S(nN). The RF power supply 154 supplies the RF signal to the input 160 of the impedance matching circuit 152 via the RF cable 162.

[0063] In addition to the RF signal for state S(nN) from the xMHz RF generator, when the RF signal for state S(nN) is received by the impedance matching circuit 152 from the yMHz RF generator, the impedance matching circuit 152 matches the impedance of the load connected to the output 134 of the impedance matching circuit 152, such as the RF transmission line 128 and the plasma chamber 108, with the sources connected to the inputs 132 and 160 of the impedance matching circuit 152, such as the RF cable 126, the x megahertz RF generator, the RF cable 162, and the yMHz RF generator. The impedance matching circuit 152 matches the impedance and, furthermore, by combining, for example, summing, the RF signals transmitted through the branch circuits 165 and 170 of the impedance matching circuit 152 during state S(nN), generates a modulated RF signal for state S(nN) that is provided from the impedance matching circuit 152 to the chuck 110 via the output 134 and the RF transmission line 128. Circuit 165 includes a series circuit 102 and a shunt circuit 104.

[0064] Similarly, when an RF signal for state S(n) is received from the yMHz RF generator by the impedance matching circuit 152, in addition to the RF signal for state S(n) from the xMHz RF generator, the impedance matching circuit 152 matches the impedance of the load connected to the output 134 of the impedance matching circuit 152 with the impedance of the source connected to the inputs 132 and 160 of the impedance matching circuit 152. The impedance matching circuit 152 matches the impedances and, furthermore, by combining (e.g., summing) the RF signals transmitted through the branch circuits 165 and 170 of the impedance matching circuit 152 during state S(n), generates a modulated RF signal for state S(n) that is provided from the impedance matching circuit 152 to the chuck 110 via the output 134 and RF transmission line 128. The substrate 112 is processed when the modulated RF signal is received from the impedance matching circuit 152 via the RF transmission line 128, in addition to one or more processing gases.

[0065] During state S(nN), a sensor 156 connected to the output 158 ​​of the yMHz RF generator detects a variable at the output 158, such as the reflected power. The reflected power is the power reflected from the plasma of the plasma chamber 108 toward the output 158 ​​of the yMHz RF generator via the RF transmission line 128, the branch circuit 170 with the series circuit 166 and the shunt circuit 168, and the RF cable 162. Similarly, during state S(n), the sensor 156 detects a variable reflected toward the output 158 ​​of the yMHz RF generator.

[0066] The values ​​of the variables detected during multiple occurrences of a state S(nN)~S(n), for example, state S(nN)~S(n), are continuously provided from sensor 156 to processor 116 via a data cable. The processor 116 determines the values ​​of one or more parameters of one or more electrical components of impedance matching circuit 152 from the variables detected during state S(nN)~S(n), until the reflected power at output 158 ​​of the yMHzRF generator is simultaneously reduced for state S(nN)~S(n), compared to the reflected power that is reduced at output 158 ​​for one state of state S(nN)~S(n) but not for the other states of state S(nN)~S(n). For example, the values ​​of one or more parameters are determined such that the amount of power reflected at output 158 ​​of the yMHzRF generator for all states S(nN)~S(n) is less than the amount of power reflected at output 158 ​​for any one state of state S(nN)~S(n). To elaborate further, if the capacitance value of the series circuit 166 is CA and the capacitance value of the shunt circuit 168 is CB, then a quantity of power PrA is reflected toward the output 158 ​​of the yMHz RF generator during state S1. However, if the same values ​​of CA and CB are used for state S2, then the quantity of power reflected toward the output 158 ​​during state S2 is PrB, which is substantially greater than PrA. If the values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 152, for example, the parameter value CC of the series circuit 166 and the parameter value CD of the shunt circuit 168, are determined from variables detected by the sensor 156 during states S(nN)~S(n), then the reflected power is a quantity of power PrC. The value PrC is less than the value PrB but greater than the value PrA. In some embodiments, the value PrC is less than or equal to the value PrA.

[0067] As another example, if the values ​​of one or more parameters of the impedance matching circuit 152, for example, the value CC of the parameter of the series circuit 166 and the value CD of the parameter of the branch circuit 168, are determined from the variables detected during state S(n-N) to S(n), then the reflected power is a power of quantity PrD for state S(n-N) and a power of quantity PrE for state S(n). The value PrD is the minimum value of the reflected power for state S(nN) among the values ​​of the reflected power for state S(nN). Multiple values ​​of the reflected power for state S(nN) are achieved when the frequency of the yMHz RF generator and / or the power of the RF signal supplied by the yMHz RF generator are changed during state S(nN). The value PrD is the minimum value of the reflected power for state S(n) among the values ​​of the reflected power for state S(n). Multiple values ​​of reflected power for state S(n) are achieved when the frequency of the yMHz RF generator and / or the power of the RF signal supplied by the yMHz RF generator are changed during state S(n). In various embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n). In some embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n), and both of these minimums are less than a predetermined level of reflected power. The value PrB is greater than a predetermined level, and the value PrA is less than a predetermined level.

[0068] During state S(nN)~S(n), processor 116 transmits a control signal to driver D3 indicating the parameter value for state S(nN)~S(n), and continues transmitting until the reflected power decreases at output 158 ​​of the yMHzRF generator relative to state S(nN)~S(n). Upon receiving the control signal, motor M3 rotates to change the parameter value of the series circuit 166 via one or more connection mechanisms connecting motor M3 to the series circuit 166. Similarly, during state S(nN)~S(n), processor 116 transmits a control signal to driver D4 indicating the parameter value for state S(nN)~S(n), and continues transmitting until the reflected power decreases at output 158 ​​relative to state S(nN)~S(n). Upon receiving the control signal, motor M4 rotates to change the parameter value of the shunt circuit 168 via one or more connection mechanisms connecting motor M4 to the shunt circuit 168. The decrease in reflected power at output 158 ​​also extends the life of the yMHzRF generator.

[0069] In some embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced to a level within a predetermined range from the level at output 136 where the reflected power is reduced for state S(nN)~S(n), and until the reflected power at output 158 ​​is reduced for state S(nN)~S(n). For example, the value PrC at output 158 ​​is within a predetermined range from the value Pr3 of the reflected power at output 136.

[0070] In various embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced from a level at output 136 relative to state S(nN)~S(n) to a level within a predetermined range. Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 136 and the reflected power at output 158 ​​are below predetermined limits. For example, the value PrC at output 158 ​​is within a predetermined range from the reflected power value Pr3 at output 136, and the values ​​PrC and Pr3 are less than the predetermined limit of reflected power. The predetermined range and predetermined limit are stored in the memory device 118 for access by the processor 116.

[0071] In some embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced to a level within a predetermined range relative to state S(nN), from a level at output 136 where the reflected power is reduced to state S(nN). Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced to a level within a predetermined range relative to state S(n), from a level at output 136 where the reflected power is reduced to state S(n). For example, the value PrD at output 158 ​​is within a predetermined range from the reflected power value Pr4 at output 136, and the value PrE at output 158 ​​is within a predetermined range from the reflected power value Pr5 at output 136.

[0072] In various embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced to a level within a predetermined range relative to state S(nN), from a level at output 136 relative to state S(nN). Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced to a level within a predetermined range relative to state S(n), from a level at output 136 relative to state S(n). Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 136 and output 158 ​​falls below predetermined limits. For example, the value PrD at output 158 ​​is within a predetermined range from the reflected power value Pr4 at output 136, and values ​​PrD and Pr4 are less than the predetermined limit of reflected power. Furthermore, the value PrE at output 158 ​​is within a predetermined range from the reflected power value Pr5 at output 136, and values ​​PrE and Pr5 are less than the predetermined limit of reflected power.

[0073] Figure 1C is a diagram of one embodiment of System 180 to illustrate the reduction of reflected power to the xMHz RF generator, yMHz RF generator, and zMHz RF generator in states S(nN)~S(n). System 180 consists of the xMHz RF generator, yMHz RF generator, zMHz RF generator, and host computer. 111 The system comprises an impedance matching circuit 182, a plasma chamber 108, motors M1-M4, drivers D1-D4, motor M5, motor M6, driver D5, and driver D6. The impedance matching circuit 182 includes a series circuit 196 and a shunt circuit 198 connected to each other.

[0074] The output 184 of the zMHz RF generator is connected to the input 186 of the impedance matching circuit 182 via an RF cable 188. The zMHz RF generator comprises a control system 190, an RF power supply 192, and a sensor 194. The sensor 194 is connected to the output 184 of the zMHz RF generator. Furthermore, the sensor 194 is connected to a processor 116 via a data cable, and the processor 116 is connected to the control system 190 via a data cable.

[0075] The processor 116 is connected to the driver D5, which is connected to the motor M5. The motor M5 is connected to the series circuit 196 via one or more connection mechanisms. Furthermore, the processor 116 is connected to the driver D6, which is connected to the motor M6. The motor M6 is connected to the shunt circuit 198 via one or more connection mechanisms.

[0076] The impedance matching circuit 182 comprises a series circuit 102, a shunt circuit 104, a series circuit 164, a shunt circuit 166, a series circuit 196, and a shunt circuit 198. One end of the series circuit 196 is connected to the input 186, and the other end of the series circuit 196 is connected to the output 134. Furthermore, one end of the shunt circuit 198 is connected to the series circuit 196 and the output 134 of the impedance matching circuit 182, and the other end of the shunt circuit 198 is connected to ground.

[0077] The processor 116 transmits a digital pulse signal 130 to the control system 190 of the zMHz RF generator via a data cable. Upon receiving the digital pulse signal 130, the control system 190 provides the power level and frequency level for state S(nN) to the RF power supply 192 in the same manner as described above, in which the control system 120 of the xMHz RF generator provides the power level and frequency level for state S(nN) to the RF power supply 124 of the xMHz RF generator. The RF power supply 192 generates an RF signal having the power level and frequency level for state S(nN) in the same manner as the RF power supply 124 of the xMHz RF generator generates an RF signal having the power level and frequency level for state S(nN). The RF power supply 192 supplies the RF signal to the input 186 of the impedance matching circuit 182 via the RF cable 188.

[0078] Similarly, upon receiving the digital pulse signal 130, the control system 190 provides the power level and frequency level for state S(n) to the RF power supply 192 in the same manner as described above, in which the control system 120 of the xMHz RF generator provides the power level and frequency level for state S(n) to the RF power supply 124 of the xMHz RF generator. The RF power supply 192 generates an RF signal having the power level and frequency level for state S(n) in the same manner as the RF power supply 124 of the xMHz RF generator generates an RF signal having the power level and frequency level for state S(n). The RF power supply 192 supplies the RF signal to the input 186 of the impedance matching circuit 182 via the RF cable 162.

[0079] In addition to the RF signals for state S(nN) from the x and y MHz RF generators, when the RF signal for state S(nN) is received by the impedance matching circuit 182 from the z MHz RF generator, the impedance matching circuit 182 matches the impedance of the load connected to the output 134 of the impedance matching circuit 182, such as the RF transmission line 128 and the plasma chamber 108, with the sources connected to the inputs 132, 160, and 186 of the impedance matching circuit 182, such as the RF cable 126, the x megahertz RF generator, the RF cable 162, the y MHz RF generator, the RF cable 188, and the z MHz RF generator. The impedance matching circuit 182 generates a modulated RF signal for state S(nN) by matching the impedances and combining the RF signals transmitted via the branch circuits 165 (Figure 1B), 170, and 199. The modulated RF signal for state S(nN) is provided from the impedance matching circuit 182 to the chuck 110 via the output 134 and the RF transmission line 128. The branch circuit 199 includes a series circuit 196 and a shunt circuit 198.

[0080] Similarly, when the RF signal for state S(n) is received by the impedance matching circuit 182 from the zMHz RF generator, in addition to the RF signals for state S(n) from the x and yMHz RF generators, the impedance matching circuit 182 matches the impedance of the load connected to the output 134 of the impedance matching circuit 182 with the impedance of the sources connected to the inputs 132, 160, and 186 of the impedance matching circuit 182. The impedance matching circuit 182 generates a modulated RF signal for state S(n) by matching the impedances and combining the RF signals transmitted through the branch circuits 165 (Figure 1B), 170, and 199. The modulated RF signal for state S(n) is provided from the impedance matching circuit 182 to the chuck 110 via the RF transmission line 128. The substrate 112 receives the modulated RF signal in addition to one or more processing gases via the RF transmission line 128 to the impedance matching circuit 182 It is processed when it is received.

[0081] During state S(nN), sensor 194 connected to the output 184 of the zMHz RF generator detects a variable at output 184, such as the reflected power. Reflected power is the power reflected from the plasma of the plasma chamber 108 towards the output 184 of the zMHz RF generator via the RF transmission line 128, the branch circuit 199 of the impedance matching circuit 182, and the RF cable 188. Similarly, during state S(n), sensor 194 detects the value of a variable reflected towards the output 184 of the zMHz RF generator.

[0082] The values ​​of the variables detected during multiple occurrences of state S(nN)~S(n), for example, state S(nN)~S(n), are continuously provided from sensor 194 to processor 116 via a data cable. The processor 116 determines the values ​​of one or more parameters of one or more electrical components of impedance matching circuit 182 from the variables detected during state S(nN)~S(n), comparing the reflected power at output 184 to the reflected power that is reduced at output 184 for one of the states S(nN)~S(n) but not for the other states of state S(nN)~S(n), until the reflected power at output 184 is reduced simultaneously for state S(nN)~S(n). For example, the values ​​of one or more parameters are determined such that the amount of power reflected to output 184 for all states S(nN)~S(n) is reduced compared to the amount of power reflected to output 184 that is reduced for any one state of states S(nN)~S(n) but not for the remaining states of states S(nN)~S(n). To elaborate further, if the capacitance value of the series circuit 196 is Ca and the capacitance value of the shunt circuit 198 is Cb, then the amount of power Pra is reflected to output 184 during state S1. However, if the same values ​​of Ca and Cb are used for state S2, then the amount of power reflected to output 184 during state S2 is Prb, which is substantially larger than Pra. If the values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 182, for example, the value Cc of the parameter of the series circuit 196 and the value Cd of the parameter of the shunt circuit 198, are determined from variables detected by the sensor 194 during states S(nN) and S(n), then the reflected power at output 184 is power of quantity Prc. The value Prc is less than the value Prb but greater than the value Pra. In some embodiments, the value Prc is less than or equal to the value Pra.

[0083] As another example, if the values ​​of one or more parameters of the impedance matching circuit 182, for example, the value Cc of the parameter of the series circuit 196 and the value Cd of the parameter of the branch circuit 198, are determined from the variables detected during state S(n-N) to S(n), then the reflected power is a power of quantity Prd for state S(n-N) and a power of quantity Pre for state S(n). The value Prd is the minimum value of the reflected power for state S(nN) among the values ​​of the reflected power for state S(nN). Multiple values ​​of the reflected power for state S(nN) are achieved when the frequency of the zMHz RF generator and / or the power of the RF signal supplied by the zMHz RF generator are changed during state S(nN). The value Prd is the minimum value of the reflected power for state S(n) among the values ​​of the reflected power for state S(n). Multiple values ​​of reflected power for state S(n) are achieved when the frequency of the zMHz RF generator and / or the power of the RF signal supplied by the zMHz RF generator are changed during state S(n). In various embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n). In some embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n), and both of these minimums are less than a predetermined level of reflected power. The value Prb is greater than the predetermined level, and the value Pra is less than the predetermined level.

[0084] During state S(nN)~S(n), processor 116 transmits a control signal to driver D5 indicating the parameter value for state S(nN)~S(n), and continues transmitting until the reflected power decreases at output 184 of the zMHz RF generator relative to state S(nN)~S(n). Upon receiving the control signal, motor M5 rotates to change the parameter value of the series circuit 196 via one or more connection mechanisms connecting motor M5 to the series circuit 196. Similarly, during state S(nN)~S(n), processor 116 transmits a control signal to driver D6 indicating the parameter value for state S(nN)~S(n), and continues transmitting until the reflected power decreases at output 184 relative to state S(nN)~S(n). Upon receiving the control signal, motor M6 rotates to change the parameter value of the shunt circuit 198 via one or more connection mechanisms connecting motor M6 to the shunt circuit 198. The decrease in reflected power at output 184 also extends the life of the zMHz RF generator.

[0085] In some embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced to a level within a predetermined range from the level at output 136 where the reflected power is reduced to a level within a predetermined range from the level at output 158 ​​where the reflected power is reduced to a level within a predetermined range from the level at output 158 ​​where the reflected power is reduced to a level within a predetermined range from the level at output 136

[0086] In various embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced to a level within a predetermined range from the level at output 136 where the reflected power is reduced to a level within a predetermined range from the level at output 158 ​​where the reflected power is reduced to a level within a predetermined range from the level at output 158 ​​where the reflected power is reduced to a level within a predetermined range from the level at output 184 where the reflected power is reduced to a level within a predetermined range from the level at output 136 where the reflected power is reduced to a level within a predetermined range from the level at output 158 ​​where the reflected power is reduced to a level within a predetermined range from the level at output 184 where the reflected power is reduced to a level within a predetermined range from the level at output 158 For example, the value PrC at output 158 ​​is within a predetermined range from the reflected power value Pr3 at output 136 and the value Prc at output 184, and the values ​​PrC, Pr3, and Prc are smaller than a predetermined limit for reflected power.

[0087] In some embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced to a level within a predetermined range from the level at output 136 where the reflected power is reduced to state S(nN) and the level at output 158 ​​where the reflected power is reduced to state S(nN), until the reflected power at output 184 is reduced to state S(nN). Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced to a level within a predetermined range from the level at which the reflected power at output 136 is reduced to a level within a predetermined range from the level at which the reflected power at output 158

[0088] In various embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced to a level within a predetermined range from the level at output 136 where the reflected power is reduced to state S(nN) and the level at output 158 ​​where the reflected power is reduced to state S(nN), until the reflected power at output 184 is reduced to state S(nN). Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced to a level within a predetermined range from the level at which the reflected power at output 136 is reduced to a level at which the reflected power at output 158 ​​is reduced to a level within a predetermined range relative to state S(n). Furthermore, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more circuits among the series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 136, the reflected power at output 158, and the reflected power at output 184 are below a predetermined limit. For example, the value Prd at output 184 is within a predetermined range from the reflected power value Pr4 at output 136 and the reflected power value PrD at output 158. Also, the value Pre at output 184 is within a predetermined range from the reflected power value Pr5 at output 136 and the reflected power value PrE at output 158. All values ​​Prd, Pr4, PrD, Pre, Pr5, and PrE are smaller than a predetermined limit.

[0089] In some embodiments, each circuit component of the impedance matching circuit described herein, such as an inductor or capacitor, is electronically controlled. For example, a motor is not used to control the circuit components.

[0090] Figure 2A shows a graph 202 of one embodiment of a digital pulse signal 206 and a graph 204 showing one embodiment of an RF signal 208 supplied by an RF generator, e.g., an xMHz RF generator, or a yMHz RF generator, or a zMHz RF generator. The digital pulse signal 206 is an example of a digital pulse signal 130 (Figures 1A-1C). Graph 202 plots the logic level against time. Furthermore, graph 204 plots the power level of the RF signal 208 against time. As an example, the power level of an RF signal is the envelope of the RF signal (e.g., amplitude from zero to peak). As another example, the power level of an RF signal is the root mean square of the amplitude of the RF signal.

[0091] During state S0, when the logic level of the digital pulse signal 206 is 0, the power level of the RF signal 208 is P1, where p1 is either zero or a positive value. Furthermore, during state S1, when the logic level of the digital pulse signal 206 is 1, the power level of the RF signal 208 is P2. Power level P2 is greater than power level P1. Also, when the digital pulse signal 206 transitions from state S0 to state S1, the RF signal 208 transitions from power level P1 to power level P2. When the digital pulse signal 206 transitions from state S1 to state S0, the RF signal 208 transitions from power level P2 to power level P1. In this way, the digital pulse signal 206 is synchronized with the RF signal 208.

[0092] Note that state S0 of the digital pulse signal 206 occurs during the clock cycle period t1. Furthermore, state S1 of the digital pulse signal 206 occurs during the clock cycle period t2.

[0093] Figure 2B is an embodiment of graph 210 of an RF signal 212 having three states S0, S1, and S2. The RF signal 212 is an example of an RF signal supplied by an xMHz RF generator, a yMHz RF generator, or a zMHz RF generator. In state S0, the RF signal 212 has a power level P1. Furthermore, in state S1, the RF signal 212 has a power level P3. Also, in state S2, the RF signal 212 has a power level P2. Power level P3 is lower than power level P2 but higher than power level P1. When the digital pulse signal 130 (Figures 1A to 1C) transitions from state S0 to state S1, the RF signal 212 transitions from power level P1 to power level P3. Furthermore, when the digital pulse signal 130 transitions from state S1 to state S2, the RF signal 212 transitions from power level P3 to power level P2. Furthermore, when the digital pulse signal 130 returns from state S2 to state S0, the RF signal 212 returns from power level P2 to power level P1. The states S0 to S2 of the RF signal 212 occur during a clock cycle which is the sum of periods t1 and t2.

[0094] Figure 2C is an embodiment of Graph 214 of an RF signal 216 having four states S0, S1, S2, and S3. The RF signal 216 is an example of an RF signal supplied by an xMHz RF generator, a yMHz RF generator, or a zMHz RF generator. In state S0, the RF signal 216 has a power level P1. Furthermore, in state S1, the RF signal 216 has a power level P2. Also, in state S2, the RF signal 216 has a power level P3. In state S3, the RF signal 216 has a power level P4. Power level P4 is lower than power level P3 but higher than power level P1. When the digital pulse signal 130 (Figures 1A to 1C) transitions from state S0 to state S1, the RF signal 216 transitions from power level P1 to power level P2. Furthermore, when the digital pulse signal 130 transitions from state S1 to state S2, the RF signal 216 transitions from power level P2 to power level P3. Also, when the digital pulse signal 130 transitions from state S2 to state S3, the RF signal 216 transitions from power level P3 to power level P4. And when the digital pulse signal 130 returns from state S3 to state S0, the RF signal 216 returns from power level P4 to power level P1. States S0 to S3 of the RF signal 216 occur during a clock cycle which is the sum of periods t1 and t2.

[0095] Figure 3A is a diagram of one embodiment of system 300 for illustrating the control of series circuit 306 and shunt circuit 308 during states S(nN) to S(n). Series circuit 306 is an example of series circuit 102, 166, or 196 (Figure 1C). Furthermore, shunt circuit 308 is an example of shunt circuit 104, 168, or 198 (Figure 1C). System 300 includes an RF generator 302, such as an xMHz RF generator, a yMHz RF generator, or a zMHz RF generator. RF generator 302 has an output 370, which is an example of output 136, output 158, or output 184 (Figure 1C). Furthermore, system 300 includes an impedance matching circuit 304, which is an example of impedance matching circuit 106 (Figure 1), branch circuit 170 (Figure 1B), or branch circuit 199 (Figure 1C).

[0096] The RF generator 302 is connected to the impedance matching circuit 304 via an RF cable 310, which is an example of RF cable 126, RF cable 162, or RF cable 188 (Figure 1C). The output 134 of the impedance matching circuit 304 is connected to the plasma chamber 108 via an RF transmission line 128.

[0097] The system 300 further comprises motors 312 and 314. Motor 312 is an example of motor M1, motor M3, or motor M5 (Figure 1C). Furthermore, motor 314 is an example of motor M2, motor M4, or motor M6 (Figure 1C).

[0098] The series circuit 306 is connected to the RF cable 310 via input 316 of the impedance matching circuit 304. Input 316 is an example of input 132, input 160, or input 186 (Figure 1C). The series circuit includes an inductor L1 in series with a variable capacitor C1. One end of inductor L1 is connected to input 316, and the other end of inductor L1 is connected to capacitor C1. The shunt circuit 308 includes an inductor L2 in series with a capacitor C2, which is also variable. One end of inductor L2 is connected to output 134, and output 134 is connected to the end of capacitor C1. Furthermore, the other end of inductor L2 is connected to capacitor C2, and capacitor C2 is connected to ground with the other end. Inductors L1 and L2 are fixed, not variable.

[0099] Motor 312 is connected to capacitor C1 via one or more connection mechanisms and rotates to change the distance or area between the parallel plates of capacitor C1. For example, the parallel plates of the capacitor move, e.g., rotate, relative to each other to change the distance or area between them. The change in distance or area changes, e.g., increases or decreases, the capacitance of the capacitor. Similarly, motor 314 is connected to capacitor C2 via one or more connection mechanisms and rotates to change the distance or area between the parallel plates of capacitor C2.

[0100] Figure 3B is a diagram of one embodiment of system 320 for illustrating the control of series circuit 324 and shunt circuit 326 during states S(nN) to S(n). Series circuit 324 is an example of series circuit 102, 166, or 196 (Figure 1C). Furthermore, shunt circuit 326 is an example of shunt circuit 104, 168, or 198 (Figure 1C). System 320 includes an RF generator 302. Furthermore, system 320 includes an impedance matching circuit 322, which is an example of impedance matching circuit 106 (Figure 1), branch circuit 170 (Figure 1B), or branch circuit 199 (Figure 1C).

[0101] The RF generator 302 is connected to the impedance matching circuit 322 via the RF cable 310. The output 134 of the impedance matching circuit 322 is connected to the plasma chamber 108 via the RF transmission line 128.

[0102] System 320 further comprises motors 312, 314, 328, and 330. Motor 328 is an example of motor M1, motor M3, or motor M5 (Figure 1C). Furthermore, motor 330 is an example of motor M2, motor M4, or motor M6 (Figure 1C).

[0103] The series circuit 324 is connected to the RF cable 310 via input 332 of the impedance matching circuit 322. Input 332 is an example of input 132, input 160, or input 186 (Figure 1C). The series circuit includes an inductor L3 in series with capacitor C1. One end of inductor L3 is connected to input 332, and the other end is connected to capacitor C1. The shunt circuit 326 includes an inductor L4 in series with capacitor C2. One end of inductor L4 is connected to output 134 and the end of capacitor C1. Furthermore, another end of inductor L4 is connected to capacitor C2, and capacitor C2 is connected to ground with the other end. Inductors L3 and L4 are variable.

[0104] Motor 328 is connected to inductor L3 via one or more connection mechanisms and rotates to change the overlapping area between the core of inductor L3 and the coil of inductor L3. For example, the core of the inductor surrounded by the coil of the inductor is moved relative to the coil to change the inductance of the inductor. The change in overlapping area increases or decreases the inductance of the inductor, for example. Similarly, motor 330 is connected to inductor L4 via one or more connection mechanisms and rotates to change the overlapping area between the core of inductor L4 and the coil of inductor L4.

[0105] In some embodiments, inductors L1 and L2 are controlled to vary their inductance, and fixed capacitors are used in the impedance matching circuit 322 instead of capacitors C1 and C2. In various embodiments, one or more of capacitors C1, C2, inductors L1, and L2 are controlled to reduce reflected power at output 370 for states S(nN)~S(n).

[0106] Figure 3C is a diagram of one embodiment of system 350 to illustrate an impedance matching circuit 352 having any number of series circuits and any number of shunt circuits. System 350 comprises an RF generator 302, an impedance matching circuit 352, a plasma chamber 108, motors 312 and 314, motor 362, and motor 364.

[0107] The RF generator 302 is connected to the input 366 of the impedance matching circuit 352 via the RF cable 310. The impedance matching circuit 352 comprises a series circuit 354, a shunt circuit 356, another series circuit 358, and another shunt circuit 360. One end of the series circuit 354 is connected to the input 366, and the other end of the series circuit 354 is connected to the end of the shunt circuit 356. Furthermore, another end of the series circuit 354 is connected to the end of the series circuit 358. Another end of the shunt circuit 356 is connected to ground. Furthermore, another end of the series circuit 358 is connected to the end of the shunt circuit 360 and to the output 134 of the impedance matching circuit 352. Another end of the shunt circuit 360 is connected to ground.

[0108] Motor 312 is connected to series circuit 354 via one or more connection mechanisms. Furthermore, motor 314 is also connected to shunt circuit 356 via one or more connection mechanisms. Additionally, motor 362 is connected to series circuit 358 via one or more connection mechanisms. Motor 364 is connected to shunt circuit 360 via one or more connection mechanisms.

[0109] Upon receiving current signals from motors 312, 314, 362, and a driver (not shown) connected to 364, motor 312 operates to modify the parameters of series circuit 354, motor 314 operates to modify the parameters of shunt circuit 356, motor 362 operates to modify the parameters of series circuit 358, and motor 364 operates to modify the parameters of shunt circuit 360. The parameters of circuits 354, 356, 358, and 360 are controlled with respect to states S(nN)~S(n) such that the reflected power at output 370 of RF generator 302 is reduced with respect to states S(nN)~S(n) compared to reflected power that is reduced with respect to one of states S(nN)~S(n) but not to the other states of states S(nN)~S(n).

[0110] In some embodiments, the impedance matching circuit 352 comprises more series circuits and more shunt circuits than those shown in Figure 3C. For example, one end of a shunt circuit 360 connected to a series circuit 358 is connected to another series circuit (not shown), and the other series circuit is connected to another shunt circuit (not shown). One end of the shunt circuit (not shown) is connected to output 134. Another end of the other shunt circuit (not shown) is connected to ground.

[0111] Figure 3D is a diagram of one embodiment of system 380 for illustrating an impedance matching circuit 382, ​​which is an L-network. The impedance matching circuit 382 comprises an inductor X1 and a capacitor X2. Note that X as described herein represents the reactance of a circuit component, such as an inductor or capacitor. For example, X1 is the reactance of inductor X1, and X2 is the reactance of capacitor X2. Inductor X1 is variable or fixed. Similarly, capacitor X2 is variable or fixed. One end of capacitor X2 is connected to ground, and the other end of capacitor X2 is connected to the end of inductor X1 and to the input 384 of the impedance matching circuit 382. Another end of inductor X1 is connected to the output 134 of the impedance matching circuit 382.

[0112] It should be noted that impedance matching circuit 382 can be used in place of any other impedance matching circuit described herein. For example, impedance matching circuit 382 can be used in place of impedance matching circuit 106, branch circuit 170, or branch circuit 199 (Figure C). Impedance matching circuit 382 has an input 384, which is an example of input 132, input 160, or input 186 (Figure 1C).

[0113] Note that the RF power supply is shown in Figure 3B, and that it is connected to resistor Rs, which is the source resistance connected to input 384. Furthermore, resistor Rp is also shown in Figure 3B. Resistor Rp has the load resistance connected to output 134.

[0114] Figure 3E is a diagram of one embodiment of system 386 for illustrating an impedance matching circuit 388, which is a pi network. The impedance matching circuit 386 comprises an inductor X2, a capacitor X3, and a capacitor X4. The inductor X2 is variable or fixed. Similarly, each of the capacitors X3 and X4 is variable or fixed. One end of capacitor X3 is connected to ground, and the other end of capacitor X3 is connected to the end of inductor X2 and the input 390 of the impedance matching circuit 388. Furthermore, another end of inductor X2 is connected to the end of capacitor X4, and the other end of capacitor X4 is connected to ground. Another end of inductor X2 is connected to the output 134 of the impedance matching circuit 388. In addition, a resistor RI is shown in Figure 3C. Resistor RI has the resistance of the load connected to the output 134.

[0115] Figure 3F is a diagram of one embodiment of an impedance matching circuit 392, which is a pi network. The pi network is represented by two L networks. The impedance matching circuit 392 comprises an inductor X21, a capacitor X3, a resistor Rx, another inductor X22, and a capacitor X4. Each of the capacitors X21 and X22 is variable or fixed. Similarly, each of the capacitors X3 and X4 is variable or fixed. One end of capacitor X3 is connected to ground, and the other end of capacitor X3 is connected to the end of inductor X21 and the input 394 of the impedance matching circuit 392. Furthermore, the other end of inductor X21 is connected to the end of resistor Rx, and the other end of resistor Rx is connected to ground. Also, the other end of inductor X21 is connected to the end of inductor X22, and the other end of inductor X22 is connected to the end of capacitor X4. The other end of capacitor X4 is connected to ground. The other end of inductor X22 and the end of capacitor X4 are connected to output 134 of impedance matching circuit 392.

[0116] It should be noted that impedance matching circuit 388 can be used in place of any other impedance matching circuit described herein. For example, impedance matching circuit 388 can be used in place of impedance matching circuit 106, branch circuit 170, or branch circuit 199 (Figure C).

[0117] Figure 4 is a diagram of one embodiment of Method 400 for describing the determination of the values ​​of one or more parameters that reduce the power reflected toward an RF generator for states S(nN)~S(n). Method 400 comprises a step 402 of measuring the reflected power at the output of the RF generator for state S(nN). For example, during the period when the RF signal generated by the RF generator is in state S(nN), the reflected power is measured at the output of the RF generator. A sensor in the RF generator (e.g., a sensor connected to the output of the RF generator) measures the reflected power. The sensor is located inside or outside the RF generator. The sensor provides the value of the reflected power measured during state S(nN) to a processor 116 (Figure 1C).

[0118] Furthermore, in step 404 of method 400, during state S(nN), the processor 116 modifies one or more parameters of an impedance matching circuit connected to the RF generator via an RF cable, such as inductance and capacitance, so that the power reflected to the output of the RF generator is reduced. For example, when the reflected power measured during state S(nN) is PRF1, the values ​​of one or more parameters of the impedance matching circuit are CV1 and CV2. Furthermore, when the values ​​of one or more parameters of the impedance matching circuit are changed from CV1 to CV3 and from CV2 to CV4, the reflected power measured during state S(nN) decreases to PRF2, which is smaller than the value PRF1.

[0119] In step 406 of method 400, the reflected power is measured at the output of the RF generator during state S(n). For example, during the period when the RF signal generated by the RF generator is in state S(n), the reflected power is measured by a sensor at the output of the RF generator. The sensor provides the processor 116 with the value of the reflected power measured during state S(n).

[0120] In step 408 of method 400, the values ​​of one or more parameters of the impedance matching circuit are changed by the processor 116 during state S(n) so that the reflected power measured at the output of the RF generator is reduced during both states S(n) and S(nN). For example, if during state S(n) the values ​​of one or more impedance parameters are controlled by the processor 116 to change from CV3 to CV5 and from CV4 to CV6, the reflected power will decrease to PRF3, which is less than the value PRF1. The value PRF3 is greater than the value PRF2. In another example, the value PRF3 is less than or equal to the value PRF2. As an example, the values ​​PRF2 and PRF3 are within a predetermined threshold of each other. The predetermined threshold is stored in the memory device 118 (Figure 1C) for access by the processor 116. In yet another example, the values ​​PRF2 and PRF3 are both less than a predetermined level and within a predetermined threshold of each other. The predetermined level is stored in the memory device 118 for access by the processor 116. PRF1 This is greater than a predetermined level. After step 408, for state S(nN)~S(n), the values ​​of one or more parameters of the impedance matching circuit are maintained at CV5 and CV6.

[0121] In some embodiments, after step 408, the values ​​CV5 and CV6 are adjusted (e.g., increased or decreased) by the processor 116 to further reduce the reflected power at the output of the RF generator during state S(nN)~S(n) as the power and / or frequency of the RF signal generated by the RF generator changes.

[0122] Note that in various embodiments, if the impedance matching circuit described herein includes a number of parameter values ​​determined such that the reflected power at the output of an RF generator connected to the impedance matching circuit is reduced for state S(nN)~S(n), then a multivariate analysis method is used by the processor 116 to determine the parameter values. For example, the processor 116 uses a multivariate analysis method to determine the capacitance and / or inductance values ​​of the series and shunt circuits of the impedance matching circuit such that the minimum reflected power at the output of the RF generator for state S(nN)~S(n) is less than a predetermined level, and the minimum reflected power at the output of the RF generator for state S(nN) is within a predetermined threshold of the minimum reflected power at the output of the RF generator for state S(n).

[0123] In some embodiments, a neural network, such as a computer system modeled after the human brain, or a network of computers modeled after the human brain, determines the relationship between one or more values ​​of parameters of the impedance matching circuit described herein and the reflected power at the output of the RF generator described herein connected to the impedance matching circuit. For example, regression analysis is used by the neural network to determine the relationship based on the values ​​of one or more parameters input to the neural network and the value of the reflected power for state S(nN)~S(n). For example, the values ​​of one or more parameters are inputs at the input node of the neural network, and the reflected power for state S(nN)~S(n) is an output at the output node of the neural network. Regression analysis is used to determine the relationship between the input and the output. The relationship is then used by the processor 116 or the neural network during processing of the substrate 112 (Figures 1A~1C) to determine the value of one or more parameters that reduces the reflected power at the output of the RF generator for state S(nN)~S(n).

[0124] Figure 5A illustrates a method for determining the electrostatic capacitance Cseries of the series circuit and the capacitance Cshunt of the shunt circuit of the impedance matching circuit described herein, for a given state S(nN)~S(n), in order to reduce reflected power at the output of the RF generator described herein. In some embodiments, the capacitance of the series circuit of the impedance matching circuit is the combination of multiple capacitors in the series circuit. For example, the capacitance of the series circuit is the product of the capacitances of the capacitors connected in series with each other in the series circuit divided by the sum of the capacitances. As another example, the capacitance of the series circuit of the impedance matching circuit is the sum of the capacitances of the capacitors connected in parallel with each other in the series circuit. Similarly, the capacitance of the shunt circuit of the impedance matching circuit is the combination of multiple capacitors in the shunt circuit.

[0125] Line 502 holds the capacitance Cseries value, and another line 504 holds the capacitance Cshunt value. When the capacitance Cseries value is reduced from value CS1 and the capacitance Cshunt value is reduced from value CSH1, the reflected power values ​​at the RF generator output are measured during state S(nN)~S(n) and plotted in graph 506. Graph 506 plots the reflected power at the RF generator output against time. The reflected power values ​​at the RF generator output during state S(nN), e.g., values ​​510A, 512A, etc., are shown in plot 508A, and the reflected power values ​​at the RF generator output during state S(n), e.g., values ​​510B, 512B, etc., are shown in plot 508B. For example, the reflected power values ​​510A and 510B are measured when capacitance Cseries is CS(-2) and capacitance Cshunt is CSH(-2). Furthermore, the reflected power values ​​512A and 512B are measured when the capacitance Cseries is CS(-3) and the capacitance Cshunt is CSH(-3). As shown in Graph 504, the reflected power values ​​at the RF generator output are greater than a predetermined level during state S(nN)~S(n) and therefore not reduced for state S(nN)~S(n).

[0126] Furthermore, when the capacitance Cseries value is decreased from value CS1 and the capacitance Cshunt value is increased from value CSH1, the reflected power values ​​at the RF generator output are measured during states S(nN)~S(n) and plotted in graph 514. Graph 514 plots the reflected power at the RF generator output against time. The reflected power values ​​at the RF generator output during state S(nN), such as values ​​518A, 520A, and 522A, are shown in plot 516A, and the reflected power values ​​at the RF generator output during state S(n), such as values ​​518B, 520B, and 522B, are shown in plot 516B. For example, the reflected power values ​​518A and 518B are measured when the capacitance Cseries is CS(-2) and the capacitance Cshunt is CSH(2). Furthermore, the reflected power values ​​520A and 520B are measured when the capacitance Cseries is CS(-3) and the capacitance Cshunt is CSH(3). Similarly, the reflected power values ​​522A and 522B are measured when the capacitance Cseries is CS(-4) and the capacitance Cshunt is CSH(4). As shown in Graph 514, the reflected power values ​​522A and 522B at the RF generator output are less than a predetermined level during state S(nN)~S(n). Furthermore, values ​​522A and 522B are within a predetermined threshold relative to each other. For example, value 522A is the absolute minimum of plot 516A, and value 522B is the absolute minimum of plot 516B. In various embodiments, value 522A is the local minimum of plot 516A, and value 522B is the local minimum of plot 516B. The local minimum is the minimum reflected power during a given period in which reflected power is measured, for example, between time t1 and time t2. In contrast, the absolute minimum is the minimum reflected power over the entire period in which reflected power is measured, for example, between time t1 and time t3. The capacitance values ​​CS(-4) and CSH(4) are the capacitance values ​​at which reflected power at the RF generator output is reduced for state S(nN)~S(n) compared to reflected power that is reduced for one state of state S(nN)~S(n) but not for the other states of state S(nN)~S(n).

[0127] Furthermore, when the capacitance Cseries value is increased from value CS1 and the capacitance Cshunt value is decreased from value CSH1, the reflected power values ​​at the RF generator output are measured during states S(nN)~S(n) and plotted in graph 524. Graph 524 plots the reflected power at the RF generator output against time. The reflected power values ​​at the RF generator output during state S(nN), for example, values ​​528A and 530A, are shown in plot 526A, and the reflected power values ​​at the RF generator output during state S(n), for example, values ​​528B and 530B, are shown in plot 526B. For example, the reflected power values ​​526A and 526B are measured when the capacitance Cseries is CS(2) and the capacitance Cshunt is CSH(-2). Furthermore, the reflected power values ​​530A and 530B are measured when the capacitance Cseries is CS(3) and the capacitance Cshunt is CSH(-3). As shown in Graph 524, the reflected power values ​​at the RF generator output are greater than a predetermined level during state S(nN)~S(n).

[0128] Furthermore, when the capacitance Cseries value is increased from value CS1 and the capacitance Cshunt value is decreased from value CSH1, the reflected power values ​​at the RF generator output are measured during states S(nN)~S(n) and plotted in graph 524. Graph 524 plots the reflected power at the RF generator output against time. The reflected power values ​​at the RF generator output during state S(nN), for example, values ​​528A and 530A, are shown in plot 526A, and the reflected power values ​​at the RF generator output during state S(n), for example, values ​​528B and 530B, are shown in plot 526B. For example, the reflected power values ​​528A and 528B are measured when the capacitance Cseries is CS(2) and the capacitance Cshunt is CSH(-2). Furthermore, the reflected power values ​​530A and 530B are measured when the capacitance Cseries is CS(3) and the capacitance Cshunt is CSH(-3). As shown in Graph 524, the reflected power values ​​at the RF generator output are greater than a predetermined level during state S(nN)~S(n) and therefore not reduced for state S(nN)~S(n).

[0129] When the capacitance Cseries value is increased from value CS1 and the capacitance Cshunt value is increased from value CSH1, the reflected power values ​​at the RF generator output are measured during states S(nN)~S(n) and plotted in graph 532. Graph 532 plots the reflected power at the RF generator output against time. The reflected power values ​​at the RF generator output during state S(nN), for example, values ​​536A and 538A, are shown in plot 534A, and the reflected power values ​​at the RF generator output during state S(n), for example, values ​​536B and 538B, are shown in plot 534B. For example, the reflected power values ​​536A and 536B are measured when the capacitance Cseries is CS(2) and the capacitance Cshunt is CSH(2). Furthermore, the reflected power values ​​538A and 538B are measured when the capacitance Cseries is CS(3) and the capacitance Cshunt is CSH(3). As shown in Graph 532, the reflected power values ​​at the RF generator output are greater than a predetermined level during state S(nN)~S(n) and therefore not reduced for state S(nN)~S(n).

[0130] In some embodiments, one of the capacitances Cseries and Cshunt is changed during the method shown in Figure 5A, while the other of the capacitances Cseries and Cshunt remains unchanged.

[0131] In various embodiments, instead of changing the capacitances Cseries and Cshunt, the method described with reference to Figure 5A is equally applicable to changing the inductance of the series circuit of an impedance matching circuit and to changing the inductance of the shunt circuit of an impedance matching circuit. In some embodiments, instead of changing the capacitances Cseries and Cshunt, the method described with reference to Figure 5A is equally applicable to changing the capacitance and inductance of the series circuit of an impedance matching circuit and to changing the capacitance and inductance of the shunt circuit of an impedance matching circuit.

[0132] Please note that the method described using Figure 5A is an empirical process for achieving the minimum reflected power for states S(nN)~S(n). For example, the method described using Figure 5A is a value Cseries Cshunt is a multivariate tuning method determined to achieve two goals (e.g., the minimum reflected power in state S(nN) and the minimum reflected power in state S(n)).

[0133] Furthermore, note that the values ​​CS(-4) to CS(4) are progressive relative to each other. For example, CS(-4) is smaller than CS(-3), CS(-3) is smaller than CS(-2), CS(-2) is smaller than CS(-1), and CS(-1) is smaller than CS(0), CS(0) is smaller than CS(1), CS(1) is smaller than CS(2), CS(2) is smaller than CS(3), and CS(3) is smaller than CS(4). To elaborate further, CS(-4) is a smaller unit than CS(-3), for example, 0.1 picofarads, 0.2 picofarads, etc., and CS(-3) is a smaller unit than CS(-2). The value CS(-2) is a smaller unit than the value CS(-1), and the value CS(-1) is a smaller unit than the value CS(0). The value CS(0) is a smaller unit than the value CS(1), and the value CS(1) is a smaller unit than the value CS(2). The value CS(2) is a smaller unit than the value CS(3), and the value CS(3) is a smaller unit than the value CS(4).

[0134] Similarly, note that the values ​​CSH(-4) to CSH(4) are progressive relative to each other. For example, CSH(-4) is smaller than CSH(-3), CSH(-3) is smaller than CSH(-2), CSH(-2) is smaller than CSH(-1), and CSH(-1) is smaller than CSH(0), CSH(0) is smaller than CSH(1), and CSH(1) is smaller than CSH(2), CSH(2) is smaller than CSH(3), and CSH(3) is smaller than CSH(4). To elaborate further, CSH(-4) is a smaller unit than CSH(-3), for example, 0.1 picofarads, 0.2 picofarads, etc., and CSH(-3) is a smaller unit than CSH(-2). The value CSH(-2) is a smaller unit than the value CSH(-1), and the value CSH(-1) is a smaller unit than the value CSH(0). The value CSH(0) is a smaller unit than the value CSH(1), and the value CSH(1) is a smaller unit than the value CSH(2). The value CSH(2) is a smaller unit than the value CSH(3), and the value CSH(3) is a smaller unit than the value CSH(4).

[0135] Figure 5B is a diagram of one embodiment of Graph 550 illustrating the technical advantages of applying a method to tune to reduce reflected power in states S(nN)~S(n). Graph 550 plots reflectance against the frequency of the RF generator. Reflectance is a measure of the power reflected toward the RF generator. Graph 550 includes plots 552, 554, 556, and 558. In some embodiments, reflectance indicates the amount of RF signal reflected from the plasma chamber 108 (Figure 1C) toward the RF generator, e.g., xMHz RF generator, yMHz RF generator, or zMHz RF generator. For example, reflectance is equal to the ratio of the amplitude of reflected power to the amplitude of forward power. Forward power is the power supplied by the RF generator to the plasma chamber 108 via an impedance matching circuit.

[0136] Plot 552 is a plot where the reflectance is zero or near zero with respect to the operating frequency of the f1MHz RF generator, which is between the operating frequency of the RF generator's Fmin and the operating frequency of the RF generator's Fmax. Furthermore, plot 554 is a plot where the parameter value that minimizes the reflectance for state S(nN) is used in state S(n). For example, the capacitance values ​​of the series circuit 102 and shunt circuit 104 of the impedance matching circuit 106 in Figure 1A (Figure 1A) for state S1 are CA1 and CA2. When capacitance values ​​CA1 and CA2 are used in state S2, the reflectance at the output 136 of the xMHz RF generator becomes as shown in plot 554. The reflectance in plot 554 is greater than a predetermined level indicated by the symbol 560. For example, the minimum value in plot 554 is greater than a predetermined level 560.

[0137] When the method described in flowchart 400, the method described using Figures 1A to 1C, or the method described using Figure 5A or Figure 6 described later is applied, the reflectance at the output of the RF generator for state S(nN) is plotted as 556, and for state S(n) it is plotted as 558. For example, when the parameter value of the series circuit 102 is CA3 and the parameter value of the shunt circuit 104 is CA4, the reflectance shown by plot 556 is achieved for state S(nN), and the reflectance shown by plot 558 is achieved for state S(n). Note that plot 556 has a minimum value (e.g., absolute minimum) at frequency f2 of the RF generator, for example, an xMHz RF generator, and plot 558 has a minimum value (e.g., absolute minimum) at frequency f3 of the RF generator. The minimum values ​​of plots 556 and 558 are less than a predetermined limit 560 and within a predetermined threshold 562 from each other, where the predetermined threshold 562 is the range of reflectance values. The frequency values ​​f2 and f3 are between the frequency values ​​Fmin and Fmax.

[0138] In some embodiments, instead of measuring reflected power, forward power and reflected power are measured by the sensor described herein. The forward power and reflected power are provided by the sensor to the processor 116 for the calculation of reflectance. Furthermore, any of the above-described information applicable to reflected power is applicable to reflectance. For example, a predetermined level of reflectance is used instead of a predetermined level of reflected power. Another example is the use of a predetermined threshold of reflectance instead of a predetermined threshold of reflected power. Yet another example is the use of a predetermined range of reflectance instead of a predetermined range of reflected power. Another example is the use of a predetermined limit of reflectance instead of a predetermined limit of reflected power.

[0139] Figure 6 shows one embodiment of a machine learning network 600 for determining the values ​​of one or more parameters that result in the minimum value of a variable for a given state S(nN)~S(n). Examples of machine learning networks 600 include computer systems modeled after the human brain, and networks of computers modeled after the human brain. The value of one parameter (e.g., Cseries, inductance, etc.) of the impedance matching circuit described herein is received as input via an input device (e.g., mouse, keyboard, button, touchscreen, etc.), and the value of another parameter of the impedance matching circuit (e.g., Cshunt) or another parameter (e.g., inductance) is received as another input by the machine learning network 600. The machine learning network 600 processes the received input values ​​to calculate the value of a variable for state S(nN)~S(n), for example, the reflected power value, as an output. Furthermore, the machine learning network 600 determines whether the value of the variable for state S(nN)~S(n) is the minimum value. If the value of the variable for state S(nN) is not the minimum value, the machine learning network 600 performs backpropagation to change the value of the parameter received as input, and then determines again whether the value of the variable for state S(nN)~S(n) is the minimum value. The machine learning network 600 iterates until the value of the variable is the minimum value to find the value of one or more parameters that results in the minimum value of the variable.

[0140] The embodiments described herein may be implemented in a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, and mainframe computers. The embodiments may also be implemented in a distributed computing environment in which tasks are performed by remote processing hardware units connected over a network.

[0141] In some embodiments, the controller is part of the system, and the system may be part of the examples described above. Such a system comprises a semiconductor processing apparatus, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (such as a wafer pedestal, a gas flow system, etc.). These systems are integrated with electronic equipment for controlling the operation of the system before, during, and after processing of semiconductor wafers or substrates. The electronic equipment may also be called a “controller,” and may control various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the controller is programmed to control any of the processing disclosed herein, such as the supply of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and operation settings, and wafer movement in and out of a load lock connected or coupled to the tool and other moving tools and / or systems.

[0142] Generally, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) and define operating parameters for performing specific operations on or for semiconductor wafers, or operating parameters to the system. Operating parameters are, in some embodiments, part of a recipe defined by a processing engineer to achieve one or more processing steps during the processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0143] In some embodiments, the controller is part of or connected to a computer, such computer is integrated with the system, connected to the system, networked with the system in other ways, or combined with the system. For example, the controller is in the “cloud” or is all or part of a fab host computer system that enables remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, or examine trends or performance indicators from multiple manufacturing operations, in order to change the parameters of the current operation, set up a processing step according to the current operation, or start a new operation.

[0144] In some embodiments, a remote computer (e.g., a server) provides processing recipes to the system via a network including a local network or the Internet. The remote computer has a user interface that allows input or programming of parameters and / or settings, which are communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps performed during one or more operations. It should be understood that the parameters are specific to the type of processing to be performed and the type of tools that the controller is configured to interface with or control. Thus, as described above, the controller is distributed by having one or more separate controllers that are networked and operate toward a common purpose, such as the processing and control described herein. An example of a distributed controller for such a purpose includes one or more integrated circuits on a chamber that communicate with one or more remotely located integrated circuits (such as at the platform level or located as part of a remote computer) that cooperate to control processing in the chamber.

[0145] Examples of systems in various embodiments, though not limited to them, include plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be related to or used in the processing and / or manufacturing of semiconductor wafers.

[0146] It should also be noted that in some embodiments, the above-described operation applies to several types of plasma chambers, such as inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, capacitively coupled plasma reactors, plasma chambers with conductive tools, dielectric tools, and plasma chambers with electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are connected to inductors within an ICP reactor. Examples of inductor shapes include solenoids, dome-shaped coils, and flat-shaped coils.

[0147] In various embodiments, the RF transmission line 128 (Figures 1A to 1C) is connected to the upper electrode 114 instead of the chuck 110, and the chuck 110 is connected to ground.

[0148] As described above, depending on the one or more processing steps performed by the tool, the controller communicates with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, the main computer, another controller, or tool locations within the semiconductor manufacturing plant and / or tools used for material transport to and from load ports to carry wafer containers.

[0149] With the embodiments described above in mind, it should be understood that some of the embodiments utilize various operations performed by a computer, including data stored in a computer system. These operations are operations that physically handle physical quantities. Any of the operations described herein that form part of these embodiments are useful mechanical operations.

[0150] Some embodiments further relate to hardware units or devices for performing these operations. The devices are specifically configured for dedicated computers. When defined as a dedicated computer, the computer can operate for a particular purpose while performing other processes, program executions, or routines not included in the particular purpose.

[0151] In some embodiments, the operation may be processed on a computer selectively activated or configured by one or more computer programs stored in computer memory, a cache, or retrieved via a computer network. Once data is retrieved via a computer network, that data may be processed by other computers on the computer network, for example, a cloud of computing resources.

[0152] One or more embodiments may be manufactured as computer-readable code on a non-temporary computer-readable medium. The non-temporary computer-readable medium is any data storage hardware unit that stores data, such as a memory device, which is then read by a computer system. Examples of non-temporary computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-temporary computer-readable medium includes computer-readable tangible media distributed across a network-attached computer system so that the computer-readable code is stored and executed in a distributed manner.

[0153] While the method operations described above are presented in a specific order, it should be understood that in various embodiments, other housekeeping processes may be performed between operations, or the method operations may be distributed to a system that allows for method operations to occur at slightly different times or at various intervals, or they may be arranged to be performed in a different order than described above.

[0154] Furthermore, it should be noted that in one embodiment, one or more features of any embodiment described herein may be combined with one or more features of any other embodiment without departing from the scope of the various embodiments described herein.

[0155] To enhance understanding, this embodiment has been described in some detail, but it is clear that some modifications and variations may be made within the scope of the appended claims. Therefore, this embodiment is considered illustrative and not limiting, and the embodiment is not limited to the details shown herein and may be modified within the scope of the appended claims and equivalents. This disclosure may be implemented in the following forms. [Form 1] A method for tuning to reduce reflected power in multiple states, The process involves supplying power by a radio frequency (RF) generator during the first state of a digital pulse signal to a plasma chamber via an impedance matching circuit, A step of measuring the amount of power reflected to the output of the RF generator during the first state, The steps include supplying power to the plasma chamber via the impedance matching circuit using the RF generator during the second state of the digital pulse signal, A step of measuring the amount of power reflected to the output of the RF generator during the second state, A step of controlling the parameters of the impedance matching circuit so as to reduce the amount of power measured during the first state to a minimum value and the amount of power measured during the second state to a minimum value, A method that includes [a certain feature]. [Form 2] The method described in Embodiment 1, A method wherein the minimum value of the first state is smaller than a predetermined level, and the minimum value of the second state is smaller than the predetermined level. [Form 3] The method described in Embodiment 2, A method wherein the minimum value of the first state and the minimum value of the second state are within a predetermined threshold relative to each other. [Form 4] The method described in Embodiment 1, The minimum value of the first state is smaller than another minimum value of the first state. The other minimum value of the first state is achieved when the parameter has a first value, A method by which the minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value. [Form 5] The method described in Embodiment 1, The minimum value of the first state is greater than another minimum value of the first state. The other minimum value of the first state is achieved when the parameter has a first value, The minimum value in the first state and the minimum value in the second state are achieved when the parameter has a second value. The other minimum value of the first state is smaller than a predetermined level. When the parameter has the first value, another minimum value of the second state is achieved. The method wherein the other minimum value of the second state is smaller than the predetermined level. [Form 6] The method described in Embodiment 1, The step of controlling the aforementioned parameters includes the step of controlling the capacitor or inductor of the impedance matching circuit. A method wherein the minimum values ​​of the first and second states correspond to constant values ​​of the parameters of the first and second states. [Form 7] The method described in Embodiment 1, The aforementioned parameters are parameters of the series circuit of the impedance matching circuit or parameters of the shunt circuit of the impedance matching circuit. The aforementioned control process is performed using machine learning processing. [Form 8] A system for tuning to reduce reflected power in multiple conditions, A radio frequency (RF) generator configured to supply power during the first state of a digital pulse signal, An impedance matching circuit connected to the RF generator via an RF cable, A plasma chamber connected to the impedance matching circuit via an RF transmission line, A sensor connected to the output of the RF generator, configured to measure the amount of power reflected to the output of the RF generator during the first state, Equipped with, The RF generator is configured to supply power to the plasma chamber during the second state of the digital pulse signal via the impedance matching circuit. The sensor is configured to measure the amount of power reflected to the output of the RF generator during the second state, The aforementioned system further, The system includes a processor connected to the impedance matching circuit to control the parameters of the impedance matching circuit, The system is controlled such that the parameters reduce the amount of power measured during the first state to a minimum value and the amount of power measured during the second state to a minimum value. [Form 9] The system described in form 8, The minimum value of the first state is smaller than a predetermined level. A system in which the minimum value of the second state is smaller than the predetermined level. [Form 10] A system according to Embodiment 9, wherein the minimum value of the first state and the minimum value of the second state are within a predetermined threshold relative to each other. [Form 11] The system described in form 8, The minimum value of the first state is smaller than another minimum value of the first state. The other minimum value of the first state is achieved when the parameter has a first value, The minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value in the system. [Form 12] The system described in form 8, The minimum value of the first state is greater than another minimum value of the first state. The other minimum value of the first state is achieved when the parameter has a first value, The minimum value in the first state and the minimum value in the second state are achieved when the parameter has a second value. The minimum value of the first state is smaller than a predetermined level. When the parameter has the first value, another minimum value of the second state is achieved. A system in which the other minimum value of the second state is smaller than the predetermined level. [Form 13] The system described in form 8, The aforementioned parameters are parameters of the capacitor or inductor of the impedance matching circuit, in a system. [Form 14] The system described in form 8, The system wherein the parameters are either parameters of the series circuit of the impedance matching circuit or parameters of the shunt circuit of the impedance matching circuit. [Form 15] A non-temporary computer-readable medium that stores a program that causes a computer to execute a method, wherein the method is A process of supplying power to a plasma chamber via an impedance matching circuit using a radio frequency (RF) generator during the first state of a digital pulse signal, The steps include receiving a measured value of the amount of power reflected from the output of the RF generator during the first state, The steps include supplying power to the plasma chamber via the impedance matching circuit using the RF generator during the second state of the digital pulse signal, The steps include receiving a measured value of the amount of power reflected to the output of the RF generator during the second state, A step of controlling the parameters of the impedance matching circuit so as to reduce the amount of power measured during the first state to a minimum value and the amount of power measured during the second state to a minimum value, A medium that is equipped with these features. [Form 16] A non-temporary computer-readable medium as described in Embodiment 15, The minimum value of the first state is smaller than a predetermined level. The minimum value of the second state is smaller than the predetermined level of the medium. [Form 17] A non-temporary computer-readable medium as described in Embodiment 16, A medium in which the minimum value of the first state and the minimum value of the second state are within a predetermined threshold relative to each other. [Form 18] A non-temporary computer-readable medium as described in Embodiment 15, The minimum value of the first state is smaller than another minimum value of the first state. The other minimum value of the first state is achieved when the parameter has a first value, The minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value, in a medium. [Form 19] A non-temporary computer-readable medium as described in Embodiment 15, The minimum value of the first state is greater than another minimum value of the first state. The other minimum value of the first state is achieved when the parameter has a first value, The minimum value in the first state and the minimum value in the second state are achieved when the parameter has a second value. The other minimum value of the first state is smaller than a predetermined level. When the parameter has the first value, another minimum value of the second state is achieved. The other minimum value of the second state is a medium that is smaller than the predetermined level. [Form 20] A non-temporary computer-readable medium as described in Embodiment 15, The step of controlling the aforementioned parameters includes the step of controlling the capacitor or inductor of the impedance matching circuit, provided the medium is used.

Claims

1. A method for controlling an impedance matching circuit that reduces reflected power reflected from the plasma of a plasma chamber in multiple states, A step of controlling an RF generator to generate a high-frequency (RF) signal, wherein the RF signal is generated based on the plurality of states, A step of controlling the parameters of an impedance matching circuit to have a first value, wherein the parameters are controlled to have a first value in order to achieve a first amount of reflected power in one of the plurality of states and a second amount of reflected power in one of the plurality of states, wherein the first amount of reflected power falls within a predetermined threshold from the second amount of reflected power, and the impedance matching circuit is connected to the RF generator to receive the RF signal. Includes, A method wherein the reflected power of the first quantity in the plurality of states is greater than the reflected power of a third quantity in one of the first states among the plurality of states, and the reflected power of the third quantity is achieved when the parameter has a second value.

2. The method according to claim 1, The RF signal has multiple power levels in the multiple states, or multiple frequency levels in the multiple states, or the multiple power levels and the multiple frequency levels in the multiple states, and each of the multiple states is a logic level of a digital pulse signal, in a method.

3. The method according to claim 1, The parameter is the inductance or capacitance of the shunt circuit in the impedance matching circuit, the reflected power of the first, second, and third quantities is the power reflected from the plasma chamber toward the RF generator via the RF transmission line, the impedance matching circuit, and the RF cable, the first value is a first value of the capacitance or inductance, and the second value is a second value of the capacitance or inductance, in the method.

4. The method according to claim 3, The shunt circuit is connected to ground potential at one end and connected between the input and output of the impedance matching circuit at the other end.

5. The method according to claim 4, The method wherein the shunt circuit is an inductor or a capacitor.

6. The method according to claim 1, The parameter is the inductance or capacitance of a series circuit in the impedance matching circuit, the reflected power of the first, second, and third quantities is the power reflected from the plasma chamber toward the RF generator via the RF transmission line, the impedance matching circuit, and the RF cable, the first value is a first value of the capacitance or inductance, and the second value is a second value of the capacitance or inductance, in the method.

7. The method according to claim 6, The series circuit is a capacitor or inductor connected between the input and output of the impedance matching circuit, in the method.

8. The method according to claim 1, A method wherein the RF generator is controlled by a processor, and the parameters of the impedance matching circuit are controlled by the processor via a driver and a motor.

9. A computer for controlling an impedance matching circuit that reduces reflected power reflected from the plasma of a plasma chamber in multiple states, It is a processor, The RF generator is controlled to generate a high-frequency (RF) signal, and the RF signal is generated based on the plurality of states. The parameters of the impedance matching circuit are controlled to have a first value, the parameters being controlled to have a first value in order to achieve a first amount of reflected power in one of the first states of the plurality of states, and to achieve a second amount of reflected power in one of the second states of the plurality of states, the first amount of reflected power being within a predetermined threshold from the second amount of reflected power, and the impedance matching circuit is connected to the RF generator to receive the RF signal. The reflected power of the first quantity in the plurality of states is greater than the reflected power of the third quantity in one of the first states among the plurality of states, and the reflected power of the third quantity is achieved when the parameter has a second value. A processor configured in such a way, A memory device connected to the aforementioned processor, A computer equipped with the following features.

10. The computer according to claim 9, The RF signal has multiple power levels in the multiple states, or multiple frequency levels in the multiple states, or the multiple power levels and the multiple frequency levels in the multiple states, each of the multiple states being a logic level of a digital pulse signal, in a computer.

11. The computer according to claim 9, The parameter is the inductance or capacitance of the shunt circuit in the impedance matching circuit, the reflected power of the first, second, and third quantities is the power reflected from the plasma chamber toward the RF generator via the RF transmission line, the impedance matching circuit, and the RF cable, the first value is a first value of the capacitance or inductance, and the second value is a second value of the capacitance or inductance, in a computer.

12. A computer according to claim 11, The aforementioned shunt circuit is connected to ground potential at one end and to the input and output of the impedance matching circuit at the other end, in a computer.

13. A computer according to claim 12, The aforementioned shunt circuit is an inductor or capacitor, in a computer.

14. The computer according to claim 9, The parameter is the inductance or capacitance of a series circuit in the impedance matching circuit, the reflected power of the first, second, and third quantities is the power reflected from the plasma chamber toward the RF generator via the RF transmission line, the impedance matching circuit, and the RF cable, the first value is a first value of the capacitance or inductance, and the second value is a second value of the capacitance or inductance, in a computer.

15. A computer according to claim 14, The series circuit is a capacitor or inductor connected between the input and output of the impedance matching circuit, in a computer.

16. The computer according to claim 9, The parameters of the impedance matching circuit are controlled by the processor via the driver and motor of the computer.

17. It is a plasma system, A radio frequency (RF) generator, An impedance matching circuit connected to the RF generator for receiving an RF signal, configured to output a modulated RF signal based on the RF signal, A plasma chamber connected to the impedance matching circuit for receiving the modulated RF signal, A computer connected to the RF generator and the impedance matching circuit, The RF generator is controlled to generate the RF signal based on multiple states, The parameters of the impedance matching circuit are controlled to have a first value, the parameters being controlled to have a first value in order to achieve a first amount of reflected power in one of the multiple states, and to achieve a second amount of reflected power in one of the multiple states, the first amount of reflected power being within a predetermined threshold from the second amount of reflected power. The reflected power of the first quantity in the plurality of states is greater than the reflected power of the third quantity in one of the first states among the plurality of states, and the reflected power of the third quantity is achieved when the parameter has a second value. A computer and, A plasma system equipped with [the necessary components].

18. A plasma system according to claim 17, A plasma system in which the RF signal has multiple power levels in the multiple states, or multiple frequency levels in the multiple states, or multiple power levels and multiple frequency levels in the multiple states, each of the multiple states being a logic level of a digital pulse signal.

19. A plasma system according to claim 17, A plasma system in which the parameter is the inductance or capacitance of a shunt circuit in the impedance matching circuit, the reflected power of the first, second, and third quantities is the power reflected from the plasma chamber toward the RF generator via the RF transmission line, the impedance matching circuit, and the RF cable, the shunt circuit is connected to ground potential at one end and connected at the other end between the input and output of the impedance matching circuit, the first value is a first value of the capacitance or inductance, and the second value is a second value of the capacitance or inductance.

20. A plasma system according to claim 17, A plasma system in which the parameter is the inductance or capacitance of a series circuit in the impedance matching circuit, the reflected power of the first, second, and third quantities is the power reflected from the plasma chamber toward the RF generator via the RF transmission line, the impedance matching circuit, and the RF cable, the series circuit is a capacitor or inductor connected between the input and output of the impedance matching circuit, the first value is a first value of the capacitance or inductance, and the second value is a second value of the capacitance or inductance.

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