Semiconductor integrated circuits, PLL circuits, and signal processing devices

Abstract

To provide a semiconductor integrated circuit, a PLL circuit and a signal processing device in which a frequency adjustment range can be expanded.SOLUTION: A semiconductor integrated circuit comprises: an oscillation circuit that has a first logical inversion element and a second logical inversion element which output a differential oscillation signal; a current source that can inject current into the oscillation circuit; a first current control circuit that injects the current from the current source into an output node of the first logical inversion element by synchronizing with a first signal synchronizing with a clock signal; and a second current control circuit that draws the current from the output node of the second logical inversion element into a reference voltage node by synchronizing with a second signal synchronizing with the clock signal.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor integrated circuit, a PLL circuit, and a signal processing device.

Background Art

[0002] An oscillation circuit is known that periodically shorts the output nodes of a pair of inverters that output differential oscillation signals in synchronization with an input clock signal. This type of oscillation circuit is configured by connecting a plurality of pairs of inverters including a pair of inverters in a ring shape. When the output nodes of the pair of inverters are not shorted, a free-running oscillation signal with an indefinite frequency is output.

[0003] In this type of oscillation circuit, it is possible to adjust the frequency of the free-running oscillation signal to a frequency lower than this frequency, but it is not easy to increase (raise) the frequency of the free-running oscillation signal. Therefore, there is a problem that the frequency adjustment range is limited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, one embodiment of the present invention provides a semiconductor integrated circuit, a PLL circuit, and a signal processing device that can preferably widen the frequency adjustment range of an oscillation signal.

Means for Solving the Problems

[0006] To solve the above problems, according to one embodiment of the present invention, an oscillation circuit having a first logic inverter and a second logic inverter that output differential oscillation signals, and <,000034>A current source capable of injecting current into the oscillation circuit, A first current control circuit that injects current from the current source into the output node of the first logic inverting element in synchronization with a first signal synchronized with the clock signal, A semiconductor integrated circuit is provided, comprising a second current control circuit that, in synchronization with a second signal synchronized with the clock signal, draws current from the output node of the second logic inverting element to a reference voltage node. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing the schematic configuration of a PLL circuit comprising a semiconductor integrated circuit according to the first embodiment. [Figure 2] Block diagram of a signal processing device equipped with a PLL circuit, as shown in Figure 1. [Figure 3] A circuit diagram showing the circuit configurations of VIC and ILICO in Figure 1. [Figure 4] Timing diagram for input clock signal INJCLK, second signal INJ, first signal INJB, and oscillation signal ILCK. [Figure 5] Figure 3 shows the frequency range of the oscillation signal output from ILICO. [Figure 6] A circuit diagram showing the circuit configurations of VIC and ILICO in one comparative example. [Figure 7] Figure 6 shows the timing diagram of ILICO for one comparative example. [Figure 8] Figure 6 is a diagram illustrating the frequency range of the oscillation signal output from ILICO. [Figure 9] A circuit diagram showing the circuit configuration of VIC and ILICO according to the second embodiment. [Figure 10] Figure 9 shows the timing diagram of each signal in ILICO. [Figure 11] Figure 9 is a diagram illustrating the frequency range of the oscillation signal output from ILICO. [Figure 12] A circuit diagram showing the circuit configuration of VIC and ILICO according to the third embodiment. [Figure 13]A circuit diagram showing the circuit configuration of VIC and ILICO according to one modified example of the third embodiment. [Modes for carrying out the invention]

[0008] The semiconductor integrated circuit, PLL circuit, and signal processing apparatus according to the embodiment will be described below with reference to the drawings. The following description will focus on the main components of the semiconductor integrated circuit, PLL circuit, and signal processing apparatus, but there may be components and functions not shown or described in the drawings. The following description does not exclude any components or functions not shown or described.

[0009] (First Embodiment) Figure 1 is a block diagram showing a schematic configuration of a PLL (Phase Locked Loop) circuit 2 equipped with a semiconductor integrated circuit 1 according to the first embodiment.

[0010] The PLL circuit 2 in Figure 1 comprises an injection-locked current (I) control oscillator (ILICO) 3, a current (I) control oscillator (ICO) 4, a first level shifter (L / S) 5, a second level shifter (L / S) 6, a divider (DIV) 7, a phase frequency detector (PFD) 8, a charge pump (CP) 9, a loop filter (LPF) 10, a voltage-current converter (VIC) 11, and a pulse generator (PulseGen) 12.

[0011] The PLL circuit 2 in Figure 1 receives the reference oscillation signal CKREF output from the oscillator (OSC) 13 and the input clock signal INJCLK from the input / output interface circuit (I / O) 14.

[0012] ILICO3 is a current-controlled oscillator having an injection lock function. As will be described later, ILICO3 locks the oscillation frequency by injecting current from the current source VIC11 and extracting current to a reference voltage node (for example, a ground voltage node) by the injection lock function. ILICO3 generates and outputs an oscillation signal ILCK having the same frequency as the frequency of the input clock signal INJCLK input to the PLL circuit 2.

[0013] ICO4 is a current-controlled oscillator without an injection lock function. ICO4 generates and outputs an oscillation signal synchronized with the reference oscillation signal CKREF from OSC13. More specifically, ICO4 generates and outputs an oscillation signal having a frequency obtained by multiplying the frequency of the reference oscillation signal CKREF.

[0014] The first L / S 5 converts the signal level of the oscillation signal output from ICO4. For example, the first L / S 5 increases the signal amplitude of the oscillation signal output from ICO4. The second L / S 6 converts the signal level of the oscillation signal ILCK output from ILICO3. For example, the second L / S 6 increases the signal amplitude of the oscillation signal ILCK output from ILICO3. The oscillation signal ILCLK output from the second L / S 6 becomes the oscillation signal ILCLK output from the PLL circuit 2.

[0015] DIV7 divides the oscillation signal output from the first L / S 5 to generate a divided signal. The division ratio of DIV7 is arbitrary. PFD8 detects the phase difference and frequency difference between the divided signal output from DIV7 and the reference oscillation signal CKREF from OSC13, and outputs a signal according to the phase difference and frequency difference.

[0016] CP9 generates a current signal corresponding to the output signal of PFD8. LPF10 removes unwanted frequency components from the current signal output from CP9 to generate a control voltage V_LPF. VIC11 generates a current signal corresponding to the control voltage V_LPF. The current signal generated by VIC11 is supplied to ILICO3 and ICO4. ILICO3 and ICO4 control the frequency of the oscillation signal according to the current signal generated by VIC11. More specifically, ICO4 performs frequency control so that it outputs an oscillation signal with a frequency that is a multiplication of the frequency of the reference oscillation signal CKREF. ILICO3 performs frequency control so that it outputs an oscillation signal with the same frequency as the input clock signal INJCLK from I / O14.

[0017] The pulse generator 12 generates a second signal INJ in synchronization with the input clock signal INJCLK from I / O 14. The second signal INJ is a pulse signal with a pulse width synchronized with the rising or falling edge of the input clock signal INJCLK. The second signal INJ generated by the pulse generator 12 is input to ILICO 3. The ICO (second oscillator) 4 in Figure 1 is PLL controlled by a feedback control circuit consisting of the first L / S 5, DIV 7, PFD 8, CP 9, LPF 10, and VIC 11. On the other hand, the ILICO (first oscillator) 3 is not PLL controlled.

[0018] The semiconductor integrated circuit 1 according to this embodiment includes at least ILICO3 in Figure 1. The semiconductor integrated circuit 1 according to this embodiment may also include at least one block other than ILICO3 in the PLL circuit 2 in Figure 1.

[0019] Figure 2 is a block diagram of a signal processing device 20 equipped with the PLL circuit 2 of Figure 1. The signal processing device 20 in Figure 2 comprises the PLL circuit 2 and a signal processing circuit 21. The oscillation signal ILCLK output from the PLL circuit 2 is input to the signal processing circuit 21. The signal processing circuit 21 performs various signal processing in synchronization with the oscillation signal ILCLK output from the PLL circuit 2. The specific content of the signal processing performed by the signal processing circuit 21 is not specified.

[0020] The signal processing circuit 21 may, for example, have the function of a memory control unit that controls a memory device (not shown). In this case, the signal processing circuit 21 controls the writing of data to the memory device and the reading of data from the memory device in synchronization with the oscillation signal ILCLK output from the PLL circuit 2.

[0021] For example, a control circuit 22 is connected to I / O 14, which inputs the input clock signal INJCLK to the PLL circuit 2. The control circuit 22 generates the input clock signal INJCLK. I / O 14 buffers the input clock signal INJCLK from the control circuit 22 and inputs it to the pulse generator 12 of the PLL circuit 2. Specifically, the control circuit 22 is a CPU (Central Processing Unit), etc.

[0022] Figure 3 is a circuit diagram showing the circuit configuration of VIC11 and ILICO3 in Figure 1. VIC11 functions as a current source that supplies current to ILICO3 according to the control voltage V_LPF output from LPF10.

[0023] As shown in Figure 3, VIC11 has three PMOS transistors Q1-Q3 and one NMOS transistor Q4. PMOS transistors Q1 and NMOS transistor Q4 are cascode-connected between the power supply voltage node VDD and the ground voltage node VSS. More specifically, the source of PMOS transistor Q1 is connected to the power supply voltage node VDD, and its drain is connected to the drain of NMOS transistor Q4. The source of NMOS transistor Q4 is connected to the ground voltage node VSS. The gate of NMOS transistor Q4 is input to the control voltage V_LPF output from LPF10.

[0024] The gates of PMOS transistors Q1, Q2, and Q3 are connected to each other, and their sources are connected to the power supply voltage node VDD. This allows PMOS transistors Q1, Q2, and Q3 to form a current mirror circuit.

[0025] The voltage level of the control voltage V_LPF output from LPF10 changes the current flowing between the source and drain of PMOS transistor Q1. A current proportional to the current flowing between the source and drain of PMOS transistor Q1 flows between the source and drain of PMOS transistor Q2 and PMOS transistor Q3. The drains of PMOS transistor Q2 and PMOS transistor Q3 are connected to ILICO3.

[0026] In this way, the source-drain current of PMOS transistors Q1, Q2, and Q3 can be controlled according to the voltage level of the control voltage V_LPF output from LPF10.

[0027] ILICO3 in Figure 3 comprises an oscillation circuit 31, a first current control circuit 32, and a second current control circuit 33.

[0028] The oscillation circuit 31 has a pair of inverters 34 and 35 that output differential oscillation signals. In this specification, the pair of inverters 34 and 35 are referred to as the first inverter 34 and the second inverter 35. As will be described later, the oscillation circuit 31 has a first series circuit 38 having a plurality of first inverters 34 and a second series circuit 39 having a plurality of second inverters 35. The oscillation signal ILCK output from the first series circuit 38 or the second series circuit 39 is output from the oscillation circuit 31 and input to the second L / S6 in Figure 1.

[0029] The first current control circuit 32 injects current from VIC11 into the output node of the first inverter 34 in synchronization with the first signal INJB, which is synchronized with the input clock signal INJCLK. The second current control circuit 33 draws current from the output node of the second inverter 35 to the reference voltage node in synchronization with the second signal INJ, which is synchronized with the input clock signal INJCLK. The reference voltage node is a node with a fixed voltage level, and in this specification, the example in which the reference voltage node is a ground voltage node VSS will be mainly described.

[0030] In this way, the oscillator circuit 31 injects current into the output node of the first inverter 34 and withdraws current from the output node of the second inverter 35 in synchronization with the first signal INJB and the second signal INJ, which are synchronized with the input clock signal INJCLK. This makes it possible not only to lower the oscillation frequency of the oscillator circuit 31 but also to raise it, thereby widening the frequency adjustment range.

[0031] Each of the first inverter 34 and the second inverter 35 has a first power terminal and a second power terminal. The first power terminal of the first inverter 34 and the second inverter 35 is supplied with the current generated in the VIC 11. More specifically, the first power terminal of the first inverter 34 and the second inverter 35 is supplied with the source-drain current of transistor Q2 in the VIC 11.

[0032] The second power terminals of the first inverter 34 and the second inverter 35 are connected to the ground voltage node VSS.

[0033] Two inverters (hereinafter referred to as third inverters) 36 and 37 are connected between the output node of the first inverter 34 and the output node of the second inverter 35, in opposite directions. By connecting the two third inverters 36 and 37 in opposite directions, the output nodes of the first inverter 34 and the second inverter 35 can be inverted. As a result, differential oscillation signals with a phase difference of 180 degrees are output from the output nodes of the pair of inverters 34 and 35 (first inverter 34 and second inverter 35).

[0034] More specifically, the oscillation circuit 31 has a first series circuit 38 and a second series circuit 39. The first series circuit 38 has two or more first inverters 34 connected in series. The second series circuit 39 has two or more second inverters 35 connected in series.

[0035] The output node of the final stage first inverter 34 in the first series circuit 38 is connected to the input node of the first stage first inverter 34. In other words, the first series circuit 38 constitutes a ring oscillator. Similarly, the output node of the final stage second inverter 35 in the second series circuit 39 is connected to the input node of the first stage second inverter 35. In other words, the second series circuit 39 constitutes a ring oscillator.

[0036] The number of connection stages of the first inverter 34 in the first series circuit 38 and the number of connection stages of the second inverter 35 in the second series circuit 39 are the same. The number of connection stages of the first inverter 34 in the first series circuit 38 and the number of connection stages of the second inverter 35 in the second series circuit 39 must be the same, but the number of connection stages themselves can be adjusted arbitrarily. More specifically, the number of connection stages can be two or more, and it can be an odd number or an even number. The specific circuit configuration when the number of connection stages is even will be described later.

[0037] The first current control circuit 32 injects current from the current source VIC11 into the output node of any inverter 34 in the first series circuit 38, in synchronization with the first signal INJB, which is synchronized with the input clock signal INJCLK. The second current control circuit 33 injects current from the output node of any inverter 35 in the second series circuit 39, in synchronization with the second signal INJ, which is synchronized with the input clock signal INJCLK.

[0038] As described above, the pulse generator 12 generates a first signal INJB and a second signal INJ, which are pulse signals synchronized with the rising or falling edge of the input clock signal INJCLK. The first current control circuit 32 injects current into one of the output nodes of the first inverter 34 in the first series circuit 38 when the level of the first signal INJB generated by the pulse generator 12 is active (low). The second current control circuit 33 draws current from one of the output nodes of the second inverter 35 in the second series circuit 39 when the level of the second signal INJ is active (high).

[0039] In this manner, the first current control circuit 32 injects current into one of the output nodes of the first inverter 34 in synchronization with the rising or falling edge of the input clock signal INJCLK. The second current control circuit 33 withdraws current from one of the output nodes of the second inverter 35 in synchronization with the rising or falling edge of the input clock signal INJCLK. This allows for frequency control, where the oscillation frequency of a free-running oscillation signal with an undefined oscillation frequency in the oscillation circuit 31 is raised or lowered to match the oscillation frequency of the input clock signal INJCLK.

[0040] More specifically, the first current control circuit 32 injects current into the output node of the first inverter 34 at a certain connection stage (the first stage in the example of Figure 3) within the first series circuit 38. The second current control circuit 33 extracts current from the output node of the second inverter 35 at a certain connection stage (the first stage in the example of Figure 3) within the second series circuit 39. In other words, the first current control circuit 32 and the second current control circuit 33 inject and extract current from the output nodes of the first inverter 34 and the second inverter 35 at the same connection stage (the first stage in the example of Figure 3) within the first series circuit 38 and the second series circuit 39.

[0041] The first current control circuit 32 includes, for example, a PMOS transistor Q5. The source of PMOS transistor Q5 is connected to the drain of PMOS transistor Q3 in VIC11. The drain of PMOS transistor Q5 is connected to, for example, the output node of the first inverter 34 in the first stage of the first series circuit 38. The gate of PMOS transistor Q5 is input to the inverted signal INJB of the second signal INJ generated by the pulse generator 12. When the second signal INJ goes high, its inverted signal INJB goes low, and PMOS transistor Q5 turns on. This causes the source-drain current of PMOS transistor Q3 in VIC11 to be injected through the source-drain of PMOS transistor Q5 into the output node of the first inverter 34 in the first stage.

[0042] The second current control circuit 33 includes, for example, an NMOS transistor Q6. The drain of the NMOS transistor Q6 is connected to the output node of the first-stage second inverter 35 in the second series circuit 39. The source of the NMOS transistor Q6 is connected to the ground voltage node VSS. The gate of the NMOS transistor Q6 is input to the second signal INJ generated by the pulse generator 12. Synchronized with the rising edge of the input clock signal INJCLK, the second signal INJ goes high, and the NMOS transistor Q6 turns on. This draws current from the output node of the first-stage second inverter 35 to the ground voltage node VSS.

[0043] In Figure 3, current is injected into the output node of the first inverter 34 in the first stage of the first series circuit 38, and current is withdrawn from the output node of the second inverter 35 in the first stage of the second series circuit 39. However, current may also be injected into the output node of the first inverter 34 at any connection stage other than the first stage in the first series circuit 38, and current may be withdrawn from the output node of the second inverter 35 at the same connection stage in the second series circuit 39.

[0044] Figure 4 shows the timing diagram of the input clock signal INJCLK input from I / O14 to PLL circuit 2, the second signal INJ generated by pulse generator 12, its inverted signal INJB, and the oscillation signal ILCK output from ILICO3.

[0045] The period from time t1 to t2 is the stop period of the input clock signal INJCLK. During this period, ILICO3 outputs a free-running oscillation signal ILCK whose oscillation frequency depends on the oscillation frequency of oscillator 13. When the input clock signal INJCLK is input at time t2, the pulse generator 12 generates a first signal INJB and a second signal INJ, which are pulse signals with a certain pulse width synchronized with the rising edge of the input clock signal INJCLK. The pulse width during the high period of the second signal INJ and the pulse width during the low period of the first signal INJB have a time width shorter than half a period of the input clock signal INJCLK. Alternatively, the pulse generator 12 may generate either the first signal INJB or the second signal INJ based on the input clock signal INJCK, and the other of the first signal INJB and the second signal INJ may be generated by an inverter provided downstream of the pulse generator 12.

[0046] During the period when the first signal INJB is low, i.e., for a certain pulse width of the first signal INJB, the first current control circuit 32 injects current from the current source VIC11 into the output node of the first inverter 34 of the first stage. Also, during the period when the second signal INJ is high, i.e., for a certain pulse width of the second signal INJ, the first current control circuit 32 draws current from the output node of the second inverter 35 of the first stage to the ground voltage node VSS. As a result, the oscillator circuit 31 outputs an oscillator signal ILCK with the same frequency as the input clock signal INJCLK.

[0047] Figure 5 shows the frequency range of the oscillation signal ILCK output from ILICO3 in Figure 3. The horizontal length in Figure 5 indicates the frequency range that can be adjusted by ILICO3. 0% in Figure 5 indicates that the free-run frequency matches the target frequency. To the left of 0% is the frequency range (hereinafter referred to as the first frequency range) fr1, in which the free-run frequency can be raised to the target frequency when the free-run frequency is lower than the target frequency. To the right of 0% is the frequency range (hereinafter referred to as the second frequency range) fr2, in which the free-run frequency can be lowered to the target frequency when the free-run frequency is higher than the target frequency.

[0048] Figure 6 is a circuit diagram showing the circuit configurations of VIC110 and ILICO30 in one comparative example. In Figure 6, the same reference numerals are used for circuit parts that are common to Figure 3, and the differences from Figure 3 will be explained below. The VIC110 in Figure 6 has PMOS transistors Q1 and Q2 and an NMOS transistor Q4. The connection relationship of these transistors Q1, Q2, and Q4 is the same as in Figure 3. A current corresponding to the control voltage V_LPF output from LPF10 flows between the source and drain of PMOS transistor Q1. PMOS transistors Q1 and Q2 constitute a current mirror circuit. Therefore, a current corresponding to the control voltage V_LPF output from LPF10 flows between the source and drain of PMOS transistor Q2. This current is supplied to the first power supply terminals of the first inverter 34 and the second inverter 35 of each stage in the first series circuit 38 and the second series circuit 39 in the oscillator circuit 31.

[0049] Similar to Figure 3, two third inverters 36 and 37 are connected in opposite directions between the output nodes of the first inverter 34 and the second inverter 35 in each stage of the first series circuit 38 and the second series circuit 39.

[0050] Furthermore, an NMOS transistor Q7 is connected between the output node of the first inverter 34 and the output node of the second inverter 35 in either of the connection stages (e.g., the first stage) within the first series circuit 38 and the second series circuit 39. Specifically, the drain of transistor Q7 is connected to the output node of the first inverter 34, and the source of transistor Q7 is connected to the output node of the second inverter 35.

[0051] The gate of transistor Q7 is input to the second signal INJ output from pulse generator 12. The transistor is temporarily turned on at the timing of the rising or falling edge of the input clock signal INJCLK input from I / O 14, short-circuiting the output nodes of the first inverter 34 and the second inverter 35. This makes it possible to match the oscillation frequency of the oscillation signal ILCK output from oscillation circuit 31a to the oscillation frequency of the input clock signal INJCLK.

[0052] The ILICO30 in Figure 6 lacks the first current control circuit 32 and the second current control circuit 33 shown in Figure 3. Also, the VIC110 in Figure 6 lacks the PMOS transistor Q3 shown in Figure 3. Therefore, the ILICO30 in Figure 6 does not inject current into the output node of the first inverter 34 of the first stage, nor does it withdraw current from the output node of the second inverter 35 of the first stage. Instead, the ILICO30 in Figure 6 uses a second signal INJ, synchronized with the rising edge of the input clock signal INJCLK, to short-circuit the output node of the first inverter 34 and the output node of the second inverter 35 of the first stage using transistor Q7.

[0053] Figure 7 is a timing diagram of ILICO30 relating to one comparative example shown in Figure 6. The timing diagram in Figure 7 is substantially the same as that in Figure 4, except that the first signal INJB, which is the inverse signal of the second signal INJ, is absent. The pulse generator 12 generates the second signal INJ of a certain pulse width in synchronization with the rising edge of the input clock signal INJCLK. Transistor Q7 in ILICO30 turns on for a certain pulse width of the second signal INJ, short-circuiting the output node of the first stage first inverter 34 and the output node of the first stage second inverter 35.

[0054] Figure 8 is a diagram illustrating the frequency range of the oscillation signal output from ILICO30 in Figure 6. As shown in Figure 8, ILICO30 in one comparative example in Figure 6 has a narrower first frequency range fr1, which allows the free-running frequency to be raised to the target frequency when it is lower than the target frequency, and a narrower second frequency range fr2, which allows the free-running frequency to be lowered to the target frequency when it is higher than the target frequency, compared to ILICO3 in the first embodiment in Figure 3.

[0055] Thus, in the first embodiment, current is injected into the output node of the first inverter 34 of any connection stage in the oscillator circuit 31, and current is withdrawn from the output node of the second inverter 35 of the same connection stage, in synchronization with the rising or falling edge of the input clock signal INJCLK. With this configuration, the oscillation frequency of the ILICO3 oscillation signal ILCK can be locked even if the oscillation frequency of the input clock signal INJCLK is over a wide range.

[0056] In particular, according to this embodiment, in the oscillation circuit 31, not only can the second frequency range fr2, in which the free-run frequency can be lowered to the target frequency when the free-run frequency is higher than the target frequency, be widened, but the first frequency range fr1, in which the free-run frequency can be raised to the target frequency when the free-run frequency is lower than the target frequency, can also be widened.

[0057] (Second embodiment) In the first embodiment, the first current control circuit 32 and the second current control circuit 33 performed current control on only one of the rising or falling edges of the input clock signal INJCLK, but a configuration in which current control is performed on both edges is also possible.

[0058] Figure 9 is a circuit diagram showing the circuit configuration of VIC11 and ILICO3a according to the second embodiment. VIC11 in Figure 9 is configured in the same way as VIC11 in Figure 3. ILICO3a in Figure 9 includes an oscillator circuit 31 with the same circuit configuration as in Figure 3, a first current control circuit 32a with a different circuit configuration than in Figure 3, and a second current control circuit 33a with a different circuit configuration than in Figure 3.

[0059] The first current control circuit 32a in Figure 9 has a PMOS transistor Q5 similar to that in Figure 3, as well as a PMOS transistor Q8. The source of transistor Q8 is connected to the drain of transistor Q3, and the drain of transistor Q8 is connected to the output node of the second inverter 35 of any connecting stage (e.g., the first stage) in the second series circuit 39.

[0060] In the following, the pulse signal input to the gate of transistor Q5 will be referred to as the first signal INJB, the pulse signal input to the gate of transistor Q6 as the second signal INJ, the pulse signal input to the gate of transistor Q8 as the third signal INJ2B, and the pulse signal input to the gate of transistor Q9 as the fourth signal INJ2. The pulse generator 12 generates the second signal INJ and its inverted signal, the first signal INJB, of a certain pulse width in synchronization with the rising edge of the input clock signal INJCLK, and generates the fourth signal INJ2 and its inverted signal, the third signal INJ2B, of a certain pulse width in synchronization with the falling edge of the input clock signal INJCLK.

[0061] The second current control circuit 33a in Figure 9 has an NMOS transistor Q6 similar to that in Figure 3, as well as an NMOS transistor Q9. The drain of transistor Q9 is connected to the output node of the first inverter 34 of any connecting stage (e.g., the first stage) in the first series circuit 38, and the source of transistor Q9 is connected to the ground voltage node VSS. The gate of transistor Q9 is input to the fourth signal INJ2.

[0062] More specifically, the first current control circuit 32a in Figure 9 is synchronized with the first signal INJB and injects current into the output node of any inverter 34 in the first series circuit 38, and is synchronized with the third signal INJ2B and injects current into the output node of any inverter 35 in the second series circuit 39. The second current control circuit 33a is synchronized with the second signal INJ and withdraws current from the output node of any inverter 35 in the second series circuit 39, and is synchronized with the fourth signal INJ2 and withdraws current from the output node of any inverter 34 in the first series circuit 38.

[0063] Figure 10 is a timing diagram of each signal in ILICO3a in Figure 9. When the rising edge of the input clock signal INJCLK is input at time t11, the pulse generator 12 generates a second signal INJ and a first signal INJB of a certain pulse width. As a result, transistor Q5 in the first current control circuit 32a turns on, and a current corresponding to the control voltage V_LPF output from LPF10 is injected into the output node of the first stage first inverter 34 via the source-drain junction of transistor Q3 and the source-drain junction of transistor Q5. At the same time, transistor Q6 in the second current control circuit 33a turns on, and current is drawn from the output node of the first stage second inverter 35 to the ground voltage node VSS.

[0064] When the falling edge of the input clock signal INJCLK is input at time t12, the pulse generator 12 generates a fourth signal INJ2 and a third signal INJ2B of a certain pulse width. This turns on transistor Q8 in the first current control circuit 32a, and a current corresponding to the control voltage V_LPF output from LPF 10 is injected into the output node of the first stage second inverter 35 via the source-drain junction of transistor Q3 and the source-drain junction of transistor Q8. At the same time, transistor Q9 in the second current control circuit 33a is turned on, and current is drawn from the output node of the first stage first inverter 34 to the ground voltage node VSS. At time t13, the same operation as at time t11 is performed.

[0065] Figure 11 is a diagram illustrating the frequency range of the oscillation signal output from ILICO3a in Figure 9. In addition to the frequency range of ILICO3a in Figure 9, Figure 11 also shows, for comparison, the frequency range of the first embodiment in Figure 5 and the frequency range of one comparative example in Figure 8.

[0066] ILICO3a in Figure 9 can further widen the first frequency range fr1, which allows the free-running frequency to be raised to the target frequency when it is lower than the target frequency, compared to the frequency range in Figure 5. Similarly, ILICO3a in Figure 9 can further widen the second frequency range fr2, which allows the free-running frequency to be lowered to the target frequency when it is higher than the target frequency, compared to the frequency range in Figure 5.

[0067] Thus, in the second embodiment, current is injected into one of the output nodes of the first stage first inverter 34 and the first stage second inverter 35, and current is withdrawn from the other, in synchronization with both the rising and falling edges of the input clock signal INJCLK. Therefore, the frequency range of ILICO3a, whose oscillation frequency can be varied to match the oscillation frequency of the input clock signal INJCLK, can be widened compared to the first embodiment.

[0068] (Third embodiment) ILICO3 and 3a according to the first and second embodiments include an oscillator circuit 31 having a first series circuit 38 having an odd number of first inverters 34 connected in series (for example, 3 stages), and a second series circuit 39 having an odd number of second inverters 35 connected in series. The number of connection stages of the first inverters 34 in the first series circuit 38 and the number of connection stages of the second inverters 35 in the second series circuit 39 may be an even number.

[0069] Figure 12 is a circuit diagram showing the circuit configuration of VIC11 and ILICO3b according to the third embodiment. In Figure 12, components common to Figure 3 are denoted by the same reference numerals. ILICO3b in Figure 12 includes an oscillator circuit 31b. The oscillator circuit 31b includes a first series circuit 38a having an even number of stages (e.g., two stages) of first inverters 34 connected in series, and a second series circuit 39a having an even number of stages of second inverters 35 connected in series. Two third inverters 36 and 37, facing in opposite directions, are connected to the output nodes of the first inverter 34 and the second inverter 35 of each stage.

[0070] The connections of the output nodes of the first series circuit 38a and the second series circuit 39a in Figure 12 are different from the connections of the output nodes of the first series circuit 38 and the second series circuit 39 in Figure 3. In Figure 12, the output node of the final stage first inverter 34 in the first series circuit 38a is connected to the input node of the first stage second inverter 35 in the second series circuit 39a. Also, the output node of the final stage second inverter 35 in the second series circuit 39a is connected to the input node of the first stage first inverter 34 in the first series circuit 38a.

[0071] In the first series circuit 38a in Figure 12, the first current control circuit 32 is connected to the output node of the first inverter 34 of one of the connection stages (e.g., the first stage), and the second current control circuit 33 is connected to the output node of the second inverter 35 of the same connection stage.

[0072] The VIC11 and ILICO3b in Figure 12 have the same circuit operation as in Figure 3, except that the number of connection stages of the first inverter 34 in the first series circuit 38a and the number of connection stages of the second inverter 35 in the second series circuit 39a are different. By injecting current into the output node of the first stage first inverter 34 and withdrawing current from the output node of the first stage second inverter 35 in synchronization with the rising or falling edge of the input clock signal INJCLK, the frequency range of ILICO3b, whose oscillation frequency can be locked to match the oscillation frequency of the input clock signal INJCLK, can be expanded.

[0073] Figure 13 is a circuit diagram showing the circuit configuration of VIC11 and ILICO3c according to a modified example of the third embodiment. In Figure 13, components common to Figure 9 are denoted by the same reference numerals, and the following explanation will focus on the differences from Figure 9.

[0074] The first series circuit 38a and the second series circuit 39a in ILICO3c shown in Figure 13 are configured in the same way as in Figure 12, but the connection destinations of their respective output nodes are different from those of the first series circuit 38 and the second series circuit 39 in Figure 9. The first series circuit 38a and the second series circuit 39a each have an even-numbered first inverter 34 and a second inverter 35.

[0075] In ILICO3c shown in Figure 13, current is injected into either the output node of the first inverter 34 or the output node of the second inverter 35, for example, and withdrawn from the other, in synchronization with not only the rising edge but also the falling edge of the input clock signal INJCLK. Therefore, it is possible to lock to the frequency of the input clock signal INJCLK over a wider frequency range than ILICO3b shown in Figure 12.

[0076] Thus, in the third embodiment, the number of connection stages between the first inverter 34 and the second inverter 35 in the first series circuit 38a and the second series circuit 39a within ILICO3c is set to an even number (at least two stages). This allows for the construction of an ILICO3c with a smaller circuit size, and makes it possible to raise or lower the free-run frequency over a wide frequency range to match the target frequency.

[0077] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not deviate from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0078] This embodiment can be summarized as follows. [Note 1] An oscillator circuit having a first logic inverting element and a second logic inverting element that output differential oscillation signals, A current source capable of injecting current into the oscillation circuit, A first current control circuit that injects current from the current source into the output node of the first logic inverting element in synchronization with a first signal synchronized with the clock signal, A semiconductor integrated circuit comprising: a second current control circuit that, in synchronization with a second signal synchronized with the clock signal, draws current from the output node of the second logic inverting element to a reference voltage node. [Note 2] The first logic inversion element and the second logic inversion element are semiconductor integrated circuits as described in Appendix 1, connected to the reference voltage node. [Note 3] The aforementioned reference voltage node is a ground voltage level node, as described in Appendix 1, in the semiconductor integrated circuit. [Note 4] The aforementioned oscillator circuit is A first series circuit having two or more of the first logic inverting elements connected in series, A second series circuit having two or more of the second logic inverting elements connected in series, The output node of the final stage first logic inverter element in the first series circuit is connected to the input node of the first stage first logic inverter element in the first series circuit. The output node of the final stage second logic inverter element in the second series circuit is connected to the input node of the first stage second logic inverter element in the second series circuit. The first current control circuit, in synchronization with the first signal, injects current from the current source into the output node of the first logic inverter element in any stage of the first series circuit. The semiconductor integrated circuit as described in Appendix 1, wherein the second current control circuit, in synchronization with the second signal, draws current from the output node of the second logic inverting element in any stage of the second series circuit. [Note 5] The number of connection stages of the first logic inverting element in the first series circuit is odd, The semiconductor integrated circuit described in Appendix 4, wherein the number of connection stages of the second logic inverting elements in the second series circuit is the same as the number of connection stages of the first logic inverting elements in the first series circuit. [Note 6] The aforementioned oscillator circuit is A first series circuit having two or more of the first logic inverting elements connected in series, A second series circuit having two or more of the second logic inverting elements connected in series, The output node of the first logic inverting element in the final stage of the first series circuit is connected to the input node of the second logic inverting element in the first stage of the second series circuit. The output node of the second logic inverting element in the final stage of the second series circuit is connected to the input node of the first logic inverting element in the first stage of the first series circuit. The first current control circuit, in synchronization with the first signal, injects current from the current source into the output node of the first logic inverter element in any stage of the first series circuit. The semiconductor integrated circuit as described in Appendix 1, wherein the second current control circuit, in synchronization with the second signal, draws current from the output node of the second logic inverting element in any stage of the second series circuit. [Note 7] The number of connection stages of the first logic inverting element in the first series circuit is even, The semiconductor integrated circuit described in Appendix 6, wherein the number of connection stages of the second logic inverting elements in the second series circuit is the same as the number of connection stages of the first logic inverting elements in the first series circuit. [Note 8] The semiconductor integrated circuit according to Appendix 4, comprising two third logic inverting elements connected in opposite directions between the output nodes of the first logic inverting element and the second logic inverting element of the same stage in the first series circuit and the second series circuit. [Note 9] The system includes a pulse generator that generates the first signal and the second signal synchronized with the rising edge or falling edge of the clock signal, The first current control circuit injects current into the output node of any of the first logic inverters in the first series circuit during the period when the level of the first signal is active. The semiconductor integrated circuit according to Appendix 4, wherein the second current control circuit draws current from any output node of the second logic inverting element in the second series circuit during the period when the level of the second signal is active. [Note 10] The pulse generator comprises a first signal and a second signal synchronized with the clock signal, and a third signal and a fourth signal synchronized with the inverted phase of the clock signal. The first current control circuit, synchronized with the first signal, injects current into the output node of any of the first logic inverting elements in the first series circuit, and synchronized with the third signal, injects current into any of the output nodes of any of the second logic inverting elements in the second series circuit. The semiconductor integrated circuit according to Appendix 4, wherein the second current control circuit is synchronized with the second signal and draws current from the output node of any of the second logic inverting elements in the second series circuit, and is synchronized with the fourth signal and draws current from any of the output nodes of any of the first logic inverting elements in the first series circuit. [Note 11] The first current control circuit injects current into the output node of the first logic inverting element of a predetermined connection stage in the first series circuit. The second current control circuit is a semiconductor integrated circuit as described in Appendix 4, which draws current from the output node of the second logic inverting element of the predetermined connection stage in the second series circuit. [Note 12] A semiconductor integrated circuit described in any one of the appendices 1 to 11, A first oscillator having the aforementioned oscillation circuit, A second oscillator that generates an oscillation signal with a frequency corresponding to the current output from the current source, A PLL circuit comprising a feedback control circuit that feedback-controls the frequency of the oscillation signal generated by the second oscillator. [Note 13] The aforementioned feedback control circuit is A frequency divider for dividing the frequency of the oscillation signal of the second oscillator, A phase comparator that generates a phase difference signal between a reference signal and a signal divided by the frequency divider, A charge pump that generates a current signal corresponding to the phase difference signal, The system includes a loop filter that removes unwanted frequency components included in the current signal, The current source is a PLL circuit as described in Appendix 12, which injects a current corresponding to the output signal of the loop filter into the first oscillator and the second oscillator. [Note 14] The frequency of the reference signal is lower than the frequency of the clock signal. The PLL circuit described in Appendix 13, wherein the frequency of the oscillation signal is equal to the frequency of the clock signal. [Note 15] The PLL circuit described in Appendix 12, further comprising a level shifter that increases the voltage amplitude of the aforementioned oscillation signal. [Note 16] The PLL circuit described in any one of the appendices 12-15, A signal processing device comprising: a signal processing circuit that performs signal processing based on the oscillation signal output from the PLL circuit. [Explanation of Symbols]

[0079] 1 Semiconductor integrated circuit, 2 PLL circuit, 3,3a,3b,3c Injection-locked current-controlled oscillator (ILICO), 4 Current-controlled oscillator (ICO), 7 Frequency divider (DIV), 8 Phase frequency detector (PFD), 9 Charge pump (CP), 10 Loop filter (LPF), 11 Voltage-current converter (VIC), 12 Pulse generator (PulseGen), 13 Oscillator (OSC), 14 Input / output interface circuit (I / O), 20 Signal processing unit, 21 Signal processing circuit, 22 Control circuit, 31,31a,31b Oscillator circuit, 32,32a First current control circuit, 33,33a Second current control circuit, 34 First inverter, 35 Second inverter, 36 Third inverter, 37 Third inverter, 38,38a First series circuit, 39,39a Second series circuit

Claims

1. An oscillator circuit that outputs a differential oscillator signal, comprising: a first series circuit having two or more first logic inverting elements connected in series; a second series circuit having two or more second logic inverting elements connected in series; and a third logic inverting element and a fourth logic inverting element connected in opposite directions between the output nodes of the first logic inverting elements and the second logic inverting elements of the same stage in the first series circuit and the second series circuit, respectively. The oscillation circuit is provided with a current source capable of injecting a current controlled according to a voltage that controls the frequency of the oscillation signal, A first current control circuit that injects the controlled current from the current source into the output node of the first logic inverting element in synchronization with a first signal synchronized with a clock signal, A semiconductor integrated circuit comprising: a second current control circuit that, in synchronization with a second signal synchronized with the clock signal, draws current from the output node of the second logic inverting element to a reference voltage node.

2. The aforementioned oscillator circuit is The output node of the final stage first logic inverter element in the first series circuit is connected to the input node of the first stage first logic inverter element in the first series circuit. The output node of the second logic inverter element in the final stage of the second series circuit is connected to the input node of the second logic inverter element in the first stage of the second series circuit. The first current control circuit, in synchronization with the first signal, injects current from the current source into the output node of the first logic inverting element in any stage of the first series circuit. The semiconductor integrated circuit according to claim 1, wherein the second current control circuit, in synchronization with the second signal, draws current from the output node of the second logic inverting element in any stage of the second series circuit.

3. The number of connection stages of the first logic inverting element in the first series circuit is odd, The semiconductor integrated circuit according to claim 2, wherein the number of connection stages of the second logic inverting elements in the second series circuit is the same as the number of connection stages of the first logic inverting elements in the first series circuit.

4. The aforementioned oscillator circuit is The output node of the first logic inverting element in the final stage of the first series circuit is connected to the input node of the second logic inverting element in the first stage of the second series circuit. The output node of the second logic inverting element in the final stage of the second series circuit is connected to the input node of the first logic inverting element in the first stage of the first series circuit. The first current control circuit, in synchronization with the first signal, injects current from the current source into the output node of the first logic inverting element in any stage of the first series circuit. The semiconductor integrated circuit according to claim 1, wherein the second current control circuit, in synchronization with the second signal, draws current from the output node of the second logic inverting element in any stage of the second series circuit.

5. The number of connection stages of the first logic inverting element in the first series circuit is even. The semiconductor integrated circuit according to claim 4, wherein the number of connection stages of the second logic inverting elements in the second series circuit is the same as the number of connection stages of the first logic inverting elements in the first series circuit.

6. The pulse generator comprises a first signal and a second signal synchronized with the clock signal, and a third signal and a fourth signal synchronized with the inverted phase of the clock signal. The first current control circuit, synchronized with the first signal, injects current into the output node of any of the first logic inverting elements in the first series circuit, and synchronized with the third signal, injects current into any of the output nodes of any of the second logic inverting elements in the second series circuit. The semiconductor integrated circuit according to claim 2, wherein the second current control circuit is synchronized with the second signal and draws current from the output node of any of the second logic inverting elements in the second series circuit, and is synchronized with the fourth signal and draws current from any of the output nodes of any of the first logic inverting elements in the first series circuit.

7. A semiconductor integrated circuit according to any one of claims 1 to 6, A first oscillator having the aforementioned oscillation circuit, A second oscillator that generates an oscillation signal with a frequency corresponding to the current output from the current source, A PLL circuit comprising a feedback control circuit that feedback-controls the frequency of the oscillation signal generated by the second oscillator.

8. The PLL circuit described in claim 7, A signal processing apparatus comprising a signal processing circuit that performs signal processing based on the oscillation signal output from the oscillation circuit of the semiconductor integrated circuit.

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