Reconfigurable mixer design enabling multiple wireless architectures

Abstract

Embodiments herein describe an integrated circuit having a digital front end (DFE) that includes multiple hardened mixers that can be configured to support multiple different radio paths. The DFE provides the ability to distribute processing across multiple mixers, which can be combined and synchronized to create larger mixers, or used in other combinations to create multiple discrete mixers.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to a reconfigurable mixer design implemented in hardened circuitry that provides flexibility of a mixer implemented in programmable logic.

Background Art

[0002] In modern wireless systems, there are several possible combinations of wireless data paths. For example, in 4G / 5G, there are LTE, FR1, and FR2 bands, each of which may require multiple individual component carriers (CCs or channels), varying carrier bandwidths, and multiple antennas. Some exemplary combinations are one radio supporting eight carriers on eight antennas, two radios each supporting eight carriers on four antennas, fewer wider-bandwidth carriers, and a hybrid configuration where two radios may have different bandwidths, different numbers of carriers, or different numbers of antennas.

[0003] Currently, to support all of these different wireless data paths, a digital front end (DFE) typically includes a mixer implemented in programmable logic. This gives the customer the flexibility to configure the mixer to enable the particular wireless data path selected by the customer. However, implementing a mixer using programmable logic incurs a larger area and power cost than a mixer implemented using hardened circuitry. That is, a mixer implemented using programmable logic provides flexibility to enable different wireless data path configurations but sacrifices larger area and power consumption compared to a hardened mixer.

Summary of the Invention

[0004] One embodiment describes a digital front-end (DFE) comprising first and second mixers implemented in hardened logic, each comprising a plurality of subunits, and a circuit configured to form an inter-mixer communication path connecting at least one of the plurality of subunits in the first mixer to at least one of the plurality of subunits in the second mixer. Furthermore, the first and second mixers are configured to operate synchronously to effectively form a single larger mixer using the inter-mixer communication path when operating in the downlink (DL) path of a radio.

[0005] Another embodiment described herein is a DPE, which includes a first mixer and a second mixer implemented in the curing logic, the first and second mixers configured to operate synchronously to effectively form a first larger mixer for use in the downlink (DL) path of the radio, and a third and a fourth mixer implemented in the curing logic, the third and fourth mixers configured to operate synchronously to effectively form a second larger mixer for use in the uplink (UL) path of the radio.

[0006] Another embodiment described herein includes an integrated circuit comprising first and second mixers, each implemented in hardened logic and comprising a plurality of subunits, and a circuit configured to form an inter-mixer communication path connecting a subset of the plurality of subunits in the first mixer to a subset of the plurality of subunits in the second mixer. The first and second mixers are configured to effectively form a single larger mixer using the inter-mixer communication path when operating in the downlink (DL) path of a radio.

[0007] To ensure a detailed understanding of the above features, a more specific explanation, concisely summarized above, can be provided by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram of a DFE with a mixer in a downlink wireless path, as an example. [Figure 2] This is a block diagram of a DFE with a mixer in an uplink wireless path, as an example. [Figure 3] An example shows a mixer in a downlink wireless path that shares data between antenna subunits. [Figure 4] This diagram shows various circuits within a mixer in a DFE, as an example. [Figure 5] Figure 4 shows an example of a different wireless path configuration for the mixer. [Figure 6] Figure 4 shows an example of a different wireless path configuration for the mixer. [Figure 7] Figure 4 shows an example of a different wireless path configuration for the mixer. [Figure 8] Figure 4 shows an example of a different wireless path configuration for the mixer. [Figure 9] Figure 4 shows an example of a different wireless path configuration for the mixer. [Figure 10] This is a flowchart illustrating the movement of carriers between mixers within a DFE (Distributed Feedback Environment). [Figure 11A] This is a block diagram showing an example of a programmable IC. [Figure 11B] This shows an example of an implementation configuration for a field-programmable gate array (FPGA) of a programmable IC. [Figure 11C]This is a block diagram illustrating an example of a multi-integrated circuit (IC) programmable device. [Modes for carrying out the invention]

[0009] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of features. They are not intended as exhaustive features of the specification or as limitations on the claims. In addition, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not illustrated or explicitly described in that way.

[0010] Embodiments of this specification describe an integrated circuit having a DFE including multiple hardened mixers, which can be configured to support multiple different radio paths. Furthermore, the inherently flexible architecture of the mixers supports dynamic switching between downlink (DL) and uplink (UL). In addition, the hardened mixers can leverage additional radio channels from programmable logic (e.g., programmable fabric) within the integrated circuit to extend customer use cases. Furthermore, the design is scalable because basic blocks such as numerically controlled oscillators (NCOs) and complex multipliers (CMs) can be scaled based on the size of the integrated circuit and the customer use case. The DFE also provides the ability to distribute processing across multiple mixers, which can be combined and synchronized to create a larger carrier / antenna mixer, or used in other combinations to create multiple discrete carrier / antenna mixers.

[0011] Figure 1 is a block diagram of a DFE100 in an integrated circuit (IC) having a mixer 125 in a DL105 radio path, as an example. The DFE100 in Figure 1 includes two DL105 paths to support eight antennas; namely, DL105A supports antennas 0-3 and DL105B supports antennas 4-7. However, as will be described below, the same circuit shown in Figure 1 may be configured to function as a UL radio path, or to function as both a DL path and a UL path using time-division duplexing (TDD).

[0012] DL105 includes pre-processing circuitry 110, channel filter 115, digital upconverter (DUC) 120, mixer 125, post-processing circuitry 135, and two copies of programmable logic (PL) 140. DL105 is configured to serve four antennas, but this is for illustrative purposes only. DFE100 may include circuitry for providing DL links to fewer than eight or more than eight antennas.

[0013] Although not shown, preprocessing circuits 110A and 110B receive analog signals from antennas 0-3. The preprocessing circuit 110 is not limited to any particular circuit and may include hardware components such as frequency domain buffers, circuits for performing transformations (e.g., FFT and IFFT), and time domain buffers. Some preprocessing circuits 110 may be implemented using hardened logic, PL, or a combination of both. Embodiments herein can benefit from integrated circuits that include some PL, such as field-programmable gate arrays (FPGAs) or systems-on-chip (SoCs) having a mixture of PL and hardened circuits, but the features described herein can be used in application-specific integrated circuits (ASICs) that do not have PL. PL (e.g., programmable fabric) provides flexibility in reconfiguring connections between the various elements in Figure 1, but this flexibility can be provided in ASICs that have routing elements such as switches and multiplexers.

[0014] The signal provided by the preprocessing circuit 110 is received by the channel filter 115. In this example, channel filter 115A filters the signals corresponding to carriers 0-3, and channel filter 115B filters the signals corresponding to carriers 4-7. Although not shown, DL105B receives data transmitted on the same carriers as DL105A (i.e., carriers 0-7), but the data is received using antennas 4-7 instead of antennas 0-3. However, other configurations of the circuit in Figure 1 can support different radio path configurations, some of which are shown in Figures 5-9 below. For example, Figure 1 shows DL105A and 105B forming a DFE100 for a single radio with eight antennas receiving data over eight carriers, but DFE100 can be reconfigured to support a single radio with more carriers (and less bandwidth per carrier), a single radio with fewer carriers (but more bandwidth per carrier), or multiple radios.

[0015] DUC120 receives the filtered signal from channel filter 115 and provides the upconverted signal to mixer 125. One advantage of the embodiments herein is that the mixers are separated into separate, independent mixers 125, which can operate independently to enable multiple radios or, as in Figure 1, can operate synchronously with one another to form a larger radio. In one embodiment, mixer 125 has its own independent clock, independent reset signal, and independent input / output. Furthermore, mixer 125 can have different sample rates. However, on the other hand, mixer 125 can be synchronized to have the same clock and dependent input / output, as shown in Figure 1, and thus can be used as a larger mixer (e.g., a mixer with more synchronized channels) to support a larger radio. As will be described below, the state of the oscillators within mixer 125 can be synchronized so that it can operate effectively as a single larger mixer.

[0016] To operate effectively as a larger mixer, the DFE100 includes an inter-mixer communication path 130 that allows mixer 125 to share data. By doing so, the DL105 can operate as a more effectively larger radio (e.g., more antennas, more carriers, or more bandwidth) than if mixer 125 could not share data. The inter-mixer communication path 130 can be implemented using hardened routing elements in the case of PL, or ASIC. The inter-mixer communication path 130 is described in more detail in Figure 3.

[0017] Mixer 125 can also be coupled to an optional PL140. In one embodiment, PL140 is used for carrier generation or processing, and when mixer 125 is used as part of DL105, PL140 provides the input to be mixed. Generally, mixer 125 mixes multiple carriers to form a composite output for each antenna.

[0018] In this example, mixer 125A outputs data corresponding to two of the antennas (e.g., antennas 0 and 1) to post-processing circuit 135A, and mixer 125B outputs data corresponding to the other two antennas (e.g., antennas 2 and 3) to post-processing circuit 135B. Embodiments herein are not limited to any particular type of post-processing circuit 135 that can include, for example, an equalizer, an I / Q imbalance correction circuit, an automatic gain control, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and the like.

[0019] The output of post-processing circuit 135 can be sent to different components within the IC that includes DFE 100. In this example, despite the fact that DFE 100 includes four independent mixers 125 (two for each DL 105), DL 105A and 105B function as a single radio. In other words, by synchronizing the mixers 125 within DL 105 and using inter-mixer communication path 130, they can act as DFE 100 for a radio having eight antennas that support eight carriers.

[0020] Figure 2 is a block diagram of a DFE100 having a mixer within the UL205 radio path, according to an example. The DFE100 of FIG. 2 represents two possible examples. In one example, the circuit of FIG. 2 can be combined with the circuit of FIG. 1 to form a single DFE100, where the circuit of circuit 1 in FIG. 1 forms the DL of the radio and the circuit of FIG. 2 forms the UL of the same radio. Further, FIGS. 1 and 2 show an embodiment in which the same circuits (e.g., preprocessing circuit 110, channel filter 115, DUC 120, mixer 125, postprocessing circuit 135, and PL 140) are used to form both the DL and UL for the same radio. In this example, FIG. 1 shows when the circuit is performing the DL function and FIG. 2 shows when the same circuit is performing the UL function. In that case, TDD can be used when, at any given point in time, the circuits of FIGS. 1 and 2 are performing only one of the DL or UL functions and not both. However, to do so, the state of the NCO in mixer 125 needs to be maintained (e.g., tracked) such that mixer 125 can switch from being part of the DL to being part of the UL and vice versa. This will be described in more detail in FIG. 4.

[0021] In general, the UL205 in Figure 2 operates in the opposite way to the DL105 in Figure 1. Other components within the same IC as the DFE100 can transmit data to be sent on antennas 0-7 to the post-processing circuit 135. Instead of mixing the signals together (which is the purpose of mixer 125 when providing service in DL), mixer 125 separates (or extracts) the signals. That is, instead of mixing multiple carriers when functioning in DL, when operating in UL205, mixer 125 takes each antenna input and splits (extracts) the signal into multiple carrier outputs. In this example, mixer 125 transmits data to PL140 to assist the extraction process. Furthermore, when mixer 125 is part of UL205, it may not be necessary to use an inter-mixer communication path to extract the input signal and form multiple carrier outputs. In other words, the inter-mixer communication path 130 in Figure 1 can only be used when mixer 125 is in DL, and only when multiple mixers are configured to operate effectively as a larger mixer. Nevertheless, as in Figure 1, mixer 125 is synchronized when operating on the UL route and therefore functions like a single larger mixer, and thus can support larger radios.

[0022] The resulting carrier data is provided to the DUC 120, channel filter 115, and preprocessing circuit 110, which then provide the signals transmitted by antennas 0-7.

[0023] Figure 3 shows a mixer 125 in a DL radio path sharing data between antenna subunits, as an example. Figure 3 provides further details of mixers 125A and 125B used in the DL shown in Figure 1. As shown, each mixer 125 includes four antenna subunits 305 (shown in more detail in Figure 4), although other embodiments may have more or fewer subunits 305. In this example, each antenna subunit 305 receives inputs corresponding to different carriers. Referring again to Figure 1, mixer 125A receives signals corresponding to carriers 0-3 from DUC 120A, and mixer 125B receives signals corresponding to carriers 4-7 from DUC 120B, but this is just an example.

[0024] As described above, the mixers 125 work together to mix the carriers to form a composite output for each antenna. This is done by synchronizing the mixers, which can be achieved by simultaneously resetting the mixers and operating them using a synchronized clock and sampling rate, as well as using the inter-mixer communication path 130.

[0025] As shown in the diagram, two outputs of the subunit 305 in each mixer 125 are used as inputs to two subunit 305 in the other mixer 125. That is, the outputs of antenna subunits 305C and 305D in mixer 125A are inputs to antenna subunits 305E and 305F in mixer 125B, respectively. Similarly, the outputs of antenna subunits 305G and 305H in mixer 125B are inputs to antenna subunits 305A and 305B in mixer 125B, respectively. The inter-mixer communication paths 130 allow antenna subunits 305 in different mixers 125 to communicate with each other as part of the mixing function. These paths 130 can be implemented using a PL fabric or circuitry such as multiple routing elements (e.g., switches and multiplexers).

[0026] Next, the antenna subunit 305, which receives the outputs of the other subunits, mixes those carriers with its own received carriers to produce the respective outputs for each antenna. That is, antenna subunit 305A provides the output corresponding to antenna 0, antenna subunit 305B provides the output corresponding to antenna 1, antenna subunit 305E provides the output corresponding to antenna 2, and antenna subunit 305F provides the output corresponding to antenna F. In one embodiment, the antenna subunit 305 in the mixer 125 that provides outputs to the other subunits 305 does not process the received data. As shown in Figure 4, the subunit 305 may include a bypass path, and therefore, when the mixer needs to use the inter-mixer communication path 130 to form a larger mixer, the mixing circuit within the subunit 305 (i.e., subunits 305B-C and 305G-H) can be bypassed.

[0027] Figure 4 shows various circuit diagrams of a mixer within DFE100, as an example. In this example, DFE100 includes four mixers 125A-D, each having five mixer subunits 405 and four antenna subunits 305. Figure 4 shows the subsequent path data in mixer 125A when the mixer is used as part of DL (shown by solid lines), bypassed in DL (shown by dashed lines), and used as part of UL (shown by dotted lines).

[0028] When configured as part of a DL path, the mixer subunit 405 receives carrier data from the DUC (not shown). After being processed by the circuitry within subunit 405 to mix the individual carriers with the associated NCO 410 and then optionally to obtain a signal, subunit 405 transfers the data to an adder circuit that sums the outputs of subunit 405 to produce individual antenna signals to be supplied to the antenna subunit 305. If mixer 125A is operating independently (i.e., not synchronized with another mixer 125 in DFE 100 to effectively form a larger mixer), the antenna subunit 305 uses the shown circuitry to process the summed data and produce outputs for one or more antennas.

[0029] However, when mixer 125A is synchronized with another mixer 125 in DFE 100, an inter-mixer communication path (not shown here) is used to allow some of the antenna subunits 305 in mixer 125A to transmit and receive data from the antenna subunits 305 in the other mixer 125. For example, assuming that antenna subunit 305A outputs data to an antenna subunit in a different mixer 125, the data received from the adder circuit travels along a bypass path 430 that bypasses the mixer circuit and is transmitted to the antenna subunit in the different mixer, as shown in Figure 3, using the inter-mixer communication path.

[0030] Alternatively, antenna subunit 305A may receive input data from antenna subunits in different mixers. This data is received by mux440 and then combined with the carrier signal of subunit 305 received from mixer subunit 405. This combined signal is then processed by the mixer circuit in antenna subunit 305A, as shown by the solid line. The output of antenna subunit 305A may correspond to one or more antennas as shown in Figure 3.

[0031] When configured as part of the UL path, the mixer subunit 405 receives data from post-processing circuitry (e.g., post-processing circuitry 135 in Figure 1). After processing by the circuitry within subunit 405 to mix (extract) individual carriers from the composite antenna input, subunit 405 transfers the data along the dotted line to the flip-flop (FF) 445. The FF 445 then outputs the data to the DUC (not shown) for further processing. Thus, Figure 4 shows the various data flows through mixer 125 when it is part of DL and UL.

[0032] In addition to subunits 405 and 305, mixer 125 also includes a plurality of NCOs 410. In one embodiment, the NCOs 410 are the only circuits in mixer 125 that maintain their state. Maintaining the state of the NCOs 410 is useful when mixer 125 switches between DL and UL operation. When switching between DL and UL modes, the UL carriers may have different NCO frequencies and / or phases than the DL carriers, and therefore require the NCOs to have different states. As shown in the figure, the NCOs 410 have a phase accumulator 415 having a DL state 420 used when mixer 125 is part of the DL path and a UL state 425 used when mixer 125 is part of the UL path. In this way, mixer 125 can switch between UL and DL using the state maintained in the phase accumulator 415 of the NCOs 410. As a result, the same circuit (i.e., the same NCO) can be used for both UL and DL by preserving and modifying their states. Other circuits within mixer 125 (e.g., subunits 305 and 405) may not need to maintain their states in order to switch between operation in the DL path and operation in the UL path.

[0033] Furthermore, when multiple mixers are synchronized to operate as a larger mixer, the NCO410s within each mixer may have the same (e.g., mirrored) state. Mixer 125 can be simultaneously reset so that its NCO410s have the same state. The NCO410s within multiple mixers 125 can be programmed to have the same frequency to ensure they operate in lockstep.

[0034] Furthermore, flexible control, programming, and synchronization of each individual NCO410 are provided, including real-time interactions such as clock gating and phase reset. All unused channels within mixer 125 are powered off. Mixer 125 can also take advantage of the fact that the time-slicing pattern of the previous stage (e.g., a 4-carrier 4-antenna radio) means that the input carriers are "repeated" across each antenna. For example, there is carrier 0 for antennas 0, 1, 2, and 3. This means that a single NCO410 can be used to generate a mixed frequency for these four input / output streams, which is an area and power-saving strategy.

[0035] Furthermore, the state of NCO410 in one mixer 125 can be maintained and copied to NCO410 in a different mixer 125. This is useful when moving carriers from one mixer to another, which is explained in more detail in Figure 10.

[0036] Figures 5 to 9 illustrate different radio path configurations of mixer 125 in Figure 4, as an example. Figure 5 shows four mixers 125 working together to form an 8x8 FR1 200MHz 4-carrier 4-antenna radio. In this embodiment, the mixers 125 are synchronized (along with the NCOs within the mixers 125) to form a single radio with eight antennas where downstream processing is performed at 100MHz. The data for the eight carriers are shared across each mixer 125.

[0037] Figure 6 shows mixers 125 working together to form a single radio with eight antennas but only four carriers. However, each carrier has a larger bandwidth (200 MHz) than the carriers in the DFE for the radio shown in Figure 5. In Figure 5, the mixers 125 rely on an inter-mixer communication path, whereas in Figure 6, each mixer 125 has four subunits (e.g., four mixer and antenna subunits) as shown in Figure 4, and therefore the four carriers can be mixed without sharing data with the antenna subunit in another mixer, so the mixers 125 do not need to share data.

[0038] Figure 7 shows mixer 125, each mixer working together to support a single radio handling eight carriers. In this example, the channels are allocated to the left, so that mixer 125 has two antennas at its input but only one at its output.

[0039] Figure 8 shows four mixers 125 forming a DFE for two separate radios. The first radio is supported by mixers 125A and 125B (synchronized), and the second radio is supported by mixers 125C and 125D (synchronized). This demonstrates one advantage of having multiple independent mixer blocks within a DFE. All mixers 125 within a DFE can be synchronized to form a single mixer for one radio, as shown in Figures 5-7, or a subset of mixers can be synchronized to operate independently of other mixers to support different radios, as in Figure 8. Here, mixers 125A and 125B are part of a first radio having four antennas and eight carriers, and mixers 125C and 125D are part of a second radio having four antennas and eight carriers. This synchronizes mixer 125A and mixer 125B, and mixer 125C and mixer 125D. However, the frequencies and sampling rates of the synchronized mixer pairs may be different.

[0040] Figure 9 shows another example where mixer 125 within the same DFE may be part of separate radios. Here, mixers 125A-C are synchronized and operate in conjunction to form a first radio with four antennas and twelve carriers, while mixer 125D is part of a second radio with four antennas and four carriers. Thus, Figure 9 shows an asymmetrical assignment of mixers 125. In this example, the first radio has a bandwidth of 300 MHz, while the second radio has only 100 MHz.

[0041] Furthermore, it may not be possible to add the outputs of the three mixers 125A to C that form the first radio within mixer 125. This can be done using external adders 905 and 910, which may be implemented in the PL. However, in another embodiment, mixer 125 may have sufficient internal adders to perform the summation within mixer 125 using hardening logic.

[0042] Therefore, Figures 5 to 9 show a hardened, independent mixer 125 in the DFE that has similar flexibility to a mixer implemented in the PL. That is, mixer 125 can be reconfigured to operate synchronously or independently to support one or more radios. Thus, mixer 125 saves space compared to a mixer implemented in the PL without losing the flexibility provided by the PL. Furthermore, unused channels in mixer 125 can be deactivated, thereby saving power.

[0043] Figure 10 is a flowchart of method 1000 for moving a carrier between mixers in a DFE, as an example. In block 1005, the system or user identifies the carrier to be moved to the destination mixer in the DFE. For example, a downstream processing resource of the source mixer currently serving the carrier may become overloaded. The system can identify the overloaded resource and the non-overloaded processing resource. The system can then use method 1000 to reroute the carrier data through a destination mixer connected to the non-overloaded resource.

[0044] However, simply rerouting the carrier to the destination mixer can lead to data corruption because the NCOs within the mixer may not be synchronized. As described above, NCOs have a state that can be tracked, for example, when the mixer switches between being part of a DL route and a UL route. If the carrier is moved to the destination mixer without the NCOs within the destination mixer having the same state as the NCOs currently servicing that carrier, data corruption may occur. This data corruption could mean the move is not seamless. Method 1000 avoids this potential problem by ensuring that the NCOs within the destination mixer have the same state as the NCOs currently servicing the carrier in the source mixer.

[0045] In block 1010, the system identifies unused NCOs in the destination mixer. That is, the destination mixer may have at least one NCO that is not currently being used to perform its mixer function.

[0046] In block 1015, the system causes an unused NCO to operate at the same frequency as the NCO that serves the carriers in the source mixer. Thus, both NCOs operate at the same frequency here. However, this does not mean that the two NCOs have the same state, as NCOs may have different phases.

[0047] In block 1020, the source mixer and destination mixer capture the phase of the NCO. In one embodiment, the mixer has state capture logic that identifies the current phase of the NCO. Each mixer (i.e., the source mixer and destination mixer currently carrying the carrier) can use this logic to capture the state or phase of the NCO.

[0048] In block 1025, the system determines the phase offset between the two NCOs. That is, the system determines the delta phase between the two NCOs that defines the phase offset.

[0049] In block 1030, the system programs a phase offset to an unused NCO so that its state matches that of an NCO currently servicing the carrier. Since the NCOs have the same frequency and phase, they are synchronized here.

[0050] In block 1035, the system moves the carrier from the source mixer to the destination mixer. Since the new NCO has the same state as the old NCO, this move is seamless from the user's perspective, and the carrier data is not interrupted. In one embodiment, the carrier is moved between the source and destination mixers by injecting the same data into both the source and destination mixers, and once the output signal has propagated, the source is switched off, allowing the destination mixer to drive the downstream system. The new mixer can then transfer the data in the carrier to its downstream processing resources for further processing. In this way, the carrier (or channel) can be moved seamlessly between mixers to take advantage of available processing resources.

[0051] Method 1000 is described in the context of moving carriers between two different mixers, but if desired, the same process can be used to mirror the state between NCOs within the same mixer.

[0052] Figure 11A is a block diagram illustrating an example of a programmable device 1. The programmable device 1 includes programmable logic (PL) 3 (also called programmable fabric), input / output (IO) circuits 68, serial transceivers 67, signal conversion circuits 66, hardening circuits 90, configuration logic 25, and configuration memory 26. The programmable device 1 can be coupled to external circuits such as non-volatile memory 27, dynamic random access memory (DRAM) 28, and other circuits 29. In various examples, the programmable device 1 further includes a processing system (PS) 2, a network-on-chip (NOC) 55, a data processing engine (DPE) array 56, peripheral interconnects 61, peripheral circuits 62, and die-to-die interconnects 64.

[0053] PL3 includes a logic cell 30, a support circuit 31, and a programmable interconnect 32. The logic cell 30 includes circuitry that can be configured to implement common logic functions for multiple inputs. The support circuit 31 includes dedicated circuitry such as a digital signal processor and memory. The logic cell and the support circuit 31 can be interconnected using the programmable interconnect 32. Information for programming the logic cell 30, setting the parameters of the support circuit 31, and programming the programmable interconnect 32 is stored in configuration memory 26 by configuration logic 25. The configuration logic 25 can retrieve configuration data from non-volatile memory 27 or any other source (e.g., DRAM 28 or other circuitry 29). In some examples, the configuration logic 25 includes a platform management controller (PMC) 72. The PMC 72 is configured to boot and configure subsystems of programmable device 1 such as PL3, PS2, NoC 55, DPE array 56, signal conversion circuit 66, and curing circuit 90.

[0054] The IO circuit 68 provides an external interface for subsystems of the programmable device 1, such as PL3 and PS2. In some examples, the IO circuit 68 includes a memory controller 70 configured to interface with external memory (e.g., DRAM 28). Other connection circuits may include peripheral interconnects 61, peripheral circuits 62, and die interconnects 64. Peripheral interconnects 61 include bus interface circuits such as PCIe (Peripheral Component Interconnect Express) circuits. Peripheral circuits 62 include USB (Universal Serial Bus) ports, Ethernet® ports, UART (Universal Asynchronous Transceiver) ports, SPI (Serial Peripheral Interface) ports, GPIO (General Purpose I / O) ports, SATA (Serial Advanced Technology Attachment) ports, etc. Die interconnects 64 include circuits configured to interface like die interconnects in other programmable devices (for example, when the programmable device 1 is one die in a multi-die integrated circuit package). The serial transceiver 67 includes a high-speed transmit / receive circuit configured to provide an external I / O interface for the programmable device 1.

[0055] The PS2 may include a microprocessor, memory, support circuits, I / O circuits, etc. The NOC55 is configured to provide communication between subsystems of the programmable device 1, such as between the PS2, PL3, curing circuit 90, and DPE array 56. The DPE array 56 may include an array of DPEs configured to perform data processing, such as an array of vector processors. The signal conversion circuit 66 includes an ADC (Analog-to-Digital Converter) and a DAC (Digital-to-Analog Converter).

[0056] The curing circuit 90 includes a circuit having a predetermined function. A given curing circuit 90 may include one or more predetermined functions. An exemplary curing circuit 90 includes a filter, a mixer, a sample rate converter, a conversion circuit (e.g., a Fast Fourier Transform (FFT)), etc. For example, the curing circuit 90 may include the mixer described above in Figures 1 to 4. The curing circuit 90 may be programmable to configure a specific predetermined function or to select from a set of predetermined functions. However, in contrast to the circuit in PL3, the curing circuit 90 cannot be configured or reconfigured with different functionalities. For example, the curing circuit 90 may include a filter having two predetermined selectable functions. A third function cannot be added to the curing circuit 90, nor can one of the two functions be removed from the curing circuit 90. In contrast, the filter configured in PL3 can be reconfigured to add one or more additional functions, or to remove one or more functions. Furthermore, the filter configured in PL3 can be completely removed and replaced with another circuit. In contrast, the curing circuit 90 cannot be removed from the programmable device 1 (but can be omitted if necessary).

[0057] Figure 11B shows an example field-programmable gate array (FPGA) implementation of PL3. The PL3 shown in Figure 11B can be used in any example of a programmable device described herein. PL3 includes a number of different programmable tiles, including a configurable logic block ("CLB") 33, blocks of random access memory ("BRAM") 34, input / output blocks ("IOB") 36, configuration and clocking logic ("CONFIG / CLOCKS") 42, digital signal processing block ("DSP") 35, dedicated input / output blocks ("I / O") 41 (e.g., configuration ports and clock ports), and other programmable logic 39 such as a digital clock manager, analog-to-digital converter, and system monitoring logic.

[0058] In some PLs, each programmable tile may include at least one programmable interconnect element ("INT") 43 having connections to input and output terminals 48 of a programmable logic element within the same tile, as shown by the example included at the top of Figure 11B. Each programmable interconnect element 43 may also include connections to interconnect segments 49 of adjacent programmable interconnect elements within the same tile or other tiles. Each programmable interconnect element 43 may also include connections to interconnect segments 50 of a generic routing resource between logic blocks (not shown). A generic routing resource may include routing channels between logic blocks (not shown) containing tracks of interconnect segments (e.g., interconnect segment 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of a generic routing resource (e.g., interconnect segment 50) may span one or more logic blocks. The programmable interconnect elements 43, together with the generic routing resources, implement a programmable interconnect structure ("programmable interconnect") for the illustrated PL.

[0059] In an exemplary implementation, the CLB 33 may include a single programmable interconnect element ("INT") 43 in addition to a configurable logic element ("CLE") 44 that can be programmed to implement user logic. The BRAM 34 may include one or more programmable interconnect elements in addition to a BRAM logic element ("BRL") 45. Typically, the number of interconnect elements included in a tile varies depending on the height of the tile. In the embodiment of the depiction, the height of the BRAM tile is the same as that of five CLBs, but other numbers (e.g., four) are also available. The DSP tile 35 may include a suitable number of programmable interconnect elements (which may include the FFT circuits in Figures 1 to 5) in addition to a DSP logic element ("DSPL") 46. The IOB 36 may include, for example, one instance of a programmable interconnect element 43 in addition to two instances of input / output logic ("IOL") 47. As will be apparent to those skilled in the art, for example, the actual I / O pads connected to the I / O logic element 47 are typically not limited to the area of ​​the input / output logic element 47.

[0060] In the embodiment of the description, a horizontal region near the center of the die (shown in Figure 11B) is used for configuration, clock, and other control logic. A vertical column 51 extending from this horizontal region or column is used to distribute the clock and configuration signals across the width of the PL.

[0061] Some PLs utilizing the architecture shown in Figure 11B include additional logic blocks that interrupt the regular columnar structure that makes up the majority of the PL. These additional logic blocks may be programmable blocks and / or dedicated logic.

[0062] It should be noted that Figure 11B is intended to show only an illustrative PL architecture. For example, the number of logic blocks in a row, the relative width of the row, the number and order of rows, the type of logic block contained in the row, the relative size of that logic block, and the interconnection / logic implementation form included in the top of Figure 11B are merely illustrative. For example, in a real PL, wherever a CLB appears, it typically contains two or more adjacent rows of CLBs to facilitate efficient implementation of user logic, although the number of adjacent CLB rows will vary depending on the overall size of the PL.

[0063] Figure 11C is a block diagram showing an example of a multi-die programmable device 54. The multi-die programmable device 54 includes a plurality of programmable devices 1, for example, programmable devices 1A, 1B, 1C, and 1D. In one example, each programmable device 1 is an IC die placed on an interposer 60. Each programmable device 1 comprises a super logic area (SLR) 53 of the programmable device 54, for example, SLRs 53A, 53B, 53C, and 53D. The programmable devices 1 are interconnected through conductors on the interposer 60 (called super long lines (SLLs) 52) and inter-die interconnection circuits 64 located within each of the programmable devices 1. The programmable IC may include a hardened portion containing the mixer circuit described above in Figures 1 to 4.

[0064] The embodiments presented in this disclosure are referenced above. However, the scope of this disclosure is not limited to any specific described embodiments. Rather, any combination of the features and elements described is intended to implement and practice the intended embodiments, whether or not they relate to different embodiments. Furthermore, while embodiments disclosed herein may achieve advantages over other possible solutions or the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aforementioned aspects, features, embodiments, and advantages are merely illustrative and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0065] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, all of which may be commonly referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0066] Any combination of one or more computer-readable media may be used. A computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any preferred combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections with one or more wires, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any preferred combination thereof. In the context of this specification, a computer-readable storage medium is any tangible medium that can contain or store programs for use by, or in connection with, an instruction execution system, apparatus, or device.

[0067] A computer-readable signal medium may include, for example, a propagating data signal in which computer-readable program code is embodied, either in the baseband or as part of a carrier wave. Such a propagating signal may take any of various forms, including but not limited to electromagnetic, optical, or any preferred combination thereof. A computer-readable signal medium may be any computer-readable medium, rather than a computer-readable storage medium, that can communicate, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device.

[0068] Program code, embodied on a computer-readable medium, can be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, or any preferred combination thereof.

[0069] Computer program code for performing the operations of the embodiments of this disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java®, Smalltalk, and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The program code may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or fully on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider).

[0070] Aspects of the present disclosure are described below with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments presented herein. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general-purpose computer, a dedicated computer, or another programmable data processing device such that instructions executed via the processor of the computer or other programmable data processing device result in a machine that creates means for performing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0071] These computer program instructions can also be stored on a computer-readable storage medium, which can instruct a computer, a programmable data processing device, and / or other device to function in a particular way, such that the instructions stored on the computer-readable storage medium produce a manufactured article containing instructions that implement the modes of function / action specified in the blocks of a flow diagram and / or block diagram.

[0072] Computer program instructions can also be loaded into a computer, other programmable data processing device, or other device to perform a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process. Thus, instructions executed on a computer or other programmable device provide a process for implementing the functions / actions specified in the blocks of a flow diagram and / or block diagram.

[0073] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in a different order than shown in the figure. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart illustrations, and combinations of blocks in the block diagram and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs a specified function or action, or combines dedicated hardware with computer instructions.

[0074] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. It is a digital front-end (DFE), A first mixer and a second mixer, each equipped with multiple subunits and implemented with hardening logic, The device comprises a circuit configured to form an inter-mixer communication path connecting at least one of the plurality of subunits in the first mixer to at least one of the plurality of subunits in the second mixer, A digital front end in which the first mixer and the second mixer are configured to operate synchronously to form a single larger mixer using the inter-mixer communication path when operating in the downlink (DL) path of a radio.

2. The communication path between mixers is: A first path that couples the output of the first subunit among the plurality of subunits in the first mixer to the input of the second subunit among the plurality of subunits in the second mixer, The system includes a second path that couples the output of a third subunit among the plurality of subunits in the second mixer to the input of a fourth subunit among the plurality of subunits in the first mixer, The second subunit and the fourth subunit combine the data received in the first and second paths with the data received from the respective digital upconverters (DUCs) in the DFE. The DFE according to claim 1, wherein each of the plurality of subunits within the first mixer and the second mixer is provided with a bypass path for bypassing an internal mixer circuit, and when operating on the DL path, the first subunit and the third subunit use their bypass paths when transmitting data to the second subunit and the fourth subunit, respectively, while the second subunit and the fourth subunit do not use their bypass paths.

3. The DFE according to claim 1, wherein the first mixer and the second mixer are configured to switch between operation of the radio on the DL path and operation on the uplink (UL) path using time division duplexing (TDD).

4. The hardening logic further includes a third mixer and a fourth mixer implemented in the hardening logic, the third mixer and the fourth mixer are The third mixer and the fourth mixer are provided as options to be synchronized with the first mixer and the second mixer so as to become part of the radio. The DFE according to claim 1, wherein the third mixer and the fourth mixer are synchronized with each other so as to be part of a second radio, but can be configured to provide an option of not being synchronized with the first mixer and the second mixer.

5. The DFE according to claim 4, wherein the third mixer and the fourth mixer are synchronized so that the first mixer, the second mixer and the third mixer are part of the radio, but the fourth mixer can be configured to provide an option for being part of the second radio.

6. The first mixer and the second mixer each include state capture logic configured to capture the state of controllable oscillators within the first mixer and the second mixer, The state capture logic is used to determine the phase offset between the controllable oscillators in the first mixer and the second mixer, The DFE according to claim 1, configured to move carriers processed using the controllable oscillator in the first mixer to the second mixer by using the phase offset to mirror the state of the controllable oscillator.

7. DFE is, A first mixer and a second mixer implemented in a hardening logic, wherein the first mixer and the second mixer are configured to operate synchronously to form a first larger mixer for use in the downlink (DL) path of a radio, A third mixer and a fourth mixer implemented in a hardening logic, wherein the third mixer and the fourth mixer are configured to operate synchronously to form a second larger mixer for use in the uplink (UL) path of the radio, DFE equipped with

8. Each of the first mixer, the second mixer, the third mixer, and the fourth mixer comprises a plurality of subunits, and the DFE is The system further includes a circuit configured to form an inter-mixer communication path connecting at least one of the plurality of subunits in the first mixer to at least one of the plurality of subunits in the second mixer, The DFE according to claim 7, wherein the first mixer and the second mixer are configured to use the inter-mixer communication path to form the first larger mixer when operating in the DL path of the radio.

9. It is an integrated circuit, A first mixer and a second mixer, each equipped with multiple subunits and implemented with hardening logic, The system includes a circuit configured to form an inter-mixer communication path connecting a subset of the plurality of subunits in the first mixer to a subset of the plurality of subunits in the second mixer, The first and second mixers are configured to form a single, larger mixer using the inter-mixer communication path when operating in the downlink (DL) path of the radio. Integrated circuit.

10. The aforementioned communication path between mixers is, A first path that connects the output of the first subunit of the subset of subunits in the first mixer to the input of the second subunit of the subset of subunits in the second mixer, The second mixer comprises a second path that connects the output of a third subunit from the subset of subunits in the second mixer to the input of a fourth subunit from the subset of subunits in the first mixer, The integrated circuit according to claim 9, wherein the second subunit and the fourth subunit combine data received on the first path and the second path with carrier data received from the respective digital upconverters (DUCs) in the digital front end (DFE).

11. The integrated circuit according to claim 10, wherein each of the plurality of subunits within the first mixer and the second mixer is provided with a bypass path for bypassing an internal mixer circuit, and when operating on the DL path, the first subunit and the third subunit use their bypass paths when transmitting data to the second subunit and the fourth subunit, respectively, while the second subunit and the fourth subunit do not use their bypass paths.

12. The integrated circuit according to claim 9, wherein the first mixer and the second mixer are configured to switch between operation on the DL path and operation on the uplink (UL) path of the radio using time division duplexing (TDD).

13. The integrated circuit according to claim 9, wherein when operating on the uplink (UL) path of the radio, the first mixer and the second mixer do not use the inter-mixer communication path to communicate.

14. The integrated circuit according to claim 9, wherein each of the first mixer and the second mixer comprises at least one controllable oscillator, and the DL state and UL state of the controllable oscillator in the first mixer and the second mixer are maintained when switching between operations in the DL path and the uplink (UL) path of the radio.

15. The integrated circuit according to claim 9, wherein each of the first mixer and the second mixer comprises at least one controllable oscillator, and when switching between operation in the DL path and the uplink (UL) path of the radio, the DL state and the UL state of the controllable oscillator in the first mixer and the second mixer are maintained, the DL state having a different frequency or phase from the UL state of the controllable oscillator.

16. The DFE according to claim 8, wherein when operating on the uplink (UL) path of the radio, the first mixer and the second mixer do not use the inter-mixer communication path to communicate.

17. The DFE according to claim 3, wherein each of the first mixer and the second mixer comprises at least one controllable oscillator, and when switching between operations in the DL path and the UL path, the DL state and the UL state of the controllable oscillator in the first mixer and the second mixer are maintained.

18. The DFE according to claim 3, wherein each of the first mixer and the second mixer comprises at least one controllable oscillator, and when switching between operation in the DL path and the UL path, the DL state and the UL state of the controllable oscillator in the first mixer and the second mixer are maintained, the DL state having a different frequency or phase from the UL state of the controllable oscillator.

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