Address translation circuit and method for performing address translation.

Abstract

An address translation circuit and method for performing address translation. The address translation circuit performs an address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in response to receiving a first address. The address translation circuit is configured to support a normal page table including 2N entries and a big page table including 2N*M entries. The address translation circuit is configured to perform intermediate lookups to retrieve information indicative of a sequentially next lookup address and page table size information, and if the page table size information indicates that the sequentially next lookup corresponds to one of the big page tables, suppress a subsequent lookup if performing the sequentially next lookup exceeds the predetermined maximum number of sequential lookups, and generate a second address based on the information indicative of the sequentially next lookup address.

Description

[Technical Field]

[0001] The present invention relates to an address translation circuit and method for performing address translation.

[0002] Address translation circuits are used to translate from a first address to a second address using a predetermined number of sequential lookups at multiple page table levels. Performing each of these lookups is time-consuming and can result in latency in address translation.

[0003] In some configurations, an address translation circuit is provided that performs address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups at multiple page table levels in response to the reception of a first address. The address translation circuit is 2 N A normal page table level containing 1 entry, and 2 N*M It supports large page table levels containing 1000 entries, where each sequential lookup at a normal page table level is considered a single-level lookup of a predetermined maximum number of sequential lookups, and each sequential lookup at a large page table level is considered an M-level lookup of a predetermined maximum number of sequential lookups. From the current intermediate page table level among multiple page table levels, sequentially retrieve information indicating the lookup address of the next page table level, and sequentially retrieve page table level size information indicating the size of the next page table level. When page table level size information indicates that the next lookup sequentially corresponds to one of the large page table levels, and that performing the next lookup sequentially exceeds a predetermined maximum number of sequential lookups, the system is configured to perform an intermediate lookup to suppress subsequent lookups after the predetermined maximum number of sequential lookups and generate a second address, based on information indicating the next lookup address sequentially.

[0004] In some configurations, in response to receiving the first address, 2 N A normal page table level containing 1 entry, and 2 N*M A method is provided for performing address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups at multiple page table levels, including a large page table level containing n entries, wherein each sequential lookup at a normal page table level is considered to be a single lookup of a predetermined maximum number of sequential lookups, and each sequential lookup at a large page table level is considered to be M lookups of a predetermined maximum number of sequential lookups. The method is, From the current intermediate page table level among multiple page table levels, retrieve information indicating the sequential lookup address of the next page table level, and sequential page table level size information indicating the size of the next page table level. When page table level size information indicates that the next lookup sequentially corresponds to one of the large page table levels, and that performing the next lookup sequentially exceeds a predetermined maximum number of sequential lookups, the intermediate lookup is performed by suppressing subsequent lookups after the predetermined maximum number of sequential lookups based on information indicating the next lookup address, and generating a second address. [Brief explanation of the drawing]

[0005] The present technology will be further described, merely as an example, with reference to the embodiments shown in the attached drawings. [Figure 1] This diagram schematically shows data processing devices with various configurations of this technology. [Figure 2] This diagram schematically shows address translation circuits with various configurations of this technology. [Figure 3]A diagram schematically showing further details of an address conversion circuit according to various configurations of the present technology. [Figure 4] A diagram schematically showing address conversion according to various configurations of the present technology. [Figure 5] A diagram schematically showing address conversion using a large page table according to various configurations of the present technology. [Figure 6] A diagram schematically showing address conversion according to various configurations of the present technology. [Figure 7] A diagram schematically showing address conversion using recursion according to various configurations of the present technology. [Figure 8a] A diagram schematically showing address conversion using recursion according to various configurations of the present technology. [Figure 8b] A diagram schematically showing address conversion using recursion according to various configurations of the present technology. [Figure 9a] A diagram schematically showing details of address conversion using recursion according to various configurations of the present technology. [Figure 9b] A diagram schematically showing details of address conversion using recursion according to various configurations of the present technology. [Figure 9c] A diagram schematically showing details of address conversion using recursion according to various configurations of the present technology. [Figure 10a] A diagram schematically showing address conversion according to various configurations of the present technology. [Figure 10b] A diagram schematically showing address conversion according to various configurations of the present technology. [Figure 10c] A diagram schematically showing address conversion according to various configurations of the present technology. [Figure 10d] A diagram schematically showing address conversion according to various configurations of the present technology. [Figure 11] A diagram schematically showing address conversion using recursion according to various configurations of the present technology. [Figure 12] A diagram schematically showing the use of a page walker cache in address conversion according to various configurations of the present technology. [Figure 13]A diagram schematically showing address translation by various configurations of the present technology. [Figure 14] A diagram schematically showing address translation by various configurations of the present technology. [Figure 15a] A diagram schematically showing address translation by various configurations of the present technology. [Figure 15b] A diagram schematically showing address translation by various configurations of the present technology. [Figure 16] A diagram schematically showing a series of steps executed to perform an intermediate lookup by various configurations of the present technology. [Figure 17] A diagram schematically showing a series of steps executed to perform an intermediate lookup by various configurations of the present technology.

[0006] According to some configurations, in response to receiving a first address, an address translation circuit is provided that performs address translation between the first address and a second address by performing a predetermined maximum number of sequential lookups at multiple page table levels. The address translation circuit includes a normal page table level with 2 N entries and 2 N*MThe circuit is configured to support large page table levels containing a certain number of entries. Each sequential lookup in a normal page table level is considered a single-level lookup of a predetermined maximum number of sequential lookups, and each sequential lookup in a large page table level is considered an M-level lookup of a predetermined maximum number of sequential lookups. The address translation circuit is further configured to perform an intermediate lookup to retrieve from the current intermediate page table level of a plurality of page table levels information indicating the sequentially next lookup address of the next page table level, and page table level size information indicating the size of the next page table level. The address translation circuit is further configured to perform an intermediate lookup to suppress subsequent lookups of a predetermined maximum number of sequential lookups and generate a second address based on the information indicating the sequentially next lookup address when the page table level size information indicates that the sequentially next lookup corresponds to one of the large page table levels and that performing the sequentially next lookup exceeds a predetermined maximum number of sequential lookups.

[0007] The address translation circuit performs address translation between a first address and a second address using a predetermined maximum number of sequential lookups. The predetermined number can be set in any way and, in some configurations, can be flexibly defined. However, in some configurations, the predetermined number is set in hardware and correlates with the number of bits or subsections of bits in the first address. Each of the predetermined lookups is performed using some indexing bits of the first address and information obtained sequentially from preceding lookups. The predetermined number of lookups is divided into intermediate lookups that generate intermediate addresses used in subsequent lookups and a final lookup used to generate the second address. Each of the multiple page tables contains a predetermined number of entries indexed by one of the indexing portions of the first address. The sequential lookups form a page table walk. The predetermined number of lookups results in a specific latency in the page table walk, which depends on the number of lookups that need to be performed. The inventors of this technique recognized that the number of lookups performed can typically be reduced through the definition of page tables and large page tables. Each normal page table is 2 where N is a positive (non-zero) integer. N It contains 2 to the power of N entries, and each large page table is 2 where M is a positive integer greater than 1. N*M It contains n entries (2 to the power of N*M). The address translation circuit is configured to treat each lookup in the normal page table as a single lookup out of a predetermined number of lookups (i.e., to count each lookup in the normal page table as a single lookup, or otherwise to treat each lookup as a lookup), and to treat each lookup in the large page table as M lookups. Therefore, it is possible to perform a single lookup in the large page table which is equivalent to M lookups in the normal page table, and as a result the number of lookups performed is reduced.

[0008] The address translation circuit is configured to determine, when performing an intermediate lookup, whether the next lookup corresponds to a large page table sequentially based on the size information in the current intermediate page table. If the size information indicates that the next lookup sequentially is a lookup in a large page table, the address translation circuit can determine that the next entry is equivalent to M lookups, and therefore can perform the next lookup using an appropriate number of bits (corresponding to an appropriate number of indexing parts) of the first address. The address translation circuit is further configured to suppress subsequent lookups of a predetermined maximum number of sequential lookups when the size information indicates that the next lookup sequentially corresponds to one of the large tables, and when performing the next lookup exceeds a predetermined number of sequential lookups. In particular, if a predetermined number of lookups is equal to an integer K and the current number of lookups is J, then if the size information indicates that the next lookup is in a large page table and J + M > K, then the remaining KJ lookups of the predetermined number of lookups are suppressed. In this situation, the address translation circuit does not perform a final lookup, but instead uses information obtained from the current intermediate page table level, which sequentially indicates the next lookup address, to generate the information from the second address and the first address. In such a configuration, the second address is generated directly from the next lookup address. In some such configurations, the upper part of the next lookup address forms the upper part of the second address, and the remaining lower part of the second address is generated by offsetting the lower part of the next lookup address by the amount indicated in the lowest part of the first address.

[0009] The number of bits used to index the page table can be defined variously and, in some configurations, differs for each lookup in a given number of lookups. However, in some configurations, the first address comprises a series of N-bit indexing portions, and the address translation circuit uses a single N-bit indexing portion of the series of N-bit indexing portions to index each successive lookup at one of the normal page table levels and is configured to index each successive lookup at one of the large page table levels using M successive N-bit indexing portions of the series of N-bit indexing portions. The series of N-bit indexing portions is also a subsection of the first address and, in some configurations, includes information for specifying the last part of the second address or information for specifying a particular start address of the first intermediate lookup. Each of the normal page tables includes a contiguous region of memory containing 2 N entries, aligned at the boundary between regions of size 2 N entries, whereby each normal page table address specifies a region of 2 N entries and a particular entry can be indexed using the N-bit indexing portion from the first address. In some configurations, the last N + D (where 2 D corresponds to the size of the page table entry in bytes) bits of the normal page table base address are 0, and the address of a particular entry is generated by replacing the last N + D bits of the normal page table base address with an N + D-bit indexing portion generated using the N-bit indexing portion from the first address with D subsequent zeros added as the least significant part. Similarly, each of the large page tables includes a contiguous region of memory containing 2 N*M entries (equal to M contiguous regions of size 2 N entries), aligned at the boundary between regions of size 2 N*M entries, whereby each large page table address is 2 N*MA region of entries is specified, and a particular entry can be indexed using M sequential N-bit indexing portions from a first address. In some configurations, the last M*N+D bits of the page table address are normally 0, and the address of a particular entry is generated by replacing the last M*N+D bits of the page table address with an (M*N+D) bit indexing portion generated using an N*M bit indexing portion from a first address with D trailing zeros appended as the least significant part.

[0010] It is desirable to provide a mechanism for mapping a first address to a lookup address at either a regular page table level or a large page table level, that is, to allow access via the first address to the memory space where one of the regular page table levels or large page table levels is stored. This can be achieved by sequentially performing recursive lookups, where the next lookup address corresponds to the address of the current intermediate page table, as one or more of a predetermined maximum number of lookups. However, the inventors have recognized that, when large page tables exist, this mechanism cannot always be used to map lookup addresses at all page table levels to the first address. For example, it may be desirable to sequentially map the lookup addresses of the first page table level. If large page tables do not exist, the lookup addresses of the first page table level can be mapped sequentially by repeatedly self-referencing the first page table level. The first page table level can then be indexed sequentially using the last indexed portion of the first address. However, if the first page table level is a large page table level treated as M lookups out of a predetermined number of lookups, then each lookup in the large page table requires M sequential N-bit portions of the first address. In such a case, there may not always be enough bits in the final indexing portion to sequentially index the first page table level, leading to failures. Therefore, in some configurations, when the page table level size information indicates that the execution of the next lookup sequentially is within a predetermined maximum number of lookups, and when the address of the next lookup sequentially corresponds to the address of the current intermediate page table, the intermediate lookup is considered a single-level lookup of a predetermined maximum number of sequential lookups, regardless of the current size of the current intermediate page table level.The address translation circuit is configured to either execute the next intermediate lookup sequentially when the execution of the next lookup is within (i.e., not exceeding) a predetermined maximum number of lookups, or to execute the final lookup when the execution of the sequential lookups results in a number of lookups equal to a predetermined maximum number of lookups. In such a situation, when the current lookup is a self-referential (recursive) lookup, i.e., a lookup that sequentially yields the address of the next lookup, which is the address of the current intermediate lookup, the current lookup is treated as a single lookup, independent of the size of the current lookup. In other words, if the current lookup is determined to be a lookup at the current large page table level, and the sequentially determined next lookup address is an address at the current large page table level, the current lookup is determined to be a single lookup, rather than M lookups associated with a non-self-referential large page table lookup. On the other hand, if the current lookup is a lookup at the current large page table level, and it is determined that the subsequent lookup addresses are different from the current large page table level addresses, then the current lookup is determined to consist of M lookups. By treating self-referencing lookups as a single lookup, it is always possible to index the page table level resulting from a predetermined number of lookups, and the lookup addresses of the large page table can be mapped as the first address.

[0011] In some configurations, the address translation circuit is configured to treat an intermediate lookup as a single-level lookup of a predetermined maximum number of sequential lookups, regardless of the current size of the current intermediate page table level, in response to a control bit indicating that the intermediate lookup should be treated as a single-level lookup. In some configurations, the control bit is provided as a control bit in the preceding page table level read in the previous lookup. Alternatively, in some configurations, the control bit is encoded in a first address. In some alternative configurations, the address translation circuit includes a memory circuit for storing a lookup table indicating page table levels, which are large page table levels, and the address translation circuit is configured to perform lookups in the lookup table to determine the value of the control bit based on the address of the current intermediate page. The control bit provides an alternative mechanism to avoid the need for the address translation circuit to determine whether a page table level is self-referential, which requires a comparison of the address of the current page table level with the addresses of the next page table level sequentially. Therefore, by using a control bit to indicate whether a page table level is self-referential, this comparison can be avoided, providing a more compact implementation.

[0012] In some configurations, the next lookup address sequentially corresponds to the address of the current intermediate page table, and when the current lookup corresponds to one of the large page table levels, the current lookup is indexed using the current M sequential parts of a set of N-bit indexing parts, and the lowest M-1 sequential N-bit indexing parts of the current M sequential indexing parts are the highest M-1 sequential N-bit indexing parts of the sequentially next M sequential indexing parts used to index the next lookup sequentially. Since each large lookup requires M sequential parts of a set of N-bit indexing parts, if a lookup in a large page table is a self-referencing lookup, then a total of 2 lots of M sequential parts of the set of N-bit indexing parts are required to perform these two lookups (the lookup that was self-referencing and the next lookup which must also be a large lookup because the current lookup is self-referencing). The inventors noticed that when a first lookup is treated as a single lookup, the total number of bits required to index a given number of sequential lookups exceeds the total number of bits available at the first address. Therefore, if a lookup is self-referential, some bits used to index the self-referential lookup are sequentially reused in subsequent lookups. For example, when M=2, a lookup at the big page table level requires two sequential N-bit indexing portions. In this example, the first address contains three sequential N-bit indexing portions, namely N-bit indexing portion 1, N-bit indexing portion 2, and N-bit indexing portion 3 (N-bit indexing portion 1 is the most significant indexing portion, followed by N-bit indexing portion 2, and then N-bit indexing portion 3). When a lookup is self-referential, a lookup at the big page table level is treated as a single-level lookup.As a result, the lowest part of the M=2 sequential indexing portion (the M-1 portion where M=2) is reused sequentially in the next lookup. In this case, the N-bit indexing portion 2 is used a second time in combination with the N-bit indexing portion 3, sequentially indexing the next lookup to the large lookup level. By using this mechanism and selecting the placement of recursive (self-referencing) entries at the large page table level, it is possible to perform a suitable number of lookups without having to add an additional N-bit portion to the first address.

[0013] In some implementations, the address translation circuit needs to access the same set of page table levels as legacy configurations that do not support large page table levels. To support such legacy configurations, in some configurations, the address translation circuit recognizes a legacy configuration region within one of the large page table levels, and the legacy configuration region identifies the next lookup address sequentially corresponding to the address of the current intermediate page table level. N It contains 2 entries and 2 sequential N-bit indexing parts N When referring to a legacy configuration area of ​​a given number of entries, it is further configured to generate a legacy configuration table failure. In such a configuration, the large pages corresponding to M of a given maximum number of sequential lookups are each 2 N 2 entries M A regular page table is included as one of several contiguous regions. A regular page table is two different pages within a large page table that can be treated as a regular page table by legacy configurations. NA legacy configuration area is reserved, containing entries that point to a specific region. In this way, the legacy configuration can interpret the page table level as if each page table level were a regular page table level. However, the address translation circuit can still achieve the advantages of using the large page table level unless it indexes into the legacy configuration area. Therefore, the M sequential N-bit indexing portions of the first address will fail if the address translation circuit is made to index into the legacy configuration area. The address translation circuit can recognize the legacy configuration in various ways. In some configurations, additional bits are provided in the page table level to indicate the legacy area. In other alternative configurations, the location of the legacy configuration area in the large table is fixed, and any attempt to index into the fixed area of ​​the large page table results in a legacy configuration failure.

[0014] In some configurations, the first address specifies a number of indexing portions equal to a predetermined number of lookups and a final portion that is used sequentially in combination with the next page table level address to generate the second address. If the intermediate lookups are lookups in a large page table containing M entries, and the size information indicates that performing the next lookups sequentially will exceed a predetermined maximum number of lookups by 1, then there are still M-1 (M minus 1) unused indexing portions. Therefore, the final portion of the first address is used in combination with the M-1 unused indexing portions and the next page table level address to form the second address. In some configurations, the address translation circuit is configured to output an invalid translation fault when the page table level size information indicates that performing the next lookups sequentially will exceed a predetermined maximum number of sequential lookups by an amount greater than 1. This is because if performing the next lookups sequentially will exceed a predetermined number of lookups by an amount greater than 1, there is insufficient information in the first address to generate the second address. Therefore, an invalid translation fault is output.

[0015] In some configurations, the address translation circuit further includes a memory circuit for storing information indicating sequentially first page table level addresses corresponding to a given maximum number of sequential lookups, and first size information indicating the size of the first page table level. In some configurations, the memory circuit is a specific memory location. In other configurations, the memory circuit is one or more registers used to store sequentially first page table level addresses. One or more registers also store size information so that sequentially the first intermediate lookups can be configured to correspond to one of the large page tables.

[0016] In some configurations, a memory circuit stores information indicating multiple page table level addresses, and an address translation circuit is configured to sequentially select a first page table level address from multiple page table level addresses based on one or more selection bits of the first address. In some configurations, the one or more selection bits are a single bit used to select between two first page table level addresses. In other configurations, the selection bits include multiple bits that enable the selection of multiple first page table level addresses. In some configurations, the address translation circuit is configured to recognize the one or more selection bits as one or more of the most significant bits of the first address. In other configurations, the address translation circuit is configured to recognize the one or more selection bits as information encoded in multiple control bits of the first address. In some configurations, each of the first page table level addresses stored in the memory circuit includes size information of its own, so as to be possible to uniquely define whether each of the first page table level addresses is a large page table level or a normal page table level. In other configurations, a single set of size information is provided that is used to determine whether all of the first page table level addresses are large page table level addresses or small page table level addresses.

[0017] In some configurations, the address translation circuit is configured to sequentially select a first page table level address from a plurality of page table level addresses, further based on the current privilege level. The privilege level is the privilege level of the processing circuit that provides the first address for translation by the address translation circuit. In this way, different first page table level addresses can be provided for higher and lower privilege levels. Using this technique, it is possible to maintain isolation between page table levels accessed by processors operating at higher privilege levels and those operating at lower privilege levels.

[0018] In some configurations, the address translation circuit further comprises a partial translation memory circuit that associates intermediate lookup information retrieved during an intermediate lookup with a corresponding subset of bits of a first address already used in the address translation, the intermediate lookup information further comprising information indicating the next lookup address sequentially and information indicating the size of the next page table level sequentially. The partial translation memory circuit allows the first subset to be skipped sequentially for a predetermined maximum number of sequential lookups, so that the first subset is performed sufficiently recently for a predetermined maximum number of sequential lookups, the translation of which is already stored in the partial translation cache. Each translation is fully defined based on the bits provided to the first address. In some configurations, the first address comprises a set of indexing portions associated with sequential lookup levels for a predetermined maximum number of sequential lookups. The partial translation memory circuit is configured to store information indicating each of these translations, and as a result, if the subsequent first address includes several indexing parts that are the same as the corresponding indexing parts of the competing translations, the results of these translations can be determined from the lookups in the partial translation memory circuit rather than repeating these lookups.

[0019] In some configurations, the address translation circuit is further configured to perform partial translation lookups in the partial translation memory circuit based on the first address, and when a partial translation lookup hits in the partial translation memory circuit, to sequentially retrieve information indicating the next lookup address and sequentially information indicating the size of the next page table level from the partial translation memory circuit, thereby suppressing lookups associated with the corresponding subset of bits of the first address that have already been used in the address translation. For example, if the first address, which includes four indexing parts, is translated, information indicating each of the lookups is stored in the partial translation memory circuit. If subsequent lookups share all four indexing parts, all four lookups can be skipped, and the second address can be determined based on the lookups in the partial translation memory circuit. However, if subsequent lookups share only two top-level indexing parts with the first address, the lookups associated with the two top-level indexing parts can be skipped, and the necessary information can be extracted from the partial address translation memory circuit. To support lookups corresponding to large page tables and normal page tables, the partial address translation memory circuit is configured to sequentially store size information indicating the size of the next page table level. Therefore, the partial address translation memory circuit can provide an additional method to reduce the total number of lookups required. When used in combination with large page table levels, the total number of lookups can be further reduced.

[0020] The first and second addresses may be defined within the same address space. However, in some configurations, the first address is defined in the first address space, and the second address is defined in the second address space. In such configurations, the second address space is a different address space from the first address space. In some configurations, each of the first and second address spaces is one of a virtual address space, an intermediate physical address space, or a physical address space. In this way, the address translation circuit can be configured to support a virtualization system in which virtual addresses are translated to intermediate physical addresses and then to physical addresses.

[0021] In some configurations, M is either a fixed value with single-bit size information, or the value of the variable and M is indicated by the size information. In some configurations where M is fixed, the value of M is defined as the central value stored in the register. In other configurations where M is fixed, the value of M is set by hardware and cannot be changed. In some configurations, M is equal to 2. Such configurations result in simpler implementations. In alternative configurations where the value of M is variable, the value of M is defined by the size information. For example, the size information can contain 2 bits, allowing for 4 values. The 4 values ​​can be used to sequentially indicate whether the next lookup corresponds to a normal lookup or a large lookup of size M=2, M=3, or M=4. This configuration can provide particularly flexible placement at the page table level.

[0022] Here, we will explain a specific example with reference to a diagram.

[0023] Figure 1 schematically shows an example of a data processing device 2 utilizing an address translation circuit in various configurations of this technology. The data processing device 2 includes multiple stages, including a fetch stage 6, a decoding stage 10, a rename stage 12, an issue stage 16, an execution stage 18, and a write-back stage 20. Instructions move from stage to stage through a pipeline, with some instructions in one stage of the pipeline and others pending in another. This is merely an example of a possible pipeline configuration, and it will be understood that other examples may have different stages or combinations of stages as needed.

[0024] The fetch stage 6 fetches instructions, for example, from the instruction cache. A branch predictor 4 may be provided to predict the outcome of a branch instruction. The fetched instructions are passed to the decode stage 10, which decodes the instructions to generate decoded instructions that can provide control signals to trigger the execution stage 18 to perform the corresponding processing operation. For some instructions fetched by the fetch stage 6, the decode stage 10 may map the instructions to two or more decoded instructions so that the “instructions” seen by later stages in the pipeline may be in a different form than the instructions fetched from the cache 8. The decoded instructions are passed to the register rename stage 12 to map the architecture register specifiers specified by the instructions to physical register specifiers that identify the corresponding physical registers 14 to be accessed in response to the instructions. The issue stage 16 queues instructions waiting to be issued for execution. The execution stage 18 executes instructions issued by the issue stage 16 and, in response to the instructions, performs various data processing operations such as arithmetic or logical operations, or load / store operations to the data cache 30 or a further level of cache 32 or memory 34. The execution unit 18 may have several execution units 22, 24, 21, 25, including a load / store unit 26 for queuing several pending load / store operations. An execution unit may be capable of speculative execution of one or more instructions, and a speculative control unit 35 may be provided to track the execution of speculatively executed instructions. The write-back stage 20 writes the results of the instructions executed by the execution stage 18 to a physical register file 14, which includes a predicate register 44 and a condition status register 42.

[0025] The pipeline also includes an address translation circuit 40 for performing translation between a first address and a second address. The address translation circuit 40 translates the first address received from the load / store unit 26 and the fetch stage 6 and returns the second address to the load / store unit 26 or fetch stage 6 from which the first address was received. The address translation circuit 40 performs address translation by performing a predetermined maximum number of sequential lookups at the page table level stored in the L2 cache 32 or memory 34.

[0026] Figure 2 schematically shows the details of the address translation circuit 40 in several exemplary configurations. The address translation circuit receives a first address 42, performs the translation, and outputs a second address 44. The address translation circuit 40 performs the translation by performing a predetermined maximum number of sequential lookups in a large number of page tables. The page tables are 2 N A normal page table level 48 containing 2 entries, and 2 N*MIt includes large page table levels containing n entries. Each lookup in one of the usual page table levels 48 is considered to be a single lookup of a predetermined maximum number of sequential lookups (i.e., counted). Each lookup in one of the large page table levels 46 is considered to be M lookups of a predetermined maximum number of sequential lookups. Each of the predetermined maximum number of lookups uses information from the preceding lookup and information from the first address. The predetermined maximum number of lookups includes intermediate lookups that sequentially generate the address of the next lookup in the next page table level and page table level size information indicating the size of the next page table level. During an intermediate lookup, if it is determined that the next lookup corresponds to a large lookup in the sequence of a predetermined maximum number of lookups, and that executing the next lookups sequentially would exceed a predetermined maximum number of sequential lookups, the subsequent lookups are suppressed, and the second address 44 is output based on the sequential lookup addresses determined from the current intermediate lookup and the information from the first address 42.

[0027] The address translation circuit 40 outputs a second address generated sequentially from the last lookup in a series of lookups. As described, this may be an output address obtained from an intermediate lookup (if it is determined that performing subsequent lookups sequentially would exceed a predetermined maximum number of lookups), or otherwise, an output address obtained from the last lookup. Unlike addresses from preceding lookups that point to a page table (large or normal) in memory, the output address is used directly to obtain the second address such that the number of bits in the second address is the same as the number of bits in the output address. In particular, the output address includes several bits, for example, a 32-bit output address used in a 32-bit address space (it is readily apparent to those skilled in the art that other address space sizes, e.g., a 64-bit address space, can also be used). At this stage, the output address indicates a region of the address space and does not indicate a specific second address. A specific second address output by the address translation circuit 40 is generated by offsetting the output address by the least significant bit from the first address. This is achieved by taking the upper part of the output address and appending the least significant bit of the first address to the upper part of the output address. For example, if the second address is a 32-bit address and the output address represents a normal-sized area of ​​memory, the second address is generated by taking the most significant 20 bits of the output address and appending the 12 bits of the first address to the most significant 20 bits. Alternatively, if the second address is a 32-bit address and the output address represents a larger-sized area of ​​memory, the second address is generated by taking the most significant 11 bits of the output address and appending the 21 bits of the first address to the most significant 11 bits. Alternatively, the second address can be generated by performing an arithmetic operation that combines the output address and the least significant part of the first address.

[0028] Figure 3 schematically illustrates further details of the address translation circuit 40 in several exemplary configurations. The address translation circuit includes a partial translation memory circuit 50 that caches information related to previous address translations. The address translation circuit 40 also includes a privileged base register 52 and a non-privileged base register 54. The privileged base register 52 and the non-privileged base register 54 each contain, sequentially, addresses of the first page table level and sequentially, size information indicating the size of the first page table level. The address translation circuit 40 makes a selection between the privileged base register 52 and the non-privileged base register 54 based on the information stored in the selection bit of the first address 42. In this way, the address translation circuit 40 maintains a distinction between translations associated with addresses provided by processing circuits operating in privileged mode and translations associated with addresses provided by processing circuits operating in non-privileged mode. The address translation circuit 40 is further provided with a fault output indicator 56. The fault output indicator 56 provides an indicator of faults that occur during the operation of the address translation circuit 40. The fault indicator 56 is used to indicate address translation faults and privilege level faults.

[0029] Figure 4 schematically shows the details of address translation performed by the address translation circuit 40 in various configurations. The address translation circuit 40 receives a first address. The first address contains 48 bits, which include a series of indexing portions (bits 47 to 39, bits 38 to 30, bits 29 to 21, and bits 20 to 12). Each indexing portion of the series of indexing portions corresponds to (or is used to correspond to) a lookup level of a predetermined maximum number of sequential lookups. In the illustrated configuration, the predetermined maximum number of lookups is 4, and the first address includes one indexing portion for each of the predetermined maximum number of lookups.

[0030] Bits 47 through 39 of the first address are L0 indexing bits, which are used to index to the page table level accessed during an L0 lookup (a first intermediate lookup sequentially for a predetermined number of lookups). The L0 lookup is performed at the page table level at the page table address (L0 base address) stored in the memory circuit of the address translation circuit. The memory circuit further includes size information indicating that the L0 lookup is a lookup at the normal page table level (next largest: 0). A lookup performed based on the L0 base address and L0 indexing bits sequentially returns the base address used for the next lookup, an L1 lookup, and size information indicating that the L1 lookup is a lookup at the normal page table level.

[0031] Bits 38 through 30 of the first address are L1 indexing bits used to index the page table level accessed during L1 lookups (second intermediate lookups sequentially following a predetermined number of lookups). L1 lookups are performed at the page table level using the base address (L1 base address) obtained during the L0 lookup. Lookups performed based on the L1 base address and L1 indexing bits sequentially return the base address used for size information indicating that the next lookup, L2 lookup, and L2 lookup are typically page table level lookups.

[0032] Bits 29 through 21 of the first address are L2 indexing bits, which are used to index to the page table level accessed during L2 lookups (a third intermediate lookup sequentially after a predetermined number of lookups). L2 lookups are performed at the page table level using the base address (L2 base address) obtained during the L1 lookup. Lookups performed based on the L2 base address and L2 indexing bits sequentially return the base address used for the next lookup, L3 lookup, and size information indicating that the L3 lookup is typically a page table level lookup.

[0033] Bits 20 through 12 of the first address are L3 indexing bits used to index at the page table level accessed during an L3 lookup (the final lookup of a predetermined number of lookups). The L3 lookup is performed at the page table level on the base address (L3 base address) obtained during the L2 lookup. The lookup performed based on the L3 base address and L3 indexing bits returns an address that is combined with the addressing portion (bits 11 through 0) of the first address to obtain the second address.

[0034] Figure 5 schematically illustrates the details of address translation performed by the address translation circuit 40 in various configurations. Similar to Figure 4, the address translation circuit 40 receives a first address. The first address contains a 48-bit first address that includes a series of indexing parts (bits 47 to 39, bits 38 to 21, and bits 20 to 12). Each indexing part of the series of indexing parts corresponds to (or is used to correspond to) a lookup level of a predetermined maximum number of sequential lookups. In the illustrated configuration, the predetermined maximum number of lookups is 4. However, the first address contains only three indexing parts. The second indexing part (bits 38 to 21) corresponds to a large lookup that is indexed using M=2 sequential indexing parts (i.e., a combination of bits 38 to 30 and bits 29 to 21). To ensure that the indexing parts of the first address are correctly interpreted by the address translation circuit, the corresponding page table level stores size information indicating when the next page table level is a large page table level. Note that size information is shown in the figure by setting the "next largest" indicator, i.e., the "NL" indicator, to 1. If the "next largest" indicator, i.e., the "NL" indicator, is not present in the figure, it implies that the "next largest" indicator, i.e., the "NL" indicator, is set to 0, indicating that the next page table level is a normal page table level. Compared to Figure 4, it can be seen that the indexing portions associated with the L1 and L2 lookups have been merged.

[0035] Bits 47 through 39 of the first address are L0 indexing bits, which are used to index to the page table level accessed during an L0 lookup (a first intermediate lookup sequentially for a predetermined number of lookups). The L0 lookup is performed at the page table level at the page table address (L0 base address) stored in the memory of the address translation circuit. The memory also includes size information indicating that the L0 lookup is normally a page table level lookup. A lookup performed based on the L0 base address and L0 indexing bits sequentially returns the base address used for the next lookup, the merged L1 / L2 lookup, and size information (next large: 1) indicating that the L1 / L2 lookup is a large page table level lookup.

[0036] Bits 38 through 21 of the first address are L1 / L2 indexing bits, which are used to index to the big page table level accessed during an L1 / L2 lookup (a single lookup in the big page table, which is a sequential second lookup equivalent to the L1 and L2 lookups in Figure 4). The L1 / L2 lookup is performed at the big page table level with the base address (L1 / L2 base address) obtained during the L0 lookup. The lookup performed based on the L1 / L2 base address and L1 / L2 indexing bits sequentially returns the base address used for the next lookup, the L3 lookup, and size information indicating that the L3 lookup is typically a page table level lookup.

[0037] Bits 20 through 12 of the first address are L3 indexing bits used to index at the page table level accessed during an L3 lookup (the final lookup of a predetermined number of lookups). The L3 lookup is performed at the page table level on the base address (L3 base address) obtained during the L1 / L2 lookup. The lookup performed based on the L3 base address and L3 indexing bits returns an address that is combined with the addressing portion (bits 11 through 0) of the first address to obtain the second address.

[0038] In the illustrated configuration, the L1 and L2 lookups are combined to form a single lookup within the large page table. It will be readily apparent to those skilled in the art that any sequential page table level lookups can be combined based on the techniques disclosed herein. Furthermore, the illustrated configuration shows that 9 bits are used for each of the N-bit portions. However, alternative configurations may provide a different number of bits, each providing different lookup levels using a different number of bits.

[0039] Figure 6 schematically shows the definition of the first page table level address based on the information stored in the memory circuit 60 of the address translation circuit 40. The first page table level address (L0 base address) is determined sequentially using one or more selection bits from the first address. The address translation circuit 40 performs a lookup in the memory circuit 60 based on one or more selection bits. One or more selection bits define the first page table level address sequentially from a plurality of first page table addresses stored in the memory circuit. In the illustrated configuration, address translation from the first address to the second address continues as described in relation to Figure 4.

[0040] Figure 7 schematically illustrates the concept of a recursive (self-referencing) lookup. A recursive lookup is used to map a first address to a page table level address. In the illustrated embodiment, the address translation circuit is configured to perform four sequential lookups (the given maximum number of sequential lookups is four). If no large page table exists, a predetermined number of lookups are performed at sequential page table levels L0, L1, L2, and L3 (as described with reference to Figure 4). When a recursive lookup occurs, the same page table level is referenced twice. As a result, one or more of the page table lookups may be looked up two or more times.

[0041] In the top lookup sequence of Figure 7, the first page table level sequentially defines the address of the first intermediate lookup 70. This is the L0 lookup 70 in the (L0) page table. The notation "L0" is used to indicate that the lookup is at the L0 level, and the notation "(L0)", i.e., the lookup level in parentheses, is used to indicate that the page table being looked up is the page table from the L0 lookup 70. In the L0 lookup 70, the (L0) page table is indexed using the L0 indexing portion of the first address. In this case, the L0 lookup returns an entry in the (L0) page table level that points to the (L0) page table. Next, the L1 lookup 72 is performed using the L1 indexing portion in the (L0) page table, i.e., the same page table used in the L0 lookup 70. In L1 lookup 72, the (L0) page table indexed using the L1 indexing portion returns the address of the (L1) page table level, i.e., the page table level that would have been referenced in L1 lookup 72 if there were no self-referencing lookup. Therefore, L2 lookup 74 is performed in the (L1) page table using the L2 indexing portion of the first address, and it returns the address of the (L2) page table level, i.e., the page table level that would have been referenced in L2 lookup 74 if there were no self-referencing lookup. Therefore, L3 lookup 76 is performed in the (L2) page table using the L3 indexing portion of the first address, and it returns the address of the (L3) page table. Since four lookups have been performed here, the address of the (L3) page table is output and used to generate the second address.

[0042] In the lookup sequence shown below in Figure 7, the first page table level sequentially defines the address of the first intermediate lookup 78. This is the L0 lookup 78 in the (L0) page table. In the L0 lookup 78, the (L0) page table is indexed using the L0 indexing portion of the first address. In this case, the L0 lookup returns an entry in the (L0) page table level that points to the (L0) page table. Next, the L1 lookup 80 is performed using the L1 indexing portion in the (L0) page table, i.e., the same page table used in the L0 lookup 78. In the L1 lookup 80, the (L0) page table indexed using the L1 indexing portion returns again the address of the (L0) page table level, i.e., the page table level that would have been referenced in the L0 lookup 78 if there were no self-referencing lookup. Therefore, the L2 lookup 82 is performed on the (L0) page table using the L2 indexed portion of the first address, and this returns the address of the (L1) page table level, i.e., the page table level that would have been referenced in the L1 lookup 80 if there had been no self-referencing lookup. Thus, the L3 lookup 84 is performed on the (L1) page table using the L3 indexed portion of the first address, and returns the address of the (L2) page table. Since four lookups have been performed here, the address of the (L2) page table is output and used to generate the second address.

[0043] The same technique can be used to generate a second address based on the (L1) page table address by using a further self-referencing lookup as L2 lookup 82. Furthermore, the same technique can be used to generate a second address based on the (L0) page table address by using two further self-referencing lookups as L2 lookup 82 and L3 lookup 84. In this way, addresses at each page table level can be mapped using self-referencing lookups.

[0044] Figures 8a and 8b schematically illustrate the use of recursion for address translation by the address translation circuit 40 when a large page table is used. Figure 8a schematically illustrates the use of recursion for mapping addresses in a large page table. Similar to Figures 4 to 7, the address translation circuit 40 is configured to perform four-level lookups in the page table as a predetermined maximum number of sequential lookups. The first address contains 48 address bits, including three 9-bit portions. Bits 47 through 39 define the index used during the L0 level lookup. Bits 38 through 30 define the index used during the L1 level lookup. Bits 29 through 21 define the index used during the L2 level lookup. The least significant 21 bits, from bit 20 to 0, are used in combination with the output from the L2 level lookup to form the second address.

[0045] In response to receiving the first address, the address translation circuit sequentially determines the first page table level address. This is determined from additional bits (not shown) of the first address, or sequentially from registers that store the first page table level address. Next, L0 level lookups are performed sequentially using the first page table level address to determine the (L0) page table indexed using bits 47 through 39 from the first address. An L0 lookup is a typical page table lookup and is therefore counted as a single lookup out of a given number of lookups. In this case, the entry in the (L0) page table is a self-referential entry pointing to the (L0) page table. Thus, an L1 lookup is performed in the (L0) page table using the L1 indexing bits (bits 38 through 30 from the first address). An L1 lookup is a typical page table lookup and is therefore counted as a single lookup out of a given number of lookups. An L1 lookup is also a self-referential entry pointing to the (L0) page table. Therefore, an L2 lookup is performed in the (L0) page table using the L2 indexing bits (bits 29 through 21 of the first address). An L2 lookup is typically a lookup in the page table and is therefore counted as one lookup out of a given number of lookups. Unlike L0 and L1 level lookups, an L2 level lookup is not a self-referential entry. Instead, an L2 level lookup results in an entry pointing to the L1 / L2 large page table. The size information determined from an L2 level lookup indicates to the address translation circuit that the next lookup is a large lookup (NL: 1, i.e., the next large one set to 1) that will be counted as M=2 lookups out of a given number of lookups.At this point, the address translation circuit 40 has performed three lookups (L0 level lookup, L1 level lookup, and L2 level lookup), each of which is considered a single-level lookup. Thus, the address translation circuit is performing three of the four maximum sequential lookups. Since the L2 level lookup indicates that the next level lookup is a large lookup, if the next lookups are performed sequentially, the number of lookups performed will be greater than the four maximum sequential lookups. Therefore, the address translation circuit 40 suppresses the remaining lookups of the four maximum sequential lookups and generates a second address using the base address of the (L1 / L2) large page table (determined during the L2 level lookup) and the least significant 21 bits of the first address to generate the second address, thus providing the address of the entry in the (L1 / L2) large page table.

[0046] Figure 8b schematically shows the alternative address translation performed by the address translation circuit 40 in response to the reception of the first address. Similar to Figures 4-7 and 8a, the address translation circuit 40 is configured to perform four-level lookups in the page table as a predetermined maximum number of sequential lookups. The first address contains 48 address bits, including two 9-bit portions. Bits 47 through 39 define the index used during the L0 level lookup. Bits 38 through 30 define the index used during the L1 level lookup. The first address further includes a single 18-bit portion. Bits 29 through 12 define the index used during the L2 / L3 level lookup. The least significant 12 bits of the first address, bits 11 through 0, are used in combination with the output from the L2 / L3 level lookup to form the second address.

[0047] In response to receiving the first address, the address translation circuit sequentially determines the first page table level address. This is determined from additional bits (not shown) of the first address, or sequentially from registers that store the first page table level address. Next, L0 level lookups are performed sequentially using the first page table level address to determine the (L0) page table indexed using bits 47 through 39 from the first address. An L0 lookup is a typical page table lookup and is therefore counted as a single lookup out of a given number of lookups. In this case, the entry in the (L0) page table is a self-referential entry pointing to the (L0) page table. Thus, an L1 lookup is performed in the (L0) page table using the L1 indexing bits (bits 38 through 30 from the first address). An L1 lookup is a typical page table lookup and is therefore counted as a single lookup out of a given number of lookups. Unlike L0 level lookups, L1 level lookups are not self-referential entries. Instead, L1 level lookups yield entries that point to the (L1 / L2) large page table. The size information determined from the L1 level lookup indicates to the address translation circuit that the next lookup is a large lookup (the next large, set to NL: 1-1) which counts as M=2 lookups out of a predetermined number of lookups. At this point, the address translation circuit 40 has performed two lookups (an L0 level lookup and an L1 level lookup), each of which is considered a single-level lookup. Thus, the address translation circuit is performing two out of four maximum sequential lookups. Since the L1 level lookup indicates that the next level lookup is a large lookup, if the next lookups are performed sequentially, the number of lookups performed will be equal to four maximum sequential lookups.Therefore, the address translation circuit 40 performs L2-level lookups and L3-level lookups as a single L2 / L3-level lookup in the (L1 / L2) large page table, which is indexed by the L2 / L3 indexing bits (bits 29 to 12 of the first address). This is the final lookup of the four largest lookups. Thus, the output from the L2 / L3 lookup in the (L1 / L2) page table is used in combination with the least significant 12 bits of the first address to generate a second address used to access the entry in the (L3) page table.

[0048] Figures 9a and 9c schematically illustrate the use of different N-bit portions of a first address to index different level lookups in address translation when the current level lookup is a lookup in a large page table. In Figure 9a, a first address 90 is provided, which includes four N-bit portions 90(A), 90(B), 90(C), and 90(D). The first address 90 also has a least significant H-bit portion 90(E) used to generate a second address based on the output from a series of level lookups. As with Figures 4 to 8, a given maximum number of sequential lookups is 4. Sequentially, the first lookup is an L0 / L1 lookup in a large page table (M=2). The L0 / L1 lookup in the large page table is indexed using the M=2 N-bit portion of the first address 90. In this case, the L0 / L1 lookup is indexed using the N-bit portion 90(A) and the N-bit portion 90(B). In Figure 9a, based on the L0 / L1 lookup, it is determined that the next level lookup is a lookup in the normal page table. Therefore, the next level lookup is an L2 level lookup indexed using a single N-bit portion 90(C) of the first address 90. Successively from the L2 lookup, the next lookups are also determined to be lookups in the normal page table. Therefore, the next level lookup is an L3 level lookup indexed using a single N-bit portion 90(D) of the first address 90. The output from the L3 level lookup is combined with the H-bit portion 90(E) of the first address 90 to generate the second address.

[0049] In Figure 9b, a first address 92 is provided, which includes four N-bit portions 92(A), 92(B), 92(C), and 92(D). The first address 92 also has a least significant H-bit portion 92(E) used to generate a second address based on the output from a series of level lookups. As in Figures 4-8, a given maximum number of sequential lookups is 4. Sequentially, the first lookup is an L0 / L1 lookup in a large page table (M=2). The L0 / L1 lookup in the large page table is indexed using the M=2 of the N-bit portion of the first address 92. In this case, the L0 / L1 lookup is indexed using the N-bit portions 92(A) and 92(B). In Figure 9b, based on the L0 / L1 lookup, it is determined that the next level lookup is a lookup in a different large page table than the one referenced in the L0 / L1 lookup. Therefore, the next level lookup is an L2 / L3 level lookup in a large page table (M=2) indexed using M=2 sequential N-bit portions 92(C) and 92(D) of the first address 92. The output from the L2 / L3 level lookup is combined with the H-bit portion 92(E) of the first address 92 to generate the second address.

[0050] Figure 9c provides a first address 94 containing four N-bit portions 94(A), 94(B), 94(C), and 94(D). The first address 94 also has a least significant H-bit portion 94(E) used to generate a second address based on the output from a series of level lookups. As with Figures 4-8, a given maximum number of sequential lookups is 4. Sequentially, the first lookups are L0 / L1 lookups in a large page table (M=2). The L0 / L1 lookups in the large page table are indexed using the M=2 of the N-bit portion of the first address 94. In this case, the L0 / L1 lookups are indexed using the N-bit portions 94(A) and 94(B). In Figure 9c, based on the L0 / L1 lookup, it is determined that the next level lookup is a lookup in the large page table, and that the L0 / L1 lookup is a self-referential lookup that references the (L0 / L1) page table. Since the L0 / L1 lookup is a self-referential lookup, it can be considered a single-level lookup. Therefore, the next level lookup is the L1 / L2 level lookup in the (L0 / L1) large page table. The L1 / L2 level lookup is indexed using M=2 of the N-bit portion of the first address 94. The address translation circuit 40 reuses the least significant M-1=1 of the N-bit portions 94(A) and 94(B) that were used to index the L0 / L1 level lookup as the most significant M-1=1 of the N-bit portion, and indexes the L1 / L2 level lookup in (L0 / L1). Therefore, the L1 / L2 lookup is performed using the N-bit portion 94(B) and the N-bit portion 94(C). Based on the L1 / L2 lookup, it is determined that the next lookup is a lookup in a regular page table. Thus, the next level lookup is an L3 level lookup in an (L2) page table indexed using a single N-bit portion 94(D) of the first address 90.The output from the L3 level lookup in the (L2) level page table is combined with the H bit portion 90(E) of the first address 90 to generate the second address in the (L3) level page table.

[0051] Figures 10a to 10d schematically illustrate address translation based on the principle shown in Figures 9a to 9c. In Figure 10a, the first address is translated to the second address by the address translation circuit 40. The predetermined maximum number of sequential lookups is 4. The address translation circuit sequentially determines the first page table level address based on the most significant bit (not shown) of the first address. Sequentially, the first address points to the large page table (M=2) indexed using M=2 of the N-bit portion of the first address. Therefore, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed from bits 47 to 30 of the first address. Sequentially, the next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using the most significant M-1=1 portion of the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table. In this case, bits 38 through 21 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns the address of the next page table in a different order than the (L0 / L1) page table level. The size information returned by the L1 / L2 lookup indicates that the next page table is a normal page table (NL set to 0). Therefore, the next lookup is an L3 lookup in the (L2) page table, which is indexed by the following N-bit portion of the first address in a different order. In this case, the L3 lookup in the (L2) page table is indexed using bits 20 through 12 of the first address.An L3 lookup sequentially returns the address of the next page table, i.e., the (L3) page table. Once a predetermined maximum number of lookups have been performed (one lookup for L0 / L1 self-referential level lookups, M=2 lookups for L1 / L2 level lookups, and one lookup for L3 level lookups), the L3 page table is combined with the least significant 12 bits (bits 11 through 0) of the first address to generate a second address.

[0052] In Figure 10b, the first address is translated to the second address by the address translation circuit 40. The predetermined maximum number of sequential lookups is 4. The address translation circuit sequentially determines the first page table level address based on the most significant bit (not shown) of the first address. Sequentially, the first address points to the large page table (M=2) indexed using M=2 of the N bit portion of the first address. Therefore, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed from bits 47 to 30 of the first address. Sequentially, the next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using the M-1=1 of the most significant M-1=1 portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table. In this case, bits 38 through 21 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns the address of the next page table sequentially, different from the (L0 / L1) page table level. The size information returned by the L1 / L2 lookup indicates that the next page table is a large page table (NL is set to 1). Up until now, the address translation circuit has performed three level lookups (one lookup for the L0 / L1 self-referential level lookup, and M=2 for the L1 / L2 level lookup). The next level lookup is in the large page table, so performing this lookup will cause the number of lookups to exceed the predetermined maximum number of lookups.Therefore, further lookups are suppressed, and the (L2 / L3) level page table address output from the (L0 / L1) page table during the L1 / L2 lookup is used to generate the second address. Since the output page table level is a large page table, the remaining 21 bits of the first address are needed to generate the second address.

[0053] In Figure 10c, the first address is translated to the second address by the address translation circuit 40. In the address translation in Figure 10c, the predetermined maximum number of sequential lookups is 5. The address translation circuit sequentially determines the first page table level address based on the most significant bit (not shown) of the first address. Sequentially, the first address points to the large page table (M=2) indexed using M=2 for the N-bit portion of the first address. Therefore, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed from bits 56 to 39 of the first address. Sequentially, the next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using the most significant M-1=1 portion of the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table. In this case, bits 47 through 30 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns the address of the next page table sequentially, different from the (L0 / L1) page table level. The size information returned by the L1 / L2 lookup indicates that the next page table is a large page table (NL is set to 1). Up to this point, the address translation circuit has performed three level lookups (one lookup for the L0 / L1 self-referential level lookup, and M=2 for the L1 / L2 level lookup). The next level lookup is in the large page table, so performing this lookup will bring the total number of lookups to equal a predetermined maximum number of lookups (5 in this address translation).Therefore, the next lookup is determined to be an L3 / L4 level lookup in the (L2 / L3) page table indexed from bit 29 to bit 12 of the first address. The L3 / L4 level lookup in the (L2 / L3) page table returns an address in the (L4) page table. This address is combined with the least significant 12 bits of the first address to generate a second address in the (L4) level page table.

[0054] Figure 10d shows an alternative configuration in which a control bit stored in the current page table level is used to indicate whether a lookup is a self-referential lookup. In Figure 10d, the first address is translated to the second address by the address translation circuit 40. In the address translation of Figure 10d, the predetermined maximum number of sequential lookups is 5. Furthermore, the address translation circuit 40 is configured to determine whether to count a page table level as a single lookup level based on the control bit, rather than by directly determining whether the page table level is a self-referential page table level. The address translation circuit sequentially determines the first page table level address based on the most significant bit (not shown) of the first address. Sequentially, the first address points to a large page table (M=2) indexed using M=2 for the N-bit portion of the first address. Thus, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed from bits 56 to 39 of the first address. The sequentially occurring page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. However, instead of determining whether the L0 / L1 lookup is a self-referential lookup by comparing the address used for the L0 / L1 lookup with the address output from the L0 / L1 lookup, the address translation circuit 40 determines that the L0 / L1 lookup is a self-referential lookup because the control bit is set. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using the M-1=1 of the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the N-bit portion of the most significant M-1=1 used to index the L1 / L2 level lookup in the (L0 / L1) page table.In this case, bits 47 through 30 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns the address of the next page table sequentially, different from the (L0 / L1) page table level. However, instead of determining that the address of the next lookup sequentially does not correspond to the address of the L1 / L2 level lookup, the address translation circuit determines that the L1 / L2 level lookup is not a self-referential lookup based on a control bit that is set to 0 in this case. The size information returned by the L1 / L2 lookup indicates that the next page table is a large page table (NL is set to 1). Up to this point, the address translation circuit has performed three level lookups (one lookup for the L0 / L1 self-referential level lookup, and M=2 for the L1 / L2 level lookup). Since the next level lookup is in a large page table, performing this lookup will result in a total number of lookups equal to a predetermined maximum number of lookups (5 in this address translation). Therefore, the next lookup is determined to be an L3 / L4 level lookup in the (L2 / L3) page table indexed from bit 29 to bit 12 of the first address. The L3 / L4 level lookup in the (L2 / L3) page table returns an address in the (L4) page table. This address is combined with the least significant 12 bits of the first address to generate a second address in the (L4) level page table.

[0055] Figure 11 schematically illustrates the effect of address translation, where the final lookup out of a predetermined number of lookups indicates that the next level lookup will be in a large page table (M>1). The address translation circuit 40 performs the translation of the first address with a predetermined maximum number of sequential lookups equal to 4. The first to third level lookups (L0 level lookup, L1 level lookup, L2 level lookup) are not self-referential lookups, but rather lookups in a normal page table. Therefore, the L3 lookup is sequentially the fourth level lookup. In the L3 lookup, the size information (NL set to 1) is determined to indicate that the address output corresponds to an address in a large page table (M=2). Since there are already four level lookups (each of which L0 through L3 is counted as a single level lookup), the address translation circuit determines that it is impossible to continue because there are not enough bits remaining in the first address to generate an address for a large page table that requires either two N-bit segments for byte addressing or two N-bit segments + 3 bits for bit addressing. Because there are insufficient bits remaining in the first address, the address translation circuit outputs a fault.

[0056] Figure 12 schematically illustrates the use of the memory circuit (pagewalker cache 100) within the address translation circuit when translating from a virtual address (VA) as the first address to a physical address (PA) as the second address. The address translation circuit receives the virtual address and performs an initial lookup in the pagewalker cache 100. The lookup in the pagewalker cache 100 determines whether the virtual address or part thereof has recently been translated by the address translation circuit. The lookup in the pagewalker cache 100 results in a hit if any sequentially most significant portion of the first address is hit in the cache. Therefore, a cache hit occurs if the most significant N bits of the virtual address are hit in the pagewalker cache 100. A hit also occurs if two most significant N bits of the virtual address are hit in the pagewalker cache 100. A hit also occurs if three most significant N bits of the virtual address are hit in the pagewalker cache. Finally, a hit occurs if four most significant N bits of the virtual address are hit in the pagewalker cache. In this way, the pagewalker cache can determine multiple hits for a single virtual address. If there are multiple hits in the pagewalker cache 100, the address translation circuit is configured to use the most specific match, i.e., the hit that matches the largest N bits of the virtual address.

[0057] If a lookup in the page walker cache 100 fails, the address translation circuit performs address translation by performing up to a predetermined number of sequential lookups at the page table level. In this case, the page walker cache 100 performs L0 level lookup 102, L1 level lookup 104, L2 level lookup 106, and L3 level lookup 108 to determine the physical address.

[0058] If the best hit in the page walker cache 100 matches only the most significant N bits of the virtual address, the address translation circuit does not need to perform the L0 lookup because it can retrieve the result from the page walker cache. Therefore, the address translation circuit performs L1 lookup 104, L2 lookup 106, and L3 lookup 108 to determine the physical address.

[0059] If the best hit in the pagewalker cache 100 matches the two most significant N bits of the virtual address, the address translation circuit can retrieve the result of the L0 lookup or L1 lookup from the pagewalker cache, and therefore does not need to perform these lookups. Consequently, the address translation circuit performs L2 lookup 106 and L3 lookup 108 to determine the physical address.

[0060] If the best hit in the pagewalker cache 100 matches the three most significant N bits of the virtual address, the address translation circuit does not need to perform L0, L1, or L2 lookups, as the results of these lookups can be retrieved from the pagewalker cache. Therefore, the address translation circuit performs only the L3 lookup 108 to determine the physical address.

[0061] Figure 13 schematically illustrates the use of the page walker cache 100 for performing address translation. The address translation circuit 40 receives a first address to be translated to a second address. The address translation circuit performs the first lookup of the first address in the page walker cache 100. The lookup in the page walker cache 100 determines whether any top-most part of the first address matches an entry in the page walker cache 100. The top 9 bits of the first address 102 are determined to be a hit in the page walker cache 100, and the page walker cache entry 104 is returned. Thus, the address translation circuit 40 can suppress the L0 lookup and proceed directly to the next level lookup based on the returned page walker cache entry 104. The page walker cache entry 104 provides the base address for the next level lookup and size information (NL set to 1) indicating that the next level lookup is a lookup in one of the large page tables. Therefore, the address translation circuit 40 determines that the next level lookup is an L1 / L2 lookup at the (L1 / L2) page table level. The address translation circuit performs this lookup and determines the entry in the (L1 / L2) page table level based on 18 bits (bits 38 to 21) of the first address. The result of the L1 / L2 level lookup is the address of the L3 lookup and size information indicating that the L3 level lookup is normally a lookup in the page table. The address translation circuit 40 uses 9 bits (bits 20 to 12) of the first address to perform an L3 lookup in the (L3) page table. The result of the L3 level lookup is used in combination with the last 12 bits of the first address to generate the second address.

[0062] Figure 14 schematically shows the interpretation of the large page table 106 in the legacy configuration. The large page table 106 is 2 MThis is a memory region occupied by 2 consecutive normal page tables. Therefore, a legacy translation circuit can be used to perform a page table walk to translate the first address to the second address by performing a page table walk in which each page table is treated as a normal page table. The large page table 106 is located in memory. N*M It is aligned to the boundary between the areas of the individual entries. Therefore, each of the contiguous regular page tables contained in the large page table is 2 NThe entries are aligned to the boundaries between regions. As a result, a specific region of the large page table 106 can be determined using the entries of the preceding page table level 108. Thus, the legacy address translation performs the first L0 lookup based on the most significant part of the first address, and determines that the next lookup, the L1 lookup, is the normal page table 108. The legacy address translation circuit performs a lookup in the normal page table 108 using index bits 38 to 30 of the first address to determine a specific normal page table from the consecutive normal page tables that make up the large page table 106. Then, using the specific normal page table of the large page table 106, an L2 level lookup is performed based on bits 29 to 21 of the first address. The page table walk then continues to perform L3 lookups, and continues to output the second address based on this information. By combining an L1-level lookup and an L2-level lookup as a single L1 / L2-level lookup, the address translation circuit 40 using this technique can perform the same translation. In this single L1 / L2-level lookup, bits 38 through 21 of the first address are used to index the large page table 106, thereby performing a single L1 / L2-level lookup instead of two lookups (one L1-level lookup and one L2-level lookup). In such a configuration, a different (L0)-level page table entry is cached than the (L0)-level page table entry used by the legacy configuration. The legacy (L0)-level page table entry points to the legacy L1 page table. In contrast, the (L0)-level page table entry used by the address translation circuit 40 points to the combined L1 / L2 page table. Thus, the legacy configuration is provided with a different (L0)-level page table entry for the address translation circuit 40.

[0063] Figures 15a and 15b schematically illustrate the translation of a first address to a second address by address translation circuits using the legacy configuration (Figure 15a) and the present technique (Figure 15b), when a preceding legacy configuration area 110 embedded within the large page table is provided at the large page table level 112. In Figure 15a, the legacy address translation circuit receives the first address and performs an L0 level lookup based on the L0 index portion of the first address (bits 47 to 39). The L0 level lookup returns a base address for an L1 level lookup that points to the legacy configuration area 110 embedded within the large page table 112. The legacy address translation circuit is unaware of the large page table and uses the L1 indexing bits of the first address (bits 38 to 30) to access the legacy configuration area as if it were a regular page table, as part of an L1 level lookup. An L1 level lookup in the legacy configuration area 110 returns the address of a specific normal page table size area of ​​the large page table 112 used for an L2 level lookup. The L2 level lookup is performed in a specific area of ​​the normal page table size area of ​​the large page table 112 using the L2 indexing bits (bits 29 to 21) of the first address. The L2 level lookup returns the address of the normal page table used in combination with the L3 indexing bits (bits 20 to 12) of the first address to perform an L3 lookup. The result of the L3 level lookup is combined with the least significant bit (bits 11 to 0) of the first address to generate a second address.

[0064] Figure 15b schematically shows the performance of the address translation circuit 40 according to this technology. The address translation circuit 40 receives a first address and performs an L0 level lookup based on the L0 index portion (bits 47 to 39) of the first address. In this case, the first address is the same as the first address used in the legacy configuration. The result of the L0 level lookup is the base address of the legacy configuration area 110 of the large page table 112 and size information (NL set to 1) indicating that the next level lookup is a lookup within the large page table. The large page table has a size of 2 N*M Aligned to the boundary between regions, page tables are typically size 2 N Since it is aligned to the boundary between the regions, the uppermost part of the base address for the legacy configuration region 110 is also the base address of the large page table 112. Therefore, by using the L1 / L2 indexing portion of the first address in combination with the base address determined from the (L0) level lookup, the address translation circuit 40 can directly index the large page table 112. Thus, the address translation circuit performs the next level lookup, the L1 / L2 level lookup, in the large page table 112 using the L1 / L2 indexing bits (bits 38 to 21) of the first address that point to a specific entry at the (L1 / L2) page table level. Before proceeding to perform the lookup, the address translation circuit 40 checks that the L1 / L2 indexing bits do not point to the legacy configuration region 110 of the large page table 112. The result of an L1 / L2 level lookup returns the address of a normal page table, which is used in combination with the L3 indexing bits (bits 20 through 12) of the first address to perform an L3 lookup, and size information indicating that the L3 level lookup is a normal level lookup. The result of the L3 level lookup is combined with the least significant bits (bits 11 through 0) of the first address to generate a second address.

[0065] Figure 16 schematically shows the series of steps performed by the address translation circuit when performing an intermediate lookup. The flow starts in step S100, where the address translation circuit starts an intermediate lookup in the current intermediate page table. The flow then proceeds to step S102, where the address translation circuit retrieves information from the current intermediate page table indicating the sequential lookup addresses of the next page tables. Next, the flow proceeds to step S104, where the address translation circuit retrieves page table size information from the current intermediate page table indicating the size of the next page tables. Next, the flow proceeds to step S106, where it is determined whether performing the next lookups sequentially will exceed a predetermined maximum number of lookups. If it is determined in step S106 that performing the next lookups will not exceed a predetermined maximum number of lookups, the flow proceeds to step S108, where the current intermediate lookup is terminated, and then the next lookup (either another intermediate level lookup or a final level lookup) is started. In step S106, if it is determined that sequentially performing the next lookup would exceed a predetermined maximum number of lookups, the flow proceeds to step S110, where subsequent lookups are suppressed, and the address translation circuit generates a second address based on information indicating the next lookup address.

[0066] Figure 17 schematically shows a set of steps performed by the address translation circuit in response to the reception of the first address in order to generate a second address. The flow begins in step S200, when the address translation circuit receives a representation of the first address and first size information. In step S200, the address translation circuit also sets counter j to equal 1. Next, the flow proceeds to step S202, where it is determined whether the j-th page table is a large page table. If it is determined in step S202 that the j-th page table is not a large page table, the flow proceeds to step S212, where the address translation circuit uses a single N-bit portion of the first address to identify an entry in the j-th page table. Then the flow proceeds to step S206. If it is determined in step S202 that the j-th page table is a large page table, the flow proceeds to step S204. In step S204, the address translation circuit uses M sequential N-bit portions of the first address to identify an entry in the j-th page table. Next, the flow proceeds to step S206. In step S206, the address translation circuit retrieves from the entry in the j-th page table information that indicates the (j+1)th lookup address in the (j+1)th page table, and the (j+1)th page table size information that indicates the size of the (j+1)th page table.

[0067] Next, the flow proceeds to step S208, where it is determined whether the size information of the (j+1)th lookup indicates that the next lookup will cause the total number of lookups to exceed a predetermined number. In particular, the size of the current lookup can be determined from steps S202, S204, and S212. Therefore, the total number of lookups required to sequentially execute the next lookups can be determined from the information regarding the size of the current (j) lookup and the information returned as size information from the j lookup. If it is determined in step S208 that executing the (j+1)th lookup will exceed a predetermined number of lookups, the flow proceeds to step S210. In step S210, the address translation circuit suppresses subsequent lookups and generates a second address based on the information indicating the lookup address of the (j+1)th lookup. If it is determined in step S208 that executing the (j+1)th lookup will not exceed a predetermined number of lookups, the flow proceeds to step S214.

[0068] In step S214, it is determined whether the j-th page table is a large page table. If it is determined in step S214 that the j-th page table is not a large page table, the flow proceeds to step S222, and the current lookup is counted as a single lookup (considered to be a single lookup). Next, the flow proceeds to step S224, where j is incremented by 1, and then the flow returns to step S202. If it is determined in step S214 that the j-th page table is a large page table, the flow proceeds to step S216. In step S216, the address translation circuit determines whether the (j+1)-th lookup address corresponds to the address of the j-th page table. If it is determined in step S216 that the (j+1)-th lookup address corresponds to the address of the j-th page table, the flow proceeds to step S222, and the current lookup is counted as a single lookup (considered to be a single lookup). Next, the flow proceeds to step S224, where j is incremented by 1, and then the flow returns to step S202. In step S216, if it is determined that the (j+1)th lookup address does not correspond to the jth page table address, the flow proceeds to step S218, where the current lookup is counted (or considered to be counted) as M lookups. Then the flow proceeds to step S220. In step S220, j is incremented by M before the flow returns to step S202.

[0069] In summary, this invention relates to an address translation circuit and method for performing address translation. The address translation circuit performs address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in response to the reception of a first address. The address translation circuit is 2 N A regular page table containing 1 entry, and 2 N*MIt is configured to support a large page table containing 100 entries. The address translation circuit performs intermediate lookups to sequentially retrieve information indicating the next lookup address and page table size information, and if the page table size information indicates that the next lookup sequentially corresponds to one of the large page tables, and the execution of the next lookups sequentially exceeds a predetermined maximum number of sequential lookups, it is configured to suppress subsequent lookups and generate a second address based on the information indicating the next lookup address sequentially.

[0070] In this application, the term "configured to..." is used to mean that an element of the device has a configuration capable of performing a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to..." does not mean that any modifications must be made to the device element in order to provide the defined operation.

[0071] While exemplary embodiments have been described in detail in this specification with reference to the accompanying drawings, it should be understood that the present invention is not limited to embodiments identical thereto, and various changes, additions, and modifications can be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, various combinations of the features of the dependent claims can be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. An address translation circuit that performs address translation between the first address and the second address by performing a predetermined maximum number of sequential lookups at multiple page table levels in response to the reception of the first address, The address translation circuit described above is 2 Ｎ A normal page table level containing 1 entry, and 2 Ｎ＊Ｍ It supports large page table levels containing 1000 entries, where each sequential lookup in the normal page table level is considered a single-level lookup of a predetermined maximum number of sequential lookups, and each sequential lookup in the large page table level is considered an M-level lookup of a predetermined maximum number of sequential lookups. From the current intermediate page table level among the multiple page table levels, information indicating the sequential lookup address of the next page table level and page table level size information indicating the size of the next page table level are extracted. An address translation circuit is configured such that, when the page table level size information indicates that the next sequential lookup corresponds to one of the large page table levels and that performing the next sequential lookup exceeds a predetermined maximum number of sequential lookups, it suppresses subsequent lookups after the predetermined maximum number of sequential lookups and performs an intermediate lookup to generate the second address, based on the information indicating the next sequential lookup address.

2. The first address includes a series of N-bit indexing portions, and the address translation circuit is Using a single N-bit indexing portion from the series of N-bit indexing portions, index each sequential lookup in one of the normal page table levels: The address translation circuit according to claim 1, configured to index each sequential lookup in one of the large page table levels using M sequential N-bit indexing portions from the series of N-bit indexing portions.

3. The address translation circuit according to claim 2, wherein when the page table level size information indicates that the execution of the next sequential lookup is within a predetermined maximum number of lookups, and when the address of the next sequential lookup corresponds to the address of the current intermediate page table, the intermediate lookup is considered to be a single-level lookup of the predetermined maximum number of sequential lookups, regardless of the current size of the current intermediate page table level.

4. The address translation circuit according to claim 2, wherein the address translation circuit is configured to treat the intermediate lookup as the single-level lookup of a predetermined maximum number of sequential lookups, in response to a control bit indicating that the intermediate entry is to be treated as a single-level lookup, regardless of the current size of the current intermediate page table level.

5. If the subsequent lookup addresses correspond to the address of the current intermediate page table, and the current lookup corresponds to one of the major page table levels, The current lookup is indexed using the current M sequential indexing portions of the series of N-bit indexing portions, The address translation circuit according to claim 3 or 4, wherein the least significant M-1 sequential N-bit indexing portion of the current M sequential indexing portions is the most significant M-1 sequential N-bit indexing portion of the next M sequential indexing portions used to sequentially index the next lookups.

6. The legacy configuration area in one of the major page table levels is recognized, and the legacy configuration area sequentially identifies the next lookup address corresponding to the address of the current intermediate page table level. Ｎ It has individual entries, The address translation circuit according to any one of claims 2 to 4, further configured to generate a legacy configuration table failure when the M sequential N-bit indexing portions point to the legacy configuration region of 2N entries.

7. The address translation circuit according to any one of claims 1 to 4, wherein the address translation circuit is configured to output an invalid translation error when the page table level size information indicates that performing the next sequential lookup will exceed the predetermined maximum number of sequential lookups by an amount greater than 1.

8. The address translation circuit according to any one of claims 1 to 4, further comprising a storage circuit for storing information indicating first page table level addresses sequentially corresponding to first intermediate lookups of a predetermined maximum number of sequential lookups, and first size information indicating the size of the first page table level.

9. The memory circuit stores information indicating multiple page table level addresses, The address translation circuit is configured to sequentially select the first page table level address from the plurality of page table level addresses based on one or more selection bits of the first address. The address translation circuit according to claim 8.

10. The address translation circuit is configured to sequentially select a first page table level address from the plurality of page table level addresses based on the current privilege level. The address translation circuit according to claim 9.

11. The address translation circuit according to any one of claims 1 to 4, further comprising a partial translation storage circuit that associates intermediate lookup information retrieved during the intermediate lookup with a corresponding subset of bits of the first address already used in the address translation, wherein the intermediate lookup information further comprises information indicating the sequentially next lookup address and information indicating the size of the sequentially next page table level.

12. Based on the first address, the partial conversion memory circuit performs a partial conversion lookup. When the partial translation lookup hits in the partial translation memory circuit, the information indicating the sequentially next lookup address and the information indicating the size of the sequentially next page table level are retrieved from the partial translation memory circuit, and the lookup associated with the corresponding subset of bits of the first address already used in the address translation is suppressed. The address translation circuit according to claim 11, further configured as follows.

13. The address translation circuit according to any one of claims 1 to 4, wherein the first address is defined in a first address space, and the second address is defined in a second address space.

14. Each of the first address space and the second address space is: Virtual address space and Intermediate physical address space and A physical address space and an address translation circuit according to claim 13, which is one of the physical address spaces.

15. In response to receiving the first address, 2 Ｎ A normal page table level containing 1 entry, and 2 Ｎ＊Ｍ A method for performing address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in a plurality of page table levels, including a large page table level containing n entries, wherein each sequential lookup in the normal page table level is considered to be a single lookup of the predetermined maximum number of sequential lookups, and each sequential lookup in the large page table level is considered to be M lookups of the predetermined maximum number of sequential lookups. The aforementioned method, From the current intermediate page table level among the multiple page table levels, information indicating the sequential lookup address of the next page table level, and page table level size information indicating the size of the next page table level are retrieved. A method for performing an intermediate lookup, which includes: when the page table level size information indicates that the sequentially subsequent lookup corresponds to one of the large page table levels and that performing the sequentially subsequent lookup exceeds a predetermined maximum number of sequential lookups, suppressing subsequent lookups after the predetermined maximum number of sequential lookups based on the information indicating the sequentially subsequent lookup addresses and generating the second address.

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