Combined imaging array, strip, and pixel noise cancellation system

Abstract

Some system embodiments include a plurality of pixels, data lines coupled to the pixels, switches coupling the pixels to the data lines, and a plurality of readout circuits coupled to the data lines. The system also includes control logic coupled to the readout circuits, the control logic configured to: for one of the pixels, obtain a first value for the pixel while a corresponding switch is in an off state, reset a corresponding readout circuit corresponding to the pixel, obtain a second value for the pixel after resetting the readout circuit, turn on the corresponding switch, obtain a third value for the pixel after turning on the corresponding switch, and combine the values ​​into a combined pixel value. Some system embodiments include a housing, an imaging array in the housing, an imaging strip in the housing, a first readout circuit coupled to the imaging array, a second readout circuit coupled to the imaging strip, and common electronics coupled to the first and second readout circuits and configured to generate image data in response to at least one of the first and second readout circuits.

Description

[Background technology]

[0001] An X-ray imaging array can be used to generate two-dimensional images or videos in response to incident X-rays. The imaging strip can be panned around an axis to generate a panoramic image.

[0002] Noise can accumulate in the pixels of an imaging array. While various techniques, such as correlated double sampling, can reduce or remove noise from other components in the chain from the pixel to the image, the noise in the pixel itself may remain. [Brief explanation of the drawing]

[0003] [Figure 1] This is a block diagram of an imaging system including an imaging array and an imaging strip, according to several embodiments. [Figure 2] This is a flowchart illustrating the operation of an imaging system according to several embodiments. [Figure 3] This is a block diagram of an imaging system including a substrate according to several embodiments. [Figure 4] This is a block diagram of an imaging system with separate row drivers in several embodiments. [Figure 5] This is a block diagram of an imaging system in which the imaging strip is a subset of the imaging array, according to several embodiments. [Figure 6] This is a block diagram of an imaging system with divided data lines according to several embodiments. [Figure 7A] This is a block diagram of an imaging system with selectively joinable partitioned data lines, according to several embodiments. [Figure 7B] This is a block diagram of an imaging system with selectively joinable partitioned data lines, according to several embodiments. [Figure 8A]This is a block diagram of an imaging system with multiple data lines according to several embodiments. [Figure 8B] This is a block diagram of an imaging system with multiple data lines according to several embodiments. [Figure 9A] This is a block diagram of pixels and associated electronics of an imaging system according to several embodiments. [Figure 9B] This is a block diagram of an imaging array and associated electronics of an imaging system according to several embodiments. [Figure 10] This is a timing diagram for the dual sampling operation. [Figure 11A] This is a timing diagram based on several embodiments. [Figure 11B] This is a flowchart illustrating the operation of an imaging system according to several embodiments. [Figure 12A] This is a timing diagram based on several embodiments. [Figure 12B] This is a flowchart illustrating the operation of an imaging system according to several embodiments. [Figure 12C] This is a flowchart illustrating the operation of an imaging system according to several embodiments. [Figure 13A] This is a timing diagram based on several embodiments. [Figure 13B] This is a flowchart illustrating the operation of an imaging system according to several embodiments. [Figure 13C] This is a timing diagram according to several other embodiments. [Figure 13D] This is a timing diagram according to several other embodiments. [Figure 14] This is a flowchart of techniques for operating imaging systems according to several embodiments. [Figure 15] This is a block diagram of a 2D X-ray imaging system according to several embodiments. [Modes for carrying out the invention]

[0004] Some embodiments relate to an imaging system that includes an imaging array and an imaging strip. The system can operate in different modes to acquire two-dimensional (2D) images using the imaging array and panoramic images using the imaging strip.

[0005] An imaging system used in a dental panel can perform a panoramic imaging operation in which the imaging strip is irradiated as the detector rotates around the patient's head. This imaging strip can be integrated as part of a large flat panel detector. The image is generated by quickly scanning the unused rows of the detector, an operation called "scrubbing", and turning on only specific rows of the panel for image readout. There are two problems with this approach. First, the frame rate is limited by the time it takes to scrub the unused pixels. Second, imaging can be limited in the dosing rate in certain applications such as medical imaging, and thus, background electronic noise can have a significant impact on image quality because the available signal is low.

[0006] Traditionally, the array can be approximately 16 x 16 centimeters (cm) in size, with a pixel size of approximately 100 micrometers (μm). The pixel matrix is ​​addressed by a series of gate drivers and read out by a series of orthogonal readout charge amplifiers. A full-size image can be acquired by sequentially turning on each row of the TFT and simultaneously reading out the pixel charge of each data line in the array. In panoramic mode, the row drivers are controlled to rapidly scan the first part of the matrix up to the first row of the imaging strip. The row drivers are controlled to slow down to a normal readout speed between rows of the imaging strip, which can be approximately 60 to 100 rows, and then quickly scan the rest of the gate lines to scrub the rest of the imager. Typically, charge readout is performed by timing the gate-on pulse of each pixel to be complemented by the gate-off pulse of the pixels in the previous row. Other readout methods are possible, but this approach allows for increased gate-on time to reduce delay and provide a relatively flat, dark image. Due to the relatively long length of the data lines, the charge amplifiers are set to high output to minimize noise from the capacitance of the data lines.

[0007] As will be described in more detail below, embodiments include different configurations of imaging arrays and imaging strips. In some embodiments, separate imaging arrays and separate imaging strips can be located in the same housing and share common electronics. In other embodiments, the imaging arrays and imaging strips may be located on the same substrate. In other embodiments, the imaging strips may be a subset of imaging arrays having various configurations of connections within the imaging array.

[0008] Figure 1 is a block diagram of an imaging system including an imaging array and an imaging strip, according to several embodiments. The imaging system 100 includes an imaging array 102 and an imaging strip 104. The imaging array 102 and the imaging strip 104 are housed in the same housing 110.

[0009] The imaging array 102 may be a two-dimensional (2D) array of pixels. For example, the imaging array 102 may include a 1600 × 1600 pixel array. Although an imaging array 102 having an equal number of pixels in rows and columns was used as an example, the number of rows and columns may differ in other embodiments. Although a specific number of pixels was used as an example, the number of pixels may differ in other embodiments. The aspect ratio of pixels with a relatively short dimension to a relatively long dimension is greater than 0.3, 0.5, 0.75, etc., or equal to 1.

[0010] The imaging strip (or linear imaging array or linear array) 104 is an array of pixels having a relatively low aspect ratio and may or may not be a 2D array. For example, the imaging strip 104 may include an array of 1 pixel × 1600 pixels. In other embodiments, the imaging strip 104 may include an array of approximately 80 pixels × 1600 pixels. In other embodiments, the aspect ratio of the relatively short dimension to the relatively long dimension is approximately 0.05, 0.1, or less than 0.3.

[0011] The imaging array 102 and the imaging strip 104 may be based on the same, similar, or different technologies. For example, the imaging array 102 may include an amorphous silicon (a-Si) based array, while the imaging strip may be based on complementary metal oxide semiconductor (CMOS), indium gallium zinc oxide (IGZO), or photon counting technologies such as cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe or CZT), or a selenium photodetector, which have higher costs and / or higher resolution. In some embodiments, one or both of the imaging array 102 and the imaging strip 104 may be based on IGZO.

[0012] In some embodiments, one or both of the imaging array 102 and the imaging strip 104 may be associated with one or more scintillators. The scintillators may include a variety of materials configured to convert X-ray photons into photons detectable by the corresponding imaging array 102 or imaging strip 104. For example, scintillators may include cesium iodide (CsI), cadmium tungstate (CdWO4), polyvinyltoluene (PVT), etc. Other examples of scintillators include gadolinium oxysulfide (Gd2O2S;GOS;Gadox), terbium-doped gadolinium oxysulfide (Gd2O2S:Tb), etc. In some embodiments, one or both of the imaging array 102 and the imaging strip may not include a scintillator but may include a direct conversion material such as CdTe, CdZnTe or CZT, selenium, etc.

[0013] The pixels of the imaging array 102 and the imaging strip 104 may be the same, similar, or different. One or more of the pixel sizes, layouts, spacings, internal components, internal electrical connections, etc., may be the same or different. For example, the imaging array 102 may include 50-micrometer (μm) pixels for better single-shot accuracy, while the imaging strip 104 may include 100-μm pixels for a better signal-to-noise ratio and / or faster speed. In another example, one of the imaging array 102 and the imaging strip 104 may have 1T pixels and the other 4T pixels. While specific examples of differences between pixels have been used as examples, in other embodiments, pixels may have other differences.

[0014] The imaging system 100 includes a readout circuit 106-1 coupled to an imaging array 102. The readout circuit 106-1 may include one or more amplifiers (e.g., charge amplifiers) for the columns of the imaging array 102. In some embodiments, the readout circuit 106-1 may include a charge amplifier for each of the columns of the imaging array 102. As will be described in more detail below, each pixel of a column may be coupled to a data line coupled to the input of one of the charge amplifiers of the readout circuit 106-1.

[0015] The imaging system 100 includes a readout circuit 106-2 coupled to an imaging strip 104. The readout circuit 106-2 may include one or more charge amplifiers for the columns of the imaging strip 104. In some embodiments, the readout circuit 106-2 may include a charge amplifier for each of the columns of the imaging array 102. As will be described in more detail below, each pixel of a column may be coupled to a data line coupled to the input of one of the charge amplifiers of the readout circuit 106-2.

[0016] The readout circuit 106-1 may differ from the readout circuit 106-2. For example, the data lines connecting the pixels of the imaging array 102 to the readout circuit 106-1 may be longer than the data lines connecting the pixels of the imaging strip 104 to the readout circuit 106-2 (for example, due to a larger number of pixel rows). Thus, the readout circuit 106-2 may have a different configuration and, for example, be operated differently due to the lower capacitance of the associated data lines. While the length of the data lines was used as an example of why the readout circuit 106-2 may differ, the readout circuit 106-2 may differ for other reasons.

[0017] The imaging system 100 includes common electronics 108 coupled to a first readout circuit 106-1 and a second readout circuit 106-2. The common electronics 108 is configured to generate image data in response to at least one of the first readout circuit 106-1 and the second readout circuit 106-2. In some operations, the common electronics 108 generates image data based on data from readout circuit 106-1. In other operations, the common electronics 108 is configured to generate image data based on data from readout circuit 106-2. In other operations, the common electronics 108 is configured to generate image data based on data from both readout circuit 106-1 and readout circuit 106-2.

[0018] Common electronics 108 may include various different circuits shared between the imaging array 102 and the imaging strip 104, and read circuits 106-1 and 106-2. For example, common electronics 108 may include a power supply configured to generate power for the imaging array 102 and the imaging strip 104, and read circuits 106-1 and 106-2. Common electronics 108 may include a processor 109 configured to control various operations described herein. Such a processor 109 may include a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit, a microcontroller, a programmable logic circuit, a discrete circuit, or a combination of such devices. The processor 109 may include internal parts, such as registers, cache memory, and processing cores, or external interfaces, such as address and data bus interfaces and interrupt interfaces. Although only one processor 109 is shown for common electronics 108, there may be multiple processors 109. Furthermore, other interface devices such as logic chipsets, hubs, memory controllers, and communication interfaces may be part of the system common electronics 108 that connect the processor 109 to internal and external components, such as the imaging array 102 and imaging strip 104, read circuits 106-1 and 106-2, and the external computer 115.

[0019] An external computer 115 is an example of a device that can be coupled to the imaging system 100 (for example, via a wired, optical, or wireless connection) to receive image data from the common electronics 108. The common electronics 108 can be configured to receive and respond to commands from the external computer 115, exchange data with the external computer 115, and so on. The external computer 115 can take various forms, such as a desktop computer, server, workstation, tablet computer, mobile device, or user interface terminal.

[0020] In some embodiments, the imaging array 102 and the imaging strip 104 are separate. The imaging array 102 and the imaging strip 104 may be arranged on separate substrates, each mounted in the housing 110. The imaging array 102 and the imaging strip 104 may be arranged so that incident radiation enters a common window or opening 112 and can be detected by either the imaging array 102 or the imaging strip 104.

[0021] In some embodiments, the imaging strip 104 may have a configuration that provides lower noise, a higher frame rate, higher resolution, etc., than the imaging array 102. Therefore, the imaging array 102 and the imaging strip 104 can be used for different applications. Since the imaging array 102 and the imaging strip 104 are housed in the same housing 110, a user can use a single imaging system 100 for different applications, or a user can use detectors in a single housing 110 in various imaging systems.

[0022] In some embodiments, the imaging array 102 and the imaging strip 104 do not have to operate simultaneously. As a result, the common electronics 108 may be used exclusively for the operation of one of the imaging array 102 and imaging strip 104 at a time. The operation of the common electronics 108 may differ for each of the imaging array 102 and imaging strip 104. For example, the common electronics 108 may drive the row drivers of the imaging strip 104 at a faster speed than that associated with the imaging array 102.

[0023] Figure 2 is a flowchart of the operation of the imaging system according to several embodiments. Referring to Figures 1 and 2, and using imaging system 100 as an example, in some embodiments, first data is read from the imaging array 102 using readout circuit 106-1 at 200. For example, row drivers associated with the imaging array 102 may be activated sequentially to read data from the imaging array 102 row by row using readout circuit 106-1. Common electronics 108 may be configured to control the row drivers and readout circuit 106-1 to read the desired data.

[0024] In 202, a second data is read from the imaging strip 104 using the readout circuit 106-2. For example, a row driver associated with the imaging strip 104 may be sequentially activated to read data from the imaging strip 104 row by row using the readout circuit 106-2. Common electronics 108 may also be configured to control the row driver and the readout circuit 106-2 to read the desired data.

[0025] In 204 and 206, data from the imaging array 102 and the imaging strip 104 are processed in the common electronics 108, respectively, to generate different sets of image data. The processing in the common electronics 108 in 204 and 206 may be the same, similar, or different. For example, data from the imaging strip 104 may be processed to produce image data that results in reduced noise compared to the processing of data from the imaging array 102. In other examples, data from the imaging array 102 may be used to generate a video stream, and data from the imaging strip 104 may be used to generate a panoramic image. The processing in 204 and 206 may be performed simultaneously, in parallel, sequentially, and so on.

[0026] In Figure 2, a specific sequence of operations has been used as an example, but in some embodiments, the order may be different. For example, 204 may be executed before 202. In another example, 200 and 204 may be executed after 206.

[0027] Figure 3 is a block diagram of an imaging system including a substrate according to several embodiments. The imaging system 300 may be similar to the imaging system 100 in Figure 1 and may include the same or similar components. Some components are omitted for clarity but may be present. As mentioned above, in some embodiments, the imaging array 102 and imaging strip 104 may be formed on separate and different substrates. In some embodiments, the imaging system 300 includes a substrate 114. The substrate 114 may be a single substrate made of glass, plastic or polymer, ceramic, organic or inorganic semiconductor, etc. The imaging array 102 and imaging strip 104 may be formed in or on the substrate 114. For example, the imaging array 102 and imaging strip 104 may be separate integrated circuit dies mounted on the substrate 114. In other embodiments, the imaging array 102 and imaging strip 104 may be formed on different parts of the same integrated circuit die, such as different parts of a semiconductor substrate.

[0028] In some embodiments, even if the imaging array 102 and the imaging strip 104 are directly adjacent to each other on the same semiconductor substrate, the imaging array 102 and the imaging strip 104 may still be separate electronic devices. That is, the imaging array 102 and the imaging strip 104 may not have electrical connections to each other except for parasitic connections via the substrate and / or connections via readout circuits 106-1 and 106-2 and common electronics 108.

[0029] In some embodiments, the read circuits 106-1 and 106-2 may be formed on a substrate different from the substrate 114. However, in other embodiments, one or both of the read circuits 106-1 and 106-2 may be formed on the substrate 114.

[0030] Figure 4 is a block diagram of an imaging system with separate row drivers according to several embodiments. The imaging system 400 may be similar to the imaging systems 100 and 300 described above. However, the imaging array 102 is coupled to row driver 416b, and the imaging strip 104 is coupled to row driver 416a. In some embodiments, row drivers 416a and 416b are separate circuits, but in other embodiments, row drivers 416a and 416b are part of the same integrated circuit as the corresponding imaging strip 104 or imaging array 102 or both. The row drivers 416a and 416b may be coupled to and controlled by common electronics 108.

[0031] Row driver 416a is configured to be activated sequentially to read the imaging strip 104 row by row. Row driver 416b is configured to be activated sequentially to read the imaging array 102 row by row. Common electronics 108 may be configured to change signals, timings, etc., when controlling row driver 416a compared to when controlling row driver 416b.

[0032] Figure 5 is a block diagram of an imaging system in which the imaging strip is a subset of the imaging array, according to several embodiments. The imaging system 500 may be similar to the imaging systems 100, 300, and 400 described above. However, the imaging strip 104 is a subset of the imaging array 102. In some embodiments, the imaging strip 104 may be located at the end of the imaging array 102. For example, the imaging array 102 may have a size of 1600 pixels × 1600 pixels. The imaging strip may include the top 80 rows of pixels of the array, which has a size of 1600 pixels × 80 pixels. Although a specific size for the imaging strip 104 is used as an example, the size may vary while maintaining the aspect ratio described above.

[0033] In some embodiments, the imaging array 102 may be coupled to a row driver 516. The row driver 516 coupled to the imaging strip 104 portion of the imaging array 102 can be shared. When generating an image using the imaging strip 104, the associated row selection line 516a can be used. When generating an image using the imaging array 102, both row selection lines 516a and 516b can be used.

[0034] In some embodiments, the pixels of the imaging strip 104 may be identical to and formed in the same way as the remaining pixels of the imaging array 102. For example, the pixels of the imaging strip 104 may have the same size, shape, pitch, etc. Conventionally, pitch refers to the length or width of a pixel, along with the spacing between pixels. As a result, when an image is generated using the imaging array 102, artifacts may not appear due to discontinuities between the imaging strip 104 and the rest of the imaging array 102.

[0035] In some embodiments, when reading the image array 102, the row driver 516 is configured to progressively activate row selection lines 516a and 516b across the image array 102.

[0036] Figure 6 is a block diagram of an imaging system with divided data lines according to several embodiments. The imaging system 600 can be similar to the imaging system 500 described above. The imaging system 600 includes divided data lines 618. The data lines 618 are divided into two groups: data lines 618a and data lines 618b. Data lines 618a are coupled to the imaging strip 104 portion of the imaging array 102 and are coupled to the readout circuit 106-2. Data lines 618b are coupled to the remaining portion of the imaging array 102 and are coupled to the readout circuit 106-1.

[0037] The position of the split between data lines 618a and 618b may vary. In some embodiments, the split is approximately 30% of the column length, with data line 618a joined to 30% of the column's pixels and data line 618b joined to 70% of the column's pixels. While 30% is used as an example, in other embodiments, the position may differ, such as splitting at 1%, 5%, 10%, 20%, etc. In other embodiments, the split is a certain number of pixels from the edge, e.g., approximately 80 pixels or less, but still less than 30% of the number of pixels in the column of the imaging array 102. In some embodiments, the split may be arranged so that only pixels in the imaging strip 104 are joined to data line 618a, and pixels outside the imaging strip 104 are joined to data line 618b. In other embodiments, some pixels outside the imaging strip 104 are joined to data line 618a, but the total number of pixels in the column joined to data line 618a may be less than approximately 30%.

[0038] Reducing the splitting to less than approximately 30% benefits the imaging strip 104. In some embodiments, since data line 618a is shorter than data line 618b, noise may be reduced. In some embodiments, this lower noise may result in artifacts appearing in the image generated using the imaging array 102. However, as will be discussed in more detail below, generating an image using the entire imaging array 102 may add additional noise or equivalent to the data generated by the imaging strip 104. In some embodiments, downstream processing may differ. For example, matching operations with different levels of darkness may be performed compared to the rest of the imaging array 102.

[0039] In some embodiments, the amount of noise reduction and / or increase in the signal-to-noise ratio may be about 10%, 20%, 40%, 50%, or more. For example, shorter data lines 618a result in lower data line capacitance and resistance, which can reduce electronic readout noise. In certain examples, the minimum noise of the charge amplifier is about 200 electrons (e - ) is proportional to the increase in data line capacitance. The noise slope is controlled by the power applied to the charge amplifier and the bandwidth setting of the associated sample-and-hold circuit. In addition, thermal noise, or Johnson noise, is generated by the resistance of the data line, which is multiplied by the capacitance of the data line. This Johnson noise increases with length but may be negligible for shorter data lines, such as data line 618a coupled to imaging strip 104. The resulting noise can be close to the minimum noise of the charge amplifier combined with the pixel's kTC noise. This noise (estimated 400 e) - ) is noise from an array of the same size where the data lines are not separated (approximately 700e - It may be about 40% less than ). The term kTC noise refers to noise generated by multiplying temperature (T) and capacitance (C) by the Boltzmann constant (k), for example, thermal noise multiplied by the capacitance of the data line and the Boltzmann constant. The Boltzmann constant (k) is a proportionality constant that relates the mean relative kinetic energy of a particle to the thermodynamic temperature of the particle.

[0040] Furthermore, shorter lengths can potentially improve read speed. For example, fewer rows can be read during the read operation of pixels on the imaging strip 104. It is not necessary to scrub the rest of the imaging array 102 in order to read pixels on the imaging strip 104. For example, if 80 rows of pixels are used for the imaging strip 104, the control logic 103 will continuously pass tokens (i.e., signals that propagate along the row driver 616 to activate rows) to the row driver 616 every 80 gate clocks, activating the row selection signal 616a. These tokens can then pass through the rest of the row driver 616 and scrub the rest of the imaging array 102 using the row selection signal 616b without interfering with the read operation of the imaging strip 104. This can increase the read speed of the imaging strip 104. For example, assuming a pixel scrubbing speed of approximately 1 microsecond (μs) per row, the time it takes to scrub a 1600-row imaging array 102 outside of an 80-row imaging strip 104 (approximately 1520 rows) is approximately 1.52 milliseconds (ms). Assuming that reading each row of imaging strip 104 takes approximately 16 μs, the 80-row imaging strip 104 takes 1.28 ms to read. The total time is approximately 2.8 ms, resulting in a maximum frame rate of 357 fps. For a dedicated imaging strip 104, the read time is exactly 1.28 ms, and the frame rate is approximately 780 fps. The remaining pixels of the array can be scrubbed with a predetermined number of reads, such as 19 frames (24 ms).

[0041] In some embodiments, read circuits 106-1 and 106-2 are the same and / or may operate in the same way, while in other embodiments, read circuits 106-1 and 106-2 may be different and / or may operate differently. For example, read circuits 106-1 and 106-2 may be identical. In other embodiments, read circuits 106-1 and 106-2 may be identical but operate in different ways, such as having different gains, currents, capacitances, etc. In other embodiments, read circuits 106-1 and 106-2 may be different if read circuit 106-2 is optimized for shorter data lines 618a.

[0042] Referring to Figures 2 and 6, in some embodiments, in 200, reading first data from imaging array 102 includes reading first data from imaging array 102 via data line 618b. In 202, reading second data from imaging strip 104 includes reading second data from imaging strip 104 using data line 618a, which is different from data line 618b.

[0043] Figures 7A and 7B are block diagrams of imaging systems with selectively connectable split data lines according to several embodiments. Referring to Figure 7A, imaging system 700a may be similar to imaging system 600 described above. However, system 700a includes data line 718a connected to imaging strip 104 and data line 718b connected to the rest of imaging array 102. Data lines 718a and 718b are separate but selectively connectable by switch 722. Each of switch 722 can selectively connect one of the data lines 718a to the corresponding data line 718b.

[0044] In some embodiments, switch 722 may include one or more transistors that couple data lines 718a and 718b. Switch 722 may be controlled by control logic 103 so that switch 722 opens when the imaging strip 104 is read. As a result, a lower capacitance from data line 718a only is presented to the readout circuit 106-2. However, when the imaging array 102 is read, data lines 718a and 718b may be coupled together to function as a single data line. Data from the imaging array 102 may be read via the coupled data line 718a and 718b through the readout circuit 106-1.

[0045] Referring to Figure 7B, the imaging system 700b may be similar to the imaging system 700a. However, the data lines associated with the imaging array 102 may include data lines 718a, 718c, and 718d. In some embodiments, the division between data lines 718c and 718d may be 50% of the distance along the imaging array 102. For example, 50% of the pixel rows may be on one side of the division between data lines 718c and 718d, and 50% of the pixel rows may be on the opposite side of the division.

[0046] Data lines 718a and 718c may be selectively coupled by switch 722 in response to control logic 103. In some embodiments, the imaging strip 104 can be read by using switch 722 to decouple data lines 718a and 718c and reading through data line 718a using readout circuit 106-2. When reading the imaging array 102, data lines 718a and 718c are coupled by switch 722 and can be read using readout circuit 106-2 through the combination of data lines 718a and 718c. The remainder of the imaging array 102 can be read through data line 718d using readout circuit 106-1. The coupling of data lines 718a and 718c may occur in less than 50% of the pixel rows, or data line 718a may cover less than 30% of the entire imaging array 102.

[0047] Therefore, in various embodiments, a portion of the data lines of the entire imaging array 102 may be detached from the data lines 718a associated with the imaging strip 104. This portion may be the remaining subset outside the imaging strip 104, or it may be the entire remainder, as in imaging systems 700a and 700b.

[0048] Referring to Figures 2, 7A, and 7B, in some embodiments, in 200, reading first data from the imaging array 102 includes electrically coupling the first data line 718a or 718c to the second data line 718b when reading first data from the imaging array 102. In 202, reading second data from the imaging strip 104 includes electrically isolating the first data line 718a or 718c from the second data line 718b when reading second data from the imaging strip 104.

[0049] Figures 8A and 8B are block diagrams of imaging systems with multiple data lines according to several embodiments. Imaging system 800a may be similar to imaging systems 500 and 600 described above. However, imaging system 800a includes data lines 818a and 818e. Data line 818a is coupled to pixels on imaging strip 104. Data line 818e is coupled to pixels throughout imaging array 102, including pixels on imaging strip 104. Thus, at least two data lines 818a and 818e are coupled to each pixel on imaging strip 104. Therefore, when imaging strip 104 is read, data line 818a is used, and when imaging array 102 is read, data line 818e is used.

[0050] Referring to Figure 8B, in some embodiments, the imaging system 800b may be similar to the imaging system 800a. In some embodiments, the data lines of the imaging array 102 may include divided data lines 818d and 818f that are split along the imaging array 102. The readout circuit 106-2 may include separate inputs for data lines 818a and 818f. The readout circuit 106-1 may be coupled to data line 818d. Thus, when the imaging strip 104 is read, data line 818a is used, and when the imaging array 102 is read, data lines 818d and 818f are used.

[0051] As described above, in various embodiments, the amount of noise present in the data read from the imaging strip 104 may be less than the amount of noise present in the data read from the rest of the imaging array 102. For example, the data lines used to read data from the imaging strip 104 may be shorter than the data lines used to read data from the imaging array 102. These data lines may have lower capacitance and contribute to lower noise. In some applications, noise reduction may be desirable. For example, the reduced noise present when reading from the imaging strip 104 may allow for the use of lower doses for the same signal-to-noise ratio in the resulting image, or higher signals for the same dose, enabling different trade-offs between the two various factors.

[0052] When data from the imaging strip 104 is combined with data from the imaging array 102, artifacts may appear due to differing noise levels, even if each pixel has the same characteristics. To compensate for this, the readout circuit 106-2 may be operated to increase the amount of noise read from the imaging strip 104. For example, an embedded test capacitor, an external capacitor, or other capacitor can be selectively coupled to the input of the readout circuit 106-2 to reduce the power of one or more amplifiers and / or increase the bandwidth of components of the readout circuit 106-2, such as amplifiers and / or sample-and-hold circuits. These operations may add electronic noise and can be adjusted to match the overall noise between the imaging strip 104 and the rest of the imaging array 102. For example, with a typical line time of 20 μs, a 40 kHz low-pass filter may be used to reduce noise. For most image readouts with data lines having capacitances of several tens of picofarads (pF), the readout circuit 106-1 is set to high-power, low-noise conditions, with electronic noise of approximately 600 to 800 e -This means that, in order for the imaging strip 104 to achieve this level of noise, a low-power normal noise operating mode can be used, and a test capacitor having a capacitance similar to that of the data line incorporated into the readout circuit 106-2 is coupled to the data line, and / or the bandwidth is increased to 105 kHz. This operation is approximately 600 to 800 e- The imaging strip 104 is given similar overall noise. Specific examples of techniques such as adding noise, simulating noise, and equalizing noise have been described above, but in other embodiments, because the noise of imaging strip 104 is low, other actions can be performed to reduce or eliminate image artifacts.

[0053] In some embodiments, the imaging systems 400, 600, 700a, 700b, 800a, 800b, etc., described above may operate in a mode in which power can be dynamically managed. For example, during operation, the control logic 103 may be configured to control the amplifiers of the readout circuits 106-1 or 106-2 to operate in a higher power mode to reduce noise when reading the entire imaging array 102. However, when reading the imaging strip 104, the amplifier of the readout circuit 106-2 can operate in a low power mode. In low power mode operation, the relative amount of noise may increase and / or the signal-to-noise ratio (SNR) may decrease, but power consumption is lower. Furthermore, the amplifier of the readout circuit 106-1 may be turned off, or put into a sleep mode with significantly lower power consumption. When the entire imaging array 102 can be read, the readout circuits 106-1 and 106-2 can be put into a higher power mode to reduce the impact of noise. By dynamically switching between these operating modes, power consumption, temperature reduction, and / or reliability improvements can be achieved for imaging systems such as the 500, 600, 700a, 700b, 800a, and 800b.

[0054] In some embodiments, the impact of pixel kTC noise in the image can be reduced. As a result, it becomes possible to achieve the desired resolution using lower doses, increase the frame rate, and so on.

[0055] Figure 9A is a block diagram of pixels and associated electronics of an imaging system according to several embodiments. Figure 9B is a block diagram of an imaging array and associated electronics of an imaging system according to several embodiments. Referring to Figures 9A and 9B, the imaging system 900 includes pixels 902 arranged in rows and columns.

[0056] Pixel 902 includes a photodetector 904 (e.g., a photodiode) and a transistor 906 (i.e., a switch). Transistor 906 is configured to selectively couple the photodetector 904 to a data line 908 in response to a row selection signal (RSS). Multiple pixels 902 may be coupled to a single data line 908 in a column.

[0057] Data line 908 is coupled to amplifier 910. In some embodiments, amplifier 910 is an integrating amplifier including a reset transistor (or reset switch) 910a and a charge storage device 910b such as a capacitor. The reset transistor 910a is configured to reset amplifier 910 in response to a reset signal Reset. The output of amplifier 910 may be selectively coupled to analog-to-digital converter (ADC) 912 via a selection transistor 911 in response to a sample signal Sample. The digitized signal may be processed by a field-programmable gate array (FPGA) 914, stored in memory 916, and / or further processed by a processor 918 or other downstream system.

[0058] The control logic 903 can be coupled to various components as described above. For example, the control logic 903 can be coupled to the row driver 901. The control logic may be configured to control the row driver 901 to generate a row selection signal RSS for rows of pixels 902. The control logic 903 may be configured to configure and control the operation of ADC 912, FPGA 914, processor 918, etc. The control logic 903 may include a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit, microcontroller, programmable logic circuit, discrete circuit, or a combination of such devices. The control logic 903 may include internal parts such as registers, cache memory, and processing cores, and external interfaces such as address and data bus interfaces and interrupt interfaces. Furthermore, other interface devices such as logic chipsets, hubs, memory controllers, and communication interfaces may be part of the imaging system 900 to connect the control logic 903 to internal and external components.

[0059] Although the control logic 903 is shown separately from the FPGA 914, processor 918, etc., the control logic 903 may be integrated with such components. For example, the control and / or execution of the operations described herein may be distributed across the FPGA 914, processor 918, or a combination of such components.

[0060] Figure 10 is a timing diagram of the dual sampling operation. Referring to FIGS. 9A, 9B, and 10, the system 900 can operate according to the timing diagram of FIG. 10. For example, the transistor 910a can be enabled to reset the amplifier 910 in response to a pulse on the reset signal Reset. During this operation, the transistor (or switch) 906 is disabled when the row selection signal RSS becomes inactive. While the row selection signal RSS is deactivated, the sample signal Sample is activated, and the reset value is sampled as R1 at the output of the amplifier 910. After obtaining the value R1, the sample signal Sample is deactivated. After deactivating the sample signal Sample, the row selection signal RSS is activated, and the transistor 906 is activated. As a result, the charge from the photodetector 904 is accumulated in the amplifier 910. The sample signal Sample is enabled to sample the value S1 at the output of the amplifier 910.

[0061] (Equation 1) and (Equation 2) show the components of the sampled values R1 and S1. V reset is the sampled reset voltage including the noise contributed by the amplifier 910. V signal,pixel is the target signal from the pixel 902. V kTC (N - 1) is the pixel kTC noise remaining from the previous readout of the pixel 902. V dataline The noise is the noise due to the data line 908.

[0062] [Number] (1)

[0063] [Number] (2)

[0064] (Equation 3) is the difference between R1 and S1, V p1 (N). The result includes the target signal V signal,pixel and the pixel kTC noise V kTC(N-1) and data line noise V data line It includes.

[0065]

number

[0066] The calculation in equation (3) can be performed in various ways, such as analog correlated double sampling (ACDS), digital correlated double sampling (DCDS), or other processes that subtract signals R1 and S1.

[0067] Fixed pattern noise sources can arise from variations between pixels or between amplifiers. Fixed pattern noise may not change from frame to frame. However, pixel kTC noise is generated by resistance within the pixel semiconductor switch and accumulates in the capacitance of the photodetector 904. Pixel kTC noise may differ from frame to frame. Fixed pattern noise can be reduced through manufacturing control. Pixel kTC noise can be reduced by reducing the capacitance of the photodetector 904 by reducing its size. However, reducing the size of the photodetector 904 may decrease other factors such as sensitivity and efficiency.

[0068] The result of equation (3) still includes pixel kTC noise. Pixel kTC noise can be reduced by modifying the pixel design, such as by adding additional transistors. However, in pixels formed using some semiconductor technologies, such as amorphous silicon (a-Si), the size of the transistors can be very large. For example, a single transistor may occupy a significant proportion of a pixel of a given pixel size. Adding more transistors would drastically reduce the pixel area available to the photodetector 904, thus decreasing the efficiency of system 900.

[0069] As will be described in more detail below, the system 900 can operate in different ways to reduce pixel kTC noise. In some embodiments, a measurement may be performed in which pixel kTC noise is acquired and can be used to reduce or eliminate pixel kTC noise from a signal measurement. Although the pixel kTC noise changes from frame to frame, the pixel kTC noise is applied from amplifier 910 to the input of amplifier 910 (and then output) after a signal sample is acquired and transistor 906 is disabled by disabling the row selection signal RSS. At this point in the operation, a sample can be acquired to capture the kTC noise. This sample is saved and then used in the next frame to reduce or eliminate pixel kTC noise from the signal from pixel 902.

[0070] Next, the measured values ​​can be used to remove or reduce the pixel kTC noise in the final value. Thus, the measured values ​​from the previous frame can be used to reduce or cancel the pixel kTC noise in the current frame. The embodiments described herein may be applicable to systems using an a-Si process or other processes where the transistor size may be relatively large compared to the pixel size, but in other embodiments, the system may be formed using other processes such as a complementary metal-oxide-semiconductor (CMOS) process.

[0071] Figure 11A is a timing diagram according to several embodiments. Figure 11B is a flowchart of the operation of the imaging system according to several embodiments. Referring to Figures 9A, 9B, 11A, and 11B, at 1100, a first value of pixel 902 coupled to data line 908 is acquired via the switch using a readout circuit while the switch is in the off state. Here, transistor 906 is an example of a switch, and the readout circuit includes amplifier 910 and at least some downstream components. This first value, sample R / S, is acquired in the (N-1)th frame while transistor 906 is disabled. Subsequent processing may occur before subsequent operations are performed for frame N.

[0072] In 1102, the readout circuit is reset. In this example, the amplifier 910 is reset. However, in other embodiments, additional components may be reset. Resetting the amplifier 910 may include discharging the charge storage device 910b by activating a reset signal Reset.

[0073] In 1104, after resetting the readout circuit, the second value of pixel 902 is obtained. In this example, the value R1 is obtained after resetting amplifier 910.

[0074] At 1106, the switch is turned on. Here, the row selection signal RSS becomes active, and transistor 906 turns on. As a result, the charge from pixel 902 can be transferred to amplifier 910.

[0075] In 1108, the third value of pixel 902 is obtained after the switch is turned on. In this example, the value S1 is obtained after transistor 906 is turned on.

[0076] In 1110, the first, second, and third values ​​are combined to form the combined value of pixel 902. In this example, the three values ​​R1, S1, and R / S are combined to form the combined value of pixel 920. As will be explained in more detail below, the three values ​​R1, S1, and R / S can be combined in various ways to reduce or eliminate pixel kTC noise. The various values ​​that are combined together may include other values ​​depending on the specific combination technique used to combine the first, second, and third values ​​together to reduce or eliminate kTC noise.

[0077] In some embodiments, 1101 stores a stored value based on a first value. For example, a value based on the value R / S may be stored in FPGA 914, memory 916, processor 920, or another downstream system. The stored value is based on a value from the previous frame N-1. The stored value may be combined with values ​​R1 and S1 from the current frame N. Thus, the combination in 1110 may include the combination of the first value by the stored value based on the first value. In some embodiments, an R / S value or derived value corresponding to the entire frame may be stored for each of the pixels 902. The frame-wide values ​​of R1 and S1 can be combined with the stored R / S value, whether separately or in combination.

[0078] The operations described herein involve acquiring additional samples during the readout process. This additional sampling takes extra time, thus increasing the readout time. However, noise may be reduced, potentially increasing the signal-to-noise ratio and enabling lower doses, among other things. Therefore, in some embodiments, the increased readout time may be traded for noise reduction, lower doses, and so on.

[0079] In some embodiments, the benefits of noise reduction are greater the smaller the capacitance of the data line 908. When values ​​are combined, the noise from the capacitance of the data line 908 increases by the square root of 2. In some embodiments, binning can be implemented during signal capture from pixels 902. For example, in 2x2 binning mode, four pixels 902 are combined to operate as a single pixel. For a single pixel 902 readout, the noise of the data line 908 may be twice as high, and the pixel kTC noise would otherwise be four times higher. However, the pixel kTC noise can be reduced or eliminated. Therefore, the operations described herein can have a greater impact when binning is performed.

[0080] Figure 12A is a timing diagram according to several embodiments. Figure 12B is a flowchart of the operation of the imaging system according to several embodiments. Referring to Figures 9A, 9B, 12A, and 12B, the operation may be similar to that of Figures 11A and 11B, and includes operations 1100, 1101 (optionally), 1102, 1104, 1106, and 1108, as described above with respect to Figure 11B. At 1200, the readout circuit is reset before acquiring the first value of pixel 902. For example, amplifier 910 may be reset by a pulse on the reset signal Reset. This operation may be the same as or similar to the reset performed later at 1102.

[0081] In 1202, the fourth value of pixel 902 is obtained while the switch is in the ON state. For example, after amplifier 910 is reset, the value R2 is obtained while switch 906 is in the ON state.

[0082] The operation continues as in Figure 11B, where R3 is the value R / S. In 1204, the values ​​S1, R1, R2, and R3 are combined together to generate the combined value for pixel 902. Equations (4) through (6) are the same as equations (1) through (3) above, using the sampled values ​​R1, S1, and V p1This shows the component of (N). reset1は This is the reset voltage sampled after the amplifier 910 has been reset.

[0083]

number

[0084]

number

[0085]

number

[0086] Equation (7) is the sampled value R2. The value R2 is sampled after amplifier 910 is reset and while switch 906 is in the ON state. Equation (8) is the value sampled at R3. The value R3 is sampled after switch 906 transitions to the OFF state. Equation (9) is the difference between R2 and R3. Equation (10) is V pixel (N) and V p1 (N) and V p2 This is the sum of (N-1). Different data line noise V dataline noise 1 and V dataline noise Although 2 has been added, the resulting combination is effectively the square root of twice the typical data line noise level.

[0087]

number

[0088]

number

[0089]

number

[0090]

number

[0091] The values ​​R2 and R3 sampled in the previous frame N-1 have pixel kTC noise from the frame before that. To explain the values ​​of R2 and R3 from the previous frame N-1, we describe the operation in frame N. Amplifier 910 is reset, and a sample is created after the reset. This generates the value R1. Pixel 902 is turned on by turning on switch 906, creating another sample on the signal and generating the value S1. The two samples R1 and S1 are then subtracted as done before.

[0092] After the signal sampling to generate value S1 has been performed, transistor 906 remains closed and in the ON state. Amplifier 910 is reset by a pulse on the reset signal Reset, and a sample of value R2 is acquired. This sample contains the reset value of amplifier 910. When switch 906 is opened in response to the deactivation of the row selection signal RSS, pixel kTC noise is transmitted and integrated by amplifier 910. In particular, when transistor 906 is turned off, some charge remains in pixel 902, and an equal opposite amount is integrated by amplifier 910. This integrated amount is the opposite of the pixel kTC noise present when pixel 902 is next read.

[0093] The output of amplifier 910 is sampled again to obtain a value R3 containing the reset value, pixel kTC noise, and data line 908 noise. The pixel kTC noise is the pixel kTC noise that appears when pixel 902 is read out next in the next frame. Therefore, if this operation is performed in frame N-1, the values ​​R2 and R3, or a combination of those values, can be used for the next frame N.

[0094] In some embodiments, the calculations in equations (6) and (9) can be performed by using correlated double sampling techniques. For example, regardless of whether it is analog or digital, the difference between R2 and R3 can be generated using correlated double sampling techniques, as shown in equation (9). Similarly, at different times, the difference between R1 and S1 can be generated using correlated double sampling techniques, as shown in equation (6). Thus, different values ​​can be combined into two different correlated values. These correlated values ​​can be combined as in equation (10). Therefore, in some embodiments, the value V can be generated by controlling various signals such as the reset signal and the row selection signal RSS using existing hardware. p1 (N) and V p2 (N-1) can be generated. Instead of performing two correlated double sampling operations to ultimately generate two frames of image data, two correlated double sampling operations can be performed to ultimately generate one frame of image data.

[0095] Referring to Figures 9A, 9B, and 12A through 12C, step 1204 in Figure 12B can be replaced by the process from 1208 onwards. After operations 1200 through 1108, at 1208, the first and fourth values ​​can be combined to form the first correlated value. As described above, values ​​R2 and R3 can be combined using the correlated double sampling technique. At 1210, the second and third values ​​can be combined to form the second correlated value. As described above, R1 and S1 can be combined using the correlated double sampling technique. At 1212, the first and second correlated values ​​are combined into the combined value of pixel 902. The combination can be performed by various devices such as FPGA 914, processor 918, control logic 903, and external computer 913.

[0096] Figure 13A is a timing diagram according to several embodiments. Figure 13B is a flowchart of the operation of the imaging system according to several embodiments. Referring to Figures 9A, 9B, 13A, and 13B, in some embodiments the signals that generate the values ​​R1 and S1 may be similar to those described above. However, a third value S2 based on the previous frame is combined with these values.

[0097] The operations from 1302 to 1308 are the same as or similar to those from 1102 to 1108 in Figure 11B, which generate the values ​​R1 and S1. These operations are for the previous frame N-1. At 1300, as with 1100, the first value of pixel 902 for use in the subsequent frame is acquired without resetting the corresponding readout circuit. For example, when acquiring the first value, the switch is in the off state. Thus, after 1306, the row selection signal RSS is disabled, turning off transistor 906. Subsequently, the value S2 is acquired as the first value for use in the subsequent frame N. Later, for frame N, operations 1302 to 1308 are repeated to generate the values ​​R1 and S1 for frame N. Operation 1310 is performed similarly to operation 1110, combining the first, second, and third values. Operation 1300 can be performed to generate the value S2 for frame N for use in frame N+1.

[0098] In a specific example, for the previous frame N-1, equations (Equation 11) and (Equation 12) give the components of R1(N-1) and S1(N-1).

[0099]

number

[0100]

number

[0101] However, after obtaining the value S1 in the previous frame N-1, the value S2 is obtained. This value S2 is obtained after transistor 906 is turned off, without resetting amplifier 910. Therefore, the resulting value S2 includes both the previously integrated value S1 and the pixel kTC noise, which is expressed by equation (Equation 13) and simplified by equation (Equation 14).

[0102]

number

[0103]

number

[0104] As shown in equation (15), subtracting S1 from S2 yields the pixel kTC noise of the previous frame N-1.

[0105]

number

[0106] For the current frame N, the values ​​R1 and S1 are obtained and combined as shown in equations (16) through (18). The pixel kTC noise in equation (15) is previously generated. To remove the pixel kTC noise from the previous frame N-1, V p1 (N) can be added.

[0107]

number

[0108]

number

[0109]

number

[0110]

number

[0111] Since only three values ​​are acquired, the processing speed of the data frame can increase beyond the speed described above for acquiring four values. As a result, the frame rate may improve. However, it is also possible to use hardware different from existing correlated double sampling hardware. That is, S1 and R1 can be combined using correlated double sampling technique to produce a single value representing the difference, while the value S2 can be generated using different electronics. Furthermore, the sampling circuit may be configured to sample the values ​​R1, S1, and S2 separately and combine them in an FPGA 914, processor 918, external computer 913, or other downstream system.

[0112] Figure 13C is a timing diagram according to several embodiments. Referring to Figures 9A, 9B, 13B, and 13C, in some embodiments, a digital correlated double sampling technique may be used. In response to an ASIC shift (ASIN) of a signal, the signal to be sampled may be shifted to a sampling capacitor or other sample storage device. The operation may be similar to the operation in Figure 13A. In some embodiments, the sampling capacitor may be a bank of sampling capacitors in which the use of the capacitors rotates between sampling operations. The sample signal Sample may be activated as described above to sample the values ​​R1, S1, and S2. However, the bank of sampling capacitors may contain an even number of sampling capacitors. A fourth sample signal 1350 or additional sample signals may be activated to ensure that the associated pixel 902 sees the same sampling capacitor. One sample signal 1350 is used as an example, but more sample signals may be present as needed. The sampled values ​​may be irrelevant; therefore, the ASIN may not be activated. Therefore, in some embodiments, the number of times the signal is shifted in for sampling may be less than the number of times the sampled signal Sample is activated.

[0113] Figure 13D is a timing diagram according to several embodiments. Referring to Figures 9A, 9B, 13B, and 13D, in some embodiments, operation can be performed using analog correlated double sampling. In response to a clamp signal Clamp, a reset value R1 can be stored in a sampling capacitor. This sampling capacitor can be coupled to an analog subtraction device, such as a differential amplifier, which performs the analog subtraction associated with analog correlated double sampling.

[0114] In some embodiments, two measurements are digitized as an intermediate value. As previously mentioned, in equations (Equation 12) and (Equation 13), both S1 and S2 include a reset value R1. Rather than directly subtracting S1 and S2, R1 is subtracted from both S1 and S2 by analog correlated double sampling before the samples are digitized. Thus, the subsequent operations that can be performed digitally can be expressed by equations (Equation 20) to (Equation 22), where S' 1は S' is the digitized value obtained by subtracting R1 from S1 in a differential amplifier, and S'2 is similarly the digitized value obtained by subtracting R1 from S2. (Equation 22) p,kTC It can be used as explained above.

[0115]

number

[0116]

number

[0117]

number

[0118] Therefore, in various embodiments, the acquisition operations of 1300, 1304, and 1308, and the combined operation of 1310, can be performed in various combinations of hardware and digital signal processing.

[0119] Figure 14 is a flowchart of techniques for operating imaging systems according to several embodiments. At 1400, the operating mode is selected. In the first operating mode, the same operation as described in Figures 11B, 12B, 12C, and 13B above is performed. As a result, low-noise data can be acquired. However, depending on the application, a higher frame rate may be required. Therefore, the additional delay due to additional samples in low-noise operation may be undesirable. Thus, a second operating mode may be selected, and at 1402, correlated double sampling operation is performed. In this mode, no first value is acquired. Therefore, the system operation can be switched from low-noise mode to high-frame-rate mode.

[0120] In certain cases, the second mode may be selected when the imaging system is used for fluoroscopy or other applications where a higher frame rate may be desirable. Once the region of interest is identified, the first mode is selected to produce images with low noise, low dose, etc. In another example where binning is performed, such as 2x2, 3x3, 4x4, or more, pixel kTC noise may dominate data line-related noise. The imaging system can operate in the first mode to reduce pixel kTC noise.

[0121] In some embodiments, data frames may be unavailable and / or discarded. For example, the first frame of data from frame N-1 can be used to generate the first and other values. That frame of data cannot be used to generate an image or frame of a video signal. Instead, that data can be used to initialize the above processing so that each subsequent frame uses the values ​​from the previous frame to perform the low-noise processing described above.

[0122] In some embodiments, the above operations for reducing or eliminating pixel kTC noise can be applied to the imaging strip 104. In particular, the imaging strip 104 may have relatively short data lines that couple the imaging strip 104 to the readout circuit 106-2. The common electronics 108 and the readout circuit 106-2 may be configured as described above to reduce kTC noise.

[0123] In some embodiments, the operating modes described with respect to Figure 14 can be switched depending on whether or not the imaging strip 104 is read. For example, if the imaging strip 104 is part of the imaging array 102 and the entire imaging array 102 is read, the above operations for reducing pixel kTC noise may not be performed. Since there are two measurements per data line, background noise from the data line is also measured twice. For imaging arrays 102 with longer data lines, this data line noise may dominate the pixel kTC noise.

[0124] Figure 15 is a block diagram of a 2D X-ray imaging system according to some embodiments. The 2D X-ray imaging system 1500 includes an X-ray source 1502 and a detector 1510. The detector 1510 may include the imaging systems 100, 200, 400, 500, 600, 700a, 700b, 800a, 800b, 900, etc. The X-ray source 1502 is positioned relative to the detector 1510 so that X-rays 1520 are generated so that they pass through a specimen 1522 and can be detected by the detector 1510. In some embodiments, the detector 1510 is part of a medical imaging system. In other embodiments, the 2D X-ray imaging system 1500 may include a portable vehicle scanning system as part of a cargo scanning system.

[0125] Some embodiments include a system comprising a housing 110, an imaging array 102 located inside the housing 110, an imaging strip 104 located inside the housing 110, a first readout circuit 106-1 coupled to the imaging array 102, a second readout circuit 106-2 coupled to the imaging strip 104, and common electronics 108 coupled to the first readout circuit 106-1 and the second readout circuit 106-2 and configured to generate image data in response to at least one of the first readout circuit 106-1 and the second readout circuit 106-2.

[0126] In some embodiments, the imaging array 102 and the imaging strip 104 are separate.

[0127] In some embodiments, the imaging array 102 and the imaging strip 104 are separate and formed on the same substrate 114.

[0128] In some embodiments, at least one of the pixel size, layout, resolution, and internal components of the imaging array 102 differs from the corresponding at least one of the pixel size, layout, resolution, and internal components of the imaging strip 104.

[0129] In some embodiments, the imaging strip 104 is a subset of the imaging array 102.

[0130] In some embodiments, the imaging strip 104 is less than 30% of the imaging array 102.

[0131] In some embodiments, the system further comprises data lines 618, 718, and 818 coupled to the imaging array 102 and the imaging strip 104.

[0132] In some embodiments, the system further comprises a plurality of switches 722 that divide the data line 718 into a plurality of first data lines 718b coupled to the imaging strip 104 and a plurality of second data lines 718b coupled to the rest of the imaging array 102 outside the imaging strip 104.

[0133] In some embodiments, the system further comprises a plurality of first data lines 618a coupled to a subset of the imaging array 102 including an imaging strip 104, and a plurality of second data lines 618b separated from the first data lines 618a and coupled to the imaging array 102 outside the imaging strip 104.

[0134] In some embodiments, the system further comprises an X-ray source configured to generate an X-ray beam, a detector positioned to receive the X-ray beam and including a housing 110, an imaging array 102, an imaging strip 104, a first readout circuit 106-1, a second readout circuit 106-2, and common electronics 108.

[0135] Some embodiments include a method that includes reading first data from an imaging array 102 located inside the housing 110 using at least a first readout circuit 106-1, reading second data from an imaging strip 104 located inside the housing 110 using at least a second readout circuit 106-2, processing the first data with common electronics 108 to generate first image data, and processing the second data with common electronics 108 to generate second image data.

[0136] In some embodiments, the imaging array 102 and the imaging strip 104 are separate.

[0137] In some embodiments, the imaging array 102 and the imaging strip 104 are formed on the same substrate 114.

[0138] In some embodiments, the pixel size of the pixels in the imaging array 102 is different from the pixel size of the pixels in the imaging strip 104.

[0139] In some embodiments, the imaging strip 104 is a subset of the imaging array 102.

[0140] In some embodiments, the imaging strip 104 is less than 30% of the imaging array 102.

[0141] In some embodiments, reading first data from an imaging array 102 located inside the housing 110 using at least a first readout circuit 106-1 includes reading first data from the imaging array 102 via first data lines 618, 718, 818, and reading second data from an imaging strip 104 located inside the housing 110 using at least a second readout circuit 106-2 includes reading second data from the imaging strip 104 using second data lines 618, 718, 818 that are different from the first data lines 618, 718, 818.

[0142] In some embodiments, reading first data from an imaging array 102 located inside the housing 110 using at least a first readout circuit 106-1 includes reading first data from the imaging array 102 via first data lines 618, 718, 818; reading second data from an imaging strip 104 located inside the housing 110 using at least a second readout circuit 106-2 includes reading second data from the imaging strip 104 using second data lines 618, 718, 818; and further includes electrically coupling the first data lines 618, 718, 818 to the second data lines 618, 718, 818 when reading first data from the imaging array 102.

[0143] Some embodiments include a system comprising means for reading first data from an imaging array located inside a housing, means for reading second data from an imaging strip located inside a housing, means for processing the first data with common electronics 108 to generate first image data, and means for processing the second data with common electronics 108 to generate second image data.

[0144] An example of means for reading first data from an imaging array located inside the housing includes a readout circuit 106-1 and associated data lines.

[0145] An example of a means for reading second data from an imaging strip located inside the housing includes a readout circuit 106-2 and associated data lines.

[0146] An example of a means of processing first data with common electronics to generate first image data includes common electronics 108.

[0147] An example of a means of processing second data with common electronics to generate second image data includes common electronics 108.

[0148] In some embodiments, the imaging strip 104 is a subset of the imaging array 102.

[0149] Some embodiments include a system comprising a plurality of pixels 902, a plurality of data lines 908 coupled to the pixels 902, a plurality of switches 906 coupling the pixels 902 to the data lines 908, a plurality of read circuits 910 to 918 coupled to the data lines 908, and control logic 903 coupled to the read circuits 910 to 918, wherein for one of the pixels 902, the control logic 903 is configured to: acquire a first value of the pixel 902 while the corresponding switch 906 is in the off state; reset the corresponding read circuits 910 to 918 corresponding to the pixel; acquire a second value of the pixel 902 after the read circuits have been reset; turn on the corresponding switch 906; acquire a third value of the pixel 902 after the corresponding switch 906 has been turned on; and combine the first, second, and third values ​​to obtain a combined value of the pixel 902.

[0150] In some embodiments, the control logic 903 is further configured to store a stored value of one of the pixels 902 based on a first value, and to combine a second value, a third value, and the stored value to obtain a combined value for pixel 902.

[0151] In some embodiments, the control logic 903 is further configured to reset the corresponding readout circuit for one of the pixels 902 before obtaining the first value of the pixel, and to obtain the fourth value of the pixel 902 while the corresponding switch 906 is ON, and to combine the first, second, third, and fourth values ​​to obtain a combined value for the pixel 902.

[0152] In some embodiments, the control logic 903 is further configured to combine the first, second, third, and fourth values ​​for one of the pixels 902 by adding the third value minus the second value and the first value minus the fourth value, thereby converting them into a combined value for pixel 902.

[0153] In some embodiments, the control logic 903 is further configured to combine a first value and a fourth value to form a first correlated value for one of the pixels 902, combine a second value and a third value to form a second correlated value, and combine the first correlated value and the second correlated value to form a combined value for pixel 902.

[0154] In some embodiments, the control logic 903 is further configured to obtain a first value for one of the pixels 902 for subsequent frames without resetting the corresponding readout circuit.

[0155] In some embodiments, the control logic 903 is further configured to subtract the first and second values ​​from a third value for one of the pixels 902, and to combine the first, second, and third values ​​to obtain a combined value for pixel 902.

[0156] In some embodiments, the control logic 903 is further configured to switch between a first operating mode in which, for one of the pixels 902, a first value, a second value, and a third value are combined to form a combined value of the pixel 902, and a second operating mode in which the second value and the third value are combined to form a combined value of the pixel 902, and the acquisition of the first value of the pixel 902 is not performed while the corresponding switch 906 is in the off state.

[0157] In some embodiments, the system includes an X-ray source configured to generate an X-ray beam, a pixel 902, and further comprises a detector positioned to receive the X-ray beam.

[0158] Some embodiments include a method that, while switch 906 is in the off state, uses read circuits 910 to 918 to obtain a first value of pixel 902 coupled to a data line via switch 906; resets the read circuits; after resetting the read circuits, obtains a second value of pixel 902; turns switch 906 on; after turning switch 906 on, obtains a third value of pixel 902; and combines the first, second, and third values ​​to obtain a combined value of pixel 902.

[0159] In some embodiments, this method further includes storing a stored value for pixel 902 based on a first value, and combining the first value, the second value, and the third value to form a combined value for pixel 902, which includes combining the second value, the third value, and the stored value to form a combined value for pixel 902.

[0160] In some embodiments, this method further includes resetting the readout circuit before obtaining a first value of the pixel, and obtaining a fourth value of the pixel 902 while the switch 906 is ON, and combining the first, second, and third values ​​to obtain a combined value of the pixel 902, and combining the first, second, third, and fourth values ​​to obtain a combined value of the pixel 902.

[0161] In some embodiments, combining the first, second, third, and fourth values ​​to obtain a combined value for pixel 902 includes adding the value obtained by subtracting the second value from the third value and the value obtained by subtracting the fourth value from the first value.

[0162] In some embodiments, the method further includes combining a first value and a fourth value to obtain a first correlated value, combining a second value and a third value to obtain a second correlated value, and combining the first correlated value and the second correlated value to obtain a combined value for pixel 902.

[0163] In some embodiments, this method further includes obtaining a first value of pixel 902 of a subsequent frame without resetting the corresponding readout circuit.

[0164] In some embodiments, combining the first, second, and third values ​​to obtain a combined value for pixel 902 includes subtracting the first and second values ​​from the third value.

[0165] In some embodiments, the method further includes switching between a first operating mode in which a first value, a second value, and a third value are combined to form a combined value for a pixel, and a second operating mode in which the second value and the third value are combined to form a combined value for pixel 902, and the acquisition of the first value for pixel 902 is not performed while the corresponding switch 906 is in the off state.

[0166] In some embodiments, the method further includes generating an X-ray beam using an X-ray source and generating an image using a detector including pixels 902 arranged to receive the X-ray beam.

[0167] Some embodiments include a system comprising means for obtaining a first value of a pixel coupled to a data line via a switch using a readout circuit while the switch is in the off state, means for resetting the readout circuit, means for obtaining a second value of the pixel after the readout circuit has been reset, means for turning the switch on, means for obtaining a third value of the pixel after the switch has been turned on, and means for combining the first value, the second value, and the third value to obtain a combined value of the pixel.

[0168] An example of a means of obtaining a first value of a pixel coupled to a data line via a switch using a read circuit while the switch is in the off state includes a switch 906, a row driver 901, a data line 908, and read circuits 910 to 918.

[0169] Examples of means for resetting the readout circuit include a switch 910a and control logic 903.

[0170] Examples of means for obtaining a second value of a pixel after resetting the readout circuit include a switch 906, a row driver 901, a data line 908, and readout circuits 910 through 918.

[0171] An example of a means of turning on the switch is the control logic 903.

[0172] An example of a means of obtaining a third value of a pixel after the switch has been turned on includes a switch 906, a row driver 901, a data line 908, and read circuits 910 to 918.

[0173] Examples of means for combining a first value, a second value, and a third value to obtain a combined value for a pixel include a switch 906, a row driver 901, a data line 908, read circuits 910 to 918, and an external computer 913.

[0174] In some embodiments, the system further includes means for obtaining a first value of a pixel in a subsequent frame without resetting the corresponding readout circuit. Examples of means for obtaining a first value of a pixel in a subsequent frame without resetting the corresponding readout circuit include a switch 906, a row driver 901, a data line 908, and readout circuits 910 to 918.

[0175] While specific examples of means for performing a particular function have been described above, in other embodiments, a particular function may be performed by other means described herein.

[0176] While structures, devices, methods, and systems are described according to specific embodiments, those skilled in the art will readily recognize that many modifications are possible to specific embodiments, and therefore any modifications should be considered to fall within the spirit and scope disclosed herein. Accordingly, many modifications can be made by those skilled in the art without departing from the spirit and scope of the appended claims.

[0177] The claims following the disclosure in this document are hereby explicitly incorporated into the disclosure in this document, and each claim stands as a separate embodiment in itself. This disclosure includes all substitutions of independent claims with dependent claims. Furthermore, additional embodiments that can be derived from the following independent and dependent claims are also explicitly incorporated into the description in this document. These additional embodiments are determined by replacing the dependency of a given dependent claim with the phrase "any of the claims beginning with claim [x] and ending with the claim immediately preceding this claim," where the parenthetical term "[x]" is replaced with the number of the most recently described independent claim. For example, for a first set of claims beginning with independent claim 1, claim 4 may depend on either claims 1 and 3, and these separate dependencies may result in two different embodiments; claim 5 may depend on any one of claims 1, 3, or 4, and these separate dependencies may result in three different embodiments; claim 6 may depend on any one of claims 1, 3, 4, or 5, and these separate dependencies may result in four different embodiments, and so on.

[0178] The term “first” in the claim relating to a feature or element does not necessarily imply the existence of a second or additional such feature or element. Embodiments of the invention for which exclusive ownership or privilege is claimed are defined as follows: [Item 1] Multiple pixels, Multiple data lines connected to the aforementioned pixel, Multiple switches that connect the aforementioned pixels to the plurality of data lines, Multiple readout circuits coupled to the data line, The system comprises control logic coupled to the readout circuit, The control logic applies to one of the pixels: While the corresponding switch is in the off state, obtain the first value of the pixel, The readout circuit corresponding to the aforementioned pixel is reset, After resetting the readout circuit, the second value of the pixel is obtained. Turn on the corresponding switch, After turning on the corresponding switch, obtain the third value of the pixel. The first value, the second value, and the third value are combined to obtain the combined value of the pixels. system. [Item 2] The control logic applies to one of the pixels, The stored value of the pixel is stored based on the first value, The system according to item 1, which combines the second value, the third value, and the stored value to obtain the combined value of the pixel. [Item 3] The control logic applies to one of the pixels: Before obtaining the first value of the aforementioned pixel, The corresponding readout circuit is reset, While the corresponding switch is in the ON state, obtain the fourth value of the pixel. The system according to item 1, which combines the first value, the second value, the third value, and the fourth value to the combined value of the pixel. [Item 4] The control logic applies to one of the pixels: The system according to item 3, wherein in order to combine the first value, the second value, the third value, and the fourth value into the combined value of the pixel, the value obtained by subtracting the second value from the third value and the value obtained by subtracting the fourth value from the first value are added. [Item 5] The control logic applies to one of the pixels: The first value and the fourth value are combined to obtain a first correlated value. The second value and the third value are combined to obtain a second correlated value. The system according to item 3, which combines the first correlated value and the second correlated value to obtain the combined value of the pixel. [Item 6] The control logic applies to one of the pixels: The system according to any one of items 1 to 5, which obtains the first value of the pixel in a subsequent frame without resetting the corresponding readout circuit. [Item 7] The control logic applies to one of the pixels: A system according to any one of items 1 to 5, wherein the first value and the second value are subtracted from the third value, and the first value, the second value, and the third value are combined to obtain the combined value of the pixel. The system. [Item 8] The control logic applies to one of the pixels: A first operating mode in which the first value, the second value, and the third value are combined to form the combined value of the pixel, A system according to any one of items 1 to 5, which switches between a second operating mode in which the second value and the third value are combined to obtain the combined value of the pixel, and the acquisition of the first value of the pixel is not performed while the corresponding switch is in the off state. [Item 9] An X-ray source that generates an X-ray beam, The system according to any one of items 1 to 5, further comprising a detector having the aforementioned pixels and being arranged to receive the aforementioned X-ray beam. [Item 10] While the switch is in the off state, the readout circuit is used to obtain a first value of the pixel coupled to the data line via the switch, Resetting the aforementioned readout circuit, After resetting the readout circuit, the second value of the pixel is obtained, Turning on the aforementioned switch, After turning on the aforementioned switch, the third value of the aforementioned pixel is obtained, A method comprising combining the first value, the second value, and the third value to obtain a combined value for the pixel. [Item 11] The stored value of the pixel is stored based on the first value, The method of item 10, further comprising combining the first value, the second value, and the third value with the combined value of the pixel, the second value, the third value, and the stored value with the combined value of the pixel. [Item 12] Before obtaining the first value of the aforementioned pixel Resetting the aforementioned readout circuit, The process further includes obtaining a fourth value of the pixel while the switch is in the ON state, The method according to item 10, wherein combining the first value, the second value, and the third value to obtain the combined value of the pixel includes combining the first value, the second value, the third value, and the fourth value to obtain the combined value of the pixel. [Item 13] The first value, the second value, the third value, and the fourth value are combined to obtain the combined value of the pixel. The method of item 12, which includes adding the value obtained by subtracting the second value from the third value and the value obtained by subtracting the fourth value from the first value. [Item 14] The first value and the fourth value are combined to obtain a first correlated value. The second value and the third value are combined to obtain a second correlated value. The method according to item 12, further comprising combining the first correlated value and the second correlated value to obtain a combined value for the pixel. [Item 15] The method according to any one of items 10 to 14, further comprising obtaining the first value of the pixel in a subsequent frame without resetting the corresponding readout circuit. [Item 16] The first value, the second value, and the third value are combined to obtain the combined value of the pixel. The method according to any one of items 10 to 14, comprising subtracting the first value and the second value from the third value. [Item 17] A first operating mode in which the first value, the second value, and the third value are combined to form the combined value of the pixel, The method according to any one of items 10 to 14, further comprising switching to a second operating mode in which the second value and the third value are combined to form the combined value of the pixel, and the acquisition of the first value of the pixel is not performed while the corresponding switch is in the off state. [Item 18] Generating an X-ray beam using an X-ray source, The method according to any one of items 10 to 14, further comprising generating an image using a detector which includes the pixels arranged to receive the X-ray beam. [Item 19] Means for obtaining a first value of a pixel coupled to a data line via the switch using a readout circuit while the switch is in the off state, Means for resetting the readout circuit, After resetting the readout circuit, means for obtaining the second value of the pixel, Means for turning on the aforementioned switch, After turning on the switch, means for obtaining the third value of the pixel, A system including means for combining the first value, the second value, and the third value to obtain a combined value for the pixels. [Item 20] The system according to item 19, further comprising means for obtaining the first value of the pixel in a subsequent frame without resetting the corresponding readout circuit. [Item 21] Housing and An imaging array disposed inside the housing, An imaging strip disposed inside the housing, A first readout circuit coupled to the imaging array, A second readout circuit coupled to the imaging strip, A system comprising common electronics coupled to the first readout circuit and the second readout circuit, which generate image data in response to at least one of the first readout circuit and the second readout circuit. [Item 22] The system according to item 21, wherein the imaging array and the imaging strip are separated. [Item 23] The system according to item 21, wherein the imaging array and the imaging strip are separate and formed on the same substrate. [Item 24] The imaging strip is a subset of the imaging array, as described in item 21. [Item 25] The system according to item 24, wherein the imaging strip is less than 30% of the imaging array. [Item 26] The system according to item 25, further comprising the imaging array and data lines coupled to the imaging strip. [Item 27] The system according to item 26, further comprising a plurality of switches that divide the data line into a plurality of first data lines coupled to the imaging strip and a plurality of second data lines coupled to the remaining portion of the imaging array outside the imaging strip. [Item 28] A plurality of first data lines coupled to the subset of the imaging array, including the imaging strip, The system according to item 25, further comprising a plurality of second data lines separated from the first data line and coupled to the imaging array outside the imaging strip. [Item 29] The system according to any one of items 21 to 28, wherein at least one of the pixel size, layout, resolution, and internal components of the imaging array is different from at least one of the corresponding pixel size, layout, resolution, and internal components of the imaging strip. [Item 30] An X-ray source that generates an X-ray beam, The system according to any one of items 21 to 28, further comprising a detector arranged to receive the X-ray beam, the housing, the imaging array, the imaging strip, the first readout circuit, the second readout circuit, and the common electronics. [Item 31] Using at least a first readout circuit, first data is read from an imaging array located inside the housing, Using at least a second readout circuit, a second data is read from an imaging strip located inside the housing, To generate the first image data, the first data is processed using common electronics, A method comprising processing the second data with common electronics in order to generate a second image data. [Item 32] The method according to item 31, wherein the imaging array and the imaging strip are separated. [Item 33] The method according to item 31, wherein the imaging strip is a subset of the imaging array. [Item 34] The method according to item 33, wherein the imaging strip is less than 30% of the imaging array. [Item 35] Reading the first data from the imaging array located inside the housing using at least the first readout circuit includes reading the first data from the imaging array via a first data line, The method of item 34, wherein reading the second data from the imaging strip located inside the housing using at least the second readout circuit includes reading the second data from the imaging strip using a second data line different from the first data line. [Item 36] Reading the first data from the imaging array located inside the housing using at least the first readout circuit includes reading the first data from the imaging array via a first data line, Reading the second data from the imaging strip located inside the housing using at least the second readout circuit includes reading the second data from the imaging strip using a second data line, The method according to item 34, further comprising electrically coupling the first data line to a second data line when reading the first data from the imaging array. [Item 37] The method according to any one of items 31 to 36, wherein the imaging array and the imaging strip are formed on the same substrate. [Item 38] The method according to any one of items 31 to 36, wherein the pixel size of the pixels of the imaging array is different from the pixel size of the pixels of the imaging strip. [Item 39] A means for reading first data from an imaging array located inside the housing, Means for reading second data from an imaging strip located inside the housing, To generate the first image data, means for processing the first data with common electronics, A system comprising means for processing the second data with the common electronics in order to generate a second image data. [Item 40] The imaging strip is a subset of the imaging array, as described in item 39.

Claims

1. Multiple pixels, Multiple data lines connected to the aforementioned pixel, Multiple switches that connect the aforementioned pixels to the plurality of data lines, Multiple readout circuits coupled to the data line, The system comprises a control logic coupled to the readout circuit, The control logic applies to one of the pixels: While the corresponding switch is in the off state, the first value of the pixel is obtained via the readout circuit corresponding to the pixel. The readout circuit is reset, After resetting the readout circuit, the second value of the pixel is obtained via the readout circuit. Turn on the corresponding switch, After turning on the corresponding switch, the third value of the pixel is obtained via the readout circuit. The first value, the second value, and the third value are combined to obtain the combined value of the pixels. system.

2. The control logic applies to one of the pixels, The stored value of the pixel is stored based on the first value, The system according to claim 1, wherein the second value, the third value, and the stored value are combined to obtain the combined value of the pixel.

3. The control logic applies to one of the pixels, Before obtaining the first value of the aforementioned pixel, The corresponding readout circuit is reset, While the corresponding switch is in the ON state, obtain the fourth value of the pixel. The system according to claim 1, wherein the first value, the second value, the third value, and the fourth value are combined to obtain the combined value of the pixel.

4. The control logic applies to one of the pixels, The system according to claim 3, wherein, in order to combine the first value, the second value, the third value, and the fourth value into the combined value of the pixel, the value obtained by subtracting the second value from the third value and the value obtained by subtracting the fourth value from the first value are added.

5. The control logic applies to one of the pixels, The first value and the fourth value are combined to obtain a first correlated value. The system according to claim 3, wherein the second value and the third value are combined to obtain a second correlated value.

6. The control logic applies to one of the pixels, The system according to claim 5, wherein the first correlated value and the second correlated value are combined to obtain the combined value of the pixel.

7. The control logic applies to one of the pixels, The system according to any one of claims 1 to 6, which obtains the first value of the pixel of a subsequent frame without resetting the corresponding readout circuit.

8. The control logic applies to one of the pixels, The system according to any one of claims 1 to 6, wherein the first value and the second value are subtracted from the third value, and the first value, the second value, and the third value are combined to obtain the combined value of the pixel.

9. The control logic applies to one of the pixels, A first operating mode in which the first value, the second value, and the third value are combined to form the combined value of the pixel, A second operating mode in which the second and third values ​​are combined to form the combined value of the pixel, and the first value of the pixel is not obtained while the corresponding switch is in the off state, A system according to any one of claims 1 to 6, which switches between the following.

10. An X-ray source that generates an X-ray beam, The system according to any one of claims 1 to 6, further comprising a detector having the aforementioned pixels and being arranged to receive the X-ray beam.

11. While the switch is in the off state, the readout circuit is used to obtain a first value of the pixel coupled to the data line via the switch, Resetting the aforementioned readout circuit, After resetting the readout circuit, the second value of the pixel is obtained using the readout circuit, Turning on the aforementioned switch, After turning on the switch, the third value of the pixel is obtained using the reading circuit, A method comprising combining the first value, the second value, and the third value to obtain a combined value for the pixel.

12. The stored value of the pixel is stored based on the first value, The method according to claim 11, wherein setting the first value, the second value, and the third value to the combined value of the pixel is the second value, the third value, and the stored value to the combined value of the pixel.

13. Before obtaining the first value of the aforementioned pixel Resetting the aforementioned readout circuit, The method further includes obtaining a fourth value of the pixel while the switch is in the ON state, The method according to claim 11, wherein combining the first value, the second value, and the third value to obtain the combined value of the pixel further comprises combining the first value, the second value, the third value, and the fourth value to obtain the combined value of the pixel.

14. The first value, the second value, the third value, and the fourth value are combined to obtain the combined value of the pixel. The method according to claim 13, comprising adding the value obtained by subtracting the second value from the third value and the value obtained by subtracting the fourth value from the first value.

15. The first value and the fourth value are combined to obtain a first correlated value. The method according to claim 13, further comprising combining the second value and the third value to obtain a second correlated value.

16. The method according to claim 15, further comprising combining the first correlated value and the second correlated value to obtain the combined value of the pixel.

17. The method according to any one of claims 11 to 16, further comprising obtaining the first value of the pixel in a subsequent frame without resetting the corresponding readout circuit.

18. The first value, the second value, and the third value are combined to obtain the combined value of the pixel. The method according to any one of claims 11 to 16, comprising subtracting the first value and the second value from the third value.

19. A first operating mode in which the first value, the second value, and the third value are combined to form the combined value of the pixel, A second operating mode in which the second value and the third value are combined to form the combined value of the pixel, and the acquisition of the first value of the pixel is not performed while the corresponding switch is in the off state, The method according to any one of claims 11 to 16, further comprising switching between the two.

20. Generating an X-ray beam using an X-ray source, The method according to any one of claims 11 to 16, further comprising generating an image using a detector including the pixels arranged to receive the X-ray beam.

Images