Slave circuit and remote control system using the same

Abstract

To stabilize an output voltage of a linear regulator circuit while reducing power consumption in a slave circuit.SOLUTION: A PMOS transistor MP11 is connected between an output of a diode bridge circuit 32 and a capacitor connection pin CCAP. An operational amplifier OA11 receives a feedback voltage VFB corresponding to a voltage VREG of the capacitor connection pin CCAP at a first input, receives a reference voltage VREF at a second input, and is connected to a gate of the PMOS transistor MP11 at an output. A receiving circuit 40 receives a communication signal COM, based on a voltage VWIRE of a bus 12. A first switch SW11 is connected between a gate and a source of the PMOS transistor MP11. A control unit 62 generates a control signal CTRL synchronized with the communication signal COM to control the first switch SW11.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a slave circuit controlled by a master circuit.

Background Art

[0002] There is a system (referred to as a remote control system) in which a master circuit supplies a power supply voltage to one or more slave circuits connected thereto via a bus and modulates the voltage of the bus to communicate between the master circuit and the slave circuits.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Such a slave circuit includes an internal regulator circuit. The input voltage of the internal regulator circuit is the power supply voltage supplied from the bus, but this power supply voltage fluctuates because a communication signal is superimposed thereon. In order to suppress the power consumption of the internal regulator circuit, if the operating current of the operational amplifier constituting the internal regulator circuit is reduced, the responsiveness of the internal regulator circuit deteriorates. As a result, fluctuations in the power supply voltage, which is the input of the internal regulator circuit, appear as the output of the internal regulator circuit. Specifically, there is a problem that when a communication signal is continuously input for a long time, the output voltage of the internal regulator circuit increases with time.

[0005] The present disclosure has been made in such a situation, and an exemplary object of one aspect thereof is to stabilize the output voltage of a linear regulator circuit while reducing power consumption in a slave circuit.

Means for Solving the Problems

[0006] A part of this disclosure relates to a slave circuit connected to a master circuit via a busbar, which receives a power supply voltage via the busbar and a communication signal superimposed on the power supply voltage. The slave circuit includes a diode bridge circuit for rectifying the busbar voltage, a capacitor connection pin to which a capacitor is connected, a P-type transistor connected between the output of the diode bridge circuit and the capacitor connection pin, an operational amplifier which receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and its output connected to the gate of the P-type transistor, a receiving circuit for receiving a communication signal based on the busbar voltage, a first switch connected between the gate and source of the P-type transistor, and a control unit which generates a control signal synchronized with the communication signal and controls the first switch.

[0007] Another aspect of the present disclosure is also a slave circuit. This slave circuit comprises a diode bridge circuit for rectifying the voltage of a bus, a capacitor connection pin to which a capacitor is connected, a P-type transistor connected between the output of the diode bridge circuit and the capacitor connection pin, an operational amplifier which receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and its output connected to the gate of the P-type transistor, a receiving circuit for receiving a communication signal based on the voltage of the bus, a second switch connected between the drain of the P-type transistor and the capacitor connection pin, and a control unit which generates a control signal synchronized with the communication signal and controls the second switch.

[0008] Furthermore, any combination of the above components, or any substitution of components or expressions between methods, apparatus, systems, etc., are also valid as embodiments of the present invention or this disclosure. Moreover, the description in this section (means for solving the problem) does not describe all the indispensable features of the present invention, and therefore, subcombinations of these described features may also constitute the present invention. [Effects of the Invention]

[0009] According to one aspect of this disclosure, the output voltage of a linear regulator circuit can be stabilized while reducing power consumption. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram of a remote communication system according to an embodiment. [Figure 2] Figure 2 is a circuit diagram of a slave circuit according to an embodiment. [Figure 3] Figure 3 is a circuit diagram of a slave circuit equipped with an internal regulator circuit according to Example 1. [Figure 4] Figure 4 shows the operating waveform of an internal regulator circuit without a first switch. [Figure 5] Figure 5 shows the operating waveform of the internal regulator circuit shown in Figure 3. [Figure 6] Figure 6 is a circuit diagram of the internal regulator circuit according to Example 2. [Figure 7] Figure 7 shows the operating waveform of the internal regulator circuit in Figure 6. [Figure 8] Figure 8 is a circuit diagram of a slave circuit equipped with an internal regulator circuit according to Embodiment 3. [Figure 9] Figure 9 is a circuit diagram of a slave circuit equipped with an internal regulator circuit according to Embodiment 4. [Modes for carrying out the invention]

[0011] (Summary of the embodiment) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow later, and is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify any or all essential elements of all embodiments, nor to delineate the scope of some or all embodiments. For convenience, “one embodiment” may be used to refer to one embodiment (example or variation) or more embodiments (example or variation) disclosed herein.

[0012] A slave circuit according to one embodiment is connected to a master circuit via a busbar, receives a power supply voltage via the busbar, and receives a communication signal superimposed on the power supply voltage. The slave circuit comprises a diode bridge circuit that rectifies the busbar voltage, a capacitor connection pin to which a capacitor is connected, a P-type (Metal Oxide Semiconductor) transistor connected between the output of the diode bridge circuit and the capacitor connection pin, an operational amplifier that receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and its output connected to the gate of the P-type transistor, a receiving circuit that receives a communication signal based on the busbar voltage, a first switch connected between the gate and source of the P-type transistor, and a control unit that generates a control signal synchronized with the communication signal and controls the first switch.

[0013] During the period when the communication signal is generated, the output of the diode bridge circuit, i.e., the source voltage of the P-type transistor, fluctuates. If the first switch is not present, and the response speed of the operational amplifier is slow, immediately after the source voltage of the P-type transistor transitions from low to high, the gate-source voltage of the P-type transistor increases, the P-type transistor becomes fully on, current flows into the capacitor through the P-type transistor, and the capacitor voltage rises above the target voltage. If the communication signal is continuous for a long time, the capacitor voltage will gradually rise. In one embodiment, the rise in capacitor voltage can be suppressed by switching the first switch in synchronization with the communication signal so that the P-type transistor turns off at the timing when the output voltage of the diode bridge circuit transitions from low to high.

[0014] In one embodiment, the slave circuit may further include a second switch connected between the drain of the P-type transistor and the capacitor connection pin. The control unit may control the second switch in conjunction with the first switch. By turning off the second switch during the period when the P-type switch is off, the charging path to the capacitor can be interrupted, and the rise in capacitor voltage can be suppressed.

[0015] A slave circuit according to one embodiment is connected to a master circuit via a busbar, receives a power supply voltage via the busbar, and receives a communication signal superimposed on the power supply voltage. The slave circuit comprises a diode bridge circuit that rectifies the busbar voltage, a capacitor connection pin to which a capacitor is connected, a P-type (Metal Oxide Semiconductor) transistor connected between the output of the diode bridge circuit and the capacitor connection pin, an operational amplifier that receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and its output connected to the gate of the P-type transistor, a receiving circuit that receives a communication signal based on the busbar voltage, a second switch connected between the drain of the P-type transistor and the capacitor connection pin, and a control unit that generates a control signal synchronized with the communication signal and controls the second switch.

[0016] In this configuration, the rise in capacitor voltage can be suppressed by switching the second switch in synchronization with the communication signal so that the second switch turns off at the timing when the output voltage of the diode bridge circuit transitions from low to high.

[0017] In one embodiment, the operational amplifier may be switchable between an on state and an off state in response to an enable signal. The control unit may generate an enable signal synchronized with a communication signal.

[0018] In one embodiment, the receiving circuit may compare the bus voltage with a threshold and generate a received signal according to the comparison result. The control unit may generate a control signal based on the received signal.

[0019] In one embodiment, the control unit may delay the edge of the received signal to generate a control signal.

[0020] In one embodiment, the operational amplifier may be switchable between an on state and an off state in response to an enable signal. The receiving circuit may compare the bus voltage with a threshold and generate a received signal according to the comparison result. The control unit may generate an enable signal by delaying the edge of the received signal by a first delay time, and generate a control signal by delaying the edge of the received signal by a second delay time longer than the first delay time.

[0021] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention.

[0022] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0023] Similarly, "the state in which member C is connected (provided) between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the function or effect produced by their combination.

[0024] Figure 1 is a block diagram of a remote communication system 10 according to an embodiment. The remote communication system 10 comprises a master circuit 20, a slave circuit 30, and a bus 12. The master circuit 20 and the slave circuit 30 are connected via the bus 12. The bus 12 includes a first wire W1 and a second wire W2. The master circuit 20 provides the slave circuit 30 with a DC power supply voltage (power) V via the bus 12. DD The power supply voltage V is supplied between the first wire W1 and the second wire W2. Specifically, the master circuit 20 supplies the power supply voltage V DD The corresponding potential difference V WIRE It generates a potential difference V. WIRE While not particularly limited, it could be 5V, 6V, 8V, 12V, 24V, etc.

[0025] The slave circuit 30 has a potential difference V between the first wire W1 and the second wire W2. WIRE Power supply voltage V DD It is configured to operate as such. The master circuit 20 and the slave circuit 30 are configured to communicate via the bus 12. Specifically, the master circuit 20 uses the potential difference V between the first wire W1 and the second wire W2. WIREBy changing [the relevant parameter], a signal is transmitted to the slave circuit 30. The voltage fluctuation between the buses due to communication is referred to as the communication signal COM. Similarly, the slave circuit 30 also changes the potential difference V between the first wire W1 and the second wire W2 to transmit a signal to the master circuit 20. WIRE By changing [the relevant parameter], a signal is transmitted to the master circuit 20.

[0026] A plurality of slave circuits 30 may be connected to the bus 12. In that case, identification numbers (IDs) are assigned to the plurality of slave circuits 30. The master circuit 20 embeds the identification number in the head part (preamble) of the communication to identify the communication partner. When the identification number of a particular slave circuit 30 is included in the preamble of the received signal, the slave circuit 30 determines that it is the communication target and responds to the signal from the master circuit 20.

[0027] FIG. 2 is a circuit diagram of the slave circuit 30 according to the embodiment. The slave circuit 30 includes a first input pin IN1, a second input pin IN2, a power supply pin VCC, a capacitor connection pin CCAP, a diode bridge circuit 32, an internal circuit 34, a communication circuit 36, and an internal regulator circuit 60. Capacitors C1 and C2 are externally connected to the VCC pin and the CCAP pin, respectively.

[0028] The power supply voltage V is supplied to the slave circuit 30 via two wires W1 and W2, and the communication signal COM is superimposed on this power supply voltage V. The input of the diode bridge circuit 32 is connected to the first input pin IN1 and the second input pin IN2. The voltage between the two wires W1 and W2 is full-wave rectified by the diode bridge circuit 32. The rectified voltage V by the diode bridge circuit 32 is used to generate the power supply voltage of the slave circuit 30. DD is supplied, and this power supply voltage V DD has the communication signal COM superimposed on it. The input of the diode bridge circuit 32 is connected to the first input pin IN1 and the second input pin IN2. The voltage between the two wires W1 and W2 is full-wave rectified by the diode bridge circuit 32. The rectified voltage V CC by the diode bridge circuit 32 is used to generate the power supply voltage of the slave circuit 30.

[0029] The internal circuit 34 has a function according to the use of the slave circuit 30, executes processing according to the control command from the master circuit 20, and also responds to the inquiry from the master circuit 20.

[0030] The communication circuit 36 ​​receives signals from the master circuit 20 and also transmits signals to the master circuit 20. The communication circuit 36 ​​includes a receiving circuit 40 and a transmitting circuit 50. The master circuit 20 uses the potential difference V between two wires W1 and W2. WIRE By changing the potential difference V between the two wires W1 and W2, the receiver circuit 40 transmits a signal to the slave circuit 30. WIRE It is configured to detect changes in the potential difference V. For example, the receiving circuit 40 is configured to detect changes in the potential difference V. WIRE The threshold voltage V TH A comparator may be included to binarize the signal by comparison. The binarized signal is referred to as the received signal RX. The receiving circuit 40 decodes the received signal RX.

[0031] The slave circuit 30 responds to an inquiry from the master circuit 20 and transmits a signal to the master circuit 20. The transmitting circuit 50 detects the potential difference V between the two wires W1 and W2. WIRE By changing this setting, the system is configured to transmit a signal to the master circuit 20.

[0032] The output of the internal regulator circuit 60 is connected to the capacitor C2 via the CCAP pin. The internal regulator circuit 60 receives the output voltage Vcc of the diode bridge circuit 32 and stabilizes the internal power supply voltage V to a predetermined voltage level. REG Generates.

[0033] Internal power supply voltage V REG This is supplied as a power supply voltage to several circuit blocks of the slave circuit 30.

[0034] Next, we will describe some configuration examples of the internal regulator circuit 60 based on several embodiments.

[0035] (Example 1) Figure 3 is a circuit diagram of a slave circuit 30 equipped with an internal regulator circuit 60A according to Embodiment 1. The internal regulator circuit 60A comprises a PMOS (Metal Oxide Semiconductor) transistor MP11, an operational amplifier OA11, resistors R11, R12, R13, a capacitor C11, a first switch SW11, and a control unit 62.

[0036] The capacitor connection pin CCAP is connected to capacitor C11. The PMOS transistor MP11 is connected between the output of the diode bridge circuit 32 and the capacitor connection pin CCAP. Specifically, the source of the PMOS transistor MP11 is connected to the output of the diode bridge circuit 32, and the drain of the PMOS transistor MP11 is connected to the capacitor connection pin CCAP.

[0037] Resistors R11 and R12 control the voltage V across the capacitor connection pin CCAP. REG The voltage is divided, and the feedback voltage V FB Generates. V FB =V REG ×R12 / (R11+R12)

[0038] The operational amplifier OA11 has the voltage across the capacitor-connected pin CCAP connected to the first input (+) V REG The corresponding feedback voltage V FB In response, the reference voltage V is applied to the second input (-). REF The output of op-amp OA11 is connected to the gate of PMOS transistor MP11. Op-amp OA11 receives the feedback voltage V FB and reference voltage V REF Feedback is applied to ensure that the error becomes zero. This feedback adjusts the output voltage V of the internal regulator circuit 60A. REG teeth, V TGT =V REF ×(R11+R12) / R12 The target voltage level V is represented by TGT It will be stabilized.

[0039] The first switch SW11 is connected between the gate and source of the PMOS transistor MP11. The first switch SW11 can be switched on or off in response to the control signal CTRL. In this embodiment, the first switch SW11 is on when the control signal CTRL is high, and the first switch SW11 is off when the control signal CTRL is low.

[0040] Capacitor C11 and resistor R13 are connected in parallel with the first switch SW11 between the gate and source of the PMOS transistor MP11.

[0041] The control unit 62 controls the power supply voltage V DD A control signal CTRL is generated in synchronization with the superimposed communication signal COM, and the first switch SW11 is controlled by the control signal CTRL. For example, the control unit 62 receives a received signal RX generated based on the communication signal COM. The control unit 62 uses the received signal RX to generate the control signal CTRL.

[0042] The above describes the configuration of the internal regulator circuit 60A. Next, we will explain the operation of the internal regulator circuit 60A.

[0043] Before explaining the operation of the internal regulator circuit 60A, we will first explain the operation of the internal regulator circuit without the first switch SW11 (not shown in the diagram, but conveniently labeled as 60R).

[0044] Figure 4 shows the operating waveform of the internal regulator circuit 60R without the first switch SW11. Figure 4 shows the wire-to-wire voltage V WIRE , the output voltage V of the diode bridge circuit 32 CC and the gate voltage V of the PMOS transistor G , the output voltage V of the internal regulator circuit 60R REG This is shown. Output voltage V of diode bridge circuit 32 CC Since this is the source voltage of the PMOS transistor, V CC and V G The potential difference is the gate-source voltage of the PMOS transistor.

[0045] Before time t0, no communication occurred, and the wire voltage V WIRE is the power supply voltage V DD The gate voltage V of the PMOS transistor MP11 is as follows. G The voltage level is feedback-controlled to the appropriate level by the operational amplifier OA11, and the internal power supply voltage V REG The appropriate target voltage level V TGT It has been stabilized.

[0046] When communication occurs at time t0, the wire voltage V WIRE 0V and V DD It fluctuates between [values]. If the response speed of the op-amp OA21 in the internal regulator circuit 60R is slow, the wire-to-wire voltage V WIRE From 0V to V DD At timing t1 immediately after the transition, the gate-source voltage of the PMOS transistor MP11 increases, causing the PMOS transistor MP11 to fully turn on. As a result, current flows into the capacitor C2 through the PMOS transistor MP11, and the output voltage V REG The voltage increases. If communication continues, the output voltage V REG It continues to rise.

[0047] Figure 5 is an operating waveform diagram of the internal regulator circuit 60A shown in Figure 3. When the communication signal COM is transmitted from the master circuit 20, V DD Wire-to-wire voltage V between and 0V WIRE The voltage fluctuates. In the receiving circuit 40, the wire-to-wire voltage V WIRE The threshold voltage V TH The received signal RX is generated by comparing it with the received signal RX. The control unit 62 generates the control signal CTRL in synchronization with the received signal RX. Specifically, the control signal CTRL is generated by delaying the edges of the received signal RX. The control signal CTRL transitions to high from the positive edge of the received signal RX after a delay time τp has elapsed, and transitions to low from the negative edge of the received signal RX after a delay time τn has elapsed.

[0048] During the period when the control signal CTRL is low, the first switch SW11 is off, so the gate of the PMOS transistor MP11 is at the output voltage V of the operational amplifier OA11. G A supply is provided, and feedback is applied.

[0049] During the period when the control signal CTRL is high, the first switch SW11 is turned on, the gate-source of the PMOS transistor MP11 is connected, and the PMOS transistor MP11 is turned off.

[0050] Wire-to-wire voltage V WIRE At the timing when the signal transitions from low to high, the PMOS transistor MP11 turns off. Therefore, even if the response speed of the operational amplifier OA11 is slow, the PMOS transistor MP11 is off, which prevents current from flowing into capacitor C2, and the output voltage V of the internal regulator circuit 60A is controlled. REG This can suppress the rise in [the substance].

[0051] (Example 2) Figure 6 is a circuit diagram of the internal regulator circuit 60B according to Embodiment 2. In the internal regulator circuit 60B, the operational amplifier OA11 can be switched between an on state and an off state according to the enable signal EN. The control unit 62 generates the enable signal EN in synchronization with the communication signal COM, specifically in synchronization with the received signal RX, and controls the operational amplifier OA11.

[0052] The above describes the configuration of the internal regulator circuit 60B. Next, we will explain its operation.

[0053] Figure 7 is an operating waveform diagram of the internal regulator circuit 60B in Figure 6. When the received signal RX transitions from low to high at time t0, that is, the wire voltage V WIRE ga V DD When the voltage transitions from 0V to 0V, the enable signal EN immediately transitions from high to low at time t1. This stops the operation of the operational amplifier OA11, and the output of the operational amplifier OA11 becomes high impedance. Wire-to-wire voltage V WIREPower consumption can be reduced by stopping the operational amplifier OA11 while the voltage is 0V. Then, at time t2 after the delay time τp has elapsed, the control signal CTRL goes high, and the first switch SW11 turns on. As a result, the PMOS transistor MP11 turns off.

[0054] When the received signal RX transitions from high to low at time t3, that is, the wire voltage V WIRE From 0V to V DD When the transition occurs, at time t4 immediately afterward, the enable signal EN transitions from low to high, and the operation of the operational amplifier OA11 resumes. Then, after the operation of the operational amplifier OA11 resumes, at time t5, the control signal CTRL goes low, and the first switch SW11 turns off.

[0055] (Example 3) Figure 8 is a circuit diagram of a slave circuit 30 equipped with an internal regulator circuit 60C according to Embodiment 3. The internal regulator circuit 60C includes a second switch SW12 in addition to the internal regulator circuit 60B in Figure 6. The second switch SW12 is connected between the drain of the PMOS transistor MP11 and the capacitor connection pin CCAP. The second switch SW12 is controlled by the control signal CTRL2. The first switch SW11 and the second switch SW12 are controlled complementaryly.

[0056] A phase compensation capacitor (not shown) is connected between the gate and drain of the PMOS transistor MP11. Power supply voltage V CC When the system starts up, the first switch SW11 turns off first, followed by the second switch SW12, which increases the gate-source voltage of the PMOS transistor MP11, causing the PMOS transistor MP11 to conduct, and an inrush current flows from the power supply line to the capacitor C2. If this inrush current becomes a problem, the power supply voltage V CC To enable the system, it is recommended to adjust the timing of control signals CTRL1 and CTRL2 so that the second switch SW12 turns on first, followed by the first switch SW11 turning off.

[0057] The above describes the configuration of the internal regulator circuit 60C. In Example 3, when the control signal CTRL is low, in addition to the PMOS transistor MP11, the second switch SW12 is also turned off, thus doubly blocking the charging path to capacitor C2. As a result, the wire-to-wire voltage V WIRE From 0V to V DD When it rises, the output voltage of the internal regulator circuit 60C is V REG This will further reliably suppress the rise.

[0058] (Example 4) Figure 9 is a circuit diagram of a slave circuit 30 equipped with an internal regulator circuit 60D according to Embodiment 4. The internal regulator circuit 60D is the same as the internal regulator circuit 60C in Figure 7, but with the first switch SW11 omitted.

[0059] With this configuration, the output voltage V of the internal regulator circuit 60C during the communication period REG This can suppress the rise.

[0060] In Examples 3 and 4, the enable / disable function of the operational amplifier OA11 may be omitted.

[0061] Those skilled in the art will understand that the embodiments are illustrative, and that various modifications exist for each component and combination of processing steps, and that such modifications are also included in this disclosure and may constitute the scope of the present invention.

[0062] (Note) This specification discloses the following technologies:

[0063] (Item 1) A slave circuit connected to a master circuit via a busbar, receiving a power supply voltage via the busbar, and receiving a communication signal superimposed on the power supply voltage, A diode bridge circuit for rectifying the voltage of the busbar, The capacitor connection pin to which the capacitor is connected, A P-type transistor connected between the output of the diode bridge circuit and the capacitor connection pin, An operational amplifier that receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and an output connected to the gate of the P-type transistor, A receiving circuit that receives the communication signal based on the voltage of the busbar, A first switch connected between the gate and source of the P-type transistor, A control unit that generates a control signal synchronized with the communication signal and controls the first switch, A slave circuit equipped with this feature.

[0064] (Item 2) The system further comprises a second switch connected between the drain of the P-type transistor and the capacitor connection pin, The control unit is a slave circuit as described in item 1, which controls the second switch in conjunction with the first switch.

[0065] (Item 3) The operational amplifier can be switched between an on state and an off state in response to an enable signal. The control unit is a slave circuit according to item 1 or 2, which generates the enable signal in synchronization with the communication signal.

[0066] (Item 4) The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The control unit is a slave circuit according to any one of items 1 to 3, which generates the control signal based on the received signal.

[0067] (Item 5) The control unit is a slave circuit according to item 4, which delays the edge of the received signal to generate the control signal.

[0068] (Item 6) The operational amplifier can be switched between an on state and an off state in response to an enable signal. The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The slave circuit according to item 1 or 2, wherein the control unit generates the enable signal by delaying the edge of the received signal by a first delay time, and generates the control signal by delaying the edge of the received signal by a second delay time longer than the first delay time.

[0069] (Item 7) A slave circuit connected to a master circuit via a busbar, receiving a power supply voltage via the busbar, and receiving a communication signal superimposed on the power supply voltage, A diode bridge circuit for rectifying the voltage of the busbar, The capacitor connection pin to which the capacitor is connected, A P-type transistor connected between the output of the diode bridge circuit and the capacitor connection pin, An operational amplifier that receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and an output connected to the gate of the P-type transistor, A receiving circuit that receives the communication signal based on the voltage of the busbar, A second switch connected between the drain of the P-type transistor and the capacitor connection pin, A control unit that generates a control signal synchronized with the communication signal and controls the second switch, A slave circuit equipped with this feature.

[0070] (Item 8) The operational amplifier can be switched between an on state and an off state in response to an enable signal. The control unit is a slave circuit according to item 7, which generates the enable signal in synchronization with the communication signal.

[0071] (Item 9) The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The control unit is a slave circuit according to item 7 or 8, which generates the control signal based on the received signal.

[0072] (Item 10) The control unit generates the control signal by delaying the edge of the received signal, as described in item 9.

[0073] (Item 11) The operational amplifier can be switched between an on state and an off state in response to an enable signal. The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The slave circuit according to item 7, wherein the control unit generates the enable signal by delaying the edge of the received signal by a first delay time, and generates the control signal by delaying the edge of the received signal by a second delay time longer than the first delay time.

[0074] (Item 12) Master circuit and A slave circuit as described in any of items 1 through 11, A busbar connecting the master circuit and the slave circuit, A remote control system equipped with the following features. [Explanation of symbols]

[0075] W1 First wire IN1: First input pin W2 Second wire IN2 2nd input pin 10. Remote communication systems 12 busbar 20 Master Circuit 30 slave circuits 32 Diode Bridge Circuits 34 Internal circuit 36 Communication Circuit 40 Receiving Circuit 50 Transmitter Circuit 60 Internal Regulator Circuit MP11 PMOS transistor R11, R12, R13 Resistors C11 Capacitor OA11 operational amplifier SW11 1st Switch SW12 2nd switch 62 Control Unit

Claims

1. A slave circuit connected to a master circuit via a busbar, receiving a power supply voltage via the busbar, and receiving a communication signal superimposed on the power supply voltage, A diode bridge circuit for rectifying the voltage of the busbar, The capacitor connection pin to which the capacitor is connected, A P-type transistor connected between the output of the diode bridge circuit and the capacitor connection pin, An operational amplifier that receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and an output connected to the gate of the P-type transistor, A receiving circuit that receives the communication signal based on the voltage of the busbar, A first switch connected between the gate and source of the P-type transistor, A control unit that generates a control signal synchronized with the communication signal and controls the first switch, A slave circuit equipped with this feature.

2. The system further comprises a second switch connected between the drain of the P-type transistor and the capacitor connection pin, The slave circuit according to claim 1, wherein the control unit controls the second switch in conjunction with the first switch.

3. The operational amplifier can be switched between an on state and an off state in response to an enable signal. The slave circuit according to claim 1 or 2, wherein the control unit generates the enable signal in synchronization with the communication signal.

4. The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The slave circuit according to claim 1 or 2, wherein the control unit generates the control signal based on the received signal.

5. The slave circuit according to claim 4, wherein the control unit delays the edge of the received signal to generate the control signal.

6. The operational amplifier can be switched between an on state and an off state in response to an enable signal. The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The slave circuit according to claim 1 or 2, wherein the control unit generates the enable signal by delaying the edge of the received signal by a first delay time, and generates the control signal by delaying the edge of the received signal by a second delay time longer than the first delay time.

7. A slave circuit connected to a master circuit via a busbar, receiving a power supply voltage via the busbar, and receiving a communication signal superimposed on the power supply voltage, A diode bridge circuit for rectifying the voltage of the busbar, The capacitor connection pin to which the capacitor is connected, A P-type transistor connected between the output of the diode bridge circuit and the capacitor connection pin, An operational amplifier that receives a feedback voltage corresponding to the voltage of the capacitor connection pin as its first input, a reference voltage as its second input, and an output connected to the gate of the P-type transistor, A receiving circuit that receives the communication signal based on the voltage of the busbar, A second switch connected between the drain of the P-type transistor and the capacitor connection pin, A control unit that generates a control signal synchronized with the communication signal and controls the second switch, A slave circuit equipped with this feature.

8. The operational amplifier can be switched between an on state and an off state in response to an enable signal. The slave circuit according to claim 7, wherein the control unit generates the enable signal in synchronization with the communication signal.

9. The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The slave circuit according to claim 7 or 8, wherein the control unit generates the control signal based on the received signal.

10. The slave circuit according to claim 9, wherein the control unit delays the edge of the received signal to generate the control signal.

11. The operational amplifier can be switched between an on state and an off state in response to an enable signal. The receiving circuit compares the voltage of the busbar with a threshold value and generates a received signal according to the comparison result. The slave circuit according to claim 7, wherein the control unit generates the enable signal by delaying the edge of the received signal by a first delay time, and generates the control signal by delaying the edge of the received signal by a second delay time longer than the first delay time.

12. Master circuit and A slave circuit according to any one of claims 1, 2, 7, or 8, A busbar connecting the master circuit and the slave circuit, A remote control system equipped with the following features.

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