Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device and a method of manufacturing the same capable of forming a diode at low cost.SOLUTION: On a front face of a semiconductor substrate 1, a diode 11 consisting of a polysilicon layer 3 is arranged between a field oxide film 2 and an interlayer insulating film 7. Contact holes 7a and 7b of the interlayer insulating film 7, contact trenches 3a and 3b of the polysilicon layer 3, and a p+ type region 6a are formed by using one resist mask. The contact trenches 3a and 3b are respectively coupled with the contact holes 7a and 7b in a depth direction. At least at a bottom part of the contact trench 3a, a low-resistance contact between the p+ type region 6a and an anode electrode 8 is formed. Although, p-type impurities are ion-injected onto an inner wall of the contact trench 3b at the formation of the p+ type region 6a, an n-type cathode region 5 maintains an n-type, and a contact with a cathode electrode 9 is formed on a side wall of the contact trench 3b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, it is well known that power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have a temperature sensor built into the same module or semiconductor substrate (semiconductor chip) to detect the device temperature during on-operation and prevent failures due to overheating.

[0003] By integrating a temperature sensor into the same semiconductor substrate as the power semiconductor element, the temperature sensor can directly measure the element temperature of the power semiconductor element (the temperature of the semiconductor substrate), thus enabling more accurate detection of the element temperature of the power semiconductor element. Conventional semiconductor devices have been proposed in which a pn junction diode is integrated as a temperature sensor into the same semiconductor substrate as the power semiconductor element (see, for example, Patent Documents 1 to 4 below). Since the current-voltage characteristics of a pn junction diode change depending on the temperature, the element temperature of the power semiconductor element can be detected from the temperature characteristics of the pn junction diode.

[0004] Patent documents 1 and 2 below disclose a structure in which a diffusion diode is provided on the surface region of the front surface of a semiconductor substrate, with a pn junction formed by an impurity diffusion region electrically insulated from the main semiconductor element. Patent document 3 below discloses a structure in which a polysilicon diode, with a pn junction formed in a polysilicon (poly-Si) layer, is embedded inside a trench formed on the front surface of a semiconductor substrate. Patent document 4 below discloses a structure in which a recess is formed on the surface of a LOCOS (Local Oxidation of Silicon) film obtained by locally oxidizing the front surface of a semiconductor substrate, and a polysilicon diode is embedded inside the recess.

[0005] The structure of a conventional semiconductor device will now be described. Figure 27 is a cross-sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device 110 shown in Figure 27 comprises a main semiconductor element (not shown), such as an IGBT or MOSFET, and a diode 111 electrically insulated from the main semiconductor element, on the same semiconductor substrate (semiconductor chip) 101. The diode 111 functions as a temperature sensor that detects the element temperature of the main semiconductor element (temperature of the semiconductor substrate 101) by utilizing its own temperature characteristics.

[0006] Diode 111 is a polysilicon diode formed by creating a pn junction between a p-type anode region 104 and an n-type cathode region 105 inside a polysilicon layer 103. The polysilicon layer 103 is provided on the front surface of the semiconductor substrate 101 via a field oxide film 102. The p-type anode region 104 and the n-type cathode region 105 are adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 101. The p-type anode region 104 and the n-type cathode region 105 have the same thickness.

[0007] In the surface region of the polysilicon layer 103, between the upper surface of the polysilicon layer 103 (the surface on the side of the interlayer insulating film 107) and the p-type anode region 104, p-type impurities are ion-implanted at a high concentration in contact with the p-type anode region 104. +A type anode contact region 106 is selectively provided. Within the polysilicon layer 103, there are no regions adjacent to the n-type cathode region 105 or within the n-type cathode region 105 where impurities are ion-implanted at a high concentration. The polysilicon layer 103 is covered by an interlayer insulating film 107.

[0008] p + The n-type anode contact region 106 and the n-type cathode region 105 are exposed. The anode electrode 108 is embedded in the contact hole 107a and is placed on the front surface of the semiconductor substrate 101. + A low-resistance contact (contact area) is formed with the n-type anode contact region 106. The cathode electrode 109 is embedded in the contact hole 107b and forms contact with the n-type cathode region 105 on the front surface of the semiconductor substrate 101.

[0009] A conventional semiconductor device manufacturing method, as shown in Figure 27, will be explained with reference to Figures 28-33. Figures 28-33 are cross-sectional views showing the state of a conventional semiconductor device during manufacturing. First, as shown in Figure 28, a field oxide film 102 is formed on the front surface of a semiconductor substrate 101 made of silicon (Si). Next, as shown in Figure 29, a p-type polysilicon layer 103 is formed on the field oxide film 102.

[0010] Next, as shown in Figure 30, a portion of the polysilicon layer 103 is impregnated with n-type impurities to form an n-type cathode region 105 that penetrates the polysilicon layer 103 in the depth direction. The portion of the polysilicon layer 103 that remains p-type adjacent to one side (the right side in Figure 30) of the n-type cathode region 105 in a direction parallel to the front surface of the semiconductor substrate 101 becomes the p-type anode region 104.

[0011] Next, as shown in Figure 31, the portion of the polysilicon layer 103 other than the diode 111 portion is removed. This forms a diode 111 consisting of a pn junction between a p-type anode region 104 and an n-type cathode region 105. Next, an interlayer insulating film 107 is formed on the front surface of the semiconductor substrate 101, and the interlayer insulating film 107 covers the p-type anode region 104 (p-type polysilicon layer 103) and the n-type cathode region 105 (n-type polysilicon layer 103).

[0012] Next, as shown in Figure 32, a resist mask 112 is formed on the interlayer insulating film 107, with openings in portions 112a and 112b corresponding to the contact hole formation regions 107a and 107b. Then, the interlayer insulating film 107 is etched using the resist mask 112 to form contact holes 107a and 107b in the interlayer insulating film 107, exposing the p-type anode region 104 and the n-type cathode region 105 in the contact holes 107a and 107b, respectively. Finally, the resist mask 112 is removed.

[0013] Next, as shown in Figure 33, a resist mask 113 having an opening 113a that exposes only the contact hole 107a is formed on the interlayer insulating film 107. Then, by ion implanting p-type impurities using the resist mask 113 and the interlayer insulating film 107 as a mask, p-type impurities are implanted into the surface region of the p-type anode region 104 in the portion exposed to the contact hole 107a. + A type anode contact region 106 is formed. No p-type impurities are ion-implanted into the n-type cathode region 105. Then, the resist mask 113 is removed.

[0014] Subsequently, the anode electrode 108 is formed so as to be embedded in the contact hole 107a, and the anode electrode 108 and p + Contact is formed with the n-type anode contact region 106. By forming the cathode electrode 109 so as to be embedded in the contact hole 107b, contact is formed between the cathode electrode 109 and the n-type cathode region 105. This completes the semiconductor device 110 shown in Figure 27.

[0015] Further, as a conventional trench gate type MOSFET, a contact trench is provided between adjacent gate trenches, and a contact between the source electrode and the n + type source region is formed on the side wall of the contact trench, and a contact between the source electrode and the p + type contact region is formed on the bottom surface of the contact trench has been proposed (see, for example, Patent Document 5 below).

Prior Art Documents

Patent Documents

[0016]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0017] However, in the manufacturing method of the conventional semiconductor device 110 described above (see FIGS. 27 to 33), in order to prevent p-type impurities from being ion-implanted into the n-type cathode region 1 during the formation of the p + type anode contact region, a step of covering the contact hole 107b with the resist mask 113 (see FIG. 33) is required. That is, in order to form the p + type anode contact region, one set of steps (resist film formation, pattern formation, and removal) for forming the resist mask 113 is increased, resulting in an increase in the number of manufacturing steps and an increase in cost.

[0018] On the other hand, if the resist mask 113 is not formed, p-type impurities are ion-implanted into the n-type cathode region 105 (n-type polysilicon layer 103) in the portion exposed to the contact hole 107b, reducing the concentration of n-type impurities and increasing the contact resistance between the cathode electrode 109 and the n-type cathode region 105. If the dose of p-type impurities ion-implanted into the n-type cathode region 105 is large, the n-type cathode region 105 may be converted back to p-type in the portion that forms contact with the cathode electrode 109, potentially causing the diode 111 to malfunction.

[0019] This invention aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can form diodes at low cost, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0020] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor device according to this invention has the following features: A polysilicon layer is provided on the front surface of a semiconductor substrate via an insulating film. A first conductivity type region and a second conductivity type region are provided in the polysilicon layer. The second conductivity type region is adjacent to the first conductivity type region in a direction parallel to the front surface of the semiconductor substrate. A diode is formed at the pn junction between the first conductivity type region and the second conductivity type region. An interlayer insulating film is provided on the front surface of the semiconductor substrate and covers the polysilicon layer. A first contact hole penetrates the interlayer insulating film in the depth direction. A second contact hole penetrates the interlayer insulating film in the depth direction. A first contact trench is provided in the polysilicon layer and connected to the first contact hole in the depth direction. The first contact trench is surrounded by the first conductivity type region.

[0021] A second contact trench is provided in the polysilicon layer and connected to the second contact hole in the depth direction. The second contact trench is surrounded by the second conductivity type region. A first high-concentration region of the first conductivity type is selectively provided inside the polysilicon layer. The first high-concentration region of the first conductivity type is in contact with the first conductivity type region and is exposed to the bottom, side wall, or both of the first contact trench. The first high-concentration region of the first conductivity type has a higher impurity concentration than the first conductivity type region. The first electrode is embedded in the first contact hole and the first contact trench and is in contact with the first high-concentration region of the first conductivity type. The second electrode is embedded in the second contact hole and the second contact trench and is in contact with the second conductivity type region.

[0022] Furthermore, the semiconductor device according to this invention, in the above-described invention, the first contact trench The second contact terminates within the first conductivity type region. trench The first high-concentration region of the first conductivity type terminates within the second conductivity type region. The first high-concentration region of the first conductivity type is exposed at least at the bottom of the first contact trench. A second high-concentration region of the first conductivity type is selectively provided within the polysilicon layer. The second high-concentration region of the first conductivity type is in contact with the second conductivity type region and is exposed only at the bottom of the second contact trench. The second high-concentration region of the first conductivity type is characterized by having a higher impurity concentration than the first conductivity type region.

[0023] Furthermore, the semiconductor device according to this invention, in the above-described invention, the first contact trench The first conductivity type region penetrates in the depth direction and reaches the insulating film. The second contact trench The first conductivity type high-concentration region penetrates the second conductivity type region in the depth direction and reaches the insulating film. The first conductivity type high-concentration region is characterized by being exposed on the side wall of the first contact trench.

[0024] Furthermore, the semiconductor device according to this invention, in the above-described invention, the first contact trenchThe second contact terminates inside the insulating film. trench It is characterized by being terminated inside the insulating film.

[0025] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, it comprises a semiconductor element having a predetermined element structure provided on the front surface side of the semiconductor substrate, and a diode provided separately from the semiconductor element and electrically insulated from the semiconductor element by the insulating film.

[0026] Furthermore, in the semiconductor device according to this invention, the semiconductor element has the element structure, a third contact hole, a third contact trench, a third high-concentration region of the first conductivity type, a third electrode, and a fourth electrode. The element structure includes a pn junction between a first semiconductor region of the first conductivity type and a second semiconductor region of the second conductivity type. The first semiconductor region is provided on the surface region of the front surface of the semiconductor substrate and is covered by the interlayer insulating film. The second semiconductor region is provided between the back surface of the semiconductor substrate and the first semiconductor region. The third contact hole penetrates the interlayer insulating film in the depth direction.

[0027] The third contact trench is connected to the third contact hole and provided in the semiconductor substrate, and is surrounded by the first semiconductor region. The third first conductivity type high-concentration region is provided between the third contact trench and the first semiconductor region, in contact with the first semiconductor region, and is exposed at least at the bottom of the third contact trench. The impurity concentration of the third first conductivity type high-concentration region is higher than that of the first semiconductor region. The third electrode is embedded in the third contact hole and the third contact trench and is in contact with the third first conductivity type high-concentration region. The fourth electrode is provided on the back surface of the semiconductor substrate.

[0028] Furthermore, in the semiconductor device according to this invention, the depth of the first contact hole from the interface between the polysilicon layer and the interlayer insulating film is the same as the depth of the third contact hole from the interface between the semiconductor substrate and the interlayer insulating film. The depth of the second contact hole from the interface between the polysilicon layer and the interlayer insulating film is the same as the depth of the third contact hole from the interface between the semiconductor substrate and the interlayer insulating film.

[0029] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the diode is a temperature sensor that detects the temperature of the semiconductor element.

[0030] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the polysilicon layer is provided on the front surface of the semiconductor substrate via the insulating film.

[0031] Furthermore, the semiconductor device according to this invention further comprises a first recess provided on the front surface of the semiconductor substrate in the invention described above. The insulating film is provided along the inner wall of the first recess. The polysilicon layer is provided on the insulating film inside the first recess.

[0032] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a semiconductor device according to this invention is a method for manufacturing a semiconductor device comprising a diode formed by a pn junction between a first conductivity type region and a second conductivity type region, and has the following features: A first step is to form a polysilicon layer on the front surface of a semiconductor substrate via an insulating film. A second step is to form the first conductivity type region and the second conductivity type region adjacent to each other in a direction parallel to the front surface of the semiconductor substrate on the polysilicon layer. A third step is to form an interlayer insulating film on the front surface of the semiconductor substrate and cover the polysilicon layer with the interlayer insulating film. A fourth step is to form a resist mask with openings at predetermined locations on the interlayer insulating film. A fifth step is to etch the interlayer insulating film using the resist mask to form a first contact hole that penetrates the interlayer insulating film in the depth direction, reaches the polysilicon layer and exposes the first conductivity type region, and a second contact hole that penetrates the interlayer insulating film in the depth direction, reaches the polysilicon layer and exposes the second conductivity type region.

[0033] A sixth step is performed in which the polysilicon layer is etched using the resist mask to form a first contact trench connected to the first contact hole in the depth direction in the first conductivity type region, and a second contact trench connected to the second contact hole in the depth direction in the second conductivity type region. A seventh step is performed in which first conductivity type impurities are ion-implanted using the resist mask to form a first high-concentration first conductivity type region with a higher impurity concentration than the first conductivity type region in the portion of the first conductivity type region exposed to the first contact trench. An eighth step is performed in which the resist mask is removed. A ninth step is performed in which a first electrode is embedded in the first contact hole and the first contact trench and in contact with the first high-concentration first conductivity type region, and a second electrode is embedded in the second contact hole and the second contact trench and in contact with the second conductivity type region.

[0034] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the invention described above, the first step includes the steps of: forming a first recess of a predetermined depth on the front surface of the semiconductor substrate; forming the insulating film along the inner wall of the first recess and leaving a second recess on the surface of the insulating film inside the first recess; and filling the second recess with the polysilicon layer.

[0035] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the invention described above, the first step includes the steps of forming a first recess of a predetermined depth on the front surface of the semiconductor substrate, filling the first recess with the insulating film, forming a second recess on the surface of the insulating film, and filling the second recess with the polysilicon layer.

[0036] Furthermore, the method for manufacturing a semiconductor device according to this invention is a method for manufacturing a semiconductor device comprising a semiconductor element and a diode on a semiconductor substrate, as described above. The semiconductor element has an element structure, a third contact hole, a third contact trench, a third high-concentration region of the first conductivity type, a third electrode, and a fourth electrode. The element structure includes a pn junction between a first semiconductor region of the first conductivity type and a second semiconductor region of the second conductivity type. The first semiconductor region is provided on the surface region of the front surface of the semiconductor substrate and is covered by the interlayer insulating film. The second semiconductor region is provided between the back surface of the semiconductor substrate and the first semiconductor region.

[0037] The third contact hole penetrates the interlayer insulating film in the depth direction. The third contact trench is connected to the third contact hole and provided in the semiconductor substrate, and is surrounded by the first semiconductor region. The third first conductivity type high-concentration region is provided between the third contact trench and the first semiconductor region, in contact with the first semiconductor region, and is exposed at least at the bottom of the third contact trench. The impurity concentration of the third first conductivity type high-concentration region is higher than that of the first semiconductor region. The third electrode is embedded in the third contact hole and the third contact trench and is in contact with the third first conductivity type high-concentration region.

[0038] The fourth electrode is provided on the back surface of the semiconductor substrate. The diode is provided separately from the semiconductor element and is electrically insulated from the semiconductor element by the insulating film. In the fifth step, the first contact hole, the second contact hole, and the third contact hole are formed simultaneously. In the sixth step, the first contact trench, the second contact trench, and the third contact trench are formed simultaneously. In the seventh step, the first high-concentration region of the first conductivity type and the third high-concentration region of the first conductivity type are formed simultaneously.

[0039] Furthermore, the method for manufacturing a semiconductor device according to this invention is characterized in that, in the invention described above, the diode is a temperature sensor that detects the temperature of the semiconductor element.

[0040] According to the invention described above, although the contact trench formation step is increased compared to the conventional method, there is no need to form a new resist mask between the formation of the contact holes in the interlayer insulating film and the formation of the first high-concentration region of the first conductivity type. Therefore, one set of steps (resist deposition, pattern formation, and removal) required for resist mask formation can be reduced by one compared to the conventional method. Consequently, the manufacturing cost can be reduced overall compared to the conventional method. [Effects of the Invention]

[0041] The semiconductor device and method for manufacturing the semiconductor device according to the present invention have the advantage of being able to form diodes at low cost. [Brief explanation of the drawing]

[0042] [Figure 1] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view (part 1) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 3] This is a cross-sectional view (part 2) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 4] This is a cross-sectional view (part 3) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 5] This is a cross-sectional view (part 4) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 6] This is a cross-sectional view (part 5) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 7] This is a cross-sectional view (part 6) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 8] This is a cross-sectional view (part 7) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 9] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2. [Figure 10] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3. [Figure 11] This is a cross-sectional view (part 1) showing the semiconductor device according to Embodiment 3 in the process of being manufactured. [Figure 12] This is a cross-sectional view (part 2) showing the semiconductor device according to Embodiment 3 in the process of being manufactured. [Figure 13] This is a cross-sectional view (part 3) showing the semiconductor device according to Embodiment 3 in the process of being manufactured. [Figure 14]This is a cross-sectional view (part 4) showing the semiconductor device according to Embodiment 3 in the process of being manufactured. [Figure 15] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 4. [Figure 16] This is a cross-sectional view (part 1) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 17] This is a cross-sectional view (part 2) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 18] This is a cross-sectional view (part 3) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 19] This is a cross-sectional view (part 4) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 20] This is a cross-sectional view (part 5) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 21] This is a cross-sectional view (part 6) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 22] This is a cross-sectional view (part 7) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 23] This is a cross-sectional view (part 8) showing the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 24] This is a cross-sectional view (part 1) showing another example of the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 25] This is a cross-sectional view (part 2) showing another example of the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 26] This is a cross-sectional view (part 3) showing another example of the semiconductor device according to Embodiment 4 in the process of being manufactured. [Figure 27] This is a cross-sectional view showing the structure of a conventional semiconductor device. [Figure 28] This is a cross-sectional view (part 1) showing a conventional semiconductor device in the process of being manufactured. [Figure 29] This is a cross-sectional view (part 2) showing the manufacturing process of a conventional semiconductor device. [Figure 30]This is a cross-sectional view (part 3) showing the manufacturing process of a conventional semiconductor device. [Figure 31] This is a cross-sectional view (part 4) showing a conventional semiconductor device in the process of being manufactured. [Figure 32] This is a cross-sectional view (part 5) showing the manufacturing process of a conventional semiconductor device. [Figure 33] This is a cross-sectional view (part 6) showing a conventional semiconductor device in the process of being manufactured. [Modes for carrying out the invention]

[0043] Preferred embodiments of the semiconductor device and method for manufacturing the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0044] (Embodiment 1) The structure of the semiconductor device according to Embodiment 1 will now be described. Figure 1 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1. In Figure 1, the semiconductor substrate 1, field oxide film 2, and interlayer insulating film 7 are labeled "Si substrate," "oxide film," and "interlayer insulating film," respectively (the same applies to Figures 2 to 10). Also in Figure 1, the p-type anode region 4 of the polysilicon layer 3 is labeled "p-type poly-Si," and the n-type cathode region 5 is labeled "n-type poly-Si" (the same applies to Figures 4 to 10).

[0045] The semiconductor device 10 according to Embodiment 1 shown in Figure 1 comprises a semiconductor substrate (semiconductor chip) 1 made of silicon (Si), a main semiconductor element (not shown) such as an IGBT or MOSFET, and a diode 11 electrically insulated from the main semiconductor element (semiconductor substrate 1). The main semiconductor element is located in the active region. The diode 11 is located in a region other than the active region. The diode 11 functions, for example, as a temperature sensor that detects the element temperature of the main semiconductor element (temperature of the semiconductor substrate 1) by utilizing its own temperature characteristics.

[0046] The diode 11 is a polysilicon diode formed by creating a pn junction between a p-type anode region (first conductivity type region) 4 and an n-type cathode region (second conductivity type region) 5 inside a polysilicon layer 3. The polysilicon layer 3 is provided on the front surface of the semiconductor substrate 1 via a field oxide film (insulating film) 2, and is electrically insulated from the main semiconductor element (semiconductor substrate 1) by the field oxide film 2 and the interlayer insulating film 7. The thickness of the polysilicon layer 3 is, for example, about 500 nm. The thickness of the field oxide film 2 is, for example, about 300 nm.

[0047] The p-type anode region 4 and the n-type cathode region 5 are adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 1. The p-type anode region 4 and the n-type cathode region 5 have the same thickness. The n-type impurity concentration in the n-type cathode region 5 is, for example, higher than the p-type impurity concentration in the p-type anode region 4. Contact trenches (first and second contact trenches) 3a and 3b are provided in the polysilicon layer 3 (p-type anode region 4 and n-type cathode region 5). The contact trenches 3a and 3b are connected in the depth direction to contact holes (first and second contact holes) 7a and 7b, which will be described later.

[0048] The contact trenches 3a and 3b terminate at approximately the same depth within the polysilicon layer 3. The polysilicon layer 3 is present between the contact trenches 3a and 3b and the field oxide film 2. Each of the contact trenches 3a and 3b has approximately the same width as the contact holes 7a and 7b, at least at the connection point (the interface between the polysilicon layer 3 and the interlayer insulating film 7). The cross-sectional shape of the contact trenches 3a and 3b may be approximately rectangular with approximately the same width from the opening to the bottom, or it may be a tapered (trapezoidal) shape with the width narrowing from the opening to the bottom.

[0049] If the cross-sectional shape of the contact trench 3a formed in the p-type anode region 4 is tapered, the side walls of the contact trench 3a will also have a p shape, as described later. + p-type impurities are ion-implanted to form type region 6a. In this case, p-type impurities described later are implanted into the sidewall of the contact trench 3a. + A mold region 6a may be formed. Contact trenches 3a and 3b are formed simultaneously and have substantially the same depth and substantially the same cross-sectional shape. Substantially the same width, substantially the same depth, substantially the same depth position, and substantially the same cross-sectional shape means that they are the same width, the same depth, the same depth position, and the same cross-sectional shape, respectively, within a range that includes tolerances due to variations in the manufacturing process.

[0050] The area around the contact trench 3a is surrounded by a p-type anode region 4. The sidewall of the contact trench 3a is exposed to the p-type anode region 4. The area around the contact trench 3b is surrounded by an n-type cathode region 5. The sidewall of the contact trench 3b is exposed to the n-type cathode region 5. In addition, within the polysilicon layer 3, at a position deeper on the semiconductor substrate 1 side than the bottom of the contact trenches 3a and 3b, there are p-type anode regions opposite the bottom of the contact trenches 3a and 3b, respectively. + Type regions (first and second first conductivity type high-concentration regions) 6a and 6b (hatched areas) are selectively provided.

[0051] p + The p-type region 6a is adjacent to the p-type anode region 4. +The mold region 6a surrounds the bottom of the contact trench 3a and is exposed at the bottom of the contact trench 3a. + Type region 6a is p + This is a type anode contact region, and it has the function of reducing the contact resistance with the anode electrode (first electrode) 8, which will be described later, by making ohmic contact with the anode electrode 8. + The type region 6a may be in contact with the field oxide film 2. + A p-type anode region 4 may exist between the type region 6a and the field oxide film 2.

[0052] p + The p-type region 6a may extend between the sidewall of the contact trench 3a and the p-type anode region 4 and be exposed to the sidewall of the contact trench 3a. For example, by making the cross-sectional shape of the contact trench 3a tapered, p-type impurities (first conductivity type impurities) can be easily ion-implanted not only at the bottom of the contact trench 3a but also at the sidewall. As a result, p-type impurities can be ion-implanted from the bottom of the contact trench 3a along the sidewall. + Type region 6a is more likely to form. + The mold region 6a may have a thinner thickness (depth from the side wall) at its side walls than at the bottom of the contact trench 3a.

[0053] p + The type region 6b is in contact with the n-type cathode region 5. + The mold region 6b surrounds the bottom of the contact trench 3b and is exposed at the bottom of the contact trench 3b. + Type region 6b is p + This region is inevitably formed when p-type impurities are ion-implanted into the contact trench 3b during the formation of the type region 6a, and is an inactive region that does not function as a diode 11. + The type region 6b may be in contact with the field oxide film 2. + An n-type cathode region 5 may exist between the type region 6b and the field oxide film 2.

[0054] Regardless of whether the cross-sectional shape of the contact trench 3a is rectangular or tapered, p +The type region 6b is provided only at the bottom of the contact trench 3b and does not exist between the side wall of the contact trench 3a and the n-type cathode region 5. + Even if p-type impurities are ion-implanted into the sidewall of the contact trench 3b during the formation of the type region 6b, the n-type cathode region 5 maintains its n-type state in the portion exposed to the sidewall of the contact trench 3b, while only the portion exposed at the bottom of the contact trench 3b is converted back to the p-type state.

[0055] The polysilicon layer 3 (p-type anode region 4 and n-type cathode region 5) is covered by an interlayer insulating film 7. The interlayer insulating film 7 is provided with contact holes 7a and 7b that penetrate the interlayer insulating film 7 in the depth direction. Contact trenches 3a and 3b of the polysilicon layer 3 (diode 11) are exposed in the contact holes 7a and 7b, respectively. The contact holes 7a and 7b have, for example, approximately the same width. The cross-sectional shape of the contact holes 7a and 7b is, for example, approximately rectangular.

[0056] The anode electrode 8 is embedded in the contact hole 7a and the contact trench 3a, forming contact with the side wall of the contact trench 3a and the p-type anode region 4 at the bottom (or bottom and side wall) of the contact trench 3a. + It forms contact with the type region 6a. The anode electrode 8 is positioned on the entire inner wall of the contact trench 3a. + Forming contact with type region 6a, p + The p-type anode region 4 may be electrically connected via the type region 6a.

[0057] In other words, the anode electrode 8 forms contact with the p-type polysilicon layer 3 across the entire inner wall of the contact trench 3a. The cathode electrode (second electrode) 9 is embedded in the contact hole 7b and the contact trench 3b, forming contact with the n-type cathode region 5 on the side wall of the contact trench 3b. At the bottom of the contact trench 3b is the p +Since the mold region 6b is exposed, no contact is formed between the cathode electrode 9 and the n-type polysilicon layer 3 (n-type cathode region 5) at the bottom of the contact trench 3b.

[0058] A method for manufacturing the semiconductor device 10 according to Embodiment 1 will be described with reference to Figures 2 to 8. Figures 2 to 8 are cross-sectional views showing the semiconductor device according to Embodiment 1 in the process of manufacturing. In Figures 2 to 8, only the region where the diode 11 is formed is shown on the semiconductor substrate 1, and the region where the main semiconductor element is not formed is omitted from the illustration. First, as shown in Figure 2, a field oxide film 2 is formed on the front surface of the semiconductor substrate 1. Next, as shown in Figure 3, a p-type polysilicon layer 3 doped with a p-type impurity such as boron (B) is formed on the field oxide film 2 (first step).

[0059] Next, as shown in Figure 4, a portion of the p-type polysilicon layer 3 is converted back to n-type by ion implantation of n-type impurities such as arsenic (As), thereby forming an n-type cathode region 5 (n-type polysilicon layer 3) that penetrates the polysilicon layer 3 in the depth direction. The n-type cathode region 5 is then processed in a later step (p + The n-type impurity concentration is set high enough to maintain the n-type state even when p-type impurities are ion-implanted during the formation of type regions 6a and 6b. For example, if a p-type polysilicon layer 3 is converted to an n-type state to form an n-type cathode region 5, the n-type cathode region 5 will be set to satisfy the above-mentioned n-type impurity concentration condition.

[0060] Furthermore, by turning the p-type polysilicon layer 3 into an n-type form to create an n-type cathode region 5, the n-type cathode region 5 is then processed in a later step (p + Even if p-type impurities are ion-implanted in the formation of type regions 6a and 6b, the n-type impurity concentration conditions remain such that the predetermined characteristics of the diode 11 do not change. Of the polysilicon layer 3, the portion that remains p-type adjacent to one side (the right side in Figure 4) of the n-type cathode region 5 in a direction parallel to the front surface of the semiconductor substrate 1 becomes the p-type anode region 4 (p-type polysilicon layer 3).

[0061] Next, as shown in Figure 5, the portion of the polysilicon layer 3 other than the diode 11 portion is removed by etching. Through these steps, a diode 11 consisting of a pn junction of a p-type anode region 4 and an n-type cathode region 5 is formed (second step). Alternatively, the remaining portion of the polysilicon layer 3, excluding the portion that will become the diode 11, may be removed before forming the n-type cathode region 5. Next, an interlayer insulating film 7 is formed on the front surface of the semiconductor substrate 1, and the polysilicon layer 3 (p-type anode region 4 and n-type cathode region 5) is covered with the interlayer insulating film 7 (third step).

[0062] Next, as shown in Figure 6, a resist mask 12 is formed on the interlayer insulating film 7, with openings in portions 12a and 12b corresponding to the contact hole 7a and 7b formation regions (fourth step). Next, the interlayer insulating film 7 is etched using the resist mask 12 to form contact holes 7a and 7b in the interlayer insulating film 7, exposing the p-type anode region 4 and the n-type cathode region 5, respectively (fifth step). For etching the interlayer insulating film 7, for example, a fluorine-based gas such as methane tetrafluoride (CF4) gas or trifluoromethane (CHF3) gas, or argon (Ar) gas, or a mixture of these gases is used.

[0063] Next, as shown in Figure 7, contact trenches 3a and 3b are formed in the polysilicon layer 3 by etching it using a resist mask 12 (sixth step). For etching the polysilicon layer 3, for example, chlorine-based gases such as methane tetrafluoride (CF4), chlorine gas (Cl2), nitrogen gas (N2), or oxygen gas (O2), or a mixture thereof, can be used. Etching of the polysilicon layer 3 can be performed using the same etching apparatus as etching the interlayer insulating film 7, but it is preferable to use a different etching apparatus than that used for etching the interlayer insulating film 7.

[0064] Next, as shown in Figure 8, p-type impurities are ion-implanted using the resist mask 12 (step 7). As a result, the concentration of p-type impurities in the p-type polysilicon layer 3 (p-type anode region 4) increases at the bottom of the contact trench 3a, and p-type impurities are implanted at the bottom of the contact trench 3a. + A mold region 6a is formed. p + It is sufficient that a type region 6a is formed, p + The thickness of the mold region 6a may be thin. In addition, the n-type polysilicon layer 3 (n-type cathode region 5) is beaten back into a p-type at the bottom of the contact trench 3b, and p + Type region 6b is formed.

[0065] If the cross-sectional shape of the contact trench 3a is tapered, p-type impurities are also ion-implanted into the side walls of the contact trench 3a, and p-type impurities are implanted into the interior of the p-type polysilicon layer 3, along the side walls from the bottom of the contact trench 3a. + Type region 6a is easily formed. The amount of p-type impurities ion-implanted into the side wall of the contact trench 3a is less than the amount of p-type impurities ion-implanted into the bottom of the contact trench 3a, so p + The thickness of the mold region 6a is thinner in the portion along the side wall of the contact trench 3a (depth from the side wall) than in the portion along the bottom of the contact trench 3a.

[0066] If the cross-sectional shape of the contact trench 3b is tapered, p-type impurities are easily ion-implanted into the sidewalls of the contact trench 3b. However, even if p-type impurities are ion-implanted into the sidewalls of the contact trench 3b, the concentration of n-type impurities in the n-type polysilicon layer 3 (n-type cathode region 5) is only slightly lower at the sidewalls of the contact trench 3b. Therefore, even if p-type impurities are ion-implanted into the sidewalls of the contact trench 3b, p + The mold region 6b is formed only at the bottom of the contact trench 3b and not on the side walls of the contact trench 3b. Then, the resist mask 12 is removed (step 8).

[0067] The resist mask 12 may be removed before the formation of contact trenches 3a and 3b. In this case, the interlayer insulating film 7 is used as a mask to form the contact trenches 3a and 3b (etching process) and p + Formation of mold regions 6a and 6b (ion implantation process) is performed. While the interlayer insulating film 7 is also etched during the formation of contact trenches 3a and 3b, the reduction in the thickness of the interlayer insulating film 7 can be suppressed by setting the etching conditions for the polysilicon layer 3 to a condition with a high selectivity ratio with the interlayer insulating film 7. + Before forming the mold regions 6a and 6b, remove the resist mask 12 and use the interlayer insulating film 7 as a mask, p + Type regions 6a and 6b may be formed.

[0068] In this way, using the resist mask 12 or the interlayer insulating film 7 as a mask, p is formed inside the p-type anode region 4. + p, which is the anode contact region. + This forms a type region 6a. + The p-type region 6a is formed at the bottom of the contact trench 3a connected to the contact hole 7a, and forms a low-resistance contact with the anode electrode 8 at a deep position on the semiconductor substrate 1 side within the p-type anode region 4. Similar to the contact trench 3a of the p-type anode region 4, a contact trench 3b is also formed in the n-type cathode region 5, connected to the contact hole 7b and reaching a deep position on the semiconductor substrate 1 side within the n-type cathode region 5.

[0069] p + When the type region 6a is formed, both contact holes 7a and 7b are exposed, so p enters the interior of the p-type anode region 4. + As the n-type region 6a is formed, p also forms inside the n-type cathode region 5. + Type region 6b is formed. p inside the n-type cathode region 5 +The type region 6b is formed only at the bottom of the contact trench 3b, and the n-type cathode region 5 is exposed on the side wall of the contact trench 3b. As a result, contact can be formed between the cathode electrode 9 and the n-type cathode region 5 on the side wall of the contact trench 3b, and a diode 11 is formed by a pn junction between the p-type anode region 4 and the n-type cathode region 5.

[0070] For example, in the conventional method (see Figures 27-33), from the formation of contact holes 107a and 107b in the interlayer insulating film 107, p + Two resist masks 112 and 113 are required before the formation of the type anode contact region 106. On the other hand, in Embodiment 1, as described above, the number of steps for forming contact trenches 3a and 3b is increased compared to the conventional method, but from the formation of contact holes 7a and 7b of the interlayer insulating film 7 to p + Type anode contact region (p + Only one resist mask 12 needs to be formed during the formation of the mold region 6a), and compared to the conventional method, the set of steps required for forming the resist mask (resist film formation, pattern formation, and removal) can be reduced to one.

[0071] Also, contact holes 7a, 7b, contact trenches 3a, 3b and p + Type anode contact region (p + The type region 6a) is a contact hole, contact trench, and p of a main semiconductor element (not shown) located in a region different from the diode 11. + It can be formed simultaneously with the type contact region (see, for example, Figures 10 and 15 described later). Therefore, when forming the diode 11 described above on the same semiconductor substrate 1 as the main semiconductor element, contact holes 7a, 7b, contact trenches 3a, 3b and p + Type anode contact region (p + No additional manufacturing steps are required to form the mold region 6a).

[0072] Next, a metal electrode film is formed on the front surface of the semiconductor substrate 1 so as to fill the contact holes 7a, 7b and contact trenches 3a, 3b. The metal electrode film may be formed from different metal materials for the portion that is embedded in the contact holes 7a, 7b and contact trenches 3a, 3b and the portion that protrudes from the surface of the interlayer insulating film 7. By patterning this metal electrode film and leaving the portions that will become the anode electrode 8 and cathode electrode 9 (step 9), the semiconductor device 10 shown in Figure 1 is completed.

[0073] As described above, according to Embodiment 1, the resist mask used to form the contact holes in the interlayer insulating film, or the interlayer insulating film itself, is used as a mask to form the contact trenches in the polysilicon layer (p-type anode region and n-type cathode region), and p + A type anode contact region is formed. The contact trenches in the polysilicon layer are formed connected to each contact hole for contact with the anode electrode and cathode electrode, respectively. + The p-type anode contact region is formed at least at the bottom of the contact trench of the p-type anode region. + The type anode contact region allows for the formation of low-resistance contact with the anode electrode.

[0074] p + When the n-type anode contact region is formed, a contact hole for contact with the cathode electrode is exposed, and p-type impurity ions are implanted into the n-type cathode region from the contact trench connected to the contact hole, but p + The type region is formed to such an extent that the n-type cathode region (n-type polysilicon layer) is exposed on the side wall of the contact trench. Therefore, contact can be formed between the cathode electrode and the n-type cathode region on the side wall of the contact trench. This makes it possible to form a diode with a pn junction between a p-type anode region and an n-type cathode region made of a polysilicon layer.

[0075] Although the number of steps for forming contact trenches increases compared to conventional methods, the contact holes in the interlayer insulating film and the contact trenches in the polysilicon layer, p + The type anode contact region and can be formed with the same resist mask. Therefore, from the formation of contact holes in the interlayer insulating film to p + Since there is no need to form a new resist mask before the anode contact region is formed, one set of steps (resist deposition, pattern formation, and removal) required for resist mask formation can be reduced compared to conventional methods. Therefore, the manufacturing cost can be reduced throughout the entire manufacturing process compared to conventional methods, allowing for the low-cost formation of diodes.

[0076] Furthermore, according to Embodiment 1, when a contact trench is also formed on the main semiconductor element, the contact trench of the diode can be formed simultaneously with the contact trench of the main semiconductor element. Since there is no need to add a new process to form a contact trench on the diode, manufacturing costs can be further reduced. In addition, according to Embodiment 1, by placing a diode that functions as a temperature sensor on the same semiconductor substrate as the main semiconductor element, the temperature of the main semiconductor element (semiconductor substrate) can be accurately measured, thereby preventing failures of the main semiconductor element due to overheating.

[0077] (Embodiment 2) The structure of the semiconductor device according to Embodiment 2 will now be described. Figure 9 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. The semiconductor device 20 according to Embodiment 2 differs from the semiconductor device 10 according to Embodiment 1 (see Figure 1) in the following two points. The first difference is that the contact trenches 21a and 21b formed in the polysilicon layer 3 (p-type anode region 4 and n-type cathode region 5) are made to a depth that reaches the underlying field oxide film 2. The second difference is that the n-type cathode region 5 has p + The key feature is that it does not create a type domain.

[0078] Specifically, the contact trenches 21a and 21b penetrate the polysilicon layer 3 in the depth direction and reach the field oxide film 2. The thickness T3 of the field oxide film 2 remaining between the bottom of the contact trenches 21a and 21b and the semiconductor substrate 1 only needs to be sufficient to electrically insulate the polysilicon layer 3 from the semiconductor substrate 1, and the contact trenches 21a and 21b may terminate inside the field oxide film 2. By increasing the depth of the contact trenches 21a and 21b, the latch-up tolerance can be improved.

[0079] The contact trenches 21a and 21b are connected to the contact holes 7a and 7b in the depth direction, respectively. The cross-sectional shape of the contact trenches 21a and 21b must be a tapered shape, narrowing in width from the opening side towards the bottom. The field oxide film 2 is exposed on the bottom surface of the contact trenches 21a and 21b. The entire exposed surface of the p-type anode region 4 (p-type polysilicon layer 3) on the side wall of the contact trench 21a is covered with p + A type region (first high-concentration region of the first conductivity type) 22 (hatched portion) is provided.

[0080] p + The p-type region 22 is in contact with the p-type anode region 4 and is exposed on the side wall of the contact trench 21a. + It is preferable that a mold region 22 is formed. The cross-sectional shape of the contact trench 21a is such that p is formed on the side walls of the contact trench 21a. + It is necessary to widen the opening side and create a tapered shape with inclined side walls so that p-type impurities for forming the type region 22 are reliably ion-implanted. + Type region 22 is p + This is a type anode contact region, which has the function of reducing contact resistance with the anode electrode 8.

[0081] The contact trench 21b is formed simultaneously with the contact trench 21a, similar to Embodiment 1, and has the same cross-sectional shape as the contact trench 21a. The contact trench 21b is surrounded by an n-type cathode region 5. The n-type cathode region 5 is exposed on the side wall of the contact trench 21b. + During the formation of the type region 22, p-type impurities are also ion-implanted into the sidewalls of the contact trench 21b, but the n-type cathode region 5 (n-type polysilicon layer 3) maintains its n-type state.

[0082] The anode electrode 8 is embedded in the contact hole 7a and the contact trench 21a. The anode electrode 8 is embedded in the side wall of the contact trench 21a. + A low-resistance contact is formed with the type region 22, p + It is electrically connected to the p-type anode region 4 via the type region 22. The cathode electrode 9 is embedded in the contact hole 7b and the contact trench 21b. The cathode electrode 9 forms contact with the n-type cathode region 5 on the side wall of the contact trench 21b.

[0083] Thus, even though contact trenches 21a and 21b are provided that penetrate the polysilicon layer 3 in the depth direction and reach the field oxide film 2, p is present only on the side wall of the contact trench 21a. + By forming the p-type region 22, a diode 11 is formed by a pn junction between the p-type anode region 4 and the n-type cathode region 5, similar to the first embodiment. + During the formation of the mold region 22, p-type impurities are ion-implanted into the field oxide film 2 from the bottom of the contact trenches 21a and 21b, but this does not adversely affect the insulating properties of the field oxide film 2.

[0084] The method for manufacturing the semiconductor device 20 according to Embodiment 2 is as follows: In the method for manufacturing the semiconductor device 10 according to Embodiment 1 (see Figures 2 to 8), either a resist mask 12 (see Figure 7) for forming contact holes 7a and 7b is used as a mask, or the interlayer insulating film 7 is used as a mask to form contact trenches 21a and 21b with a tapered cross-sectional shape in the p-type anode region 4 and the n-type cathode region 5, respectively, to penetrate the polysilicon layer 3 in the depth direction and reach the field oxide film 2.

[0085] As described above, according to Embodiment 2, even when a contact trench is formed that penetrates the polysilicon layer forming the diode in the depth direction, the same effects as in Embodiment 1 can be obtained.

[0086] (Embodiment 3) As a semiconductor device according to Embodiment 3, the structure of the main semiconductor element fabricated (manufactured) together with the diode 11 on the semiconductor substrate 1 in the semiconductor devices 10 and 20 according to Embodiments 1 and 2 (see Figures 1 and 9) will be described. Figure 10 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3. Here, the region in which the diode 11 having contact trenches 21a and 21b of Embodiment 2 (see Figure 9) is arranged is defined as the diode region 30. In the diode region 30, instead of the diode 11 of Embodiment 2, the diode 11 having contact trenches 3a and 3b of Embodiment 1 (see Figure 1) may be arranged.

[0087] The semiconductor device 50 according to Embodiment 3 shown in Figure 10 includes, for example, an IGBT as the main semiconductor element in the active region 40 of the semiconductor substrate 1, and a diode 11 in the diode region 30 of the semiconductor substrate 1. The semiconductor substrate 1 is, for example, n - It is of type n of IGBT - This constitutes the type drift region (second semiconductor region) 41. -The drift region 41 is provided from the center to the edge of the semiconductor substrate 1. The active region 40 is the region through which the main current (drift current) flows when the IGBT is turned on, and multiple unit cells (functional units of the device) of the same IGBT structure (device structure) are arranged adjacent to each other.

[0088] The area between the active region 40 and the edge of the semiconductor substrate 1 is an edge termination region (not shown) equipped with a predetermined breakdown voltage structure. The edge termination region surrounds the active region 40 and has the function of mitigating the electric field near the boundary between the active region and the edge termination region to maintain breakdown voltage. Breakdown voltage is the upper limit voltage at which the element does not malfunction or break down at the operating voltage. The diode region 30 may be provided in the edge termination region, or it may be placed between the active region 40 and the edge termination region, or it may be surrounded by the active region 40. No IGBT unit cells are provided in the diode region 30.

[0089] In the diode region 30, the front surface of the semiconductor substrate 1 and n - A p-type region 31 is provided between the diode region 30 and the IGBT drift region 41, separated from the trench gate structure of the IGBT in the active region 40 and the breakdown voltage structure of the edge termination region. The upper surface of the p-type region 31 (the front surface of the semiconductor substrate 1) is covered with a field oxide film 2 and an interlayer insulating film 7. The p-type region 31 has the function of making the electric field uniform in the plane of the front surface of the semiconductor substrate 1 in the diode region 30. The thickness of the p-type region 31 (depth from the front surface of the semiconductor substrate 1) is approximately the same as the thickness of the p-type region constituting the breakdown voltage structure of the edge termination region (for example, about 8 μm).

[0090] In the diode region 30, a diode 11 made of a polysilicon layer 3 is provided on the front surface of the semiconductor substrate 1, similar to the second embodiment. The entire polysilicon layer 3 faces the p-type region 31 in the depth direction via the field oxide film 2. The polysilicon layer 3 is electrically insulated from the active region 40 and the edge termination region by the field oxide film 2 and the interlayer insulating film 7. Diode 11 (polysilicon layer 3), contact trenches 21a, 21b, p +The configurations of the p-type region 22, the contact holes 7a and 7b, the anode electrode 8, and the cathode electrode 9 are the same as those in the second embodiment.

[0091] The interlayer insulating film 7 is provided with a uniform thickness over the entire front surface of the semiconductor substrate 1 and covers the polysilicon layer 3 and the gate electrode 46 described later. By disposing the polysilicon layer 3 (diode 11) on the front surface of the semiconductor substrate 1, the height T1 from the front surface of the semiconductor substrate 1 in the diode region 30 to the upper surface (the outermost surface or the interface with the passivation film) of the interlayer insulating film 7 is, for example, about 5000 nm higher than the height T2 from the front surface of the semiconductor substrate 1 in the active region 40 to the upper surface of the interlayer insulating film 7. A step is formed at the boundary between the diode region 30 and the active region 40 on the upper surface of the interlayer insulating film 7.

[0092] In the active region 40, an IGBT trench gate structure is provided between the front surface of the semiconductor substrate 1 and the n- - type drift region 41. The IGBT trench gate structure is composed of a p-type base region (first semiconductor region) 42, an n- + type emitter region 43, a contact trench (third contact trench) 47, a p- + type emitter contact region (third high-concentration region of the first conductivity type) 48 (hatched portion), a gate trench 44, a gate insulating film 45, and a gate electrode 46.

[0093] The p-type base region 42 is provided apart from the p-type region 31 between the front surface of the semiconductor substrate 1 and the n- - type drift region 41 in the active region 40. The depth position of the lower surface (the surface on the side of the p- + type collector region 52) of the p-type base region 42 is, for example, shallower on the side of the n- + type emitter region 43 than the lower surface of the p-type region 31. The n- + type emitter region 43 is selectively provided between the front surface of the semiconductor substrate 1 and the p-type base region 42.

[0094] The gate trench 44 extends in the depth direction as an n- +The n-type drift region 41 is reached through the p-type emitter region 43 and the p-type base region 42. Inside the gate trench 44, a gate electrode 46 is provided via a gate insulating film 45. The upper surface of the gate electrode 46 (the surface on the opening side of the gate trench 44) is covered with an interlayer insulating film 7. Between adjacent gate trenches 44, a contact trench 47 is provided away from the gate trench 44. -

[0095] The contact trench 47 penetrates the n-type emitter region 43 and terminates inside the p-type base region 42 in the depth direction. The contact trench 47 is connected to a contact hole (third contact hole) 7c described later in the depth direction. The contact trench 47 has substantially the same width as the contact hole 7c at the connection point with the contact hole 7c (the interface between the semiconductor substrate 1 and the interlayer insulating film 7). The contact trench 47 is formed simultaneously with the contact trenches 21a and 21b of the diode 11 and has substantially the same depth and substantially the same cross-sectional shape as the contact trenches 21a and 21b. On the side wall of the contact trench 47, the n-type emitter region 43 is exposed on the opening side of the contact trench 47. + +

[0096] The p-type emitter contact region 48 is provided between the contact trench 47 and the p-type base region 42. + + The p-type emitter contact region 48 contacts the p-type base region 42 and the n-type emitter region 43 and is exposed at least at the bottom of the contact trench 47. For example, when the contact trench 47 has a rectangular cross-sectional shape, the p-type emitter contact region 48 is exposed only at the bottom of the contact trench 47. When the contact trench 47 has a tapered cross-sectional shape, the p-type emitter contact region 48 is exposed on the inner wall of the contact trench 47 on the bottom side of the contact trench 47. + + + + The p-type emitter contact region 48 is the p- + ​​​​​​​Type anode contact region (p + It is formed simultaneously with the type region 22).

[0097] In the active region 40, the interlayer insulating film 7 covering the front surface of the semiconductor substrate 1 is provided with contact holes 7c. The contact holes 7c penetrate the interlayer insulating film 7 in the depth direction between adjacent gate trenches 44. The contact holes 7c are formed simultaneously with the contact holes 7a and 7b of the diode region 30. The contact trench 47 of the main semiconductor element (IGBT) is exposed in the contact holes 7c.

[0098] The emitter electrode (third electrode) 49 is embedded in the contact hole 7c and the contact trench 47. The emitter electrode 49 is embedded in the inner wall of the contact trench 47. + Type emitter region 43 and p + It contacts the type emitter contact region 48. The emitter electrode 49 is on the inner wall of the contact trench 47. + It forms a low-resistance contact with the type emitter contact region 48. The emitter electrode 49 is p + It is electrically connected to the p-type base region 42 via the p-type emitter contact region 48. The emitter electrode 49 is formed simultaneously with the anode electrode 8 and cathode electrode 9 of the diode 11.

[0099] The back surface of semiconductor substrate 1 and n - Between the type drift region 41 and the entire back surface of the semiconductor substrate 1, p + A collector region 52 is provided. The back surface of the semiconductor substrate 1 and n - Between the type drift region 41, p + From the back surface of the semiconductor substrate 1, n + Deeply located on the emitter region 43 side, n + A type buffer area 51 is provided. + Type buffer area 51 is p + It may be in contact with the type collector area 52, and p + It is provided separately from the type collector area 52, p +n between the type collector area 52 - A type drift region 41 may exist. The collector electrode (fourth electrode) 53 is on the back surface of the semiconductor substrate 1, p + It is in contact with the entire area of ​​the type collector region 52.

[0100] Next, the manufacturing method of the semiconductor device 50 according to Embodiment 3 will be described with reference to Figures 11 to 14. Figures 11 to 14 are cross-sectional views showing the semiconductor device according to Embodiment 3 in the process of manufacturing. First, as shown in Figure 11, by ion implantation of p-type impurities, n is implanted in almost the entire diode region 30. - A p-type region 31 is formed on the surface area of ​​the front surface of the type semiconductor substrate 1. The p-type region 31 is formed, for example, at the same time as the p-type region that constitutes the breakdown voltage structure of the edge termination region.

[0101] Next, as shown in Figure 12, a p-type base region 42 is formed on the surface region of the front surface of the semiconductor substrate 1 in substantially the entire area of ​​the active region 40 by ion implantation of p-type impurities. Next, by etching, n-type impurities are formed to penetrate the p-type base region 42 in the depth direction. - A gate trench 44 is formed that reaches the type drift region 41 (the portion of the semiconductor substrate 1 that is on the back side of the semiconductor substrate 1, beyond the p-type base region 42). Next, a gate electrode 46 is formed inside the gate trench 44 via a gate insulating film 45.

[0102] Next, as shown in Figure 13, n-type impurities are ion-implanted into the surface region of the p-type base region 42, in contact with the gate insulating film 45 of the side wall of the gate trench 44. + A p-type emitter region 43 is formed. Next, on the front surface of the semiconductor substrate 1, facing the p-type region 31 in the depth direction, a diode 11 consisting of a polysilicon layer 3 (p-type anode region 4 and n-type cathode region 5) is formed via a field oxide film 2, similar to the second embodiment. + The n-type emitter region 43 and the n-type cathode region 5 may be formed simultaneously.

[0103] Next, as shown in Figure 14, an interlayer insulating film 7 is formed over the entire surface of the front surface of the semiconductor substrate 1, covering the polysilicon layer 3 and the gate electrode 46 with the interlayer insulating film 7. Then, similar to Embodiment 2, contact holes 7a and 7b are formed in the interlayer insulating film 7 in the diode region 30. The contact holes 7a and 7b may be formed at the same time as the contact hole 7c of the active region 40. The contact holes 7a to 7c are for the p-type anode region 4, the n-type cathode region 5 and n-type cathode region, respectively. + The type emitter region 43 is exposed.

[0104] Next, similar to Embodiment 2, contact trenches 21a and 21b are formed in the polysilicon layer 3 (p-type anode region 4 and n-type cathode region 5). The contact trenches 21a and 21b may be formed simultaneously with the contact trench 47 of the active region 40. The side walls of the contact trenches 21a and 21b expose the p-type anode region 4 and the n-type cathode region 5, respectively. The inner wall of the contact trench 47 is n + The p-type emitter region 43 and the p-type base region 42 are exposed.

[0105] Next, similar to Embodiment 2, p in the p-type anode region 4 + Forms type region 22. + Type region 22 is p of active region 40 + The emitter contact region 48 may be formed at the same time as the emitter contact region 48. Next, the anode electrode 8 and cathode electrode 9 are formed in the same manner as in Embodiment 2. The anode electrode 8 and cathode electrode 9 may be formed at the same time as the emitter electrode 49. After that, on the back side of the semiconductor substrate 1, n + Type buffer area 51, p + By forming the type collector region 52 and the collector electrode 53, the semiconductor device 50 shown in Figure 10 is completed.

[0106] By applying Embodiment 1 (see Figure 1) to the semiconductor device 50 according to Embodiment 3, contact trenches 3a and 3b that terminate inside the polysilicon layer 3 may be formed instead of contact trenches 21a and 21b. In this case, p +Instead of type region 22, p + Formation regions 6a and 6b are created. In addition, the cross-sectional shapes of the contact trenches 3a and 3b may be approximately rectangular. The contact trench 47 of the main semiconductor element has approximately the same cross-sectional shape as the contact trenches 3a and 3b of the polysilicon layer 3.

[0107] As described above, according to Embodiment 3, similar to Embodiments 1 and 2, the contact trench for the diode and the contact trench for the main semiconductor element can be formed simultaneously.

[0108] (Embodiment 4) The structure of the semiconductor device according to Embodiment 4 will now be described. Figure 15 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 4. The difference between the semiconductor device 60 according to Embodiment 4 and the semiconductor device according to Embodiment 3 (see Figure 10) is that in the diode region 30, a diode 71 is embedded inside the semiconductor substrate 1 so as to be electrically insulated from the main semiconductor element (semiconductor substrate 1) of the active region 40. The configuration of the active region 40 is the same as in Embodiment 3.

[0109] Specifically, in Embodiment 4, a recess (hereinafter referred to as the recess region (first recess)) 61 of a predetermined depth is provided on the front surface of the semiconductor substrate 1 in the diode region 30. A field oxide film (insulating film) 62 is provided along the inner wall of the recess region 61. Inside the recess region 61, a diode 71 is provided on the field oxide film 62. The diode 71 is a polysilicon diode formed by creating a pn junction between a p-type anode region 64 and an n-type cathode region 65 inside a polysilicon layer 63.

[0110] Contact trenches 63a and 63b are provided that penetrate the polysilicon layer 63 (p-type anode region 64 and n-type cathode region 65) in the depth direction and reach the field oxide film 62. The contact trenches 63a and 63b may terminate inside the field oxide film 62. Between the side wall of the contact trench 63a and the p-type anode region 64, p + A type region (first high-concentration region of the first conductivity type) 66 (hatched portion) is provided. The side walls of the contact trenches 63a and 63b are respectively p + The n-type region 66 and the n-type cathode region 65 are exposed.

[0111] The thickness T13 of the field oxide film 62 remaining between the bottoms of the contact trenches 63a and 63b and the bottom of the recess region 61 should be thick enough to electrically insulate the polysilicon layer 63 from the semiconductor substrate 1, and the depths of the contact trenches 63a and 63b and the recess region 61 can be set as appropriate. The thickness T14 of the field oxide film 62 existing between the polysilicon layer 63 and the p-type region 72 on the sidewall of the recess region 61 should be thick enough to electrically insulate the polysilicon layer 63 from the semiconductor substrate 1, and the width of the recess region 61 can be set as appropriate.

[0112] The interlayer insulating film 67 is provided with a uniform thickness over the entire surface of the front surface of the semiconductor substrate 1, covering the polysilicon layer 63 and the gate electrode 46. Because the polysilicon layer 63 (diode 71) is located inside the recess region 61, the upper surface of the polysilicon layer 63 (the interface between the polysilicon layer 63 and the interlayer insulating film 67) is at approximately the same height as the front surface of the semiconductor substrate 1 (the interface between the semiconductor substrate 1 and the interlayer insulating film 67). That is, the upper surface of the interlayer insulating film 67 is substantially flat over its entire surface. The configuration of the contact hole 67c is the same as that of the contact hole 7c in Embodiment 3.

[0113] Therefore, the height T11 from the front surface of the semiconductor substrate 1 to the upper surface of the interlayer insulating film 67 in the diode region 30 is approximately the same as the height T12 from the front surface of the semiconductor substrate 1 to the upper surface of the interlayer insulating film 67 in the active region 40. In the diode region 30, the interlayer insulating film 67 is provided with contact holes 67a and 67b that penetrate the interlayer insulating film 67 in the depth direction. Contact trenches 63a and 63b of the polysilicon layer 63 (diode 71) are exposed in the contact holes 67a and 67b, respectively.

[0114] Polysilicon layer 63, p-type anode region 64, n-type cathode region 65, contact trenches 63a, 63b, p + The configuration of the type region 66, contact holes 67a, 67b, anode electrode 68 and cathode electrode 69 is the same as that of Embodiment 3, except that the polysilicon layer 63 (diode 71) is located inside the recess region 61, and consists of the polysilicon layer 3, p-type anode region 4, n-type cathode region 5, contact trenches 21a, 21b, p + The same applies to the mold region 22, contact holes 7a and 7b, anode electrode 8, and cathode electrode 9.

[0115] Recess area 61 and n - A p-type region 72 is provided between the active region 40 and the IGBT drift region 41, separated from the trench gate structure of the IGBT and the breakdown voltage structure of the edge termination region (not shown). The p-type region 72 surrounds the recess region 61 and is exposed on the inner wall of the recess region 61. The p-type region 72 has the function of making the electric field on the front side of the semiconductor substrate 1 in the diode region 30 uniform.

[0116] The thickness of the portion of the p-type region 72 along the side wall of the recess region 61 (thickness in the direction perpendicular to the side wall of the recess region 61) and the thickness of the portion of the p-type region 72 along the bottom of the recess region 61 (thickness in the direction perpendicular to the bottom of the recess region 61) may be different. The depth of the p-type region 72 (depth from the front surface of the semiconductor substrate 1) is approximately the same as the depth of the p-type region constituting the breakdown structure of the edge termination region (not shown).

[0117] For example, if the depth of the p-type region 72 is made shallower, the breakdown voltage of the semiconductor device 60 decreases. However, in Embodiment 4, without changing the depth of the p-type region 72, the diode 71 can be placed inside the semiconductor substrate 1 (inside the recess region 61) facing the p-type region 72 in the depth direction. Although not particularly limited, for example, the depth of the recess region 61 is about 1.5 μm, and the depth of the p-type region 72 (depth from the front surface of the semiconductor substrate 1) is about 8 μm.

[0118] Next, a method for manufacturing the semiconductor device 60 according to Embodiment 4 will be described. Figures 16 to 23 are cross-sectional views showing the semiconductor device according to Embodiment 4 in the process of manufacturing. First, as shown in Figure 16, etching is performed on the diode region 30. - A recess region 61 is formed on the front surface of the semiconductor substrate 1. Next, as shown in Figure 17, a p-type region 72 is formed along the inner wall of the recess region 61 by ion implantation of p-type impurities on the surface area of ​​the inner wall (side wall and bottom) of the recess region 61.

[0119] Next, as shown in Figure 18, a p-type base region 42, a gate trench 44, a gate insulating film 45, and a gate electrode 46 are formed, similar to Embodiment 3. The recess region 61 and the gate trench 44 may be formed simultaneously. Next, as shown in Figure 19, a field oxide film 62 is formed along the front surface of the semiconductor substrate 1 and the inner wall of the recess region 61, for example by chemical vapor deposition (CVD). The field oxide film 62 may be, for example, a high-temperature oxide (HTO) film.

[0120] The field oxide film 62 is formed with a uniform thickness along the front surface of the semiconductor substrate 1 and the inner wall of the recess region 61. At this time, the field oxide film 62 is formed such that a recess (second recess) 62a remains on the field oxide film 62 inside the recess region 61. The recess 62a has predetermined dimensions (width and depth) that allow the diode 71 to be placed. In addition, the thickness T21 of the field oxide film 62 on the bottom of the recess region 61 is ensured so that a predetermined thickness T13 (see Figure 15) of the field oxide film 62 remains between the bottom of the contact trenches 63a and 63b formed in a later process and the bottom of the recess region 61.

[0121] The field oxide film 62 has approximately the same thickness in all areas: the front surface of the semiconductor substrate 1, the sidewall portion of the recess region 61, and the bottom portion of the recess region 61. Therefore, the dimensions of the recess region 61 can be appropriately set so that a recess 62a of a predetermined size remains on the field oxide film 62 inside the recess region 61, and the field oxide film 62 has a predetermined thickness T21 in the bottom portion of the recess region 61. In Figures 16 to 23, the recess region 61 is illustrated with a different aspect ratio than in Figure 15, and the thicknesses T14 and T21 of the field oxide film 62 in the sidewall portion and the bottom portion of the recess region 61 are the same.

[0122] Next, as shown in Figure 20, a polysilicon layer 63 is deposited on the field oxide film 62 to completely fill the recess 62a remaining on the field oxide film 62 inside the recess region 61 with the polysilicon layer 63. Then, the polysilicon layer 63 and the field oxide film 62 are etched back, leaving them only inside the recess region 61. Next, as shown in Figure 21, a diode 71 (p-type anode region 64 and n-type cathode region 65) is formed on the polysilicon layer 63. The method for forming the p-type anode region 64 and n-type cathode region 65 is the same as that of the p-type anode region 4 and n-type cathode region 5 in Embodiment 3, respectively. Also, similar to Embodiment 3, the active region 40 is n + A type emitter region 43 is formed.

[0123] Next, as shown in Figure 22, an interlayer insulating film 67 is formed over the entire surface of the front surface of the semiconductor substrate 1, covering the diode 71 and the gate electrode 46 with the interlayer insulating film 67. Next, contact holes 67a, 67b, and 67c are formed in the interlayer insulating film 67, similar to the contact holes 7a, 7b, and 7c in Embodiment 3. Next, contact trenches 63a and 63b are formed in the polysilicon layer 63, similar to the contact trenches 21a and 21b in Embodiment 3. A contact trench 47 is formed, similar to Embodiment 3.

[0124] Next, as shown in Figure 23, the p of Embodiment 3 + Similar to the p-type region 22, the p-type anode region 64 is p + Forms a type region 66. Similar to Embodiment 3, p + A type emitter contact region 48 is formed. Next, an anode electrode 68 and a cathode electrode 69 are formed in the same manner as the anode electrode 8 and cathode electrode 9 of Embodiment 3, and the emitter electrode 49, n + Type buffer area 51, p + By forming the collector region 52 and the collector electrode 53, the semiconductor device 60 shown in Figure 15 is completed.

[0125] Another example of a method for manufacturing the semiconductor device 60 according to Embodiment 4 will be described. Figures 24 to 26 are cross-sectional views showing another example of the semiconductor device during manufacturing according to Embodiment 4. First, as described above, the recess region 61, p-type region 72, p-type base region 42, gate trench 44, gate insulating film 45, and gate electrode 46 are formed (see Figures 16 to 18). Next, as shown in Figure 24, a field oxide film 62 is formed inside the recess region 61, completely filling the recess region 61 with the field oxide film 62.

[0126] For example, by making the field oxide film 62 a LOCOS film (local oxide film), the field oxide film 62 can be formed locally only inside the recess region 61. In this case, since the inner wall of the recess region 61 is oxidized to form a LOCOS film, the dimensions (width and depth) of the recess region 61 become larger than before the formation of the field oxide film 62. Alternatively, the field oxide film 62 may be formed on the front surface of the semiconductor substrate 1 so as to completely fill the recess region 61, and then the field oxide film 62 on the front surface of the semiconductor substrate 1 may be etched back.

[0127] Next, as shown in Figure 25, etching is used to form a recess (second recess) 62b of predetermined dimensions (width and depth) on the surface of the field oxide film 62, where the diode 71 can be placed. Then, as shown in Figure 26, the recess 62b on the surface of the field oxide film 62 is completely filled with a polysilicon layer 63. Then, the diode 71 is formed in the polysilicon layer 63 as described above. Also, as described above, n is formed in the active region 40. + A type emitter region 43 is formed. Then, as described above, the steps from the formation of the interlayer insulating film 67 onward are carried out in order to complete the semiconductor device 60 shown in Figure 15.

[0128] Thus, in this alternative example of the method for manufacturing the semiconductor device 60 according to Embodiment 4, since the recess 62b for arranging the diode 71 is actively formed on the surface of the field oxide film 62, the dimensions of the recess region 61, the thickness of the field oxide film 62, and the dimensions of the recess 62b are independent of each other. For this reason, the thickness T14 of the field oxide film 62 on the side wall of the recess region 61 and the thickness T22 of the field oxide film 62 on the bottom of the recess region 61 may be different, and the dimensions of the recess region 61, the thickness of the field oxide film 62, and the dimensions of the recess 62b can be appropriately set according to the insulating properties of the field oxide film 62, the chip size, etc.

[0129] The semiconductor device 60 according to Embodiment 4 may be modified by applying Embodiment 1 (see Figure 1) to form a contact trench that terminates inside the polysilicon layer 63 instead of the contact holes 67a and 67b. In this case, p + Instead of the mold region 66, p is placed at the bottom of the contact trench of the polysilicon layer 63, similar to Embodiment 1. + A mold region is formed. In addition, the cross-sectional shape of the contact trench of the polysilicon layer 63 and the contact trench 47 of the main semiconductor element may be substantially rectangular.

[0130] As described above, Embodiment 4 provides the same effects as Embodiments 1 to 3.

[0131] Furthermore, when a polysilicon layer (diode) is placed on the front surface of a semiconductor substrate via a field oxide film, increasing the thickness of the field oxide film and polysilicon layer increases the step difference on the upper surface of the interlayer insulating film at the boundary between the active region and the diode region. This can make it difficult to form fine device structure patterns (such as contact trenches and contact holes) of the main semiconductor device, and may cause contact holes in the diode region to collapse during patterning of the front surface electrodes (anode electrode, cathode electrode, emitter electrode).

[0132] Furthermore, when a polysilicon layer (diode) is placed on the surface of a semiconductor substrate via a field oxide film, increasing the depth of the contact trench in the polysilicon layer may cause the contact trench to penetrate the field oxide film and reach the semiconductor substrate, or the thickness of the field oxide film to become too thin directly below the bottom of the contact trench. In this case, static electricity or voltage applied to the main semiconductor element may cause dielectric breakdown of the field oxide film, leading to a short circuit between the diode and the semiconductor substrate, and causing it to cease functioning as a temperature sensor.

[0133] On the other hand, according to Embodiment 4, by arranging the polysilicon layer (diode) inside the recess (recess region) on the front surface of the semiconductor substrate, no step is created on the upper surface of the interlayer insulating film. This prevents pattern defects in the main semiconductor element and wiring defects in the diode. Furthermore, by appropriately increasing the depth of the recess region, the thickness of the field oxide film can be appropriately increased. As a result, even if the depth of the contact trench in the polysilicon layer is increased, a predetermined dielectric strength can be ensured.

[0134] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. Furthermore, the same effects as the present invention are obtained when manufacturing individual diodes of the embodiments described above, and such individual diodes can be manufactured at low cost. The invention is also applicable when the main semiconductor element is a MOSFET instead of an IGBT. Moreover, even when the main semiconductor element is a planar gate structure instead of a trench gate structure, the same effects as the present invention are obtained as long as the main semiconductor element has a contact trench. Furthermore, although the first conductivity type is p-type and the second conductivity type is n-type in each embodiment, the present invention is similarly valid even if the first conductivity type is n-type and the second conductivity type is p-type. [Industrial applicability]

[0135] As described above, the semiconductor device and method for manufacturing a semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for semiconductor devices in which a diode serving as a temperature sensor is arranged on the same semiconductor substrate as the main semiconductor element. [Explanation of Symbols]

[0136] 1. Semiconductor substrate 2,62 Field oxide film 3.63 Polysilicon layer 3a, 3b, 21a, 21b, 47, 63a, 63b Contact Trench 4.64 p-type anode region 5,65 n-type cathode region 6a,6b,22,66 p + type area 7,67 Interlayer insulating film 7a, 7b, 7c, 67a, 67b, 67c Contact Holes 8,68 Anode electrode 9.69 Cathode electrode 10, 20, 50, 60 Semiconductor equipment 11.71 diodes 12 Resist Mask 12a, 12b Openings in the resist mask 30 Diode region 31,72 p-type region of the diode region 40 active area 41 n - Type drift region 42 p-type base region 43 n + Type emitter region 44 Gate Trench 45 Gate insulating film 46 Terminal 48 pages + Type emitter contact area 49. Emitter electrode 51 n-type buffer area 52 p + Type collector area 53 Collector electrode 61 Recess Area 62a Recesses remaining on the field oxide film within the recess region 62b Recesses formed on the surface of the field oxide film within the recess region T1, T11: Height from the top surface of the semiconductor substrate to the top surface of the interlayer insulating film in the diode region. T2, T12 Height from the top surface of the semiconductor substrate to the top surface of the interlayer insulating film in the active region Thickness of the field oxide film remaining between the bottom of the T3 contact trench and the semiconductor substrate Thickness of the field oxide film remaining between the bottom of the T13 contact trench and the bottom of the recess area. Thickness of the field oxide film on the sidewall of the T14 recess region Thickness of the field oxide film on the bottom of the T21, T22 recess regions

Claims

1. A polysilicon layer is provided on the front surface of a semiconductor substrate via an insulating film, A first conductivity type region provided in the polysilicon layer, A second conductivity type region is provided in the polysilicon layer and is adjacent to the first conductivity type region in a direction parallel to the front surface of the semiconductor substrate, A diode formed by a pn junction between the first conductivity type region and the second conductivity type region, An interlayer insulating film is provided on the front surface of the semiconductor substrate and covers the polysilicon layer, A first contact hole that penetrates the interlayer insulating film in the depth direction, A second contact hole that penetrates the interlayer insulating film in the depth direction, A first contact trench is provided in the polysilicon layer, connected to the first contact hole in the depth direction, and surrounded by the first conductive region. A second contact trench is provided in the polysilicon layer, connected to the second contact hole in the depth direction, and surrounded by the second conductive region. A first high-concentration region of the first conductivity type, having a higher impurity concentration than the first conductivity type region, is selectively provided inside the polysilicon layer, is in contact with the first conductivity type region, and is exposed to the bottom or side wall of the first contact trench, or both. A first electrode embedded in the first contact hole and the first contact trench and in contact with the first high-concentration region of the first conductivity type, A second electrode embedded in the second contact hole and the second contact trench and in contact with the second conductivity region, Equipped with, The first contact trench terminates inside the first conductivity type region, The second contact trench terminates within the second conductivity type region, The first high-concentration region of the first conductivity type is exposed at least at the bottom of the first contact trench, A semiconductor device further comprising a second high-concentration region of a first conductivity type, which has a higher impurity concentration than the first conductivity type region, and is selectively provided inside the polysilicon layer, is in contact with the second conductivity type region, and is exposed only at the bottom of the second contact trench.

2. A polysilicon layer provided on the front surface of a semiconductor substrate via an insulating film, A first conductivity type region provided in the polysilicon layer, A second conductivity type region is provided in the polysilicon layer and is adjacent to the first conductivity type region in a direction parallel to the front surface of the semiconductor substrate, A diode formed by a pn junction between the first conductivity type region and the second conductivity type region, An interlayer insulating film is provided on the front surface of the semiconductor substrate and covers the polysilicon layer, A first contact hole that penetrates the interlayer insulating film in the depth direction, A second contact hole that penetrates the interlayer insulating film in the depth direction, A first contact trench is provided in the polysilicon layer, connected to the first contact hole in the depth direction, and surrounded by the first conductive region. A second contact trench is provided in the polysilicon layer, connected to the second contact hole in the depth direction, and surrounded by the second conductive region. A first high-concentration region of the first conductivity type, having a higher impurity concentration than the first conductivity type region, is selectively provided inside the polysilicon layer, is in contact with the first conductivity type region, and is exposed to the bottom or side wall of the first contact trench, or both. A first electrode embedded in the first contact hole and the first contact trench and in contact with the first high-concentration region of the first conductivity type, A second electrode embedded in the second contact hole and the second contact trench and in contact with the second conductivity region, Equipped with, The first contact trench penetrates the first conductivity type region in the depth direction and reaches the insulating film. The second contact trench penetrates the second conductivity type region in the depth direction and reaches the insulating film. The semiconductor device is characterized in that the first high-concentration region of the first conductivity type is exposed on the side wall of the first contact trench.

3. The first contact trench penetrates the first conductivity type region in the depth direction and reaches the insulating film. The second contact trench penetrates the second conductivity type region in the depth direction and reaches the insulating film. The semiconductor device according to claim 1, characterized in that the first high-concentration region of the first conductivity type is exposed on the side wall of the first contact trench.

4. The first contact trench terminates inside the insulating film, The semiconductor device according to claim 2 or 3, characterized in that the second contact trench is terminated inside the insulating film.

5. A semiconductor element having a predetermined element structure is provided on the front side of the semiconductor substrate, The semiconductor device according to claim 1 or 2, further comprising: a diode provided separately from the semiconductor element and electrically insulated from the semiconductor element by the insulating film.

6. The aforementioned semiconductor device is A first semiconductor region of a first conductivity type is provided on the surface region of the front surface of the semiconductor substrate and is covered by the interlayer insulating film, A second semiconductor region of a second conductivity type is provided between the back surface of the semiconductor substrate and the first semiconductor region, The device structure includes a pn junction between the first semiconductor region and the second semiconductor region, A third contact hole that penetrates the interlayer insulating film in the depth direction, A third contact trench is provided in the semiconductor substrate and connected to the third contact hole, and is surrounded by the first semiconductor region. Between the third contact trench and the first semiconductor region, a third first conductivity type high-concentration region is provided in contact with the first semiconductor region and exposed at least at the bottom of the third contact trench, having a higher impurity concentration than the first semiconductor region. A third electrode embedded in the third contact hole and the third contact trench and in contact with the third first conductivity type high concentration region, The semiconductor device according to claim 5, further comprising a fourth electrode provided on the back surface of the semiconductor substrate.

7. The depth of the first contact hole from the interface between the polysilicon layer and the interlayer insulating film is the same as the depth of the third contact hole from the interface between the semiconductor substrate and the interlayer insulating film. The semiconductor device according to claim 6, characterized in that the depth of the second contact hole from the interface between the polysilicon layer and the interlayer insulating film is the same as the depth of the third contact hole from the interface between the semiconductor substrate and the interlayer insulating film.

8. The semiconductor device according to claim 5, characterized in that the diode is a temperature sensor for detecting the temperature of the semiconductor element.

9. A polysilicon layer provided on the front surface of a semiconductor substrate via an insulating film, A first conductivity type region provided in the polysilicon layer, A second conductivity type region is provided in the polysilicon layer and is adjacent to the first conductivity type region in a direction parallel to the front surface of the semiconductor substrate, A diode formed by a pn junction between the first conductivity type region and the second conductivity type region, An interlayer insulating film is provided on the front surface of the semiconductor substrate and covers the polysilicon layer, A first contact hole that penetrates the interlayer insulating film in the depth direction, A second contact hole that penetrates the interlayer insulating film in the depth direction, A first contact trench is provided in the polysilicon layer, connected to the first contact hole in the depth direction, and surrounded by the first conductive region. A second contact trench is provided in the polysilicon layer, connected to the second contact hole in the depth direction, and surrounded by the second conductive region. A first high-concentration region of the first conductivity type, having a higher impurity concentration than the first conductivity type region, is selectively provided inside the polysilicon layer, is in contact with the first conductivity type region, and is exposed to the bottom or side wall of the first contact trench, or both. A first electrode embedded in the first contact hole and the first contact trench and in contact with the first high-concentration region of the first conductivity type, A second electrode embedded in the second contact hole and the second contact trench and in contact with the second conductivity region, A semiconductor element having a predetermined element structure is provided on the front side of the semiconductor substrate, The diode is provided separately from the semiconductor element and is electrically insulated from the semiconductor element by the insulating film, Equipped with, The aforementioned semiconductor device is A first semiconductor region of a first conductivity type is provided on the surface region of the front surface of the semiconductor substrate and is covered by the interlayer insulating film, A second semiconductor region of a second conductivity type is provided between the back surface of the semiconductor substrate and the first semiconductor region, The device structure includes a pn junction between the first semiconductor region and the second semiconductor region, A third contact hole that penetrates the interlayer insulating film in the depth direction, A third contact trench is provided in the semiconductor substrate and connected to the third contact hole, and is surrounded by the first semiconductor region. Between the third contact trench and the first semiconductor region, a third first conductivity type high-concentration region is provided in contact with the first semiconductor region and exposed at least at the bottom of the third contact trench, having a higher impurity concentration than the first semiconductor region. A third electrode embedded in the third contact hole and the third contact trench and in contact with the third first conductivity type high concentration region, The semiconductor substrate has a fourth electrode provided on its back surface, The depth of the first contact hole from the interface between the polysilicon layer and the interlayer insulating film is the same as the depth of the third contact hole from the interface between the semiconductor substrate and the interlayer insulating film. A semiconductor device characterized in that the depth of the second contact hole from the interface between the polysilicon layer and the interlayer insulating film is the same as the depth of the third contact hole from the interface between the semiconductor substrate and the interlayer insulating film.

10. The semiconductor substrate further comprises a first recess provided on the front surface, The insulating film is provided along the inner wall of the first recess, The semiconductor device according to any one of claims 1, 2, or 9, characterized in that the polysilicon layer is provided on the insulating film inside the first recess.

11. A method for manufacturing a semiconductor device comprising a diode formed by a pn junction between a first conductivity type region and a second conductivity type region, A first step involves forming a polysilicon layer on the front surface of a semiconductor substrate via an insulating film, A second step involves forming a first conductivity type region and a second conductivity type region adjacent to each other in the polysilicon layer in a direction parallel to the front surface of the semiconductor substrate, A third step involves forming an interlayer insulating film on the front surface of the semiconductor substrate and covering the polysilicon layer with the interlayer insulating film. A fourth step involves forming a resist mask with openings at predetermined locations on the interlayer insulating film, A fifth step involves etching the interlayer insulating film using the resist mask to form a first contact hole that penetrates the interlayer insulating film in the depth direction, reaches the polysilicon layer, and exposes a first conductivity type region, and a second contact hole that penetrates the interlayer insulating film in the depth direction, reaches the polysilicon layer, and exposes a second conductivity type region. A sixth step involves etching the polysilicon layer using the resist mask to form a first contact trench connected to the first contact hole in the depth direction in the first conductivity region, and a second contact trench connected to the second contact hole in the depth direction in the second conductivity region. A seventh step involves ion implanting a first conductivity type impurity using the resist mask to form a first high-concentration first conductivity type region with a higher impurity concentration than the first conductivity type region in the portion of the first conductivity type region exposed to the first contact trench, The eighth step is to remove the resist mask, A ninth step of forming a first electrode embedded in the first contact hole and the first contact trench and in contact with the first high-concentration region of the first conductivity type, and a second electrode embedded in the second contact hole and the second contact trench and in contact with the second conductivity type region, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

12. The first step is, The process of forming a first recess of a predetermined depth on the front surface of the semiconductor substrate, The process involves forming the insulating film along the inner wall of the first recess, leaving a second recess on the surface of the insulating film inside the first recess, The method for manufacturing a semiconductor device according to claim 11, comprising the step of filling the second recess with the polysilicon layer.

13. The first step is, The process of forming a first recess of a predetermined depth on the front surface of the semiconductor substrate, The steps include filling the first recess with the insulating film, A step of forming a second recess on the surface of the insulating film, The method for manufacturing a semiconductor device according to claim 11, comprising the step of filling the second recess with the polysilicon layer.

14. A method for manufacturing a semiconductor device comprising a semiconductor element and a diode on the semiconductor substrate, The aforementioned semiconductor device is A first semiconductor region of a first conductivity type is provided on the surface region of the front surface of the semiconductor substrate and is covered by the interlayer insulating film, A second semiconductor region of a second conductivity type is provided between the back surface of the semiconductor substrate and the first semiconductor region, A device structure including a pn junction between the first semiconductor region and the second semiconductor region, A third contact hole that penetrates the interlayer insulating film in the depth direction, A third contact trench is provided in the semiconductor substrate and connected to the third contact hole, and is surrounded by the first semiconductor region. Between the third contact trench and the first semiconductor region, a third first conductivity type high-concentration region is provided in contact with the first semiconductor region and exposed at least at the bottom of the third contact trench, having a higher impurity concentration than the first semiconductor region. A third electrode embedded in the third contact hole and the third contact trench and in contact with the third first conductivity type high concentration region, The semiconductor substrate has a fourth electrode provided on its back surface, The diode is provided separately from the semiconductor element and is electrically insulated from the semiconductor element by the insulating film. In the fifth step, the first contact hole, the second contact hole, and the third contact hole are formed simultaneously. In the sixth step, the first contact trench, the second contact trench, and the third contact trench are formed simultaneously. The method for manufacturing a semiconductor device according to claim 11, characterized in that the seventh step simultaneously forms the first high-concentration region of the first conductivity type and the third high-concentration region of the first conductivity type.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that the diode is a temperature sensor for detecting the temperature of the semiconductor element.

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