Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device that has a high surge current resistance while maintaining low Vf characteristics by forming a low-resistance ohmic electrode, and to provide a method of manufacturing the same.SOLUTION: A silicon carbide semiconductor device comprises an active region 10, a first-conductivity-type region 12, and a termination region 20. The active region 10 has a first second-conductivity-type region 13, a silicide film 33, and a first electrode 14. The termination region 20 has a second second-conductivity-type region 21. The active region 10 is composed of: an ohmic region where the first electrode 14 is in contact with the silicide film 33; an ineffective region where the first electrode 14 is in contact with the first second-conductivity-type region 13; and a Schottky region where the first electrode 14 is in contact with the first-conductivity-type region 12. The ohmic region, the ineffective region, and the Schottky region are provided in a stripe pattern. A bottom face of the silicide film 33 is provided at a position deeper than an interface between the first electrode 14 and the first second-conductivity-type region 13.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) semiconductors have recently attracted attention as a semiconductor material capable of fabricating semiconductor devices that exceed the limitations of silicon (Si) semiconductors (hereinafter referred to as silicon carbide semiconductor devices). In particular, silicon carbide semiconductors are expected to be applied to high-voltage (e.g., 1700V or more) semiconductor devices, taking advantage of their characteristics of having a higher dielectric breakdown field strength and higher thermal conductivity compared to silicon semiconductors.

[0003] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), n - n constitutes the drift region of type - Because the design specifications for the type epitaxial layer can be set to a thin thickness and a high impurity concentration, silicon carbide diodes up to about 3300V class generally use a Schottky barrier diode (SBD) structure.

[0004] Typically, SBD structures suffer from problems such as increased reverse leakage current due to high electric field strength at the junction between the semiconductor substrate and the front electrode, which causes electrons to tunnel through the Schottky barrier when a reverse voltage is applied, or increased reverse leakage current due to surface defects inherent to silicon carbide. For this reason, silicon carbide diodes employing a Junction Barrier Schottky (JBS) structure, in which Schottky junctions and pn junctions are mixed on the front side of the semiconductor substrate, have been proposed.

[0005] This section describes the structure of a silicon carbide diode employing a JBS structure, in contrast to the structure of a conventional SBD structure silicon carbide diode. Figure 27 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0006] The conventional silicon carbide semiconductor device 140 shown in FIG. 27 has an SBD structure formed by a Schottky junction between an n - -type drift region 112 and a titanium film 131 constituting a front surface electrode 114 on the front surface side of a semiconductor substrate 130 in an active region 110, and a JBS structure formed by a pn junction between a p + -type region 113 and the n - -type drift region 112, and is a vertical silicon carbide diode in which these are mixed. Further, a nickel silicide film 133 is provided on the p + -type region 113 as the lowermost layer of the front surface electrode 114.

[0007] The Schottky junction of the conventional silicon carbide semiconductor device 140 is formed by an n - -type drift region 112 exposed on the front surface of the semiconductor substrate 130 and a front surface electrode 114 composed of a titanium film 131 and an aluminum alloy film 132 provided on the front surface of the semiconductor substrate 130. The semiconductor substrate 130 is an epitaxial substrate in which an n + -type starting substrate 111, an n - -type drift region 112 serving as an n - -type epitaxial layer is laminated on the front surface of the n[[ID=A]] + -type starting substrate 111 is an n + -type cathode region. A back surface electrode 119 is provided on the entire back surface of the semiconductor substrate 130 and is electrically connected to the n + -type starting substrate 111. Reference numerals 115, 120, 121, and 122 denote a field oxide film, an edge termination region, a field limiting ring (FLR), and a p - -type region constituting a JTE structure, respectively.

[0008] The p + -type region 113 is selectively provided in the surface region of the front surface of the semiconductor substrate 130 in the active region 110. The n + -type drift region 112 is exposed on the front surface of the semiconductor substrate 130 between adjacent p - -type regions 113. The p + -type region 113 and the n- A pn junction is formed on the front surface of the semiconductor substrate 130 with the type drift region 112. + n between type regions 113 - The drift region 112 forms a Schottky junction with the bottom layer titanium film 131 of the front surface electrode 114, which is provided on the front surface of the semiconductor substrate 130.

[0009] With this structure, when the rated current flows in the forward direction, p + n other than type region 113 - Current flows in the Schottky junction region of the drift region 112. Furthermore, when a surge current flows due to lightning strikes, etc., the Schottky junction region alone is insufficient to allow current to flow, so p + Type region 113 performs bipolar operation, and current flows. Also, p + By providing a nickel silicide film 133 that forms an ohmic region on the mold region 113, p + Bipolar operation becomes easier than with a stripe structure consisting only of type region 113.

[0010] Furthermore, in order to provide a highly reliable silicon carbide semiconductor device, a semiconductor device has been proposed in which the ohmic electrode has a first portion that protrudes from the front surface of the semiconductor substrate in a direction away from the front surface of the semiconductor substrate, and a second portion that protrudes in the depth direction from the front surface of the semiconductor substrate into the interior of the semiconductor substrate, with the second portion having a wider cross-sectional shape than the first portion (see, for example, Patent Document 1 below).

[0011] Furthermore, to suppress device failure during reverse biasing, a semiconductor device having a trench-type JBS with a p-type region at the bottom of a trench formed in the device region has been proposed (see, for example, Patent Document 2 below). [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Japanese Patent Publication No. 2021-197420 [Patent Document 2] Patent No. 6400544 [Overview of the Initiative] [Problems that the invention aims to solve]

[0013] However, p + When a surge current flows through type region 113, p + Due to the contact resistance of type region 113, p + In some cases, the bipolar operation of type region 113 may be delayed, causing the semiconductor element to overheat and be destroyed. Furthermore, in normal p + Apart from the stripe structure of type region 113, p + When a type region is established, n - The area of ​​the Schottky junction region in the drift region 112 decreases, the forward voltage Vf at the rated current increases, and the on-voltage becomes high. Thus, in order to ensure surge current withstand capability (IFSM), p + There is a trade-off in that increasing the area of ​​type region 113 increases Vf. Furthermore, in structures where ohmic regions on semiconductor devices such as dot structures are independent of each other, there is a resistance bias, which makes it easy to generate heat locally and makes it difficult to ensure surge withstand capability.

[0014] This invention aims to solve the problems of the prior art described above by forming low-resistance ohmic electrodes, thereby providing a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that maintains low Vf characteristics while having high surge current withstand capability. [Means for solving the problem]

[0015] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: An active region is provided on a semiconductor substrate made of silicon carbide. A termination region is provided on the semiconductor substrate surrounding the active region. A first conductivity type region is provided inside the semiconductor substrate, exposed on the first main surface of the semiconductor substrate. A first trench is provided in the active region from the front surface of the first conductivity type region into the interior of the first conductivity type region. A first second conductivity type region is provided in the active region, in contact with the first conductivity type region, at the bottom of the first trench. A silicide film is provided to ohmic-bond to the first second conductivity type region. A first electrode is provided that contacts the silicide film, the first second conductivity type region, and the first conductivity type region. A second electrode is provided on the second main surface of the semiconductor substrate. A second second conductivity type region is provided in the termination region, surrounding the active region. The active region comprises an ohmic region in which the first electrode is in contact with the silicide film, an inactive region in which the first electrode is in contact with the first second conductivity type region, and a Schottky region in which the first electrode is in contact with the first conductivity type region. The ohmic region, the inactive region, and the Schottky region are arranged in a stripe shape. The bottom surface of the silicide film is located deeper than the interface between the first electrode and the first second conductivity type region.

[0016] Furthermore, the silicon carbide semiconductor device according to this invention further comprises a second trench provided in the active region from the front surface of the first second conductivity type region into the interior of the first second conductivity type region, and the silicide film is provided on the bottom surface and side walls of the second trench.

[0017] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the front surface of the silicide film is provided at a position shallower than the interface between the first electrode and the first second conductivity type region.

[0018] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the width of the silicide film is narrower than the width of the first second conductivity type region, and the width of the inactive region is 0.1 μm or more and 1.0 μm or less.

[0019] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the area ratio of the ineffective region to the surface area of ​​the silicon carbide semiconductor device is 5% or more and 35% or less.

[0020] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the area ratio of the ineffective region to the surface area of ​​the first second conductivity region is 35% or more and 90% or less.

[0021] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the ratio of the area of ​​the inactive region to the surface area of ​​the active region is 15% or more and 40% or less.

[0022] Furthermore, the silicon carbide semiconductor device according to this invention further comprises, in the above-described invention, a third trench provided in the terminal region from the front surface of the first conductivity type region into the interior of the first conductivity type region, wherein the second conductivity type region is selectively provided inside the third trench in contact with the first conductivity type region and is in contact with the first electrode on the active region side.

[0023] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the width of the third trench is wider than the width of the first trench.

[0024] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first second conductivity type region and the second second conductivity type region are connected.

[0025] To solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to this invention has the following features. The method for manufacturing a silicon carbide semiconductor device comprises a semiconductor substrate made of silicon carbide, an active region, and a termination region surrounding the active region. First, a first step is performed to form a first conductivity type region forming a first main surface of the semiconductor substrate inside the semiconductor substrate. Next, a second step is performed to form a first trench in the active region from the front surface of the first conductivity type region into the interior of the first conductivity type region. Next, a third step is performed to form a first second conductivity type region at the bottom of the first trench in contact with the first conductivity type region in the active region. Next, a fourth step is performed to form a second second conductivity type region surrounding the active region in the termination region. Next, a fifth step is performed to form an oxide film covering the first conductivity type region and the first second conductivity type region on the first main surface of the semiconductor substrate. Next, a sixth step is performed to selectively remove the oxide film and form a first opening in the oxide film that exposes the first second conductivity type region. Next, a seventh step is performed to form a metal material film by sequentially laminating a first nickel film, an aluminum film, and a second nickel film that are in contact with the first main surface of the semiconductor substrate at the first opening in the oxide film. Next, an eighth step is performed to react the metal material film and the semiconductor substrate by a first heat treatment to generate a self-aligned compound layer on the first main surface of the semiconductor substrate at the first opening in the oxide film, using the oxide film as a mask. Next, after the eighth step, a ninth step is performed to remove the excess portion of the metal material film excluding the compound layer. Next, after the ninth step, a tenth step is performed to generate nickel silicide inside the compound layer by a second heat treatment at a higher temperature than the first heat treatment to form a silicide film that ohmic bonds to the semiconductor substrate. Next, after the 10th step, an 11th step is performed in which the oxide film sandwiched between the silicide films is removed to form a contact hole connecting all of the first openings. Next, a 12th step is performed in which a titanium film that contacts the first conductivity type region and forms a Schottky bond with the first conductivity type region, and a metal electrode film containing aluminum are sequentially laminated on the first main surface of the semiconductor substrate inside the contact hole to form a first electrode.Next, a 13th step is performed in which a second electrode is formed on the second main surface of the semiconductor substrate. In the 6th step, the width of the first opening is made narrower than the width of the first second conductivity type region, so that the active region is composed of an ohmic region in which the first electrode contacts the silicide film, an inactive region in which the first electrode contacts the first second conductivity type region, and a Schottky region in which the first electrode contacts the first conductivity type region. Furthermore, in the 6th step, the ohmic region, the inactive region, and the Schottky region are formed in a stripe shape. In the 10th step, the bottom surface of the silicide film is formed at a position deeper than the interface between the first electrode and the first second conductivity type region.

[0026] Furthermore, the silicon carbide semiconductor device manufacturing method according to the present invention further includes, in the above-described invention, a 14th step after the third step, in which a second trench is formed in the active region from the front surface of the first second conductivity type region into the interior of the first second conductivity type region, and in the 10th step, the silicide film is formed on the bottom surface and side walls of the second trench.

[0027] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the tenth step described above, the front surface of the silicide film is formed at a position shallower than the interface between the first electrode and the first second conductivity type region.

[0028] According to the invention described above, a fine ohmic stripe structure is provided within the JBS stripe structure, resulting in a two-stage trench structure. This increases the area of ​​the SBD structure composed of Schottky junctions, increases the on-voltage, and lowers Vf. Furthermore, the surface area of ​​the first nickel silicide film can be increased, and during surges, p + By facilitating current flow into the type region (the first second conductivity type region), surge current withstand capability (IFSM) can be ensured. Therefore, both surge current withstand capability and on-voltage characteristics can be improved. [Effects of the Invention]

[0029] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, by forming low-resistance ohmic electrodes, it is possible to achieve high surge current withstand capability while maintaining low Vf characteristics. [Brief explanation of the drawing]

[0030] [Figure 1] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 3] This is a cross-sectional view showing the detailed structure of region S enclosed by the dashed line in Figure 1. [Figure 4] This is a cross-sectional view showing the ohmic region, the inactive region, and the Schottky region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 5] This is a flowchart illustrating the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 7] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 8] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 9] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 10] This is a cross-sectional view (part 5) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 11] This is a cross-sectional view (part 6) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 12] This is a cross-sectional view (part 7) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 13] This is a cross-sectional view (part 8) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 14] This is a cross-sectional view (part 9) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 15] This is a cross-sectional view (part 10) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 16] This is a cross-sectional view (part 11) showing the state of the silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 17] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 18] Figure 17 is a cross-sectional view showing the detailed structure of region S enclosed by the dashed line. [Figure 19] This is a cross-sectional view showing the ohmic region, inactive region, and Schottky region of the silicon carbide semiconductor device according to Embodiment 2. [Figure 20] This is a cross-sectional view showing the detailed structure of the nickel silicide film in the silicon carbide semiconductor device according to Embodiment 2. [Figure 21] This is a cross-sectional view (part 1) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 2. [Figure 22] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 23] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 24] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 2 during the manufacturing process. [Figure 25] This is a cross-sectional view (part 5) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 26] This is a cross-sectional view (part 6) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of being manufactured. [Figure 27] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0031] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these prefixes. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In Miller index notation, "-" indicates a bar attached to the exponent immediately following it, and placing "-" before an exponent indicates a negative exponent.

[0032] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will be described. Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. In the silicon carbide semiconductor device 40 according to Embodiment 1 shown in Figures 1 and 2, the front side electrode (first electrode) 14 and n are located on the front side of the semiconductor substrate 30 in the active region 10. - The SBD structure is composed of a Schottky junction with a type drift region (first conductivity type region) 12, and p + Type region (first second conductivity type region) 13 and n - This silicon carbide diode is a JBS structure composed of a pn junction with a drift region 12, and a mixture of other structures.

[0033] n - Type drift region 12 and p + The type regions 13 are arranged substantially uniformly in a substantially uniform pattern within the plane of the active region 10. - Type drift region 12 and p +The mold regions 13 are arranged in a stripe pattern, for example, extending in the same direction parallel to the front surface of the semiconductor substrate 30, and are alternately and repeatedly arranged in contact with each other in the longitudinal direction extending in the stripe pattern and in the short direction perpendicular to it (see Figure 2). - The drift region 12 is adjacent to p + It is exposed on the front surface of the semiconductor substrate 30 between the mold regions 13.

[0034] The active region 10 is the region through which current flows when the silicon carbide diode is in the ON state. The active region 10 has, for example, a roughly rectangular planar shape and is located approximately in the center of the semiconductor substrate 30. The edge termination region 20 is the region between the active region 10 and the edge of the semiconductor substrate 30, and surrounds the active region 10. The edge termination region 20 is n - The drift region 12 is a region that relaxes the electric field on the front side of the semiconductor substrate 30 and maintains the breakdown voltage. Breakdown voltage is the limit voltage at which the element does not malfunction or break down.

[0035] A breakdown structure such as a Junction Termination Extension (JTE) structure is placed in the edge termination region 20. The JTE structure has multiple p-type regions with different impurity concentrations, such that the p-type regions with lower impurity concentrations are arranged from the inside (center side of the semiconductor substrate 30) to the outside (edge ​​side of the semiconductor substrate 30). - The mold region 22 is a pressure-resistant structure with a roughly rectangular planar shape that surrounds the active region 10.

[0036] Furthermore, a field limiting ring (FLR) 21 is positioned in the connecting region 20a of the edge termination region 20. The FLR 21 (second second conductivity region) surrounds the active region 10 in a roughly rectangular shape. + This is a type region (see Figure 2), and extends outward from the connecting region 20a of the edge termination region 20 to the p region described later. - It is in contact with type region 22. FLR21 is p + In the longitudinal direction in which the type region 13 extends in a stripe-like manner, p +It may be in contact with the type region 13. In Figure 2, only one FLR21 is provided, but it may also be a structure that double-encloses the periphery of the active region 10. FLR21 is p + The same impurity concentration as in type region 13 may be used.

[0037] The connecting region 20a of the edge termination region 20 is the region between the active region 10 and the field oxide film 15, which will be described later. It surrounds the active region 10 and connects the active region 10 to the breakdown structure portion of the edge termination region 20. The breakdown structure portion of the edge termination region 20 is the part of the edge termination region 20 from the inner edge of the field oxide film 15, which will be described later, to the edge of the semiconductor substrate (chip edge), and includes a JTE structure and n + A predetermined pressure-resistant structure, such as a channel stopper region (not shown), is provided.

[0038] The front surface electrode 14 is provided on the front surface of the semiconductor substrate 30 in the active region 10. The front surface electrode 14 is n - Type drift region 12 and p + Attached to type region 13, n - Type drift region 12 and p + It is electrically connected to the mold region 13. A passivation film (not shown) is provided on the front surface of the semiconductor substrate 30. The passivation film functions as a protective film that protects the element structure on the front side of the semiconductor substrate 30 and the front surface electrode 14.

[0039] The semiconductor substrate 30 is made of n + On the front surface of the mold starting substrate 11, n - n is in the drift region 12. - This is an epitaxial substrate with stacked type epitaxial layers. + The starting substrate 11 is n + This is a type cathode region. The semiconductor substrate 30 is n - Main surface (n) on the drift region 12 side - n is in the drift region 12. - With the surface of the type epitaxial layer as the front surface, + Main surface (n) on the mold starting substrate 11 side +The back surface of the mold starting substrate 11 is designated as the back surface.

[0040] In the active region 10, the surface region on the front side of the semiconductor substrate 30 contains one or more p that constitute the JBS structure. + Type region 13 is selectively provided. + The type region 13 is the front surface of the semiconductor substrate 30 and n - It is provided between the type drift region 12. + The mold region 13 is exposed on the front surface of the semiconductor substrate 30, and n - It is in contact with the drift region 12.

[0041] In the edge termination region 20, the surface region on the front side of the semiconductor substrate 30 has an FLR 21 and one or more p-type regions (here, one: p) that constitute the JTE structure. - Type region 22) and n + Each channel stopper region (not shown) is selectively provided. The FLR21 is provided throughout the entire connecting region 20a of the edge termination region 20, and extends outward from the connecting region 20a to p - It is in contact with type region 22. The area inside FLR21 is the active region 10.

[0042] p - The mold region 22 is located outside the FLR21, away from the connecting region 20a of the edge termination region 20, and is adjacent to the FLR21. + The type channel stopper region is p - Outside of type region 22, p - It is provided separately from the type region 22. + The channel stopper region is exposed at the edge (chip edge) of the semiconductor substrate 30.

[0043] FLR21, p - Type region 22 and n + The channel stopper region is located on the front surface of the semiconductor substrate 30 and n - It is provided between the type drift region 12. FLR21, p - Type region 22 and n +The channel stopper region is exposed on the front surface of the semiconductor substrate 30, and n - It touches the drift region 12. FLR21, p - Type region 22 and n + The depth of the channel stopper region is, for example, p + The depth may be the same as that of type domain 13.

[0044] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15. The field oxide film 15 may be a multilayer film in which a thermal oxide film and a deposited oxide film are sequentially stacked. The thermal oxide film can improve the adhesion between the semiconductor substrate 30 and the field oxide film 15. By including a deposited oxide film in the field oxide film 15, the field oxide film 15 can be formed in a shorter time than when the entire field oxide film 15 is a thermal oxide film.

[0045] The field oxide film 15 is provided with contact holes 15a that expose almost the entire surface of the front surface of the semiconductor substrate 30 in the active region 10. The side walls of the contact holes 15a of the field oxide film 15 (the inner surfaces of the field oxide film 15) are, for example, approximately perpendicular to the front surface of the semiconductor substrate 30. The contact holes 15a of the field oxide film 15 are provided throughout the entire area from the active region 10 to the connecting region 20a of the edge termination region 20.

[0046] In the contact hole 15a of the field oxide film 15, n in the active region 10 - Type drift region 12 and p + The mold region 13 and the inner portion of the FLR 21 in the edge termination region 20 are exposed. Inside the contact hole 15a of the field oxide film 15, a front surface electrode 14 that functions as an anode electrode is provided on the front surface of the semiconductor substrate 30, along the front surface of the semiconductor substrate 30.

[0047] The front surface electrode 14 has a laminated structure formed by laminating a titanium film 31 and an aluminum alloy film (a metal electrode film containing aluminum) 32 in this order. In addition, the front surface electrode 14 has a bottommost nickel silicide (NiSi) film 33 (33a, 33b) selectively provided between the front surface of the semiconductor substrate 30 and the titanium film 31. The nickel silicide film 33 contains aluminum. The nickel silicide film 33 may contain carbon (C). The front surface electrode 14 may extend outwardly over the field oxide film 15.

[0048] The titanium film 31 is provided on the entire front surface of the semiconductor substrate 30 inside the contact hole 15a and is in contact with the n - -type drift region 12. The joint portion of the titanium film 31 with the n - -type drift region 12 is a Schottky electrode that forms a Schottky junction with the n - -type drift region 12. The titanium film 31 may extend outwardly over the field oxide film 15 and may terminate, for example, at a position facing the FLR21 in the depth direction.

[0049] The aluminum alloy film 32 covers the entire surface of the titanium film 31, is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide film 33 via the titanium film 31. The aluminum alloy film 32 extends outwardly over the field oxide film 15 more than the titanium film 31 and may terminate, for example, at a position facing the p - -type region 22 in the depth direction. The aluminum alloy film 32 is, for example, an aluminum silicon (AlSi) film. Instead of the aluminum alloy film 32, an aluminum film may be provided.

[0050] The nickel silicide film 33 has a first nickel silicide film 33a provided between the p + -type region 13 and the titanium film 31 and a second nickel silicide film 33b provided between the FLR21 and the titanium film 31. The width w2b of the second nickel silicide film 33b is preferably wider than the width w2a of the first nickel silicide film. The first nickel silicide film 33a is p+ It is an ohmic electrode that makes an ohmic contact with the p-type region 13. The first nickel silicide film 33a has a function of increasing the amount of surge current (extraction amount) extracted from the semiconductor substrate 30 to the front surface electrode 14 when a surge voltage is applied and flowing in the forward direction, thereby improving the surge current withstand capacity.

[0051] As will be described later, the first nickel silicide film 33a is formed by reacting the surface region of the semiconductor substrate 30 with the metal material film 52 (see FIG. 12) deposited on the front surface of the semiconductor substrate 30 at the contact point between the p-type region 13 and the metal material film 52 by heat treatment. [[ID= / / ]]As will be described later, the first nickel silicide film 33a is formed by reacting the p-type region 13 with the metal material film 52 (see FIG. 12) deposited on the front surface of the semiconductor substrate 30 at the contact point between the p-type region 13 and the metal material film 52 by heat treatment. + It is formed by reacting the surface region of the semiconductor substrate 30 with the metal material film 52 at the contact point between the p-type region 13 and the metal material film 52 (see FIG. 12) deposited on the front surface of the semiconductor substrate 30 by heat treatment.

[0052] FIG. 3 is a cross-sectional view showing the detailed structure of the region S surrounded by the broken line in FIG. 1. As shown in FIG. 3, a fine ohmic stripe structure is provided in the JBS stripe structure, forming a two-stage trench structure. The first trench 25 is provided on the front surface of the semiconductor substrate 30, and a p-type region 13 is provided at the bottom of the first trench 25. For example, the width L1 of the first trench 25 is preferably 0.7 μm or more and 3 μm or less, and the depth D1 of the first trench 25 is preferably 100 nm or more and 1000 nm or less. + The inside of the first trench 25 is filled with the front surface electrode 14, and the side wall of the first trench 25 is in contact with the front surface electrode 14. Therefore, the area of the SBD structure formed by the Schottky junction between the front surface electrode 14 and the n-type drift region 12 increases, the on-voltage becomes high, and Vf can be reduced.

[0053] The second trench 26 is provided in the p-type region 13 at the bottom of the first trench 25, and the first nickel silicide film 33a is provided on the side wall and the bottom of the second trench. Therefore, the bottom surface (the surface on the n-type starting substrate 11 side) of the first nickel silicide film 33a is in contact with the front surface electrode 14 and the p-type region 13. - The inside of the first trench 25 is filled with the front surface electrode 14, and the side wall of the first trench 25 is in contact with the front surface electrode 14. As a result, the area of the SBD structure formed by the Schottky junction between the front surface electrode 14 and the n-type drift region 12 increases, the on-voltage becomes high, and Vf can be reduced.

[0054] 26 + The second trench 26 is provided in the p-type region 13 at the bottom of the first trench 25, and the first nickel silicide film 33a is provided on the side wall and the bottom of the second trench. 26 The side wall and the bottom of the second trench are provided with the first nickel silicide film 33a. Therefore, the bottom surface (the surface on the n-type starting substrate 11 side) of the first nickel silicide film 33a is in contact with the front surface electrode 14 and the p-type region 13. + The bottom surface (the surface on the n-type starting substrate 11 side) of the first nickel silicide film 33a is in contact with the front surface electrode 14 and the p-type region 13. +It is located deeper than the interface with the mold region 13. For example, the width L2 of the second trench 26 is preferably 0.5 μm or more and 2.8 μm or less, and the depth D2 of the second trench 26 is preferably 100 nm or more and 1000 nm or less.

[0055] By providing the first nickel silicide film 33a within the second trench 26, the surface area of ​​the first nickel silicide film 33a can be increased. Therefore, during a surge, p + Current flows more easily into the mold region 13, ensuring surge current withstand capability (IFSM). In this way, both surge current withstand capability and on-voltage characteristics can be improved in Embodiment 1.

[0056] Figure 4 is a cross-sectional view showing the ohmic region, inactive region, and Schottky region of the silicon carbide semiconductor device according to Embodiment 1. The active region 10 is where the titanium film 31 constitutes the JBS structure. + A striped inactive region 80 that contacts the mold region 13, a striped ohmic region 81 in which the titanium film 31 contacts the first nickel silicide film 33a, and the titanium film 31 is n - It consists of a type drift region 12 and a striped Schottky region 82 that is in contact with it. In this way, the active region 10 repeats a cycle consisting of four regions: an ohmic region 81, two inactive regions 80 surrounding the ohmic region 81, and the Schottky region 82. The striped shape is a long, narrow rectangle whose horizontal direction is shorter than its vertical direction, as shown in Figure 2.

[0057] By adopting this periodic structure, the ohmic regions 81 can be uniformly and densely arranged throughout the active region 10. Therefore, when a high surge current flows in the forward direction within the semiconductor substrate, the surge current can be dispersed, thereby improving the IFSM characteristics.

[0058] Furthermore, the area ratio of the inactive region 80 to the surface area of ​​the silicon carbide semiconductor device 40 is preferably 5% or more and 35% or less. +The area ratio of the inactive region 80 to the surface area of ​​the mold region 13 is preferably 35% to 90%. Furthermore, the area ratio of the inactive region 80 to the surface area of ​​the active region 10 is preferably 15% to 40%. By setting the area ratio within these ranges, it is possible to achieve both improved surge current withstand capability and low Vf characteristics.

[0059] Here, the area ratio of the inactive region 80 to the surface area of ​​the silicon carbide semiconductor device 40 is the surface area of ​​the inactive region 80 / the surface area of ​​the silicon carbide semiconductor device 40. The surface area of ​​the silicon carbide semiconductor device 40 is the sum of the surface area of ​​the active region 10 and the surface area of ​​the edge termination region 20. Inactive region 80, p + If the length in the depth direction of the type region 13 and the active region 10 is common and is denoted as w, then, as shown in Figure 4, when Schottky regions 82 and ohmic regions 81 are alternately provided one by one, the area of ​​the inactive region 80 is (2 × w₁₄) × w. Also, p + The ratio of the area of ​​the inactive region 80 to the surface area of ​​the type region 13 is the surface area of ​​the inactive region 80 / p + This is the surface area of ​​type region 13, and in the case of Figure 4, p + The surface area of ​​the type region 13 is w1 × w. Furthermore, the area ratio of the inactive region 80 to the surface area of ​​the active region 10 is the surface area of ​​the inactive region 80 / the surface area of ​​the active region 10. In the case of Figure 4, the surface area of ​​the active region 10 is (w1 + w5) × w. Note that the above is based on p + This is the calculation formula when the connection between type region 13 and FLR21 is at a right angle, and p + When the connection between mold region 13 and FLR21 is curved, this effect must be taken into consideration.

[0060] Also, as shown in Figure 1, p + The mold region 13 is connected to a guard ring (FLR21 in Figures 1 and 2) provided in the edge termination region 20. In other words, in the edge termination region 20, the ohmic region 81 and the invalid region 80 are connected to the edge termination region 20. Furthermore, if the guard ring is also provided with a second nickel silicide film 33b, the first nickel silicide film 33a of the ohmic region 81 is connected to the second nickel silicide film 33b.

[0061] In conventional configurations where dot-shaped ohmic electrodes are arranged, areas far from the ohmic electrodes and areas close to them occur near the outer periphery. However, in Embodiment 1, the ohmic electrodes are uniformly arranged even near the outer periphery. This allows surge currents to be distributed more uniformly when they flow, avoiding localized current concentration and thus improving IFSM characteristics. Furthermore, an inactive region 80 is always sandwiched between the ohmic region 81 and the Schottky region 82. This reduces leakage current because the inactive region 80 directs carriers into the ohmic region 81.

[0062] Furthermore, an inactive region 80 is provided around the ohmic region 81, and the ohmic regions 81 are not connected to each other in the active region 10. In other words, an inactive region 80 and a Schottky region 82 exist between adjacent first nickel silicide films 33a. Thus, in Embodiment 1, there are no wide ohmic regions that span multiple stripes of ohmic region 81. As a result, the area of ​​the ohmic region 81 does not increase, and the Vf characteristics can be maintained.

[0063] Such a structure can be formed, for example, by using nickel silicide produced by reacting a metal material film 52, in which nickel, aluminum, and nickel are deposited in this order, with the surface region of a semiconductor substrate 30 by heat treatment, as will be described later. The low-resistance first nickel silicide film 33a is formed by self-alignment, which involves removing the non-silicided portion (excluding the heating reaction layer) of the metal material film 52 by etching. By using a metal material film 52 in which nickel, aluminum, and nickel are deposited in this order, a low-resistance p-type ohmic electrode is formed. Furthermore, by forming it by self-alignment, the ohmic electrode is formed inside the JBS structure with a width of several μm, and the Vf characteristics can be maintained. In this way, a low-resistance ohmic region 81 can be formed without narrowing the area of ​​the Schottky region 82, so that the IFSM characteristics can be improved while maintaining the Vf characteristics.

[0064] Furthermore, the width w2a of the first nickel silicide film 33a is p + By making the width w1 of the mold region 13 narrower than the width w4 of the ineffective region 80 0.1 μm or more and 1.0 μm or less, a design margin can be taken to improve the alignment accuracy of the mask used when forming the first nickel silicide film 33a (the remainder of the oxide film 51 described later: see Figure 11). This allows the first nickel silicide film 33a to be formed in the depth direction p + It can be positioned with high positional accuracy opposite the mold region 13.

[0065] The second nickel silicide film 33b is an ohmic electrode that ohmic-bonds to the FLR 21. The second nickel silicide film 33b is provided on the sidewall and bottom of the third trench 27 provided in the FLR 21 in the connecting region 20a of the edge termination region 20. The second nickel silicide film 33b is separated from the field oxide film 15 at the sidewall of the field oxide film 15. Similar to the first nickel silicide film 33a, the second nickel silicide film 33b has the function of increasing the amount of surge current drawn out and improving the surge current withstand capability.

[0066] As shown in Figure 1, the side wall of the third trench 27 on the active region 10 side is in contact with the front electrode 14. Therefore, similar to the first trench 25, the area of ​​the SBD structure, which is composed of Schottky junctions, can be increased. In addition, the second nickel silicide film 33b may have an inactive region 80 on the active region 10 side that is in contact with the front electrode 14.

[0067] As will be described later, the second nickel silicide film 33b is formed by reacting the semiconductor substrate 30 and the metal material film 52 deposited on the front surface of the semiconductor substrate 30 with heat treatment at the contact point between the FLR 21 and the metal material film 52 deposited on the front surface of the semiconductor substrate 30.

[0068] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15 in all areas except those in contact with the front surface electrode 14. A passivation film (not shown) made of polyimide is provided on the outermost surface of the front surface of the semiconductor substrate 30. Here, n + At the top of the channel stopper region, n + A channel stopper electrode may be provided that is in contact with the channel stopper region and electrically connected. The channel stopper electrode may be, for example, an aluminum alloy film formed simultaneously with the aluminum alloy film 32. The back surface (n + A back electrode (second electrode) 19 is provided on the entire surface of the back surface of the mold starting substrate 11, n + It is electrically connected to the mold starting substrate 11.

[0069] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1) Next, a method for manufacturing the silicon carbide semiconductor device 40 according to Embodiment 1 will be described. Figure 5 is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to Embodiment 1. Figures 6 to 16 are cross-sectional views showing the silicon carbide semiconductor device during the manufacturing process according to Embodiment 1.

[0070] First, as shown in Figure 6, n + For example, a starting substrate (semiconductor wafer) 11 can be 5 × 10 18 / cm3 A four-layer periodic hexagonal (4H-SiC) silicon carbide substrate doped with a certain amount of nitrogen (N) is prepared. + The front surface of the mold starting substrate 11 may have an off-angle of about 4° with respect to the (0001) plane, for example. Next, n + On the front surface of the mold starting substrate 11, n - For example, 1.8 × 10⁻¹⁰ results in a drift region of type 12. 16 / cm 3 A certain amount of nitrogen is doped into the n - The first step involves growing a type epitaxial layer.

[0071] n + n becomes a type cathode region + The thickness of the mold starting substrate 11 may be, for example, about 350 μm. - n is in the drift region 12. - The thickness of the epitaxial layer may be, for example, about 6 μm. Through the steps up to this point, n + n - n is in the drift region 12. - A semiconductor substrate (semiconductor wafer) 30 is fabricated by stacking n-type epitaxial layers. Next, a trench-forming mask, for example, an oxide film 51, is formed on the entire surface of the front surface of the semiconductor substrate 30 (step S1). As described above, the semiconductor substrate 30 is n - The main surface on the side of the drift region 12 is the front surface, n + The main surface on the mold starting substrate 11 side is designated as the back surface.

[0072] Next, as shown in Figure 7, the oxide film 51 is selectively removed by photolithography and etching to form an opening, and then dry etching is performed to n - From the surface of the drift region 12, n + A first trench 25 that does not reach the mold starting substrate 11 is selectively formed (Step S2: Second step).

[0073] Next, as shown in Figure 8, p-type impurities such as aluminum are implanted into the bottom of the first trench 25 in the active region 10 by ion implantation (step S3). Similarly, p- p-type impurities such as aluminum are injected into the region corresponding to the mold region 22, n + n-type impurities such as nitrogen are implanted into the portion corresponding to the channel stopper region. Next, as shown in Figure 9, the ion-implanted impurities are activated by heat treatment (Step S4: 3rd and 4th steps). As a result, one or more p-type impurities constituting the JBS structure are introduced into the bottom of the first trench 25. + Type region 13, FLR21, and p - Type region 22 and n + A channel stopper region (not shown) and a channel stopper region are selectively formed. Next, the oxide film 51 is removed.

[0074] Next, as shown in Figure 10, a trench-forming mask, for example, an oxide film 51, is formed on the front surface of the semiconductor substrate 30 (Step S5: Fifth step). Next, as shown in Figure 11, the oxide film 51 is selectively removed by photolithography and etching to form openings 51a and 51b, and then p is removed by dry etching. + From the surface of type region 13 and FLR21 n - A second trench 26 is selectively formed that does not reach the mold drift region 12 (step S6: 6th step, 14th step).

[0075] Next, as shown in Figure 12, a metal material film 52 is formed on the surface of the oxide film 51, for example by sputtering, extending from the surface of the oxide film 51 to the front surface of the semiconductor substrate 30 within the openings 51a and 51b of the oxide film 51 (Step S7: 7th step). The metal material film 52 is a laminated metal film formed by sequentially stacking a first nickel film, an aluminum film (a metal film containing aluminum), and a second nickel film. In Figure 12, the first nickel film, aluminum film, and second nickel film are shown together as a single layer of metal material film 52. In the following description, a three-layer structure of metal material film 52 is described, but the metal material film 52 may also be a two-layer laminated metal film formed by sequentially stacking an aluminum film and a second nickel film. Preferably, the combined thickness of the metal material film 52, consisting of the first nickel film, aluminum film, and second nickel film, or the aluminum film and second nickel film, is 50 nm or more and 250 nm or less.

[0076] Next, as shown in Figure 13, the metal material film 52 is subjected to first sintering (step S8: eighth step) by heat treatment to generate aluminum-nickel-silicon (Al-Ni-Si) compound 55 within the openings 51a and 51b of the oxide film 51. The Al-Ni-Si compound 55 is formed at the contact points between the metal material film 52 and the semiconductor substrate 30 by thermal diffusion of aluminum atoms into the first nickel film, thermal diffusion of nickel atoms into the semiconductor substrate 30, and thermal diffusion of silicon atoms into the first nickel film and the aluminum film. The Al-Ni-Si compound 55 is p + A low-resistance ohmic junction is formed with the high impurity concentration in the mold region 13 or FLR21.

[0077] Next, as shown in Figure 14, excess metal (excess portion) is removed from the oxide film 51 and from the openings 51a and 51b of the oxide film 51 (Step S9: 9th step). Excess metal refers to metals other than the Al-Ni-Si compound 55 that are unreacted metal material film 52 and generated from the metal material film 52, specifically the aluminum nickel compound 56 (see Figure 13) that did not contribute to the formation of the Al-Ni-Si compound 55.

[0078] Next, the Al-Ni-Si compound 55 is subjected to a second sintering by heat treatment (step S10: 10th step). The heat treatment in step S10 generates nickel silicide within the Al-Ni-Si compound 55, transforming the Al-Ni-Si compound 55 into a nickel silicide film 33 that ohmic-bonds to the semiconductor substrate 30. As a result, nickel silicide films 33 that ohmic-bond to the semiconductor substrate 30 are formed in each of the openings 51a and 51b of the oxide film 51, respectively, using the oxide film 51 as a mask in a self-aligned manner. The thickness of the nickel silicide film 33 is approximately twice the thickness of the metal material film 52, ranging from 100 nm to 500 nm.

[0079] Next, as shown in Figure 15, a resist film (not shown) is formed by photolithography, in which the contact hole 15a formation region of the field oxide film 15 is open. Next, the oxide film 51 in the center of the active region is removed by etching using the resist film as a mask, thereby forming a contact hole 15a that penetrates the field oxide film 15 in the depth direction (Step S11: 11th step). In this Step S11 process, only the portion of the oxide film 51 that will become the field oxide film 15 is left.

[0080] Next, as shown in Figure 16, a titanium film 31 is formed over the entire surface from the surface of the field oxide film 15 to the front surface of the semiconductor substrate 30 within the contact hole 15a by a physical vapor deposition (PVD) method such as sputtering. Then, the titanium film 31 is left only within the contact hole 15a by photolithography and etching (step S12). The thickness of the titanium film 31 may be, for example, about 100 nm. The titanium film 31 may extend from within the contact hole 15a onto the field oxide film 15.

[0081] Next, the titanium film 31 is sintered by heat treatment at a temperature of approximately 500°C for about 10 minutes. This heat treatment causes the titanium film 31 and n - A Schottky junction is formed with the type drift region 12. Next, an aluminum alloy film with a thickness of approximately 5 μm is formed over the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by a physical vapor deposition method such as sputtering. Next, the aluminum alloy film is selectively removed by photolithography and etching, leaving an aluminum alloy film 32 on the surface of the titanium film 31 that will become the front electrode 14 (step 12).

[0082] Next, the front surface of the semiconductor substrate 30 (semiconductor wafer) is covered and protected with a protective film (not shown), and then the semiconductor substrate 30 is thinned to the product thickness by polishing the back side. Next, the back surface of the semiconductor substrate 30 is thinned (n+ After forming nickel or titanium on the entire surface of the back surface of the mold starting substrate 11, the back surface electrode 19 is formed by laser annealing (step S13: 13th step). Subsequently, after removing the protective film from the front surface of the semiconductor substrate 30, the semiconductor substrate 30 is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 40 shown in Figure 1.

[0083] As described above, according to Embodiment 1, a fine ohmic stripe structure is provided within the JBS stripe structure, resulting in a two-stage trench structure. This increases the area of ​​the SBD structure composed of Schottky junctions, increases the on-voltage, and lowers Vf. Furthermore, the surface area of ​​the first nickel silicide film can be increased, and during surges, p + By facilitating current flow into the type region, surge current withstand capability (IFSM) can be ensured. Therefore, both surge current withstand capability and on-voltage characteristics can be improved.

[0084] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 17 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 2 as seen from the front side is the same as that of Embodiment 1, so it is omitted (see Figure 2).

[0085] The silicon carbide semiconductor device 40 according to Embodiment 2 differs from the silicon carbide semiconductor device 40 according to Embodiment 1 in the shape of the nickel silicide film 33 in the region S enclosed by the dashed line. For this reason, a description of the other structures of the silicon carbide semiconductor device 40 according to Embodiment 2 will be omitted.

[0086] Figure 18 is a cross-sectional view showing the detailed structure of region S enclosed by the dashed line in Figure 17. As shown in Figure 18, a fine ohmic stripe structure is provided within the JBS stripe structure, forming a trench structure. At the bottom of the first trench 25 is p +A mold region 13 is provided. For example, the width L3 of the first trench 25 is preferably 0.7 μm or more and 3 μm or less, and the depth D3 of the first trench 25 is preferably 100 nm or more and 1000 nm or less.

[0087] The first trench 25 is filled with surface electrodes 14, and the side walls of the first trench 25 are in contact with the surface electrodes 14. Therefore, the surface electrodes 14 and n - The area of ​​the SBD structure, which is formed by a Schottky junction with the drift region 12, increases, the on-voltage increases, and Vf can be reduced.

[0088] At the bottom of the first trench 25, p + A first nickel silicide film 33a is provided on the surface of the mold region 13. The bottom surface of the first nickel silicide film 33a is connected to the front electrode 14 and p + It is located deeper than the interface with the mold region 13. Also, the front surface (n + The side opposite to the mold starting substrate 11 is the front surface electrode 14 and p + It is located at a shallower position than the interface with the mold region 13. Furthermore, in Embodiment 2, the first nickel silicide film 33a is thicker than in the conventional embodiment. For example, the width L4 of the first nickel silicide film 33a is preferably 0.5 μm or more and 2.8 μm or less, and the thickness T1 of the first nickel silicide film 33a is preferably 100 nm or more and 1000 nm or less.

[0089] By making the first nickel silicide film 33a thicker than conventional films, the surface area of ​​the first nickel silicide film 33a can be increased, and p during surges + By facilitating current flow into the type region 13, surge current withstand capability (IFSM) can be ensured. In this way, both surge current withstand capability and on-voltage characteristics can be improved.

[0090] Figure 19 is a cross-sectional view showing the ohmic region, inactive region, and Schottky region of the silicon carbide semiconductor device according to Embodiment 2. In Embodiment 2 as well, the active region 10 is where the titanium film 31 constitutes the JBS structure.+ A striped inactive region 80 that contacts the mold region 13, a striped ohmic region 81 in which the titanium film 31 contacts the first nickel silicide film 33a, and the titanium film 31 is n - It consists of a type drift region 12 and a stripe-shaped Schottky region 82 that is in contact with it. Thus, in the active region 10, one cycle consisting of four regions—an ohmic region 81, two inactive regions 80 surrounding the ohmic region 81, and the Schottky region 82—is repeated.

[0091] By adopting this periodic structure, the ohmic regions 81 can be uniformly and densely arranged throughout the active region 10. Therefore, when a high surge current flows in the forward direction within the semiconductor substrate, the surge current can be dispersed, thereby improving the IFSM characteristics.

[0092] Furthermore, in Embodiment 2 as well, the area ratio of the inactive region 80 to the surface area of ​​the silicon carbide semiconductor device 40 is preferably 5% or more and 35% or less. + The area ratio of the inactive region 80 to the surface area of ​​the mold region 13 is preferably 35% to 90%. Furthermore, the area ratio of the inactive region 80 in the active region 10 is preferably 15% to 40%. By setting the area ratio within these ranges, it is possible to achieve both improved surge current withstand capability and low Vf characteristics.

[0093] Here, Figure 20 is a cross-sectional view showing the detailed structure of the nickel silicide film of the silicon carbide semiconductor device according to Embodiment 2. As shown in Figure 20, the nickel silicide film 33 has a thickness of 2t, and about half of that t is p + It is preferable that it protrudes from the surface of the mold region 13. Also, p + Within the mold region 13, it is preferable that the nickel silicide film 33 extends to about half of its thickness 2t on both sides. Therefore, on both sides of the nickel silicide film 33, - p exposed on the surface of the drift region 12 + The width w1 of the type region 13 is approximately 0.5 μm. Also, p +The width of the nickel silicide film 33 on the surface of the type region 13 is p + The width of the nickel silicide film 33 in the portion protruding from the surface of the mold region 13 becomes larger than the width of the nickel silicide film 33.

[0094] The nickel silicide film 33 can also be adjusted in thickness by modifying the nickel film during sputtering. By increasing the thickness of the nickel film, the thickness of the nickel silicide film 33 can be increased. For example, the thickness of the nickel silicide film 33 can be about twice that of the metal material film 52, which is composed of the first nickel film, the aluminum film, and the second nickel film.

[0095] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 2) Next, a method for manufacturing the silicon carbide semiconductor device 40 according to Embodiment 1 will be described. The flowchart showing the outline of the method for manufacturing the silicon carbide semiconductor device according to Embodiment 2 is the same as that for Embodiment 1, so its description is omitted (see Figure 5). Figures 21 to 26 are cross-sectional views showing the silicon carbide semiconductor device during the manufacturing process according to Embodiment 2. Here, the description of the cross-sectional view showing the manufacturing process, which is the same as that for Embodiment 1, is omitted.

[0096] First, similar to Embodiment 1, n + Prepare a starting substrate (semiconductor wafer) 11, - A type epitaxial layer is grown (first step) to produce a semiconductor substrate (semiconductor wafer) 30. Next, a trench-forming mask, for example, an oxide film 51, is formed on the entire surface of the front surface of the semiconductor substrate 30 (step S1). After this, in the same manner as in Embodiment 1, processing is carried out from the step of selectively forming the first trench 25 (step S2: second step) to the step of forming a trench-forming mask, for example, an oxide film 51, on the front surface of the semiconductor substrate 30 (step S5: fifth step) (see Figures 6 to 10).

[0097] Next, as shown in Figure 21, the oxide film 51 is selectively removed by photolithography and etching to form openings 51a and 51b, and then p is removed by dry etching. +A second trench 26 is selectively formed that reaches the surface of the mold region 13 and the FLR 21 (step S6: sixth step).

[0098] Next, as shown in Figure 22, a metal material film 52 is formed on the surface of the oxide film 51, for example by sputtering, extending from the surface of the oxide film 51 to the front surface of the semiconductor substrate 30 within the openings 51a and 51b of the oxide film 51 (Step S7: 7th step). The metal material film 52 is a laminated metal film formed by sequentially stacking a first nickel film, an aluminum film (a metal film containing aluminum), and a second nickel film. In Figure 22, the first nickel film, aluminum film, and second nickel film are shown together as a single layer of metal material film 52. In the following description, a three-layer structure of metal material film 52 is described, but the metal material film 52 may also be a two-layer laminated metal film formed by sequentially stacking an aluminum film and a second nickel film. Preferably, the combined thickness of the metal material film 52, consisting of the first nickel film, aluminum film, and second nickel film, or the aluminum film and second nickel film, is 250 nm or more and 500 nm or less.

[0099] Next, as shown in Figure 23, the metal material film 52 is subjected to first sintering (step S8: eighth step) by heat treatment to generate aluminum-nickel-silicon (Al-Ni-Si) compound 55 within the openings 51a and 51b of the oxide film 51. The Al-Ni-Si compound 55 is formed at the contact points between the metal material film 52 and the semiconductor substrate 30 by thermal diffusion of aluminum atoms into the first nickel film, thermal diffusion of nickel atoms into the semiconductor substrate 30, and thermal diffusion of silicon atoms into the first nickel film and the aluminum film. The Al-Ni-Si compound 55 is p + A low-resistance ohmic junction is formed with the high impurity concentration in the mold region 13 or FLR21.

[0100] Next, as shown in Figure 24, excess metal (excess portion) is removed from the oxide film 51 and from the openings 51a and 51b of the oxide film 51 (Step S9: 9th step). Excess metal refers to metals other than the Al-Ni-Si compound 55 that are unreacted metal material film 52 and generated from the metal material film 52, specifically aluminum nickel compound 56 (see Figure 23) that did not contribute to the formation of the Al-Ni-Si compound 55.

[0101] Next, the Al-Ni-Si compound 55 is subjected to a second sintering by heat treatment (step S10: 10th step). The heat treatment in step S10 generates nickel silicide within the Al-Ni-Si compound 55, converting the Al-Ni-Si compound 55 into a nickel silicide film 33 that ohmic-bonds to the semiconductor substrate 30. As a result, nickel silicide films 33 that ohmic-bond to the semiconductor substrate 30 are formed in each of the openings 51a and 51b of the oxide film 51, respectively, using the oxide film 51 as a mask in a self-aligned manner. The thickness of the nickel silicide film 33 is approximately twice the thickness of the metal material film 52, ranging from 500 nm to 1000 nm.

[0102] Next, as shown in Figure 25, a resist film (not shown) is formed by photolithography, in which the contact hole 15a formation region of the field oxide film 15 is open. Next, etching is performed using the resist film as a mask to form contact holes 15a that penetrate the field oxide film 15 in the depth direction (step S11: 11th step). In this step S11 process, only the portion of the oxide film 51 that will become the field oxide film 15 is left.

[0103] Next, as shown in Figure 26, a titanium film 31 is formed over the entire surface from the surface of the field oxide film 15 to the front surface of the semiconductor substrate 30 within the contact hole 15a by a physical vapor deposition (PVD) method such as sputtering. Then, the titanium film 31 is left only within the contact hole 15a by photolithography and etching (step S12). The thickness of the titanium film 31 may be, for example, about 100 nm. The titanium film 31 may extend from within the contact hole 15a onto the field oxide film 15.

[0104] Next, the titanium film 31 is sintered by heat treatment at a temperature of approximately 500°C for about 10 minutes. This heat treatment causes the titanium film 31 and n - A Schottky junction is formed with the type drift region 12. Next, an aluminum alloy film with a thickness of approximately 5 μm is formed over the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by a physical vapor deposition method such as sputtering. Next, the aluminum alloy film is selectively removed by photolithography and etching, leaving an aluminum alloy film 32 on the surface of the titanium film 31 that will become the front electrode 14 (step 12).

[0105] Next, the front surface of the semiconductor substrate 30 (semiconductor wafer) is covered and protected with a protective film (not shown), and then the semiconductor substrate 30 is thinned to the product thickness by polishing the back side. Next, the back surface of the semiconductor substrate 30 is thinned (n + After forming nickel or titanium on the entire surface of the back surface of the mold starting substrate 11, the back surface electrode 19 is formed by laser annealing (step S13: 13th step). Subsequently, after removing the protective film from the front surface of the semiconductor substrate 30, the semiconductor substrate 30 is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 40 shown in Figure 17.

[0106] As described above, according to Embodiment 2, a fine ohmic stripe structure is provided within the JBS stripe structure, forming a trench structure, and a thick nickel silicide film is provided at the bottom of the first trench. This increases the area of ​​the SBD structure composed of Schottky junctions, increases the on-voltage, and can lower Vf. Furthermore, it can increase the surface area of ​​the first nickel silicide film, and during surges, p + By facilitating current flow into the type region, surge current withstand capability (IFSM) can be ensured. Therefore, both surge current withstand capability and on-voltage characteristics can be improved.

[0107] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. It is applicable to silicon carbide semiconductor devices equipped with ohmic electrodes that are ohmic-bonded to p-type regions arranged in a predetermined pattern.

[0108] Specifically, for example, the present invention relates to a p-type region (or a p-type region disposed between the p-type region and the main surface of the semiconductor substrate). + This is useful for silicon carbide semiconductor devices with a configuration that reduces the contact resistance between the p-type contact region and the ohmic electrode, and for silicon carbide semiconductor devices with a structure in which the ohmic electrode, which is ohmic-bonded to the p-type region, is in contact with the oxide film. [Industrial applicability]

[0109] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0110] 10, 110 active area 11, 111 n + Mold starting substrate 12, 112 n - Type drift region 13, 113 p that constitutes the JBS structure + type area 14, 114 Front surface electrodes 15, 115 Field oxide film 19, 119 Backside electrodes 20, 120 edge termination region 20a Connecting area 21, 121 Field Limiting Ring (FLR) 22, 122 p that constitutes the JTE structure - type area 25 Trench 1 26. Trench No. 2 27 Third Trench 30, 130 Semiconductor substrates 31, 131 Titanium film 32, 132 Aluminum alloy film 33(33a,33b), 133(133a,133b) Nickel silicide film (1st and 2nd nickel silicide films) 40, 140 Silicon Carbide Semiconductor Devices 51. Oxide film (Oxide film mask) 52 Metal material film 55. Aluminum-nickel-silicon (Al-Ni-Si) compounds 56 Aluminum-nickel compounds 80 Invalid area 81 Ohmic Region 82 Schottky region w1 JBS structural configuration p + Width of the type domain w2a Width of the first nickel silicide film w2b Width of the second nickel silicide film w4 JBS structure invalid area width w5 Width of the Schottky area

Claims

1. An active region provided on a semiconductor substrate made of silicon carbide, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first conductivity type region is provided inside the semiconductor substrate and is exposed on the first main surface of the semiconductor substrate, In the active region, a first trench is provided from the front surface of the first conductivity region into the interior of the first conductivity region, In the active region, a first second conductivity region is provided at the bottom of the first trench, adjacent to the first conductivity region, A silicide film that forms an ohmic bond to the first second conductivity region, The silicide film, the first second conductivity type region, and the first electrode in contact with the first conductivity type region, A second electrode provided on the second main surface of the semiconductor substrate, A second conductivity type region is provided in the terminal region, surrounding the active region, Equipped with, The active region is composed of an ohmic region in which the first electrode is in contact with the silicide film, an inactive region in which the first electrode is in contact with the first second conductivity type region, and a Schottky region in which the first electrode is in contact with the first conductivity type region. The ohmic region, the inactive region, and the Schottky region are arranged in a stripe shape. The bottom surface of the silicide film is located at a position deeper than the interface between the first electrode and the first second conductivity type region. A silicon carbide semiconductor device characterized in that the width of the silicide film is narrower than the width of the first second conductivity type region, and the width of the inactive region is 0.1 μm or more and 1.0 μm or less.

2. The active region further comprises a second trench provided from the front surface of the first second conductivity type region into the interior of the first second conductivity type region, The silicon carbide semiconductor device according to claim 1, characterized in that the silicide film is provided on the bottom surface and side walls of the second trench.

3. The silicon carbide semiconductor device according to claim 1, characterized in that the front surface of the silicide film is provided at a position shallower than the interface between the first electrode and the first second conductivity type region.

4. An active region provided on a semiconductor substrate made of silicon carbide, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first conductivity type region is provided inside the semiconductor substrate and is exposed on the first main surface of the semiconductor substrate, In the active region, a first trench is provided from the front surface of the first conductivity region into the interior of the first conductivity region, In the active region, a first second conductivity region is provided at the bottom of the first trench, adjacent to the first conductivity region, A silicide film that forms an ohmic bond to the first second conductivity region, The silicide film, the first second conductivity type region, and the first electrode in contact with the first conductivity type region, A second electrode provided on the second main surface of the semiconductor substrate, A second conductivity type region is provided in the terminal region, surrounding the active region, Equipped with, The active region is composed of an ohmic region in which the first electrode is in contact with the silicide film, an inactive region in which the first electrode is in contact with the first second conductivity type region, and a Schottky region in which the first electrode is in contact with the first conductivity type region. The ohmic region, the inactive region, and the Schottky region are arranged in a stripe shape. The bottom surface of the silicide film is located at a position deeper than the interface between the first electrode and the first second conductivity type region. A silicon carbide semiconductor device characterized in that the area ratio of the inactive region to the surface area of ​​the silicon carbide semiconductor device is 5% or more and 35% or less.

5. An active region provided on a semiconductor substrate made of silicon carbide, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first conductivity type region is provided inside the semiconductor substrate and is exposed on the first main surface of the semiconductor substrate, In the active region, a first trench is provided from the front surface of the first conductivity region into the interior of the first conductivity region, In the active region, a first second conductivity region is provided at the bottom of the first trench, adjacent to the first conductivity region, A silicide film that forms an ohmic bond to the first second conductivity region, The silicide film, the first second conductivity type region, and the first electrode in contact with the first conductivity type region, A second electrode provided on the second main surface of the semiconductor substrate, A second conductivity type region is provided in the terminal region, surrounding the active region, Equipped with, The active region is composed of an ohmic region in which the first electrode is in contact with the silicide film, an inactive region in which the first electrode is in contact with the first second conductivity type region, and a Schottky region in which the first electrode is in contact with the first conductivity type region. The ohmic region, the inactive region, and the Schottky region are arranged in a stripe shape. The bottom surface of the silicide film is located at a position deeper than the interface between the first electrode and the first second conductivity type region. A silicon carbide semiconductor device characterized in that the area ratio of the inactive region to the surface area of ​​the first second conductivity type region is 35% or more and 90% or less.

6. An active region provided on a semiconductor substrate made of silicon carbide, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first conductivity type region is provided inside the semiconductor substrate and is exposed on the first main surface of the semiconductor substrate, In the active region, a first trench is provided from the front surface of the first conductivity region into the interior of the first conductivity region, In the active region, a first second conductivity region is provided at the bottom of the first trench, adjacent to the first conductivity region, A silicide film that forms an ohmic bond to the first second conductivity region, The silicide film, the first second conductivity type region, and the first electrode in contact with the first conductivity type region, A second electrode provided on the second main surface of the semiconductor substrate, A second conductivity type region is provided in the terminal region, surrounding the active region, Equipped with, The active region is composed of an ohmic region in which the first electrode is in contact with the silicide film, an inactive region in which the first electrode is in contact with the first second conductivity type region, and a Schottky region in which the first electrode is in contact with the first conductivity type region. The ohmic region, the inactive region, and the Schottky region are arranged in a stripe shape. The bottom surface of the silicide film is located at a position deeper than the interface between the first electrode and the first second conductivity type region. A silicon carbide semiconductor device characterized in that the ratio of the area of ​​the inactive region to the surface area of ​​the active region is 15% or more and 40% or less.

7. An active region provided on a semiconductor substrate made of silicon carbide, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first conductivity type region is provided inside the semiconductor substrate and is exposed on the first main surface of the semiconductor substrate, In the active region, a first trench is provided from the front surface of the first conductivity region into the interior of the first conductivity region, In the active region, a first second conductivity region is provided at the bottom of the first trench, adjacent to the first conductivity region, A silicide film that forms an ohmic bond to the first second conductivity region, The silicide film, the first second conductivity type region, and the first electrode in contact with the first conductivity type region, A second electrode provided on the second main surface of the semiconductor substrate, A second conductivity type region is provided in the terminal region, surrounding the active region, Equipped with, The active region is composed of an ohmic region in which the first electrode is in contact with the silicide film, an inactive region in which the first electrode is in contact with the first second conductivity type region, and a Schottky region in which the first electrode is in contact with the first conductivity type region. The ohmic region, the inactive region, and the Schottky region are arranged in a stripe shape. The bottom surface of the silicide film is located at a position deeper than the interface between the first electrode and the first second conductivity type region. The terminal region further comprises a third trench provided from the front surface of the first conductivity type region into the interior of the first conductivity type region, The second conductivity type region is selectively provided inside the third trench, adjacent to the first conductivity type region, and is in contact with the first electrode on the active region side. A silicon carbide semiconductor device characterized in that the width of the third trench is wider than the width of the first trench.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7, characterized in that the first second conductivity type region and the second second conductivity type region are connected.

9. A method for manufacturing a silicon carbide semiconductor device comprising a silicon carbide semiconductor substrate, an active region, and a termination region surrounding the active region, A first step is to form a first conductivity type region that forms the first main surface of the semiconductor substrate inside the semiconductor substrate, A second step is to form a first trench in the active region from the front surface of the first conductivity type region into the interior of the first conductivity type region, A third step is to form a first second conductivity region at the bottom of the first trench in the active region, in contact with the first conductivity region, A fourth step is to form a second conductivity type region surrounding the active region in the terminal region, A fifth step involves forming an oxide film on the first main surface of the semiconductor substrate, covering the first conductivity type region and the first second conductivity type region. A sixth step involves selectively removing the oxide film to form a first opening in the oxide film that exposes the first second conductivity type region, A seventh step involves sequentially stacking a first nickel film, an aluminum film, and a second nickel film in contact with the first main surface of the semiconductor substrate at the first opening of the oxide film to form a metallic material film. An eighth step involves reacting the metal material film with the semiconductor substrate by a first heat treatment to generate a self-aligned compound layer on the first main surface of the semiconductor substrate at the first opening of the oxide film, using the oxide film as a mask. After the eighth step, a ninth step is performed to remove the excess portion of the metal material film excluding the compound layer, A tenth step is performed, in which a second heat treatment at a higher temperature than the first heat treatment generates nickel silicide inside the compound layer, thereby forming a silicide film that forms an ohmic bond to the semiconductor substrate. After the 10th step, the 11th step is to remove the oxide film sandwiched between the silicide films to form a contact hole that connects all of the first openings, A 12th step in which a titanium film that contacts the first conductivity region and forms a Schottky bond with the first conductivity region, and a metal electrode film containing aluminum are sequentially laminated on the first main surface of the semiconductor substrate inside the contact hole to form a first electrode, A 13th step involves forming a second electrode on the second main surface of the semiconductor substrate, Includes, In the sixth step, the width of the first opening is made narrower than the width of the first second conductivity type region, thereby forming the active region to consist of an ohmic region in which the first electrode contacts the silicide film, an inactive region in which the first electrode contacts the first second conductivity type region, and a Schottky region in which the first electrode contacts the first conductivity type region. Furthermore, in the sixth step, the ohmic region, the inactive region, and the Schottky region are formed in a stripe shape. In the tenth step, the bottom surface of the silicide film is formed at a position deeper than the interface between the first electrode and the first second conductivity type region. The process further includes a 14th step, after the third step, of forming a second trench in the active region from the front surface of the first second conductivity type region into the interior of the first second conductivity type region, A method for manufacturing a silicon carbide semiconductor device, characterized in that the silicide film is formed on the bottom surface and side walls of the second trench in the tenth step.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, characterized in that in the tenth step, the front surface of the silicide film is formed at a position shallower than the interface between the first electrode and the first second conductivity type region.

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