Low-intensity photomasks, and systems, methods, and program products for creating low-intensity photomasks for use in flat panel display lithography.

Abstract

A method of manufacturing a photomask, the method including receiving initial photomask design data associated with one or more patterns to be formed on the photomask, and optimizing the initial photomask design data to minimize printing exposure energy while maintaining acceptable pattern quality and size. In some embodiments, the optimizing includes setting minimization of printing exposure energy as a priority design rule, setting optimization of pattern quality and size as a secondary design rule, iterating sizing of mask design features to determine a range of size bias that satisfies both the priority design rule and the secondary design rule to provide an initial optimized mask design, and adjusting mask variations across the range of size bias to determine mask variations that further optimize the initial optimized mask design to obtain a final optimized mask design.

Description

Technical Field

[0001] Related Applications This application claims the priority and benefit of U.S. Provisional Patent Application No. 63 / 323,527, entitled "LOW INTENSITY PHOTOMASK AND SYSTEM, METHOD AND PROGRAM PRODUCT FOR MAKING LOW INTENSITY PHOTOMASK FOR USE IN FLAT PANEL DISPLAY LITHOGRAPHY," filed on March 25, 2022, the entire content of which is incorporated herein by reference.

[0002] The present invention generally relates to the manufacture of photomasks, and more particularly to the manufacture of photomasks used in flat panel display (FPD) lithography.

Background Art

[0003] The lithography process in flat panel display (FPD) manufacturing determines the performance and output capacity of flat panel products. Shortening the process time in the lithography step is an important factor for shortening the product turnaround time (TAT) and thus improving the overall production capacity output of the product, which means improving productivity in panel manufacturing.

[0004] When optimizing the mask layout to improve general lithography performance, it is often necessary to adjust the feature size, shape, and optical characteristics (e.g., phase shift, transmission level) of the mask to improve the printing of the mask onto the substrate. The optical characteristics are often adjusted using the mask structure, such as by adding or adjusting thin films on the mask. In optical proximity effect correction, the edges of the mask features are adjusted so that the printed mask features best match the desired design features when the mask is printed onto the substrate by a lithography scanner. Typical performance metrics leading to the adjustment of mask features are related to pattern fidelity, image focus range, and exposure tolerance.

[0005] Photomask technology has contributed to the capabilities and productivity of integrated circuit (IC) and flat panel display (FPD) manufacturing, including the implementation of masks that improve process capability, margins, and yield. Examples of such masks include advanced binary or multitone masks and phase-shift masks. These masks primarily consist of a transparent substrate and patterned absorption films (e.g., CrOx, CrON) and phase-shift films (e.g., MoSi, SiN) to provide and maintain the optical, physical, and mechanical requirements of the mask. Therefore, in mask fabrication, the optimal mask process conditions for processing these films and their controllability affect the patterning quality and performance of the mask in the lithography process.

[0006] However, in the case of FPD panel processes, the design and processes are very different from those of conventional IC products and require special, dedicated solutions. For example, state-of-the-art panel product designs have features of fairly large dimensions that are patterned over a fairly large area, and the lineage of shapes of such features often differs compared to advanced IC designs. In this regard, FPD panel design does not require the higher performance masking processes used in complex IC designs. Therefore, a masking process more suitable for FPD lithography processes is required. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The object of the present invention is to provide a mask manufacturing process in which the mask shape and structure are optimized to achieve the minimum printing exposure energy while maintaining acceptable pattern quality and size. This is in contrast to conventional techniques used, for example, in IC lithography, where the mask shape and structure are optimized to achieve optimal pattern quality and size. By effectively shifting the priority of the optimization merit function from improving pattern quality to achieving the minimum exposure dose level, a significant improvement in throughput for lithography scanners can be achieved while maintaining acceptable image quality for flat panel display applications. [Means for solving the problem]

[0008] In some exemplary embodiments, a method for manufacturing a photomask includes (A) receiving initial photomask design data relating to one or more patterns to be formed on the photomask; (B) optimizing the initial photomask design data to minimize printing exposure energy while maintaining acceptable pattern quality and size, comprising: 1. setting minimizing printing exposure energy as a priority design rule; 2. setting optimization of pattern quality and size as a secondary design rule; 3. iterating over the sizing of mask design features to determine a range of size bias that satisfies both the priority and secondary design rules, thereby providing an initial optimized mask design; and 4. adjusting the mask deformation morph across the range of size bias to determine a mask deformation morph that further optimizes the initial optimized mask design, thereby obtaining a final optimized mask design; and (C) generating optimized photomask design data based on the final optimized mask design.

[0009] In some exemplary embodiments, the size bias range includes a negative size bias.

[0010] In some exemplary embodiments, the size bias range includes a positive size bias.

[0011] In some exemplary embodiments, the mask deformation mode includes a pattern edge compensation deformation mode.

[0012] In some exemplary embodiments, the mask deformation form includes the mask structure deformation form.

[0013] In some exemplary embodiments, the mask deformation form includes the scanner illumination shape deformation form.

[0014] In some exemplary embodiments, the mask deformation modes include pattern edge compensation deformation modes, mask structure deformation modes, scanner illumination shape deformation modes, and combinations thereof.

[0015] In some exemplary embodiments, the method further includes the step of performing optical proximity effect correction on optimized photomask design data.

[0016] In some exemplary embodiments, the method further includes the step of providing a mask blank.

[0017] In some exemplary embodiments, the method further includes the step of processing a mask blank using optimized photomask design data to form a photomask for use in a lithography process.

[0018] In some exemplary embodiments, the photomask is a large photomask for use in a lithography process to manufacture a flat panel display (FPD).

[0019] In some exemplary embodiments, a method for forming a flat panel display, comprising the step of irradiating a glass plate substrate with light from a light energy source via a large photomask formed according to the method of claim 11, wherein at least one circuit pattern is transferred from the large photomask to the glass plate substrate.

[0020] In some exemplary embodiments, the flat panel display is a liquid crystal display, an active matrix liquid crystal display, an organic light emitting diode, a light emitting diode, a plasma display panel, or an active matrix organic light emitting diode.

[0021] These and other features and advantages of the present invention will be presented in more detail in the following detailed description and the accompanying drawings, which illustrate the principles of the invention by way of example.

[0022] Various exemplary embodiments of the present invention will be described in detail below with reference to the following figures.

Brief Description of the Drawings

[0023] [Figure 1] A diagram showing the original mask pattern layout compared to the modified mask pattern layout according to an exemplary embodiment of the present invention. [Figure 2] A graph showing the trend of dose vs. CD for line and space features with different biases according to an exemplary embodiment of the present invention. [Figure 3] A graph showing the trend of dose vs. CD for insulating contact features according to an exemplary embodiment of the present invention. [Figure 4A] A diagram showing a variant form of a mask that can be considered in the optimization process of dose minimization according to an exemplary embodiment of the present invention. [Figure 4B] A diagram showing another variant form of a mask that can be considered in the optimization process of dose minimization according to an exemplary embodiment of the present invention. [Figure 4C] A diagram showing another variant form of a mask that can be considered in the optimization process of dose minimization according to an exemplary embodiment of the present invention. [Figure 5] A simplified block diagram of an embodiment of a flat panel display (FPD) manufacturing system and an associated FPD manufacturing flow according to an exemplary embodiment of the present invention. [Figure 6] This is a schematic diagram of an exemplary mask enhancer system. [Figure 7] This figure shows an exemplary computer system related to a mask enhancer system according to various embodiments of the present invention. [Figure 8] This figure shows a process for optimizing mask design according to an exemplary embodiment of the present invention. [Figure 9] This graph shows the relationship between position on the x-axis (nm) and spatial image intensity (mJ / cm2), illustrating the intensity profile according to an exemplary embodiment of the present invention. [Figure 10] This graph shows the relationship between the optimal energy level and pattern size according to an exemplary embodiment of the present invention. [Figure 11] Refer to Figure 8, which shows the process flow of the low-intensity mask design optimization process described above, enhanced by additional steps. [Figure 12A] This figure shows an example of preparing a low-intensity mask for an FPD design pattern according to an exemplary embodiment of the present invention. [Figure 12B] This figure shows another example of preparing a low-intensity mask for an FPD design pattern according to an exemplary embodiment of the present invention. [Figure 12C] This figure shows another example of preparing a low-intensity mask for an FPD design pattern according to an exemplary embodiment of the present invention. [Figure 13] This figure shows the structure and strength of a PSM mask according to an exemplary embodiment of the present invention. [Figure 14] This figure shows a comparison between the intensity profiles of various PSM masks according to exemplary embodiments of the present invention. [Figure 15] This table shows the percentage gain in productivity for 1.5 μm line-space patterns due to low-intensity mask bias and dose variation according to exemplary embodiments of the present invention. [Figure 16] This table shows the percentage gain in productivity for 1.8 μm contact hole patterns by varying low-intensity mask bias and dose according to exemplary embodiments of the present invention. [Modes for carrying out the invention]

[0024] Flat panel displays (FPDs) are electronic viewing technologies used to display content (e.g., still images, videos, text, or other visual materials) in various entertainment, consumer electronics, personal computers, and mobile devices, as well as many types of medical, transportation, and industrial equipment. Current types of FPDs include, for example, LCDs (liquid crystal displays), AMLCDs (active-matrix liquid crystal displays), OLEDs (organic light-emitting diodes), LEDs (light-emitting diodes), PDPs (plasma display panels), and AMOLEDs (active-matrix OLEDs).

[0025] During the manufacturing of flat panel displays (FPDs), the FPD lithography system illuminates a photomask on which the original thin-film transistor (TFT) circuit pattern is drawn, and this light passes through a lens to expose the pattern onto a glass plate substrate. For large glass plates, the exposure process is repeated several times to form a pattern across the entire plate.

[0026] Figure 1 shows the original mask pattern layout compared to a modified mask pattern layout according to an exemplary embodiment of the present invention. The original pattern layout, shown by the solid line, is designed to acquire the target critical dimension (CD) or layout using optimal dose conditions to obtain a CD tolerance of ±10% in panel lithography. This conventional method originates from the history of integrated circuits and is limited by the narrower process degrees of freedom in this type of lithography. However, in flat panel lithography processes, larger pattern sizes often already have a sufficient process window for exposure tolerance and depth of field, and there is greater flexibility to adjust the pattern size to lower the intensity threshold, thus improving scanner throughput. In this regard, the dotted line in Figure 1 shows a preferred pattern bias for achieving lower threshold exposure with respect to the specific pattern in this example.

[0027] In this case, a lower intensity mask is generated with a smaller design shape, indicated by the dotted line in Figure 1, resulting in a lower exposure time for these fully transparent feature patterns. Although not shown in Figure 1, other specific features on the mask, such as dark-field contact hole designs, require a larger design feature bias (rather than a smaller bias) to achieve shorter exposure times. In some embodiments, these size bias techniques are applied to the flat-panel process to create more productive masks.

[0028] Figure 2 is a graph showing dose vs. CD trends for line-and-space features with different biases. Line 6 shows the data trend of exposure energy targeting a 1.5 μm CD for line-and-space patterns. According to this graph, 115 mJ / cm² is required to obtain a 1.5 μm CD target. 2 Exposure energy must be used. However, in some embodiments, the lithography process can be optimized to minimize exposure energy, in which case smaller lines with the same pitch size can be used. This is represented by lines 7, 8, and 9, which require lower exposure energy to obtain the same pattern size on the panel, resulting in higher throughput.

[0029] Figure 3 is a graph showing the inverse effect when the design pattern is an insulating contact feature, according to an exemplary embodiment of the present invention. Specifically, in this exemplary embodiment, a positive bias is applied to the design contact to create larger features in the mask, resulting in a lower dose mask effect to define the target CD pattern on the panel. Line 10 represents 180 mJ / cm 2 The conditions for obtaining a 2.0 μm contact CD at a given dose are shown, while the other lines demonstrate the dose minimization effect when larger contact features are formed on the mask.

[0030] In some embodiments, this bias optimization method can be applied to the entire mask pattern, which consists of various feature shapes and sizes, by simultaneously optimizing the shape bias according to exposure minimization rules. More specifically, in some embodiments, by using a pattern correction tool with exposure minimization bias rules, the print dose for the entire mask can be effectively reduced while simultaneously printing the pattern correctly onto the panel for proper display device functionality.

[0031] Figures 4A, 4B, and 4C show various variations of the mask that may be considered in the dose minimization optimization process according to exemplary embodiments of the present invention.

[0032] Figure 4A shows pattern edge compensation modification forms that can be adjusted to minimize dose according to exemplary embodiments of the present invention. Some examples of pattern edge compensation modification forms include bias, hammerhead, serif, jog, scattering bar, and combinations thereof.

[0033] Figure 4B shows a modified mask structure that can be adjusted to minimize dose according to an exemplary embodiment of the present invention. Some examples of modified mask structures include a phase shifter layer, an absorber layer, a transmission layer, an anti-reflection layer, and combinations thereof.

[0034] Figure 4C shows a scanner illumination shape modification that can be adjusted to minimize dose, according to an exemplary embodiment of the present invention. Examples of scanner illumination shape modifications include, for example, modifications of the arc shape of the illumination, such as adjustments to the arc width, arc degree, arc spacing, arc shape, and combinations thereof.

[0035] In some exemplary embodiments, mask deformations may be adjusted individually or in combination to minimize the dose. For example, pattern edge compensation, mask structure, and / or scanner illumination shape may be adjusted individually or in any combination of two or more deformations.

[0036] Figure 5 is a simplified block diagram of one embodiment of a flat panel display (FPD) manufacturing system 100 and related FPD manufacturing flow according to an exemplary embodiment of the present invention. The FPD manufacturing system 100 includes multiple entities, such as a design house 120, a mask house 130, and an FPD manufacturer 150 (i.e., a factory), which interact with each other in the design, development, and manufacturing cycle and / or service related to the manufacture of an FPD device 160. The multiple entities can be connected by a communication network, which may be a single network or various different networks, such as an intranet or the internet, and may include wired and / or wireless communication channels. Each entity can interact with other entities, provide services to other entities and / or receive services from other entities. In some embodiments, one or more of the design house 120, mask house 130, and FPD manufacturer 150 may have a common owner, coexist in a common facility, and even use common resources.

[0037] In various embodiments, a design house 120, which may include one or more design teams, generates an FPD design layout 122. The FPD design layout 122 may include various geometric patterns designed for the manufacture of an FPD device 160. For example, the geometric patterns may correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the FPD device 160 to be manufactured. The various layers combine to form various features of the FPD device 160, such as thin-film transistors (TFTs). For example, various parts of the FPD design layout 122 may include features such as active regions, gate electrodes, source and drain regions, metal lines or vias for metal interconnects, openings for bond pads, and other features known in the art to be formed on the FPD glass substrate and the various material layers disposed on the glass substrate. In exemplary embodiments, the design house 120 implements a design procedure for forming the FPD design layout 122. The design procedure may include logic design, physical design, and / or place and route. The FPD design layout 122 may be presented in one or more data files containing information related to the geometric patterns to be used to fabricate the FPD device 160. In some embodiments, the FPD design layout 122 may be represented in various formats, such as the Open Artwork System Interchange Standard (OASIS) file format, the GDSII file format, or the DFII file format.

[0038] In some embodiments, the design house 120 can transmit the FPD design layout 122 to the mask house 130, for example, via the network connection described above. The mask house 130 can then use the FPD design layout 122 to manufacture one or more masks to be used to fabricate the various layers of the FPD device 160 according to the FPD design layout 122. In various examples, the mask house 130 performs mask data preparation 132, converting the FPD design layout 122 into a format that can be physically written by a mask writer, and further performs mask fabrication 144, modifying the design layout prepared by mask data preparation 132 to suit a particular mask writer and / or mask manufacturer, and then fabricating it. In the example in Figure 2, mask data preparation 132 and mask fabrication 144 are shown as separate elements. However, in some embodiments, mask data preparation 132 and mask fabrication 144 are sometimes collectively referred to as mask data preparation.

[0039] In some embodiments, the mask data preparation 132 includes the application of one or more resolution enhancement techniques (RETs) to compensate for potential lithography errors, such as those arising from diffraction, interference, or other process effects. In some embodiments, optical proximity effect correction (OPC) may be used to adjust line width according to the density of the surrounding geometric shape, add "dogbone" end caps to the ends of lines to prevent shortening of line ends, correct electron beam (e-beam) proximity effects, or achieve other objectives. For example, the OPC technique may include adding sub-resolution auxiliary features (SRAFs), which may include, for example, adding scattering bars, serifs, and / or hammerheads to the FPD design layout 122 according to an optical model or rules, thereby improving the final pattern on the glass substrate after the lithography process to enhance resolution and accuracy. The mask data preparation 132 may also include further RETs such as off-axis illumination (OAI), phase-shift masks (PSMs), other appropriate techniques, or combinations thereof.

[0040] In some embodiments, mask data preparation 132 may include mask process correction (MPC) used to compensate for errors introduced during the masking process. For example, MPC can be used to compensate for the effects of the masking process, such as fogging, developing and etching loads, and e-beam proximity effects. In some embodiments, the MPC process modifies the post-OPC design layout to compensate for limitations that may occur during masking 144.

[0041] In some embodiments, mask data preparation 132 may include a lithography process check (LPC) that simulates the process performed by the FPD manufacturer 150 to fabricate the FPD device 160. The LPC can simulate this process based on the FPD design layout 122 to create a simulated manufactured device such as the FPD device 160. Process parameters in the LPC simulation may include parameters related to various processes in the FPD manufacturing cycle, parameters related to the tools used to manufacture the FPD, and / or other aspects of the manufacturing process. For example, the LPC may take into account various factors such as spatial image contrast, depth of field (DOF), mask error enhancement factor (MEEF), other appropriate factors, or a combination thereof.

[0042] In some embodiments, if, after the simulated device to be manufactured is made by LPC, the simulated device layout is not close enough to the shape required to satisfy the design rules, certain steps of mask data preparation 132, such as OPC or MPC, may be repeated to further refine the IC design layout 122.

[0043] The above description of mask data preparation 132 has been simplified for clarity, and it should be understood that data preparation may also include additional functions such as logical operations (LOP) to modify the FPD design layout according to manufacturing rules. Furthermore, the processes applied to the FPD design layout 122 during data preparation 132 can be performed in various different orders.

[0044] After mask data preparation 132, during mask fabrication 144, one mask or a group of masks can be fabricated based on the modified FPD design layout. In some embodiments, an electron beam (e-beam) or a multiple e-beam mechanism is used to form a pattern on the mask (photomask or reticle) based on the modified FPD design layout. In some embodiments, the mask pattern includes opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam used to expose a radiation-sensitive material layer (e.g., photoresist) coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In some embodiments, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the mask. In some embodiments, the mask is formed using phase-shift techniques. In a phase-shift mask (PSM), various features of the pattern formed on the mask are configured to have a preset phase difference to improve image resolution and imaging quality. In some embodiments, the phase-shift mask may be an attenuated PSM or an alternating PSM.

[0045] In some embodiments, the FPD manufacturer 150 can use a mask (or more masks) fabricated by the mask house 130 to transfer one or more mask patterns onto a product glass substrate 152, and thus fabricate an FPD device 160 on the product glass substrate 152. The FPD manufacturer 150 may include an FPD manufacturing facility that may include a number of manufacturing facilities for producing various different FPD products. For example, the FPD manufacturer 150 may include a first manufacturing facility for front-end fabrication (i.e., front-end-of-line (FEOL) fabrication) of multiple FPD products, a second manufacturing facility may provide back-end fabrication (i.e., back-end-of-line (BEOL) fabrication) for interconnection and packaging of FPD products, and a third manufacturing facility may provide other services. In various embodiments, the product FPD 152 on which the FPD device 160 is fabricated may include a glass substrate, and the type of glass may be, to name a few, aluminosilicate glass, borosilicate glass, or fused silica. In some embodiments, the large photomask may be appropriately sized to accommodate the photolithography process of the glass plate substrate used to form the FPD.

[0046] In some exemplary embodiments, mask data preparation may involve the use of a mask enhancer system. In this regard, Figure 6 shows a schematic diagram of an exemplary mask enhancer system 204 for enhancing a photomask layout according to some embodiments. Some embodiments of the mask enhancer system 204 include an OPC enhancer 222 that receives a mask layout M generated by a design house 120 and generates an OPC-processed (e.g., corrected) mask layout M. As described above, OPC is a lithography technique used to correct or enhance a mask layout M and produce an improved imaging effect to reproduce the original layout drawn by the FPD design house 120 on a glass substrate. For example, OPC can be used to compensate for imaging distortion due to light diffraction. In some embodiments, the mask layout M is a data file containing information about the geometric pattern to be generated on the substrate, and the OPC enhancer 222 modifies the data file and generates a corrected data file representing the corrected mask layout M'.

[0047] In some exemplary embodiments, a corrected mask layout M can be applied to a mask projection device 230 to generate a projected mask layout 238 on a wafer. In some embodiments, the corrected mask layout M is a data file, and the mask projection device 230 simulates the projection of the corrected mask layout M' onto the wafer to generate a simulated projected mask layout 238. A defect detector 232 of the mask enhancer 204 inspects the projected mask layout 238 and finds defect regions 236 in the projected mask layout 238. The corrected mask layout M' is OPC processed, but defect regions may be generated when the corrected mask layout M' is projected onto the substrate 208.

[0048] In some embodiments, the defect corrector 234 of the mask enhancer 204 receives the defect region 236 and the corrected mask layout M', and can perform further corrections, such as enhancements, on the corrected mask layout M' to generate an enhanced mask layout M''. In some embodiments, the defect detector 232 may be coupled to the defect corrector 234 to receive the projected mask layout 238 and the corrected mask layout M' to create a layout detection and correction system 233 that provides an enhanced mask layout M''.

[0049] In some exemplary embodiments, the mask enhancer system 204 includes specialized hardware components, software components, and / or combinations of both hardware and software components, enabling various procedures related to enhancing and correcting the functionality of the photomask as part of the FPD manufacturing process. In this regard, Figure 7 shows an exemplary computer system related to a mask enhancer system according to various embodiments of the present invention. In some embodiments, the computer system includes a server 401, a display 402, one or more input interfaces 403, and one or more output interfaces 404, all of which are conventionally coupled by one or more buses 405. Some examples of suitable buses include, for example, PCI-Express®, AGP, PCI, and ISA.

[0050] A computer system may contain any number of graphics processors. Graphics processors may reside on the motherboard, such as being integrated with the motherboard chipset. One or more graphics processors may reside on external boards connected to the system via buses such as the ISA bus, PCI bus, AGP port, PCI Express, or other system buses. Graphics processors may reside on separate boards, each connected to a bus such as the PCI Express bus, connected to each other, and connected to the rest of the system. Furthermore, there may be separate buses or connections that graphics processors can communicate with each other (for example, Nvidia SLI or ATI CrossFire connections). These separate buses or connections may be used in addition to or instead of the system bus.

[0051] Server 401 may include one or more CPUs 406, one or more GPUs 407, and one or more memory modules 412. Each CPU and GPU may be a single-core or multi-core unit. Suitable CPUs include Intel Pentium®, Intel Core® 2 Duo, AMD Athlon 64, and AMD Opteron®. Suitable GPUs include Nvidia GeForce® and ATI Radeon®. The input interface 403 may include a keyboard 408 and a mouse 409. The output interface 404 may include a printer 410.

[0052] In some embodiments, the communication interface 411 is a network interface that allows a computer system to communicate over a wireless or wired network. The communication interface 411 may be coupled to a network transmission path, a transmission medium (not shown) such as twisted pair, coaxial cable, or fiber optic cable, to name a few. In another embodiment, the communication interface 411 provides a wireless interface, i.e., the communication interface 411 uses a wireless transmission medium. Examples of other devices that can be used to access the computer system via the communication interface 411 include, to name a few, mobile phones, PDAs, personal computers, etc. (not shown).

[0053] The memory module 412 may generally include different modalities, such as semiconductor memory including random access memory (RAM) and disk drives. In various embodiments, the memory module 412 stores an operating system 413, data structures 414, instructions 415, applications 416, and procedures 417.

[0054] Storage devices include high-capacity disk drives, floppy disks, magnetic disks, optical disks, magneto-optical disks, fixed disks, hard disks, CD-ROMs, recordable CDs, DVDs, recordable DVDs (e.g., DVD-R, DVD+R, DVD-RW, DVD+RW, HD-DVD, or Blu-ray discs), flash and other non-volatile solid-state storage (e.g., USB flash drives), battery-backed volatile memory, tape storage, readers, and other similar media, as well as combinations thereof.

[0055] In various embodiments, specific software instructions, data structures, and data implementing various embodiments of the present invention are typically incorporated into server 401. Generally, one embodiment of the present invention includes instructions, applications, and procedures that are tangibly embodied using a computer-readable medium, such as memory, and that, when executed by a processor, allow a computer system to utilize the present invention to perform tasks such as data collection and analysis, structure pixelation, edge placement error determination, edge fragment movement, and edge fragment placement optimization. The memory may store software instructions, data structures, and data relating to any operating system, data collection applications, data aggregation applications, data analysis procedures, etc., in semiconductor memory, disk memory, or a combination thereof.

[0056] A computer implementation or computer-executable version of the present invention may be embodied using a computer-readable medium, stored on a computer-readable medium, or associated with a computer-readable medium. The computer-readable medium may include any medium involved in providing instructions to one or more processors for execution. Such mediums can take many forms, but are not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, flash memory, or optical or magnetic disks. Volatile media include static or dynamic memory such as cache memory and RAM. Transmission media include coaxial cables, copper wires, optical fiber lines, and wires arranged on buses. The transmission medium may also take the form of electromagnetic waves, radio frequency waves, acoustic waves, or light waves, such as radio waves or light waves generated during infrared data communication.

[0057] For example, a machine-executable binary version of the software of the present invention can be stored or reside in RAM or cache memory or a mass storage device. The source code of the software of the present invention can also be stored or reside in a mass storage device (e.g., a hard disk, magnetic disk, tape, or CD-ROM). As a further example, the code of the present invention may be transmitted over a network such as wires, radio waves, or the Internet.

[0058] The operating system may be implemented by any conventional operating system, including Windows® (registered trademark of Microsoft Corporation), Unix® (registered trademark of the Open Group in the United States and other countries), Mac OS® (registered trademark of Apple Computer, Inc.), Linux® (registered trademark of Linus Torvalds), and other operating systems not expressly listed herein.

[0059] In various embodiments, the present invention may be implemented as a method, system, or product using standard programming and / or engineering techniques to generate software, firmware, hardware, or any combination thereof. As used in this application, the term “product” (or alternatively “computer program product”) is intended to encompass computer programs accessible from any computer-readable device, carrier, or medium. Furthermore, the software in which various embodiments are implemented may be accessible via a transmission medium, for example, from a server via a network. Products in which code is implemented also include transmission media such as network transmission lines and wireless transmission media. Thus, products also include media in which code is embedded. Those skilled in the art will understand that many modifications can be made to this configuration without departing from the scope of the present invention.

[0060] The computer system shown in Figure 7 is not intended to limit the present invention. Other alternative hardware and / or software environments may also be used without departing from the scope of the present invention.

[0061] Figure 8 shows a process for optimizing mask design according to an exemplary embodiment of the present invention. In step S01 of the process, the mask correction tool can receive or otherwise acquire data related to the original mask design layer and the lithography tool scanner illumination conditions. In step S03, a dose minimization rule is set as the priority rule, and a minimum allowable design for matching with the target layer is set as the secondary rule. In some embodiments, the minimum allowable design may be the minimum allowable CD tolerance range. In step S05, the mask model is calibrated with respect to pattern dose for printing over a wide bias range. In this step, mask data is generated that represents the changes in mask features according to the bias range. For example, line and space patterns may be reduced in size over a negative bias range compared to the original mask pattern data, and contact hole patterns may be increased in size over a positive bias range compared to the original mask pattern data.

[0062] In step S07, the pattern edges, mask structure, and / or scanner illumination geometry are modified across negative and / or positive bias ranges to satisfy the minimum dose rule while still achieving minimum acceptable target layer matching. In this step, either only one of the deformation forms is adjusted across the bias range, or two or more deformation forms are combined and modified across the bias range to determine the iteration that achieves the minimum dose while maintaining minimum acceptable quality and size of the features.

[0063] In some embodiments, the process flow shown in Figure 8 advances the optimization of mask patterns for low exposure cases, which increases throughput when masks are applied in lithography printing. While not bound by theory, in panel manufacturing processes, lithography processes have larger process margins compared to IC manufacturing. Larger pattern design and exposure tool capabilities enable the use of low-intensity masks in panel lithography processes for better throughput and productivity.

[0064] Figure 9 shows the position on the x-axis (nm) and spatial image intensity (mJ / cm²). 2 This graph shows the relationship between intensity profile 1 and a 1.5 μm line and 1.5 μm space pattern (3.0 μm pitch), and intensity profile 2 for a 1.7 μm line and 1.3 μm space pattern (3.0 μm pitch) according to an exemplary embodiment of the present invention. In some embodiments, such intensity profiles generated using the results of spatial image simulations can be used to select the optimal design and intensity level. In this example, with respect to intensity profile 1, the intensity level or energy level will be close to 0.3 to achieve the target CD (shown as line 3) in order to obtain a pattern size of 1.5 μm. If 0.2 μm oversizing is used to produce a low-intensity mask (intensity profile 2), the target CD (shown as line 4) can be achieved using an energy level of 0.2. That is, a pattern of the same size can be defined using a lower dose or energy. Thus, shorter exposure times can be used in the panel lithography process to improve the throughput and manufacturability of the panel process.

[0065] Figure 10 is a graph showing the relationship between the optimal energy level and pattern size according to an exemplary embodiment of the present invention. By using a low-intensity mask with optimal size adjustment, lower energies can be used as the trend toward optimal dose conditions.

[0066] Since the present invention prioritizes the low exposure case over the pattern fidelity case, as in conventional pattern correction methods, in some embodiments, functionality can be added to the optimization flow to identify and compensate for problems that may arise from prioritizing dose minimization rules. In this regard, Figure 11 shows a process flow in which the low-intensity mask design optimization process described above is enhanced by additional steps with reference to Figure 8. The first additional step (step S09) is MRC (Mask Rules Checking), which ensures that the low-intensity mask design does not introduce mask shapes and features that are too complex for manufacturing. The second additional step is PM (Pattern Matching) (step S11), which selectively positions and adjusts special mask patterns to address printing problems that may arise from the low-intensity mask optimization process. The third additional step is OPC (Optical Proximity Correction) (step S13), which continues to adjust the pattern for pattern quality without negating the dose minimization benefits of the low-intensity mask design process flow. The final low-intensity mask design, as an enhancement by these steps, is completed in step S15. In some embodiments, as shown by the dashed arrows in Figure 11, the overall low-intensity mask design process may include any number of iterations of low-intensity optimization with additional steps to compensate for problems until a final mask design that satisfies the desired parameters is achieved. In some embodiments, the additional steps described above may or may not be necessary in the overall low-intensity mask data correction flow, and any number of these additional steps can be included in the overall process individually or in combination.

[0067] Figures 12A–12C illustrate an example of preparing a low-intensity mask for an FPD design pattern. The mask in this example is intended to form part of the contact array layer in the FPD panel process. The original mask, redesigned as low-intensity mask design 400, is shown in Figure 12A and includes contact openings 410. The MRC tool can then be used to detect design and process feature overlaps or rule violations, and corrections can be made in the MRC process and pattern matching using the applied rules. Figure 12B shows a mask after the MRC and OPC processes, which can be applied to improve process windows or for other specific purposes. Figure 12C illustrates the verification and validation steps, where a simulation method on the optimized low-intensity mask can be used to identify potential problems (such as bridging issues shown in the simulated feature 412 projected by the mask), and then the problems can be corrected in the data for final low-intensity mask manufacturing.

[0068] As described above with reference to Figures 4A-4C, in some embodiments, special lighting and mask structural conditions can be employed in the manufacturing and printing of the mask to improve the effectiveness of the low-intensity mask and the opportunity for dose reduction. In some embodiments, low-intensity optimization can be benefited by setting the phase shift and light transmission parameters (including multiple transmission levels) of the mask, along with other film properties that can create high-contrast masks, thereby providing more flexibility for optimizing the low-intensity mask design flow and achieving further productivity improvements and speed increases in FPD production.

[0069] Conventionally, masks used in FPD panel manufacturing processes are exposed using exposure tools with circular apertures. In some embodiments, larger aperture types can be used to deliver more energy to the mask. Also, off-axis illumination (OAI) is currently used in the FPD field (see Figure 4C). In some embodiments, the design and sizing of the OAI can be optimized to improve the effectiveness of low-intensity masks.

[0070] Furthermore, referring again to Figure 4B, mask technology in panel lithography can contribute to improving process windows and productivity in FPD manufacturing. In this regard, in some embodiments, various types of masks can be used in the FPD manufacturing process, including, to name a few, binary intensity masks (BIM), phase-shift masks (PSM), RIM-type PSMs, high transmittance masks (HTM), composites of PSM and HTM, and double-sided anti-reflective masks (DAR).

[0071] Figure 13 shows the structure and strength of a PSM mask, and Figure 14 shows a comparison between the strength profiles of various PSM masks. In some embodiments, PSM masks can be used in the FPD manufacturing process to improve process windows and resolution. Although not bound by theory, higher quality strength profiles can be obtained by a 180-degree phase shift through a phase material, as shown in Figure 13. In some embodiments, PSM masks are processed to suit the low-strength mask optimization discussed herein, and the improved strength profiles and higher contrast of such masks can further enhance the overall process. As an example, Figure 14 shows simulation results for various mask types, demonstrating that the strength profiles of PSM have better contrast and profile characteristics compared to BIM. Strength profile 510 corresponds to a BIM mask, strength profiles 520-560 correspond to PSM masks in the transmittance range of 5%-50%, and strength profile 570 corresponds to a contact mask.

[0072] In some embodiments, dose minimization features can be used to apply feature bias to binary-type masks with a 1.5 μm design rule, achieving a 10-30% improvement in FPD manufacturing. In some embodiments, high-contrast masks, such as PSM masks, can achieve a productivity gain of 30% or more.

[0073] Figure 15 is a table showing the percentage productivity gain for a 1.5 μm line space pattern due to variations in low-intensity mask bias and dose according to exemplary embodiments of the present invention, and Figure 16 is a table showing the percentage productivity gain for a 1.8 μm contact hole pattern due to variations in low-intensity mask bias and dose according to exemplary embodiments of the present invention. The tables in Figures 15 and 16 demonstrate that various redesign optimizations according to exemplary embodiments result in significant improvements in process flow.

[0074] In some embodiments, to address the problem of obtaining consistent results using the dose minimization process described herein, particularly when applied to an entire FPD design layout consisting of patterns with various designs and design rules, a mask rule checker tool can be used to verify rule checks, and a pattern matching tool can be used to find critical patterns. In some embodiments, an FPD OPC model can be applied to eliminate data errors that may occur throughout the field FPD area.

[0075] While the above specification provides a detailed description of specific embodiments of the present invention, it should be understood that many of the details described herein can be substantially modified by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a photomask, (A) A step of receiving initial photomask design data relating to one or more patterns to be formed on the photomask, (B) A step of optimizing the initial photomask design data to minimize the printing exposure energy while maintaining acceptable pattern quality and size, 1. Minimizing printing exposure energy should be set as a priority design rule.

2. Optimize pattern quality and size as secondary design rules.

3. Iteratively resizing the mask design features to determine a range of size bias that satisfies both the priority design rule and the secondary design rule, thereby providing an initial optimized mask design, and 4. Determine the mask deformation mode over the aforementioned range of size bias to determine a mask deformation mode that further optimizes the initial optimized mask design, thereby obtaining the final optimized mask design. Optimization steps, including, (C) A step of generating optimized photomask design data based on the final optimized mask design. A method that includes this.

2. The method according to claim 1, wherein the range of the size bias includes a negative size bias.

3. The method according to claim 1, wherein the range of the size bias includes a positive size bias.

4. The method according to claim 1, wherein the mask deformation mode includes a pattern edge compensation deformation mode.

5. The method according to claim 1, wherein the mask deformation form includes a mask structure deformation form.

6. The method according to claim 1, wherein the mask deformation form includes a scanner illumination shape deformation form.

7. The method according to claim 1, wherein the mask deformation mode includes a pattern edge compensation deformation mode, a mask structure deformation mode, a scanner illumination shape deformation mode, and combinations thereof.

8. The method according to claim 1, further comprising the step of performing optical proximity effect correction on the optimized photomask design data.

9. The method according to claim 1, further comprising the step of providing a mask blank.

10. The method according to claim 9, further comprising the step of processing the mask blank using the optimized photomask design data to form a photomask for use in a lithography process.

11. The method according to claim 10, wherein the photomask is a large photomask for use in a lithography process to manufacture a flat panel display (FPD).

12. A method for forming a flat panel display, comprising the step of irradiating a glass plate substrate with light from a light energy source through a large photomask formed according to the method of claim 11 in a photolithography process, wherein at least one circuit pattern is transferred from the large photomask to the glass plate substrate.

13. The method according to claim 12, wherein the flat panel display is a liquid crystal display, an active-matrix liquid crystal display, an organic light-emitting diode, a light-emitting diode, a plasma display panel, or an active-matrix organic light-emitting diode.

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