Display panel and method for manufacturing the same

Abstract

To provide a display panel with high resolution and a manufacturing method of the same.SOLUTION: A display panel comprises: a window containing a display region and a non-display region adjacent to the display region; a color filter layer arranged on the window: a circuit element layer containing a low refraction layer covering the color filter layer and a transistor arranged on the low refraction layer; a light control layer containing division separation walls arranged on the circuit element layer and a light control pattern that is arranged between the division separation walls and contains a quantum dot; and a display element layer arranged on the light control layer and containing a light emission element that contains a first electrode, a second electrode arranged on the first electrode, and a light emission layer that is arranged between the first electrode and the second electrode and generates light. The light is transmitted to the window through the light control layer, the circuit element layer, and the color filter layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a display panel, and more particularly, to a display panel including a light control pattern and a method for manufacturing the display panel.

Background Art

[0002] Display panels include transmissive display panels that selectively transmit source light generated from a light source and emissive display panels that generate source light from the display panel itself. The display panel includes different types of light control patterns by pixels to generate a color image. The light control pattern transmits only a partial wavelength range of the source light or converts the color of the source light. Some light control patterns may not change the color of the source light but may change the characteristics of the light.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a high-resolution display panel and a method for manufacturing the same.

Means for Solving the Problems

[0004] A display panel according to an embodiment includes a window including a display area and a non-display area adjacent to the display area, a color filter layer disposed on the window, a low-refractive-index layer covering the color filter layer, a circuit element layer including a transistor disposed on the low-refractive-index layer, a partition wall disposed on the circuit element layer, and a light control layer including a light control pattern disposed between the partition walls and including quantum dots, a first electrode, a second electrode disposed on the first electrode, and a light-emitting element including a light-emitting layer disposed between the first electrode and the second electrode and generating light, and a display element layer disposed on the light control layer, wherein the light passes through the light control layer, the circuit element layer, and the color filter layer and is transmitted to the window.

[0005] The color filter layer includes first to third filter layers that transmit different types of light and are sequentially stacked on the window, wherein the region that overlaps with the light control pattern is located on only one of the first to third filter layers, and in the remaining region, at least two filter layers are stacked.

[0006] The thickness of the low-refractive-index layer in the region overlapping with the light control pattern is greater than the thickness of the low-refractive-index layer in the other regions.

[0007] The transistor includes a semiconductor pattern comprising a source, an active layer, and a drain, and a gate superimposed on the active layer, wherein the semiconductor pattern does not superimpose on the optical control pattern.

[0008] The circuit element layer is characterized by including a passivation layer disposed on the low refractive index layer, a light-shielding pattern disposed on the passivation layer, a buffer layer covering the light-shielding pattern and on which the semiconductor pattern is disposed, an intervening insulating layer disposed between the active layer and the gate, an intermediate insulating layer covering the gate and the buffer layer, a connecting electrode disposed on the intermediate insulating layer and connecting the source and the first electrode, and a cover insulating layer covering the connecting electrode.

[0009] The light-shielding pattern is characterized by being superimposed on at least a portion of the semiconductor pattern and separated from the light-control pattern.

[0010] The connecting electrode is characterized by penetrating the buffer layer and being connected to the light-shielding pattern.

[0011] The circuit element layer includes a capacitor, and the capacitor is characterized by including a first capacitor electrode disposed on the intervening insulating layer and a second capacitor electrode superimposed on the first capacitor electrode and disposed on the intermediate insulating layer.

[0012] The present invention further includes a pad that overlaps with the non-display area, is positioned on the intermediate insulating layer, and is exposed by the cover insulating layer, wherein the pad contains the same material as the connecting electrode.

[0013] The display element layer is characterized by including a pixel definition film that defines a display aperture superimposed on the light control pattern.

[0014] The present invention includes a dam portion that overlaps with the non-display region and is disposed on the circuit element layer, wherein the dam portion contains the same material as at least one of the dividing partition and the pixel defining film.

[0015] The display element layer is characterized by further including a sealing layer that covers the light-emitting element.

[0016] The light-emitting layer is characterized by generating blue light.

[0017] The display panel is characterized by being curved along an axis that extends in one direction.

[0018] The display panel according to the present invention includes a window divided into an emitting region and a non-emitting region adjacent to the emitting region; a color filter layer disposed on the window and including first to third filter layers that transmit different types of light; a transistor disposed on the color filter layer; an optical control layer superimposed on the corresponding first to third filter layers and including first to third optical control patterns, at least one of which includes quantum dots; and a light-emitting element connected to the corresponding transistor and generating light, wherein only one of the first to third filter layers is disposed on the window that superimposes the emitting region, and the first to third filter layers are stacked on the window that superimposes the non-emitting region.

[0019] The first to third filter layers are sequentially stacked on the window, the first filter layer transmits blue light, the second filter layer transmits green light, and the third filter layer transmits red light.

[0020] The device further includes a low-refractive index layer covering the color filter layer, and the transistor is characterized in that it is separated from the first to third filter layers with the low-refractive index layer in between.

[0021] The thickness of the low-refractive-index layer in the region overlapping with the light-emitting region is greater than the thickness of the low-refractive-index layer in the region overlapping with the non-light-emitting region.

[0022] The invention further includes dividing partitions that demarcate the first to third control patterns, wherein the dividing partitions overlap with the non-luminescent region.

[0023] Each of the light-emitting elements includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode, and each of the light-emitting layer and the second electrode included in each of the light-emitting elements is characterized in that it is a single pattern connected to each other.

[0024] The light generated from the aforementioned light-emitting element is characterized by being blue light.

[0025] The light is transmitted to the window by passing through the light control layer and the color filter layer.

[0026] The manufacturing method of the display panel according to the present invention includes a step of forming a color filter layer on a window, a step of forming a low refractive index layer covering the color filter layer, a step of forming a passivation layer covering the low refractive index layer, a step of forming a circuit element layer including a light shielding pattern disposed on the passivation layer and a transistor connected to the light shielding pattern, a step of forming a partition wall on the circuit element layer, a step of forming a light control pattern including quantum dots formed between the partition walls, and a step of forming a light emitting element disposed on the light control pattern and connected to the transistor.

[0027] The step of forming the color filter layer includes a step of forming a first filter layer on the window and then forming a first opening, a step of forming a second filter layer on the first filter layer and then forming a second opening, and a step of forming a third filter layer on the second filter layer and then forming a third opening.

[0028] In a region overlapping with the light control pattern, openings are formed only in any two of the first to third filter layers of the color filter layer, and the remaining one color filter layer is disposed within the two openings and contacts the window.

[0029] The step of forming the color filter layer, the step of forming the low refractive index layer and an additional low refractive index layer, the step of forming the circuit element layer, the step of forming the light control pattern, and the step of forming the light emitting element are performed by continuous processes on the window.

Effect of the Invention

[0030] According to the present invention, by including a structure in which a color filter layer that selectively transmits light, a circuit-constituting layer, and a light-controlling layer containing quantum dots are sequentially laminated on a window without a separate bonding process, defects such as loss or color mixing of source light due to the thickness of the sealing layer or the thickness of the adhesive layer used in a separate bonding process can be prevented. Furthermore, a slim display panel can be provided. [Brief explanation of the drawing]

[0031] [Figure 1a] This is a perspective view of a display panel according to one embodiment of the present invention. [Figure 1b] This is a perspective view of a curved display panel according to one embodiment of the present invention. [Figure 1c] This is a cross-sectional view of a display panel according to one embodiment of the present invention. [Figure 1d] This is a plan view of a display panel according to one embodiment of the present invention. [Figure 2] This is an equivalent circuit diagram according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view taken along the line I-I' in Figure 1d. [Figure 4] This is a plan view of a display area according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view taken along the line II-II' in Figure 4. [Figure 6a] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 6b] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 6c] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 6d] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 6e] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 6f] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 7a]This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 7b] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 7c] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Figure 7d] This is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. [Modes for carrying out the invention]

[0032] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on top of" or "combined with" another component, it means that it can be directly placed on top of, connected to, or combined with the other component, or that a third component can be placed between them.

[0033] The same drawing symbol refers to the same component. Furthermore, in drawings, the thickness, proportions, and dimensions of components are exaggerated for the sake of effective explanation of the technical content. "and / or" includes all combinations of one or more components defined by the relevant component.

[0034] Terms such as "first," "second," etc., are used to describe a variety of components, but the components are not limited to those defined by these terms. These terms are used solely for the purpose of distinguishing one component from another. For example, within the scope of the present invention, the first component may be called the second component, and similarly, the second component may also be called the first component. A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0035] Furthermore, terms such as "down," "on the lower side," "up," and "on the upper side" are used to describe the relative relationships of the components shown in the drawing. These terms are relative concepts and are described in relation to the direction shown in the drawing.

[0036] Terms such as "includes" or "has" indicate the presence of features, figures, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood not to pre-exist to exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0037] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art in the field to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an overly idealistic or formal sense unless expressly defined herein.

[0038] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0039] Figure 1a is a perspective view of a display panel according to one embodiment of the present invention. Figure 1b is a perspective view of a curved display panel according to one embodiment of the present invention. Figure 1c is a cross-sectional view of a display panel according to one embodiment of the present invention. Figure 1d is a plan view of a display panel according to one embodiment of the present invention. Figure 2 is an equivalent circuit diagram according to one embodiment of the present invention.

[0040] The display panels DP and DP-A shown in Figures 1a and 1b are light-emitting display panels, and are any one of the following, but are not particularly limited: liquid crystal display panel, electrophoretic display panel, microelectromechanical system display panel, electrowetting display panel, organic light-emitting display panel, and inorganic light-emitting display panel.

[0041] Referring to Figure 1a, the display panel DP displays an image via the display surface DP-IS. The display surface DP-IS is parallel to the planes defined by the first direction DR1 and the second direction DR2. The upper surface of the member located on the uppermost side of the display panel DP is defined as the display surface DP-IS. According to the present invention, the upper surface of the window WD shown in Figure 1c is defined as the display surface DP-IS of the display panel DP.

[0042] The display surface DP-IS is parallel to the planes defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DP-IS, i.e., the thickness direction of the display panel DP, is the third direction DR3. The front (or top) and back (or bottom) of each layer or unit described below are separated by the third direction DR3.

[0043] The display panel DP includes a display area DA and a non-display area NDA. Pixels PX are arranged in the display area DA, and pixels PX are not arranged in the non-display area NDA. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA surrounds the display area DA. In one embodiment of the present invention, the non-display area NDA may be omitted or arranged only on one side of the display area DA.

[0044] In one embodiment of the present invention, a display panel DP equipped with a planar display surface DP-IS is shown, but the invention is not limited thereto. The display panel DP may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas that indicate different directions from one another.

[0045] For example, referring to Figure 1b, the display panel DP-A in one embodiment is curved along the first direction DR1 with respect to a virtual axis that extends in the second direction DR2. However, it is not limited to this, and the axis may extend in the first direction DR1, or it may be curved with respect to multiple axes that extend in different directions.

[0046] Furthermore, the display panel is either a retractable display panel, a foldable display panel, or a sliding display panel. The display panel has a flexible nature and is installed on the display device and can be folded or rolled up.

[0047] Referring to Figure 1c, the display panel DP according to the present invention includes a window WD, a color filter layer CFL disposed on the window WD, a circuit element layer DP-CL disposed on the color filter layer CFL, an optical control layer OSL disposed on the circuit element layer DP-CL, and a display element layer DP-OLED disposed on the optical control layer OSL.

[0048] In the present invention, window WD is a base layer formed by vapor deposition and patterning of the display panel DP. Window WD contains an optically transparent insulating material. For example, window WM may include a glass substrate or a synthetic resin film.

[0049] The color filter layer (CFL) is positioned above the window (WD). The color filter layer (CFL) contains multiple filter layers. Each filter layer transmits light within a specific wavelength range and blocks light outside that range. This selectively transmits the light that has passed through the optical control layer (OSL) to the window (WD).

[0050] The circuit element layer DP-CL is located above the color filter layer CFL. The circuit element layer DP-CL contains the drive circuit or signal lines for the pixel PX.

[0051] The optical control layer (OSL) is located on top of the circuit element layer (DP-CL). The OSL includes an optical control pattern that alters the optical properties of the source light provided by the light-emitting element. The optical control pattern includes quantum dots.

[0052] The display element layer DP-OLED is placed on top of the light control layer OSL. The display element layer DP-OLED includes light-emitting elements, which are arranged for each pixel PX, and a sealing layer that seals the light-emitting elements.

[0053] According to the present invention, the stacking order of the window WD, color filter layer CFL, circuit element layer DP-CL, light control layer OSL, and display element layer DP-OLED is in the opposite direction to the direction in which the light generated by the display element layer DP-OLED passes through the window WD.

[0054] Referring to Figure 1d, the spatial arrangement of signal lines GL1-GLn, DL1-DLm, and pixels PX11-PXnm is shown. Each signal line GL1-GLn and DL1-DLm includes multiple gate lines GL1-GLn and multiple data lines DL1-DLm.

[0055] Each of the pixels PX11 to PXnm is connected to a corresponding gate line from among multiple gate lines GL1 to GLn and a corresponding data line from among multiple data lines DL1 to DLm. Each of the pixels PX11 to PXnm includes a pixel driving circuit and a display element. The display panel DP is provided with even more types of signal lines depending on the configuration of the pixel driving circuit for each of the pixels PX11 to PXnm.

[0056] Figure 1d shows an illustrative matrix of pixels PX11 to PXnm, but is not limited to this arrangement. Pixels PX11 to PXnm may also be arranged in a diamond-like, pentile (registered trademark) pattern. The gate driver circuit GDC is integrated into the display panel DP by an OSG (oxide silicon gate driver circuit) or ASG (amorphose silicon gate driver circuit) process.

[0057] Referring to Figure 2, pixel PXij includes an OLED light-emitting element, a plurality of transistors T1-T3, and a capacitor Cst. The plurality of transistors T1-T3 are formed by an LTPS (Low Temperature Polycrystalline Silicon) process or an LTPO (Low Temperature Polycrystalline Oxide) process.

[0058] Figure 2 illustrates pixel PXij connected to the i-th first gate line SCLi, SSLi, the j-th data line DLj, and the j-th reference line RLj.

[0059] The i-th first gate line SCLi, SSLi receives the i-th gate signal SCi, SSi. The i-th gate signal SCi, SSi includes the i-th write gate signal SCi and the i-th sampling gate signal SSi.

[0060] Transistors T1 to T3 include a drive transistor T1, a first switch transistor T2, and a second switch transistor T3.

[0061] Transistors T1 to T3 are NMOS transistors, but are not limited to NMOS transistors; PMOS transistors may also be used. Each of transistors T1 to T3 includes sources S1, S2, and S3, drains D1, D2, and D3, and gates G1, G2, and G3.

[0062] An OLED (Organic Light-Emitting Device) is an organic light-emitting device that includes an anode (first electrode) and a cathode (second electrode). A first voltage ELVDD is supplied to the anode of the OLED via a drive transistor T1, and a second voltage ELVSS is supplied to the cathode of the OLED. The OLED emits light when supplied with the first voltage ELVDD and the second voltage ELVSS.

[0063] The drive transistor T1 includes a source S1 to which a first voltage ELVDD is supplied, a drain D1 connected to the anode of the light-emitting element OLED, and a gate G1 connected to the capacitor Cst.

[0064] The first switch transistor T2 includes a source S2 connected to the j-th data line DLj, a drain D2 connected to a capacitor Cst, and a gate G2 supplied with the i-th write gate signal SCi. The j-th data line DLj receives the data voltage Vd and the sensing data voltage.

[0065] The second switching transistor T3 includes a drain D3 connected to the j-th reference line RLj, a source S3 connected to the anode of the light-emitting element OLED, and a gate G3 to which the i-th sampling gate signal SSi is supplied. A reference voltage Vr is supplied to the j-th reference line RLj.

[0066] The capacitor Cst is connected to the gate G1 of the driving transistor T1 and the anode of the light-emitting element OLED. The capacitor Cst includes a first capacitor electrode connected to the gate G1 of the driving transistor T1 and a second capacitor electrode connected to the anode of the light-emitting element OLED.

[0067] In the present invention, the equivalent circuit of pixel PXij is not limited to the equivalent circuit shown in Figure 2. In other embodiments of the present invention, pixel PXij may be embodied in various forms for emitting light from the light-emitting element OLED.

[0068] Figure 3 is a cross-sectional view taken along the line I-I' in Figure 1d.

[0069] Referring to Figure 3, the display panel DP according to this embodiment includes a window WD, a color filter layer CFL, a circuit element layer DP-CL, an optical control layer OSL, and a display element layer DP-OLED.

[0070] The window WD contains an optically transparent insulating material. For example, the window WM may contain a glass substrate or a synthetic resin film.

[0071] If the window WD is a synthetic resin film, then the window WD includes a polyimide (Pl) film or a polyethylene terephthalate (PET) film.

[0072] The window WD has a multilayer or single-layer structure. For example, the window WD may include multiple synthetic resin films bonded together with an adhesive, or it may include a glass substrate and a synthetic resin film bonded together with an adhesive. Although not shown, the window WD further includes functional layers such as an anti-fingerprint layer and an impact-absorbing layer.

[0073] The color filter layer CFL is positioned above the window WD. The color filter layer CFL includes the first to third filter layers CF1, CF2, and CF3. Each of the first to third filter layers CF1, CF2, and CF3 transmits light within a specific wavelength range and blocks light outside that wavelength range.

[0074] In this embodiment, in the region overlapping with the light-emitting region PXA, the second filter layer CF2 includes a second aperture OP2, and the third filter layer CF3 includes a third aperture OP3. Therefore, in the region overlapping with the light-emitting region PXA, only the first filter layer CF1 is placed on the window WD. In this case, if the first filter layer CF1 transmits blue light and blocks red and green light, then the light-emitting region PXA in this embodiment is a region that transmits only blue light. Figure 3 shows the direction in which the light generated by the light-emitting element OLED is supplied to the window WD with arrows.

[0075] Therefore, in the light-emitting region PXA and adjacent light-emitting regions not shown, only the second filter layer CF2 or the third filter layer CF3 is placed above the window WD, thereby defining light-emitting regions that selectively transmit red or green light.

[0076] The circuit element layer DP-CL is placed on top of the color filter layer CFL. The circuit element layer DP-CL includes multiple insulating layers 10-60, a transistor, a capacitor Cst, and a pad PD. Figure 3 shows an example of the driving transistor T1 among the transistors T1-T3 described in Figure 2.

[0077] The low-refractive-index layer 10 is positioned on top of the color filter layer CFL and covers the first to third filter layers CF1, CF2, and CF3. The low-refractive-index layer 10 contains either an inorganic material or an organic material. For example, the inorganic material includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. For example, the organic material includes a silicon-based resin and hollow silica.

[0078] The low-refractive-index layer 10 is positioned inside the apertures OP2 and OP3 defined in the first to third filter layers CF1, CF2, and CF3, providing a flat surface. Therefore, the thickness of the low-refractive-index layer 10 differs between the region overlapping with the light-emitting region PXA and the other regions.

[0079] For example, the low-refractive-index layer 10 is positioned within the second and third apertures OP2 and OP3 defined in the light-emitting region PXA. Therefore, in the region overlapping with the light-emitting region PXA, the first thickness TH1 of the low-refractive-index layer 10 is greater than the second thickness TH2 of the low-refractive-index layer 10 in regions other than the light-emitting region PXA.

[0080] The low refractive index layer 10 is in contact with the first filter layer CF-E, which is superimposed on the light-emitting region PXA of the first filter layer CF1.

[0081] The passivation layer 20 is placed on top of the low refractive index layer 10. The passivation layer 20 contains an inorganic substance. For example, the passivation layer 20 contains at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0082] The light-shielding pattern BML is placed on the passivation layer 20. The light-shielding pattern BML overlaps with at least a portion of the semiconductor patterns S1, A1, and D1, but does not overlap with the light-emitting region PXA. The light-shielding pattern BML contains a metal. For example, the light-shielding pattern BML contains molybdenum Mo.

[0083] The light-shielding pattern BML protects semiconductor patterns S1, A1, and D1 from light incident through the window WD. Specifically, by positioning the light-shielding pattern BML beneath the drive transistor T1, it prevents the residual voltage characteristics of semiconductor patterns S1, A1, and D1 from degrading due to external light. This provides a display panel DP with improved reliability.

[0084] Furthermore, even when the light-shielding pattern BML is placed between the light-emitting element OLED and the color filter layer CFL, it does not reduce the light emission efficiency of the light-emitting element OLED.

[0085] The buffer layer 30 is placed on top of the passivation layer 20 and covers the light-shielding pattern BML. The buffer layer 30 improves the bonding force between the low-refractive index layers 10, 20 and the semiconductor pattern. The buffer layer 30 contains an inorganic material. For example, the buffer layer 30 contains at least one of silicon oxide and silicon nitride. Alternatively, the buffer layer 30 may consist of alternating layers of silicon oxide and silicon nitride.

[0086] The semiconductor patterns S1, A1, and D1 included in the drive transistor T1 are placed on a buffer layer 30. An intervening insulating layer 40 is placed in the region of the semiconductor patterns S1, A1, and D1 that overlaps with the active layer A1, and the gate G1 of the drive transistor T1 is placed on the intervening insulating layer 40. The intervening insulating layer 40 and the gate G1 are patterned simultaneously. The active layer A1, source S1, and drain D1 are regions separated by the doping concentration or conductivity of the semiconductor patterns.

[0087] The first capacitor electrode CS1 of capacitor Cst is placed on the intervening insulating layer 40. The first capacitor electrode CS1 and the intervening insulating layer 40 are patterned simultaneously.

[0088] The intermediate insulating layer 50 is placed on top of the buffer layer 30 and covers parts of the semiconductor patterns S1, A1, and D1, as well as the gate G1 and the first capacitor electrode CS1. The intermediate insulating layer 50 contains an organic or inorganic material.

[0089] The connecting electrode CNE, the second capacitor electrode CS2, and the pad PD are placed on top of the intermediate insulating layer 50.

[0090] One side of the connecting electrode CNE penetrates the intermediate insulating layer 50 and is connected to the source S1, electrically connecting the drive transistor T1 and the first electrode AE ​​of the light-emitting element OLED.

[0091] In this embodiment, the other side of the connecting electrode CNE is connected to the light-shielding pattern BML by penetrating the intermediate insulating layer 50 and the buffer layer 30. Thus, a predetermined signal is supplied to the light-shielding pattern BML. However, the configuration is not limited to this; the connecting electrode CNE may be separated from the light-shielding pattern BML, and the light-shielding pattern BML may be arranged in a floating state.

[0092] The second capacitor electrode CS2 is placed on the intermediate insulating layer 50 and superimposed on the first capacitor electrode CS1. The first capacitor electrode CS1, together with the second capacitor electrode CS2, forms a cap.

[0093] The pad PD is positioned so as to overlap with the non-display area (NDA) of the intermediate insulating layer 50. A flexible circuit board on which a drive chip is mounted is attached to the pad PD. The flexible circuit board is connected to the main circuit board.

[0094] The cover insulating layer 60 is placed on top of the intermediate insulating layer 50. The cover insulating layer 60 exposes the upper surfaces of the connecting electrode CNE and the pad PD. Additional electrodes CNE-S are further included on top of the connecting electrode CNE and the pad PD.

[0095] The optical control layer (OSL) includes a partition wall (BK) and an optical control pattern (CCF).

[0096] The dividing partitions BK have a shape that corresponds to the shape of the non-luminescent region on a plane. Therefore, the dividing partitions BK do not overlap with the luminescent region PXA, and a space that overlaps with the luminescent region PXA is provided between the dividing partitions BK.

[0097] The divided partition BK contains a black component (black coloring agent) to block light. The divided partition BK contains a black dye or black pigment mixed with the base resin. In one embodiment, the black component contains carbon black, or a metal such as chromium or an oxide thereof.

[0098] The light control pattern CCF is positioned in the space provided by the partition wall BK. Therefore, the light control pattern CCF superimposes with the light emission region PXA. In addition, the light control pattern CCF superimposes with the apertures OP2 and OP3 defined in the color filter layer CFL.

[0099] The CCF (Color Conversion Pattern) alters the optical properties of the source light provided by the OLED (OLED) light-emitting element. The CCF is a color conversion pattern that converts blue light source light into red or green light within a single light-emitting region (PXA).

[0100] A color conversion pattern includes a base resin and quantum dots mixed (or dispersed) in the base resin. Color conversion patterns that convert each other into different types of light include each other's quantum dots.

[0101] The base resin BR is a medium in which quantum dots are dispersed, and consists of various resin compositions generally referred to as binders. However, it is not limited to these; in this specification, any medium in which quantum dots can be dispersed is referred to as the base resin, regardless of its name, additional functions, constituent materials, etc.

[0102] The base resin is a polymer resin. For example, the base resin may be an acrylic resin, urethane resin, silicone resin, or epoxy resin. The base resin is a transparent resin.

[0103] Furthermore, the CCF (Critical Control Focus) is a transmission pattern that transmits blue light in other light-emitting regions (PXA). In this case, the CCF, as a transmission pattern, contains scattering particles that scatter the received blue light before it is emitted. The CCF improves the brightness of the emitted light relative to the incident light.

[0104] The color conversion pattern further includes scattering particles mixed into the base resin, similar to the transmission pattern described above. These scattering particles are titanium dioxide (TiO2) or silica-based nanoparticles, etc.

[0105] Quantum dots are particles that convert the wavelength of incident light. Quantum dots are materials with a crystalline structure on the size of a few nanometers, consisting of hundreds to thousands of atoms. Due to their small size, they exhibit a quantum confinement effect, resulting in a large energy band gap. When light with a wavelength higher than the band gap is incident on a quantum dot, the quantum dot absorbs the light, becomes suspended, and then falls back to the ground state while emitting light of a specific wavelength. The energy of the emitted light corresponds to the band gap. By adjusting the size and composition of quantum dots, the emission properties due to the quantum confinement effect can be controlled.

[0106] Quantum dots are selected from group II-VI compounds, group I-III-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0107] Group II-VI compounds are binary compounds selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HeTe, MgSe, MgS, and mixtures thereof, AgInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HeSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, C A ternary compound selected from the group consisting of dHgTe, HgZnS, HeZnSe, HeZnTe, MgZnSe, MgZnS, and mixtures thereof, and a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof.

[0108] Group I-III-VI compounds are selected from the group consisting of AgInS2, CuInS2, AgGaS2, CuGaS2, and mixtures thereof, or from quaternary compounds such as AgInGaS2 and CuInGaS2.

[0109] The group III-V compounds are selected from the group consisting of binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. On the other hand, the group III-V compounds further contain group II metals. For example, InZnP may be selected as a III-II-V compound.

[0110] Group IV-VI compounds are selected from the group consisting of binary compounds selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements are selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds are binary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0111] In this case, the binary, ternary, or quaternary compounds are either present within the particle at a uniform concentration, or separated into two states with partially different concentration distributions and present within the same particle.

[0112] A quantum dot has a core-shell structure, consisting of a core and a shell surrounding the core. Alternatively, one quantum dot may have a core / shell structure where it surrounds other quantum dots. The interface between the core and the shell has a concentration gradient, where the concentration of elements in the shell decreases as you move towards the core.

[0113] Quantum dots are particles with a nanometer-scale size. Quantum dots have an emission wavelength spectrum with a full width at half maximum (FWHM) of approximately 45 nm or less, preferably approximately 40 nm or less, and more preferably approximately 30 nm or less. Within this range, color purity and color reproducibility can be improved. Furthermore, since the light emitted through such quantum dots is emitted in all directions, the optical viewing angle is improved.

[0114] Furthermore, the morphology of quantum dots is not limited to those commonly used in this field, but more specifically, spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplate-like particles are used. Quantum dots adjust the hue of the light they emit depending on the particle size, thereby allowing the dots to emit a variety of light hues, such as red, green, and blue light.

[0115] The light-controlled pattern CCF is formed by an inkjet process. After the liquid composition is supplied into the space of the partition wall BK, the composition is polymerized by a thermocuring or photocuring process, and the volume decreases after curing. As a result, a step is created between the upper surface of the partition wall BK and the upper surface of the light-controlled pattern CCF.

[0116] The display element layer DP-OLED includes a light-emitting element OLED, a pixel definition film PDL, and a encapsulation layer TFE.

[0117] The light-emitting OLED includes a first electrode AE, a second electrode CE, and a light-emitting layer EML disposed between the first electrode AE ​​and the second electrode CE.

[0118] The first electrode AE ​​covers the partition wall BK and the light control pattern CCF and is connected to the connecting electrode CNE. In this invention, the first electrode AE ​​is either a transmissive electrode or a semi-transmissive electrode. The material of the first electrode AE ​​is not limited to just one of either a transmissive electrode or a semi-transmissive electrode.

[0119] The light-emitting layer (EML) is positioned between the first electrode (AE) and the second voltage (CE) and provides source light to the optical control pattern (CCF). In this embodiment, the light-emitting layer (EML) generates blue light as source light. The blue light includes wavelengths between 410 nm and 480 nm. The emission spectrum of the blue light has a peak wavelength in the range of 440 nm to 460 nm.

[0120] The second electrode CE is placed on the light-emitting layer EML. The second electrode CE is a reflective electrode. Therefore, the second voltage CE contains at least one of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, and compounds or mixtures thereof (for example, a mixture of Ag and Mg).

[0121] Although not shown in the figures, the light-emitting OLED further includes a hole transport region located between the first electrode AE ​​and the light-emitting layer EML, and an electron transport region located between the light-emitting layer EML and the second electrode CE. The hole transport region includes a hole injection layer and other hole transport layers. The electron transport region includes at least one of a hole blocking layer (not shown), an electron transport layer, and an electron injection layer, but the examples are not limited to these.

[0122] The pixel definition film (PDL) is placed on top of the optical control layer (OSL). A display aperture (D-OP) is defined in the pixel definition film (PDL). The display aperture (D-OP) exposes at least a portion of the first electrode (AE) that overlaps with the light-emitting region (PXA). Thus, the first electrode (AE) is located below the pixel definition film (PDL), while the light-emitting layer (EML) and the second electrode (CE) are located above the pixel definition film (PDL).

[0123] The pixel definition film PDL is an organic layer. The pixel definition film PDL contains a typical black component. The pixel definition film PDL contains a black dye or black pigment mixed with the base resin. In one embodiment, the black component contains carbon black, a metal such as chromium, or an oxide thereof. However, it is not limited to these, and the pixel definition film PDL may be colorless.

[0124] The TFE encapsulation layer covers the OLED light-emitting element. The TFE encapsulation layer has a laminated structure in which an organic layer is placed between inorganic layers. The inorganic layers protect the OLED light-emitting element from external moisture, the organic layers prevent defects such as indentations in the OLED caused by foreign matter introduced during the manufacturing process, and provide a flat surface on the TFE encapsulation layer when a module or frame is bonded to it.

[0125] In this embodiment, the display panel DP further includes a dam section DMP. The dam section DMP is superimposed on the non-display area NDA and is positioned on the circuit element layer DP-CL. The dam section DMP controls the spread of the liquid composition during the manufacturing process of the organic layer of the sealing layer TFE so that the liquid composition does not deviate from a certain area.

[0126] The dam section DMP includes multiple layers. For example, the dam section DMP includes a first dam section DM1 placed on the cover insulating layer 60 and a second dam section DM2 placed on the first dam section DM1. In one embodiment, the dam section DMP contains the same material as at least one of the dividing partition wall BK and the pixel definition film PDL. For example, the first dam section DM1 may contain the same material as the dividing partition wall BK, and the second dam section DM2 may contain the same material as the pixel definition film PDL. However, it is not limited to this, and the dam section DMP may be omitted or have a laminated structure of one or three or more layers, and is not limited to any one embodiment.

[0127] Figure 4 is a plan view of a display area according to one embodiment of the present invention. Figure 5 is a cross-sectional view taken along the line II-II' in Figure 4. Figure 4 exemplifies six light-emitting regions PXA-R, PXA-G, and PXA-B contained in two pixel rows PXL. Figure 5 omits the drive transistor T1 and capacitor Cst described in Figure 3.

[0128] In this embodiment, the three types of light-emitting regions PXA-R, PXA-G, and PXA-B shown in Figure 4 are repeatedly arranged throughout the display region DA (see Figure 1a). Non-light-emitting regions NPXA are arranged around the first to third light-emitting regions PXA-R, PXA-G, and PXA-B. The non-light-emitting regions NPXA define the boundaries between the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, and structures are arranged to prevent color mixing between the first to third light-emitting regions PXA-R, PXA-G, and PXA-B.

[0129] The partition wall BK described in Figure 3 has a shape corresponding to the non-emitting region NPXA, and does not overlap with the first to third emitting regions PXA-R, PXA-G, and PXA-B, but provides an empty space that overlaps with the first to third emitting regions PXA-R, PXA-G, and PXA-B.

[0130] In this embodiment, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, which have the same area on a plane, are shown as examples, but the embodiment is not limited to these. At least two of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have different areas.

[0131] The first to third light-emitting regions PXA-R, PXA-G, and PXA-B are shown as rectangles with rounded corners on a plane, but are not limited to these. On a plane, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have other polygonal shapes such as rhombuses or pentagons.

[0132] One of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B provides third-color light corresponding to the source light, another provides first-color light different from the third-color light, and the remaining one provides second-color light different from both the third-color and first-color light.

[0133] In this embodiment, the first filter layer CF1 transmits blue light and blocks red and green light. The second filter layer CF2 transmits green light and blocks red and blue light. The third filter layer CF3 transmits red light and blocks green light.

[0134] As a result, the third light-emitting region PXA-B provides a third color light corresponding to the source light. In this embodiment, the first light-emitting region PXA-R provides red light, the second light-emitting region PXA-G provides green light, and the third light-emitting region PXA-B provides blue light.

[0135] Referring to Figure 5, the first to third filter layers CF1, CF2, and CF3 of the color filter layer CFL are positioned only in the corresponding light-emitting regions of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B.

[0136] For example, the first filter layer CF1 defines a first aperture OP1 superimposed on the first and second light-emitting regions PXA-R and PXA-G. The second filter layer CF2 defines a second aperture OP2 superimposed on the first and third light-emitting regions PXA-R and PXA-B. The third filter layer CF3 defines a third aperture OP3 superimposed on the second and third light-emitting regions PXA-G and PXA-B.

[0137] Therefore, in the first light-emitting region PXA-R, only a portion C3 of the third filter layer CF3, which transmits red light, is in contact with the window WD, and in the second light-emitting region PXA-G, only a portion C2 of the second filter layer CF2, which transmits green light, is in contact with the window WD. In addition, in the third light-emitting region PXA-B, only a portion C3 of the first filter layer CF1, which transmits blue light, is in contact with the window WD.

[0138] According to the present invention, the non-emitting region NPXA has a structure in which first to third filter layers CF1, CF2, and CF3 are sequentially stacked. The first to third filter layers CF1, CF2, and CF3 sequentially stacked in the non-emitting region NPXA play a role in blocking external light flowing in from the window WD. This prevents defects in which conductive patterns placed on the circuit element layer DP-CL are reflected by external light and become visible.

[0139] In this embodiment, the optical control pattern CCF superimposed on the first and second light-emitting regions PXA-R and PXA-G is a color conversion pattern that converts the blue light source light provided from the light-emitting layer EML into red and green light. Therefore, it contains different quantum dots. Furthermore, the optical control pattern CCF superimposed on the third light-emitting region PXA-B is a transmission pattern.

[0140] In this embodiment, the first electrode AE ​​included in multiple light-emitting OLEDs is individually patterned and placed on the corresponding light-emitting region. At least one of the light-emitting layer EML and the second electrode CE is provided as a single pattern, commonly arranged in multiple light-emitting OLEDs. Although not shown, at least one of the hole control layer placed between the first electrode AE ​​and the light-emitting layer EML and the electron control layer placed between the light-emitting layer EML and the second electrode CE is also provided as a single pattern, and the embodiment is not limited to any one of these examples.

[0141] According to the present invention, the transistor T1 (see Figure 3) constituting the pixel PX (see Figure 1a), the layer containing the light-emitting element OLED, the light control layer containing quantum dots, and the color filter layer that selectively transmits light are directly placed on the window WD without a separate bonding process. This prevents defects in which source light is lost or mixed due to the thickness of the sealing layer TFE or the thickness of the adhesive layer used in a separate bonding process. Furthermore, a slim display panel DP can be provided.

[0142] Figure 6a is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 6b is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 6c is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 6d is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 6e is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 6f is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention.

[0143] Figure 7a is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 7b is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 7c is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention. Figure 7d is a cross-sectional view showing a method for manufacturing a display panel according to one embodiment of the present invention.

[0144] Figures 6a to 6f are stepwise cross-sectional views showing how to form the color filter layer on top of the window WD described in Figures 3 and 5, and Figures 7a to 7d are cross-sectional views showing how to form the other components of the display panel DP on top of the color filter layer CFL formed in Figures 6a to 6f.

[0145] The method for manufacturing a display panel according to one embodiment of the present invention will be described below with reference to Figures 6a to 7d.

[0146] Referring to Figures 6a and 6b, a method for manufacturing a display panel according to one embodiment includes the step of forming an initial first filter layer CF1-A on a window WD. The initial first filter layer CF1-A is formed to overlap first to third light-emitting regions PXA-R, PXA-G, PXA-B and a non-light-emitting region NPXA.

[0147] The initial first filter layer CF1-A is formed by coating a base resin and a substance containing dyes and / or pigments dispersed in the base resin onto the window WD.

[0148] Next, the process includes forming a first filter layer CF1 which includes a first aperture OP1 formed through the initial first filter layer CF1-A. The first aperture OP1 overlaps with the first and second light-emitting regions PXA-R and PXA-G. Thus, the window WD is exposed from the first filter layer CF1 by the first aperture OP1.

[0149] Next, referring to Figures 6c and 6d, a method for manufacturing a display panel according to one embodiment includes the step of forming an initial second filter layer CF2-A on a first filter layer CF1. The initial second filter layer CF2-A is formed to overlap the first to third light-emitting regions PXA-R, PXA-G, PXA-B and the non-light-emitting region NPXA.

[0150] The initial second filter layer CF2-A is formed by coating a base resin and a substance containing dyes and / or pigments dispersed in the base resin onto the window WD.

[0151] Next, the process includes forming a second filter layer CF2 which includes a second aperture OP2 formed by penetrating the initial second filter layer CF2-A. The second aperture OP2 overlaps the first and third light-emitting regions PXA-R and PXA-B. Thus, the window WD overlapping with the first light-emitting region PXA-R is exposed from the second filter layer CF2 by one of the second apertures OP2. Also, the first filter layer CF1 overlapping with the third light-emitting region PXA-B is exposed from the second filter layer CF2 by the other second aperture OP2.

[0152] Next, referring to Figures 6e and 6f, a method for manufacturing a display panel according to one embodiment includes the step of forming an initial third filter layer CF3-A on the second filter layer CF2. The initial third filter layer CF3-A is formed to overlap the first to third light-emitting regions PXA-R, PXA-G, PXA-B and the non-light-emitting region NPXA.

[0153] The initial third filter layer CF3-A is formed by coating a base resin and a substance containing dyes and / or pigments dispersed in the base resin onto the window WD.

[0154] Next, the process includes forming a third filter layer CF3 which includes a third aperture OP3 formed by penetrating the initial third filter layer CF3-A. The third aperture OP3 overlaps with the second and third light-emitting regions PXA-G and PXA-B. Thus, the second filter layer CF2, which overlaps with the third light-emitting region PXA-G, is exposed from the third filter layer CF3 by one of the third apertures OP3. Also, the first filter layer CF1, which overlaps with the third light-emitting region PXA-B, is exposed from the third filter layer CF3 by the other third aperture OP3.

[0155] Figure 7a is the same as the color filter layer CFL formed in Figures 6a to 6f.

[0156] Referring to Figure 7b, a method for manufacturing a display panel according to one embodiment includes the step of forming a plurality of insulating layers 10, 20, 30, and 50 that are placed on a color filter layer CFL. According to the present invention, the plurality of insulating layers 10, 20, 30, and 50 formed on the color filter layer CFL are carried out in a continuous process on the color filter layer CFL without a separate bonding process.

[0157] In Figure 3, the intervening insulating layer 40 and the cover insulating layer 60 are omitted from the explanation of the insulating layers.

[0158] The step of forming the insulating layers 10, 20, 30, and 50 includes the step of forming multiple conductive patterns to be placed between the insulating layers 10, 20, 30, and 50. The conductive patterns include the process of forming transistors T1 to T3, capacitor Cst, and light-shielding pattern BML as described in Figure 2. On the color filter layer CFL, the circuit element layer DP-CL (see Figure 3) is formed by a patterning process of insulating layers, semiconductor layers, and conductive layers using a photolithography process, following processes such as coating and vapor deposition.

[0159] Next, referring to Figure 7c, a method for manufacturing a display panel according to one embodiment includes the step of forming a segmented partition wall BK and a light control pattern CCF. The segmented partition wall BK is formed by coating and patterning a dye and / or pigment mixed with a base resin onto the uppermost insulating layer 50. The segmented partition wall BK is patterned to overlap with a non-luminescent region NPXA.

[0160] The light-controlled pattern CCF is formed by an inkjet process. A liquid composition is applied between the corresponding segmented partition walls BK, and then cured by a thermocuring or photocuring process. During this process, the volume of the polymerized composition decreases, and a step is created between the upper surface of the segmented partition walls BK and the light-controlled pattern CCF.

[0161] Next, referring to Figure 7d, the method for manufacturing a display panel according to one embodiment includes the step of forming a light-emitting OLED.

[0162] The first electrode AE ​​is formed by coating a semi-transparent or transmissive material onto the partition wall BK and the light control pattern CCF, and then patterning it to overlap the corresponding first to third light-emitting regions PXA-R, PXA-G, and PXA-B. Thus, the first electrodes contained in each light-emitting element OLED are separated from each other.

[0163] A pixel definition film (PDL) is formed on the first electrode (AE). After applying an organic material to the pixel definition film (PDL), the portion overlapping with the first electrode (AE) is removed to form a display aperture.

[0164] Next, the process includes forming an emissive layer (EML) and a second electrode (CE) on the pixel definition film (PDL). The emissive layer (EML) in each light-emitting OLED is formed as a single pattern and provides the same source light to the first to third light-emitting regions (PXA-R, PXA-G, PXA-B). The second electrode (CE) is also formed as a single pattern on the emissive layer (EML). The second electrode (CE) is formed by coating a reflective material. The process then further includes forming a encapsulation layer (TFE) that covers the light-emitting OLED.

[0165] The method for manufacturing a display panel according to the present invention involves forming a color filter layer CFL, a circuit element layer DP-CL (see Figure 3), a light control layer OSL (see Figure 3), and a display element layer DP-OLED on a window WD in a continuous process without a separate bonding step. This improves the misalignment problem that occurs in the process of bonding a separate substrate, and makes it possible to provide a slim display panel.

[0166] Although preferred embodiments of the present invention have been described so far with reference, a person skilled in the art or with ordinary knowledge in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and technical domain of the invention as described in the claims below.

[0167] Therefore, the technical scope of the present invention is not limited to what is described in the detailed description of the specification, but should be determined by the claims. [Explanation of symbols]

[0168] DP: Display Panel WD: Window DP-CL: Circuit element layer BML: Light-shielding pattern CFL: Color filter layer CF1: First filter layer CF2: Second filter layer CF3: Third filter layer DP-OLED: Display element layer OSL: Light control layer BK: Divided partition wall CCF: Light control pattern

Claims

1. A window including a display area and a hidden area adjacent to the display area, A color filter layer placed on the aforementioned window, A circuit element layer including a low refractive index layer covering the color filter layer and a transistor disposed on the low refractive index layer, A light control layer comprising: a divided partition wall disposed on the circuit element layer; and a light control pattern including quantum dots, disposed between the divided partition walls. A display element layer disposed on the optical control layer includes a light-emitting element comprising a first electrode, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode to generate light, Includes, The light is transmitted to the window of the display panel by passing through the light control layer, the circuit element layer, and the color filter layer.

2. The aforementioned color filter layer is It includes first to third filter layers that transmit different types of light and are sequentially stacked on the window, The region that overlaps with the aforementioned light control pattern is located in only one of the first to third filter layers. The display panel according to claim 1, characterized in that at least two filter layers are stacked in the other areas.

3. The thickness of the low-refractive index layer in the region overlapping with the aforementioned optical control pattern is, The display panel according to claim 2, characterized in that the thickness of the low refractive index layer in the other regions is greater than that of the display panel according to claim 2.

4. The transistor includes a semiconductor pattern comprising a source, an active layer, and a drain, and a gate superimposed on the active layer. The display panel according to claim 1, characterized in that the semiconductor pattern does not overlap with the optical control pattern.

5. The circuit element layer is A passivation layer is placed on the low refractive index layer, A light-shielding pattern placed on the passivation layer, A buffer layer covering the light-shielding pattern and on which the semiconductor pattern is arranged, An intervening insulating layer is disposed between the active layer and the gate, An intermediate insulating layer covering the gate and buffer layer, A connecting electrode is disposed on the intermediate insulating layer and connects the source and the first electrode, The display panel according to claim 4, characterized in that it includes a cover insulating layer that covers the connecting electrode.

6. The display panel according to claim 5, characterized in that the light-shielding pattern is superimposed on at least a portion of the semiconductor pattern and separated from the light control pattern.

7. The display panel according to claim 5, characterized in that the connecting electrode penetrates the buffer layer and is connected to the light-shielding pattern.

8. The circuit element layer includes a capacitor, The aforementioned capacitor is A first capacitor electrode is disposed on the aforementioned insulating layer, A second capacitor electrode is superimposed on the first capacitor electrode and placed on the intermediate insulating layer, The display panel according to claim 5, characterized by including the following:

9. The present invention further includes a pad that overlaps with the non-display area, is positioned on the intermediate insulating layer, and is exposed by the cover insulating layer, The display panel according to claim 5, characterized in that the pad contains the same material as the connecting electrode.

10. The aforementioned display element layer is The display panel according to claim 1, characterized in that it includes a pixel defining film in which a display aperture superimposed on the light control pattern is defined.

11. It includes a dam portion that overlaps with the non-display region and is positioned on the circuit element layer, The display panel according to claim 10, characterized in that the dam portion contains the same material as at least one of the dividing partition wall and the pixel defining film.

12. The display panel according to claim 1, characterized in that the display element layer further includes a sealing layer that covers the light-emitting element.

13. The display panel according to claim 1, characterized in that the light-emitting layer generates blue light.

14. The display panel according to claim 1, characterized in that the display panel is curved along an axis that extends in one direction.

15. A window divided into an emitting region and a non-emitting region adjacent to the emitting region, A color filter layer is placed on the aforementioned window and includes first to third filter layers that transmit different types of light from each other. A transistor placed on the aforementioned color filter layer, An optical control layer superimposed on the corresponding first to third filter layers, the optical control layer including at least one of the first to third optical control patterns which includes quantum dots, Includes a light-emitting element connected to the corresponding transistor and generating light, A display panel in which, among the windows, only one of the first to third filter layers is placed on the window that overlaps with the light-emitting region, and the first to third filter layers are stacked on the window that overlaps with the non-light-emitting region.

16. The first to third filter layers are sequentially stacked on the window, The first filter layer transmits blue light, The second filter layer transmits green light, The display panel according to claim 15, characterized in that the third filter layer transmits red light.

17. The color filter layer further includes a low refractive index layer covering the aforementioned color filter layer, The display panel according to claim 15, characterized in that the transistor is separated from the first to third filter layers with the low refractive index layer in between.

18. The thickness of the low-refractive index layer in the region overlapping with the light-emitting region is, The display panel according to claim 17, characterized in that the thickness of the low refractive index layer in the region overlapping with the non-luminescent region is greater than the thickness of the low refractive index layer in the region overlapping with the non-luminescent region.

19. The system further includes dividing partitions that demarcate the first to third control patterns, The display panel according to claim 15, characterized in that the dividing partition wall overlaps with the non-luminescent region.

20. Each of the aforementioned light-emitting elements is It includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode, The display panel according to claim 15, characterized in that at least one of the light-emitting layer and the second electrode contained in each of the light-emitting elements is a single pattern connected to each other.

21. The display panel according to claim 15, characterized in that the light generated from the light-emitting element is blue light.

22. The display panel according to claim 15, characterized in that the light is transmitted to the window by passing through the light control layer and the color filter layer.

23. The steps include forming a color filter layer on top of the window, The steps include forming a low refractive index layer covering the color filter layer and a passivation layer covering the low refractive index layer, The steps include forming a circuit element layer which includes a light-shielding pattern disposed on the passivation layer and a transistor connected to the light-shielding pattern, The steps include forming a partition wall on the circuit element layer, The steps include forming a light-controlled pattern containing quantum dots between the partition walls, A method for manufacturing a display panel, comprising the step of forming a light-emitting element that is arranged on the light control pattern and connected to the transistor.

24. The step of forming the color filter layer is, The steps include forming a first filter layer on the window and then forming a first opening, The steps include forming a second filter layer on the first filter layer and then forming a second opening, A method for manufacturing a display panel according to claim 23, characterized by comprising the step of forming a third filter layer on the second filter layer and then forming a third opening.

25. In the region overlapping with the aforementioned light control pattern, an opening is formed in only two of the first to third filter layers, The remaining color filter layer is, The method for manufacturing a display panel according to claim 24, characterized in that it is arranged within the two openings and in contact with the window.

26. The method for manufacturing a display panel according to claim 23, characterized in that the steps of forming the color filter layer, forming the low refractive index layer and an additional low refractive index layer, forming the circuit element layer, forming the light control pattern, and forming the light-emitting element are carried out in a continuous process on the window.

Images