System and method for identifying local foci during inspection in charged particle systems

Abstract

Apparatus, systems, and methods for determining local focal points (LFPs) on a sample are provided. In some embodiments, a controller including circuitry can be configured to cause the system to: select a first plurality of resist pattern designs; perform a plurality of process simulations using the first plurality of resist pattern designs; identify hot spots corresponding to the resist pattern designs based on results of the performed process simulations; identify focus-related properties corresponding to a plurality of candidate resist pattern designs, where the plurality of candidate resist pattern designs are a subset of the first plurality of resist pattern designs, where the subset is selected based on the identified hot spots; and determine locations of a plurality of LFPs based on the generated focus-related properties.

Description

Technical Field

[0005]

[0001] Cross - reference to Related Applications

[0001] This application claims the priority of U.S. Patent Application No. 63 / 168,197, filed on March 30, 2021, which is hereby incorporated by reference in its entirety.

[0002]

[0002] The present description relates to the field of charged particle beam systems, and more particularly, to a system for identifying local foci of a sample during inspection in an inspection system of a charged particle system.

Background Art

[0003]

[0003] In the manufacturing process of integrated circuits (ICs), unfinished or completed circuit components are inspected to ensure that they are manufactured as designed and free of defects. Inspection systems using optical microscopes typically have a resolution reaching hundreds of nanometers, which is limited by the wavelength of light. As the physical size of IC components continues to shrink to sub - 100, or even further to sub - 10 nanometers, an inspection system with higher resolution than that using an optical microscope is required.

[0004]

[0004] Charged particle (e.g., electron) beam microscopes such as scanning electron microscopes (SEM) or transmission electron microscopes (TEM) capable of resolutions less than 1 nanometer function as practical tools for inspecting IC components with feature sizes of sub - 100 nanometers. When using an SEM, electrons of a single primary electron beam or electrons of multiple primary electron beams can be focused on the target location of the wafer being inspected. The primary electrons can interact with the wafer and be backscattered, or cause the wafer to emit secondary electrons. The intensity of the electron beam including the backscattered electrons and secondary electrons can vary based on the nature of the internal and external structures of the wafer, thereby indicating whether there are defects in the wafer.

Summary of the Invention

[0005] Embodiments of the present disclosure provide apparatus, systems, and methods for determining local foci (LFPs) of a sample. In some embodiments, a controller including circuitry configured to cause the system to: select a first plurality of resist pattern designs; perform a plurality of process simulations using the first plurality of resist pattern designs; identify hotspots corresponding to the resist pattern designs based on the results of the performed process simulations; identify focus-related characteristics corresponding to a plurality of candidate resist pattern designs, wherein the plurality of candidate resist pattern designs are subsets of the first plurality of resist pattern designs, and the subsets are selected based on the identified hotspots; and determine the locations of the plurality of LFPs based on the generated focus-related characteristics.

[0006]

[0006] In some embodiments, a method for determining LFPs on a sample may include selecting a first plurality of resist pattern designs, performing a plurality of process simulations using the first plurality of resist pattern designs, identifying hotspots corresponding to the resist pattern designs based on the results of the performed process simulations, identifying focus-related characteristics corresponding to a plurality of candidate resist pattern designs, wherein the plurality of candidate resist pattern designs are subsets of the first plurality of resist pattern designs, and the subsets are selected based on the identified hotspots, and determining the locations of the plurality of LFPs based on the generated focus-related characteristics.

[0007]

[0007] In some embodiments, a non-temporary computer-readable medium can be runnable by at least one processor of a computing device, thereby storing a set of instructions that cause the computing device to perform a method for determining LFPs on a sample. The method may include selecting a first plurality of resist pattern designs, performing a plurality of process simulations using the first plurality of resist pattern designs, identifying hotspots corresponding to the resist pattern designs based on the results of the performed process simulations, identifying focus-related characteristics corresponding to a plurality of candidate resist pattern designs, wherein the plurality of candidate resist pattern designs are subsets of the first plurality of resist pattern designs, and the subsets are selected based on the identified hotspots, and determining the locations of the plurality of LFPs based on the generated focus-related characteristics. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] This is a schematic diagram showing an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure. [Figure 2]

[0009] This is a schematic diagram showing an exemplary multibeam system, which is part of the exemplary charged particle beam inspection system shown in Figure 1, consistent with embodiments of the present disclosure. [Figure 3]

[0010] This is a schematic diagram of an exemplary system for determining the LFP of a sample, consistent with the embodiments of this disclosure. [Figure 4]

[0011] This is a schematic diagram showing an exemplary contour image of a resist pattern design consistent with the embodiments of this disclosure. [Figure 5]

[0012] This is a schematic diagram showing an exemplary contour image of a resist pattern design consistent with the embodiments of this disclosure. [Figure 6]

[0013] This is a schematic diagram showing a generated SEM image consistent with the embodiments of this disclosure. [Figure 7]

[0014] This flowchart shows an exemplary process for determining the LFP of a sample, consistent with embodiments of the present disclosure. [Modes for carrying out the invention]

[0009]

[0015] Hereinafter, exemplary embodiments are described in detail. Examples of these embodiments are shown in the accompanying drawings. The following description refers to the accompanying drawings, and the same numbers in different drawings represent the same or similar elements unless otherwise noted. The embodiments described in the following description of exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects related to the subject matter enumerated in the accompanying claims. For example, some embodiments are described in relation to the use of electron beams, but the present disclosure is not limited in that way. Other types of charged particle beams can be applied similarly. Furthermore, other imaging systems such as optical imaging, photodetection, X-ray detection, extreme ultraviolet detection, and deep ultraviolet inspection may be used.

[0010]

[0016] Electronic devices consist of circuits formed on a piece of silicon called a substrate. Numerous circuits can be formed together on the same silicon piece, and these are called integrated circuits or ICs. The dimensions of these circuits have been dramatically reduced to allow more circuits to fit on a substrate. For example, an IC chip in a smartphone can be as small as a thumbnail, yet it can contain over 2 billion transistors, each transistor being less than 1 / 1000th the size of a human hair.

[0011]

[0017] Manufacturing these extremely small ICs is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. An error in just one step can result in a defect in the finished IC, rendering it unusable. Therefore, one of the goals of the manufacturing process is to avoid such defects and maximize the number of functional ICs produced in the process, i.e., to improve the overall yield of the process.

[0012]

[0018] One component of improving yield is monitoring the chip fabrication process to ensure that a sufficient number of functional integrated circuits are manufactured. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection may be performed using a scanning electron microscope (SEM). Using an SEM, it is possible to image these very small structures—in short, to take "photographs" of these structures on the wafer. This image can be used to determine whether the structures were formed properly and whether they were formed in the correct locations. If there are defects in the structures, the process can be adjusted to reduce the likelihood of the defects recurring. Defects can occur at various stages of semiconductor processing. For the reasons mentioned above, it is important to find defects as early, accurately, and efficiently as possible.

[0013]

[0019] The operating principle of a scanning electron microscope (SEM) is similar to that of a camera. A camera takes a photograph by receiving and recording the brightness and color of light reflected or emitted from a person or object. A SEM takes a "photograph" by receiving and recording the energy or quantity of electrons reflected or emitted from a structure. Before taking such a "photograph," an electron beam may be provided over the structure, and as electrons are reflected or emitted (emitted) from that structure, the SEM's detector can receive and record the energy or quantity of those electrons to generate an image. To take such a "photograph," some SEMs use a single electron beam (called a "single-beam SEM"), while others use multiple electron beams (called a "multi-beam SEM") to take multiple "photographs" of a wafer. By using multiple electron beams, the SEM can provide more electron beams over the structure to acquire these multiple "photographs," resulting in more electrons emitting from the structure. Therefore, the detector can receive more emitting electrons simultaneously, generating an image of the wafer structure with higher efficiency and at a faster rate.

[0014]

[0020] During inspection, it is advantageous to generate SEM images with higher resolution so that features on the sample (e.g., contacts, metal wires, gates, etc.) in the SEM image accurately represent the actual sample. To generate higher resolution SEM images, the images of features on the sample need to be in focus. To facilitate the acquisition of high-quality focus, multiple points are selected for focus use. These points are called local foci (LFPs). As the sample becomes ready for imaging, the SEM electron beam needs to be focused. To obtain sufficient focus across the sample, such as across the sample at the start of sample inspection and across the field of view (FOV) during FOV scanning preparation, several LFPs on the wafer are located and the electron beam is focused to each of these LFPs.

[0015]

[0021] One example of a problem in the focusing process is selecting an LFP (Light Focusing Panel) that can produce sufficient focus. If a poor focus is selected, it can lead to several potential problems, such as a focus lacking suitable features to enable sufficient focus (e.g., features in the LFP do not have the appropriate density, height, or other properties), susceptibility to charge effects that negatively affect image quality, defects, or susceptibility to damage from the electron beam. Another example is that manual selection of LFPs is a time-consuming process.

[0016]

[0022] In some cases, LFPs may be placed near, rather than on, sample features due to the effects of the SEM inspection itself. SEM inspection involves bombarding the sample with electrons. Because photoresist can be susceptible to electron impact, as a result of SEM inspection, the photoresist may shrink or compress by a non-negligible amount. That is, SEM inspection can damage the photoresist on the sample and alter the sample's pattern. This alteration may lead to altered key performance indicators (e.g., defects, line edge roughness, line width roughness, local critical dimension uniformity, etc.) that do not reflect the true key performance indicators of the sample if not inspected by SEM after development. Therefore, to avoid damaging sample features during inspection, LFPs may be placed near, rather than on, the features on the sample.

[0017]

[0023] LFPs are typically placed on a sample by manually searching the sample for a point to focus on during the examination. In some cases, the LFP is a fixed location on the sample. However, these typical methods for determining LFPs have limitations. For example, manual searching for LFPs on a sample is time-intensive because it requires many iterations to test different points and determine whether or not a point is a suitable LFP. Even after many iterations, manual searching for LFPs may not lead to the determination of the highest quality LFP. Therefore, manual determination of LFPs and fixed LFPs are not robust because they only encompass a limited number of locations on the sample that may not contain the target point during the examination.

[0018]

[0024] Furthermore, inspection can be performed at several stages that vary with different samples. For example, images of a sample can be taken at various stages, particularly after the photoresist applied to the sample has been developed (e.g., after lithography) and after etching. Inspection of developed samples is sometimes desirable because it provides a direct link between the SEM image acquired during inspection and the various exposure process conditions (e.g., focus, dose, etc.) that define the patterning performance. Inspection of developed samples can allow for the optimization of exposure process conditions.

[0019]

[0025] The local fiducial point (LFP) at a fixed location on the sample (the "fixed LFP") is undesirable because sample processing varies across different samples, and for some samples, the fixed LFP may not be near any design target or other point of interest. For example, the fixed LFP may be placed on a hot spot (e.g., an area with a higher likelihood of having a defect), which can result in inaccurate focus height adjustments for inspection. A hot spot is a feature or area on the sample that is less stable during sample processing and, thus, an LFP to be avoided. For example, since a defect can change the focusing characteristics of a location on the sample, an area with a higher likelihood of having a defect can be an undesirable LFP. In some embodiments, the fixed LFP may be aligned with a specific resist pattern design of the wafer design, but this may be undesirable because the sample during inspection may have a higher likelihood of having a defect at the fixed LFP. In these embodiments, the fixed LFP may be undesirable because a defect may affect the alignment of the fixed LFP. In some cases, the fixed LFP can lead to damage to the design target.

[0020]

[0026] Some of the disclosed embodiments provide systems and methods for addressing some or all of these drawbacks by determining a robust and high-quality LFP on the sample, even before or during inspection. The disclosed embodiments can perform process simulations of multiple resists or other patterns to locate hot spots, identify points on the sample that are susceptible to the effects of focusing, and identify imaging characteristics at those points, thereby enabling the determination of the location of a robust and high-quality LFP on the sample.

[0021]

[0027] The relative dimensions of the components in the drawings may be exaggerated for ease of understanding. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and only the differences with respect to individual embodiments are described.

[0022]

[0028] As used herein, unless otherwise specified, the term "or" includes all possible combinations except where it is not feasible. For example, if a component is described as being able to include A or B, unless otherwise specified or infeasible, the component can include A, or B, or A and B. As a second example, if a component is described as being able to include A, B, or C, unless otherwise specified or infeasible, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0023]

[0029] FIG. 1 shows an exemplary electron beam inspection (EBI) system 100 that is consistent with an embodiment of the present disclosure. The EBI system 100 can be used for imaging. As shown in FIG. 1, the EBI system 100 includes a main chamber 101, a load / lock chamber 102, an electron beam tool 104, and an equipment front end module (EFEM) 106. The electron beam tool 104 is disposed inside the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 can include additional loading ports. The first loading port 106a and the second loading port 106b receive a wafer FOUP (front opening unified pod) that houses a wafer to be inspected (e.g., a semiconductor wafer or a wafer made of other materials) or a sample (the wafer and the sample can be used interchangeably). A "lot" is a plurality of wafers that can be loaded for processing as a batch.

[0024]

[0030] One or more robotic arms (not shown) within the EFEM 106 can transport wafers to the loading / locking chamber 102. The loading / locking chamber 102 is connected to a loading / locking vacuum pump system (not shown), which removes gas molecules from within the loading / locking chamber 102 to reach a first pressure lower than atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport wafers from the loading / locking chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules from within the main chamber 101 to reach a second pressure lower than the first pressure. After reaching the second pressure, the wafers are subjected to inspection by an electron beam tool 104. The electron beam tool 104 may be a single-beam system or a multi-beam system.

[0025]

[0031] The controller 109 is electronically connected to the electron beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. In Figure 1, the controller 109 is shown as being outside the structure, which includes the main chamber 101, the loading / locking chamber 102, and the EFEM 106, but it will be understood that the controller 109 can also be part of this structure.

[0026]

[0032] Depending on the embodiment, the controller 109 may include one or more processors (not shown). A processor may be a general-purpose or specific electronic device capable of manipulating or processing information. For example, a processor may include any number of central processing units (i.e., "CPUs"), graphics processing units (i.e., "GPUs"), optical processors, programmable logic control units, microcontrollers, microprocessors, digital signal processors, IP (intellectual property) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), systems-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any kind of circuitry capable of data processing. A processor may also be a virtual processor, including one or more processors distributed across multiple machines or devices connected via a network.

[0027]

[0033] Depending on the embodiment, the controller 109 may further include one or more memories (not shown). The memory may be a general-purpose or specific electronic device capable of storing code and data accessible by the processor (e.g., via a bus). For example, the memory may include any number of random-access memories (RAM), read-only memories (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code may include an operating system (OS) and one or more application programs (i.e., "apps") for a particular task. The memory may also be virtual memory, including one or more memories distributed across multiple machines or devices connected via a network.

[0028]

[0034] Referring here to Figure 2, Figure 2 is a schematic diagram showing an exemplary electron beam tool 104, which includes a multibeam inspection tool that is part of the EBI system 100 of Figure 1, consistent with embodiments of the present disclosure. In some embodiments, the electron beam tool 104 may operate as a single-beam inspection tool that is part of the EBI system 100 of Figure 1. The multibeam electron beam tool 104 (also referred to herein as apparatus 104) includes an electron source 201, a Coulomb aperture plate (or "Gun aperture plate") 271, a focusing lens 210, a source conversion unit 220, a primary projection system 230, a motorized stage 209, and a sample holder 207 supported by the motorized stage 209 for holding a sample 208 to be inspected (e.g., a wafer or photomask). The multibeam electron beam tool 104 may further include a secondary projection system 250 and an electron detection device 240. The primary projection system 230 may include an objective lens 231. The electronic detection device 240 may include a plurality of detection elements 241, 242, and 243. The beam separator 233 and the deflection scanning unit 232 may be located inside the primary projection system 230.

[0029]

[0035] The electron source 201, Coulomb aperture plate 271, focusing lens 210, radiation source conversion unit 220, beam separator 233, deflection scanning unit 232, and primary projection system 230 can be aligned with the primary optical axis 204 of the device 104. The secondary projection system 250 and electron detection device 240 can be aligned with the secondary optical axis 251 of the device 104.

[0030]

[0036] The electron source 201 may include a cathode (not shown) and an extractor or anode (not shown), and during operation, the electron source 201 is configured to emit primary electrons from the cathode, which are extracted or accelerated by the extractor and / or anode to form a primary electron beam 202, which forms a (virtual or real) primary beam crossover 203. The primary electron beam 202 can be visualized as being emitted from the primary beam crossover 203.

[0031]

[0037] The radiation source conversion unit 220 may include an image forming element array (not shown), an aberration compensator array (not shown), a beam limiting aperture array (not shown), and a pre-bending micro-deflector array (not shown). In some embodiments, the pre-bending micro-deflector array deflects multiple primary beamlets 211, 212, 213 of the primary electron beam 202 so that they are incident perpendicularly to the beam limiting aperture array, the image forming element array, and the aberration compensator array. In some embodiments, the device 104 may operate as a single-beam system so that a single primary beamlet is generated. In some embodiments, the focusing lens 210 is designed to focus the primary electron beam 202 so that it becomes a parallel beam and is incident perpendicularly to the radiation source conversion unit 220. The image forming element array may include a plurality of micro-deflectors or microlenses to influence a plurality of primary beamlets 211, 212, and 213 of the primary electron beam 202, and may form a plurality of (virtual or real) parallel images of the primary beam crossover 203, one for each of the primary beamlets 211, 212, and 213. Depending on the embodiment, the aberration compensator array may include a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may include a plurality of microlenses to compensate for the field curvature of the primary beamlets 211, 212, and 213. The astigmatism compensator array may include a plurality of micro-astigmatism correctors to compensate for the astigmatism of the primary beamlets 211, 212, and 213. The beam limiting aperture array may be configured to limit the diameter of the individual primary beamlets 211, 212, and 213. Figure 2 shows three primary beamlets 211, 212, and 213 as an example, and it will be understood that the radiation source conversion unit 220 may be configured to form any number of primary beamlets. The controller 109 can be connected to various parts of the EBI system 100 in Figure 1, such as the radiation source conversion unit 220, the electron detection device 240, the primary projection system 230, or the motorized stage 209. Depending on the embodiment, the controller 109 may perform various image and signal processing functions, as will be described in more detail below.The controller 109 may also generate various control signals to control the operation of the charged particle beam inspection system.

[0032]

[0038] The focusing lens 210 is configured to focus the primary electron beam 202. The focusing lens 210 can be further configured to adjust the currents of the primary beamlets 211, 212, and 213 downstream of the radiation source conversion unit 220 by changing the focusing force of the focusing lens 210. Alternatively, the current can be changed by changing the size of the radius of the beam limiting aperture within the beam limiting aperture array corresponding to each primary beamlet. The current can be changed by changing both the size of the radius of the beam limiting aperture and the focusing force of the focusing lens 210. The focusing lens 210 may be an adjustable focusing lens, which can be configured such that the position of the first principle plane is movable. The adjustable focusing lens may be configured to be magnetic, as a result, the off-axis beamlets 212 and 213 may irradiate the radiation source conversion unit 220 with a rotation angle. The rotation angle changes with the focusing force or the position of the first principle plane of the adjustable focusing lens. The focusing lens 210 may be a rotation-preventing focusing lens that can be configured to keep its rotation angle constant while the focusing force of the focusing lens 210 is changing. In some embodiments, the focusing lens 210 may be an adjustable rotation-preventing focusing lens in which the rotation angle does not change when the focusing force and the position of the first principal plane change.

[0033]

[0039] The objective lens 231 may be configured to focus the beamlets 211, 212, and 213 onto the sample 208 for inspection, and in the present embodiment, three probe spots 221, 222, and 223 may be formed on the surface of the sample 208. The Coulomb aperture plate 271 is configured to reduce the Coulomb effect by blocking peripheral electrons of the primary electron beam 202 during operation. The Coulomb effect can enlarge the size of each of the probe spots 221, 222, and 223 of the primary beamlets 211, 212, and 213, and thus reduce the inspection resolution.

[0034]

[0040] The beam separator 233 may be, for example, a Wien filter including an electrostatic deflector that generates an electrostatic dipole field and a magnetic dipole field (not shown in Figure 2). When in operation, the beam separator 233 can be configured to exert an electrostatic force on the individual electrons of the primary beamlets 211, 212, and 213 by the electrostatic dipole field. The electrostatic force is equal in magnitude to the magnetic force exerted on the individual electrons by the magnetic dipole field of the beam separator 233, but in the opposite direction. Thus, the primary beamlets 211, 212, and 213 can pass through the beam separator 233 at least substantially straight with at least a substantially zero deflection angle.

[0035]

[0041] During operation, the deflection scanning unit 232 is configured to deflect the primary beamlets 211, 212, and 213 to scan probe spots 221, 222, and 223 across individual scan areas within sections of the surface of sample 208. In response to the incidence of the primary beamlets 211, 212, and 213 or probe spots 221, 222, and 223 on sample 208, electrons emerge from sample 208, generating three secondary electron beams 261, 262, and 263. Each of the secondary electron beams 261, 262, and 263 typically contains secondary electrons (with electron energies of 50 eV or less) and backscattered electrons (with electron energies between 50 eV and the landing energies of the primary beamlets 211, 212, and 213). The beam separator 233 is configured to deflect the secondary electron beams 261, 262, and 263 toward the secondary projection system 250. Subsequently, the secondary projection system 250 focuses the secondary electron beams 261, 262, and 263 toward the detection elements 241, 242, and 243 of the electron detection device 240. The detection elements 241, 242, and 243 are configured to detect the corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals that are transmitted to the controller 109 or a signal processing system (not shown) to construct an image of the corresponding scan area of ​​the sample 208, for example.

[0036]

[0042] In some embodiments, detection elements 241, 242, and 243 detect the corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signal outputs (not shown) toward an image processing system (e.g., controller 109). In some embodiments, each detection element 241, 242, and 243 may include one or more pixels. The intensity signal output of a detection element may be the sum of the signals generated by all pixels within the detection element.

[0037]

[0043] Depending on the embodiment, the controller 109 may include an image processing system including an image acquirer (not shown) and storage (not shown). The image acquirer may include one or more processors. For example, the image acquirer may include a computer, server, mainframe host, terminal, personal computer, any type of portable computer device, or a combination thereof. The image acquirer may be communicatively coupled to the electronic detection device 240 of the device 104 via a medium, in particular a conductor, fiber optic cable, portable storage medium, IR, Bluetooth, the Internet, a wireless network, wireless communication, or a combination thereof. Depending on the embodiment, the image acquirer may receive signals from the electronic detection device 240 and construct an image. The image acquirer may thus acquire an image of sample 208. The image acquirer may also perform various post-processing functions, such as generating contour lines and overlaying indicators onto the acquired image. The image acquirer may be configured to perform adjustments such as brightness and contrast of the acquired image. Depending on the embodiment, the storage may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), or other types of computer-readable memory. The storage may be coupled to an image acquirer and can be used to store scanned raw image data as source images and to store processed images.

[0038]

[0044] In some embodiments, the image acquirer may acquire one or more images of a sample based on an imaging signal received from the electronic detection device 240. The imaging signal may correspond to a scan operation for performing charged particle imaging. The acquired image may be a single image containing multiple imaging areas. This single image may be stored in storage. This single image may be a source image that can be divided into multiple regions. Each of these regions may contain one imaging area encompassing a feature of sample 208. The acquired image may include multiple images of a single imaging area of ​​sample 208, sampled multiple times in time series. These multiple images may be stored in storage. In some embodiments, the controller 109 may be configured to perform image processing steps using multiple images of the same location of sample 208.

[0039]

[0045] Depending on the embodiment, the controller 109 may include a measurement circuit (e.g., an analog-to-digital converter) to acquire the distribution of detected secondary electrons. The electron distribution data collected during the detection time window can be used in combination with the corresponding scan data of the primary beamlets 211, 212, and 213 incident on the wafer surface to reconstruct an image of the wafer structure under inspection. The reconstructed image can be used to reveal various features of the internal or external structure of sample 208, thereby revealing any defects that may be present in the wafer.

[0040]

[0046] In some embodiments, the controller 109 may control the motorized stage 209 to move the sample 208 during inspection. In some embodiments, the controller 109 may allow the motorized stage 209 to move the sample 208 continuously at a constant speed in a certain direction. In other embodiments, the controller 109 may allow the motorized stage 209 to change the speed at which the sample 208 moves out of time depending on the step of the scanning process.

[0041]

[0047] Figure 2 shows that the apparatus 104 uses three primary electron beams, but it will be understood that the apparatus 104 may use two or more primary electron beams. This disclosure does not limit the number of primary electron beams used in the apparatus 104. In some embodiments, the apparatus 104 may be a SEM used for lithography. In some embodiments, the electron beam tool 104 may be a single-beam system or a multi-beam system.

[0042]

[0048] Compared to a single-charged particle beam imaging system ("single-beam system"), a multi-beam imaging system ("multi-beam system") can be designed to optimize throughput for different scanning modes. Embodiments of the present disclosure provide a multi-beam system that has the ability to optimize throughput in different scanning modes by using beam arrays with different geometries and adapting to different throughput and resolution requirements.

[0043]

[0049] Figure 3 shows a schematic diagram of system 300 for determining LFP on a sample (e.g., sample 208 in Figure 2). System 300 may include an inspection system 310, a pattern pre-selection server 320, a process response simulation server 330, an image construction and calibration server 340, and a focus target sensitivity server 350. The inspection system 310, pattern pre-selection server 320, process response simulation server 330, image construction and calibration server 340, and focus target sensitivity server 350 may be electrically coupled to each other (directly or indirectly) either physically (e.g., by cables) or remotely. The inspection system 310 may be the system described with respect to Figures 1 and 2, used to acquire an image of a wafer (e.g., sample 208 in Figure 2).

[0044]

[0050] The pattern pre-selection server 320 may include a processor 322 and storage 324. The pattern pre-selection server 320 may also include a communication interface 326 for sending data to the process response simulation server 330. The processor 322 may be configured to receive (e.g., from one or more users) one or more resist pattern designs to be used for developing (e.g., lithography) a sample. The resist pattern design may include one or more layout structures (e.g., layout structure 403 in Figure 4) that can be developed on the sample. The resist pattern design may be stored in a layout file of the wafer design. The layout file may be in Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, Open Artwork System Interchange Standard (OASIS) format, Calteck Intermediate Format (CIF), etc. The wafer design may include patterns or structures to be included on the wafer. The patterns or structures may be mask patterns used to transfer features from a photolithography mask or rectil to the wafer. In some embodiments, the layout in GDS or OASIS format, among other things, may include feature information stored in a binary file format representing flat geometric shapes, text, and other information related to wafer design. In some embodiments, the resist pattern design may correspond to the field of view (FOV) of the inspection system 310 (for example, the FOV of the inspection system 310 may include one or more layout structures of the resist pattern design).

[0045]

[0051] The processor 322 can analyze one or more resist pattern designs and group them by pattern type (e.g., shape type of the resist pattern design). For example, the processor 322 can group resist pattern designs with shapes that include several contact holes in a sample with other resist pattern designs that include the same number of contact holes in a sample. Based on the grouped resist pattern designs, the processor 322 can sample one or more resist pattern designs from each group to determine the LFP. By selecting a representative number of resist pattern designs from each group, the processor 322 can reduce the number of resist pattern designs analyzed by the system 300, thereby lowering the likelihood of repeated analysis of resist pattern designs and, advantageously, increasing system throughput. The pattern pre-selection server 320 can send data containing the selected resist pattern designs to the process response simulation server 330.

[0046]

[0052] The process response simulation server 330 may include a processor 332 and storage 334. The process response simulation server 330 may also include a communication interface 336 to receive data from the pattern pre-selection server 320 and transmit the data to the image construction and calibration server 340. The processor 332 may be configured to receive one or more selected resist pattern designs from the pattern pre-selection server 320. The processor 332 may be configured to generate contour images of the selected resist pattern designs (e.g., contour image 401 in Figure 4, contour images 501, 503, 505, and 507 in Figure 5). In some embodiments, the processor 332 may be configured to run multiple process simulations using the selected resist pattern designs. For example, the processor 332 may receive a set of process variations, and the process simulation may include the received set of process variations during sample (e.g., wafer) processing. In some embodiments, process variations may include at least one set of data defining multiple focus adjustments of light emitted onto a resist pattern on a sample (e.g., a focus height of 280 in Figure 2, where the focal length ranges from negative to positive) or data defining multiple adjustments related to the intensity of light emitted onto the resist pattern (e.g., light dose). In some embodiments, process simulations using a set of process variations may be performed using at least one of the following: a resist model, a development (e.g., lithography) model, an etching model, a scanning model (e.g., a scanner lens model). For example, the models may use known parameters from a physics-based model and materials.

[0047]

[0053] In some embodiments, the processor 332 may perform multiple process simulations for each of the selected resist pattern designs and generate contour images of each resist pattern design based on the process simulations. The processor 332 may generate contour images that show the effect of process variations on each of the resist pattern designs. For example, the generated contour images may show the effect of different focus heights on the resulting sharpness of the resist pattern during sample processing.

[0048]

[0054] In some embodiments, the results of the performed process simulation may include the dimensions of features on the resist pattern. In some embodiments, hotspots (e.g., defects such as necking, bridging, and edge placement errors) may be defined based on the dimensions of features on the resist pattern (e.g., by the user). For example, a threshold (e.g., 20 nm) may be defined so that feature widths on the resist pattern below the threshold are identified as hotspots (e.g., necking) that should be excluded from the determined LFP. In some embodiments, one or more thresholds (e.g., ranges) for the sidewall angles of features may be defined so that the processor 332 determines that features with sidewall angles outside the threshold are hotspots. In some embodiments, the processor 332 may determine a plurality of resist pattern candidates based on the selected resist pattern design, and the plurality of resist pattern candidates exclude resist patterns containing hotspots. In some embodiments, the plurality of resist pattern candidates may include resists containing a limited number of hotspots. The process response simulation server 330 may transmit data including the resist pattern candidates to the image construction and calibration server 340.

[0049]

[0055] The image construction and calibration server 340 may include a processor 342 and storage 344. The image construction and calibration server 340 may also include a communication interface 346 to receive data from the process response simulation server 330 and transmit the data to the focus target sensitivity server 350. The processor 342 may be configured to receive one or more resist pattern design candidates from the process response simulation server 330. The processor 342 may be configured to generate an SEM image (e.g., a grayscale voltage contrast image) of the resist pattern design. In some embodiments, the processor 342 may be configured to run multiple process simulations using the resist pattern design. For example, the processor 342 may receive image parameter variations for use in process simulations, and the process simulations may include simulating the effects of image parameter variations during sample (e.g., wafer) processing. In some embodiments, process variations may include data defining multiple focus adjustments of the electron beam emitted onto the resist pattern on the sample (e.g., focus height between the objective lens and the sample such that the focal length ranges from negative to positive values), shifts in image-related measurements (e.g., brightness or contrast to represent samples containing different materials, inspection tool shifts, sample processing shifts, sample position shifts, noise, etc.), or at least one of the parameters used by the photolithography system when determining the exposure settings for a sample having one or more candidate resist pattern designs. For example, processor 342 may simulate noise during inspection by changing the brightness level of the generated SEM image by a certain percentage. In some embodiments, process simulation using image parameter variations may be performed using at least one of the following: a resist model, a development (e.g., lithography) model, an etching model, a scanning model (e.g., a scanner lens model). For example, the model may use parameters known from a physics-based model and materials.

[0050]

[0056] In some embodiments, the processor 342 may perform multiple process simulations for each of the candidate resist pattern designs and generate SEM images of each resist pattern based on the process simulations. The processor 342 may generate SEM images that show the effect of image parameter variations on each resist pattern. For example, the generated SEM images may show the effect of different focus heights on the resolution obtained as a result of the SEM image of the resist pattern during sample processing.

[0051]

[0057] In some embodiments, the system 300 may operate in real time during inspection so that the image construction and calibration server 340 can receive actual SEM images generated during inspection from the inspection system 310. In some embodiments, the processor 342 may generate SEM images using actual SEM images by adding the effects of process variations to the actual SEM images, as described above. In some embodiments, actual SEM images generated during actual inspection may be used to calibrate inspection tools so that the focusing of the inspection tools is more accurate. In some embodiments, actual SEM images may be used to calibrate models used by the image construction and calibration server 340. For example, the image construction and calibration server 340 may compare key performance indicators (KPIs) of SEM images generated during process simulation (e.g., defects, line edge roughness, line width roughness, local critical dimension, gray level, brightness, contrast, background noise, etc.) with the KPIs of SEM images generated during actual inspection and adjust the parameters of one or more models based on the difference in KPIs between the simulated SEM image and the actual SEM image from inspection. The image reconstruction and calibration server 340 can transmit data, including the generated SEM image, to the focus target sensitivity server 350.

[0052]

[0058] The focus target sensitivity server 350 may include a processor 352 and storage 354. The focus target sensitivity server 350 may also include a communication interface 356 for receiving data from the image construction and calibration server 340. The processor 352 may be configured to receive one or more generated SEM images from the image construction and calibration server 340. The processor 352 may be configured to identify focus-related characteristics of a plurality of resist pattern design candidates based on the generated SEM images. In some embodiments, the focus-related characteristics may include at least one of the following: resist pattern density, number of layout structures in the resist pattern, ratio of acceptable to unacceptable layout structures, sidewall angles in the resist pattern, ratio of acceptable to unacceptable sidewall angles, or charge effects (e.g., pattern shape, pattern surface area, etc.). The processor 352 may be configured to determine a plurality of LFPs in the plurality of resist pattern design candidates based on the identified focus-related characteristics. The LFPs may be determined based on their robustness and location on the resist pattern design candidate that is most susceptible to the effects of focus adjustment. In some embodiments, LFPs may be determined based on weight values ​​assigned to focus-related characteristics (for example, more important focus-related characteristics are assigned larger weight values ​​than less important focus-related characteristics). In some embodiments, the LFPs used during inspection may be selected based on a predetermined number of LFPs (e.g., the top 10% of the highest-ranked LFPs) or one or more of the layout structure coverage on the sample (e.g., based on the number of layout structures in the resist pattern in the FOV, the ratio of acceptable to unacceptable layout structures, etc.).

[0053]

[0059] The resist pattern density can be the number of layout structures in the field of view (FOV). In some embodiments, a higher density of resist patterns may be desirable for LFPs because it can result in more stable focus during lithography. However, in some embodiments, a high density of resist patterns may be undesirable for LFPs because it can lead to reduced resolution, coarse patterns, or defects unsuitable for image focusing. In some embodiments, a lower density of resist patterns may be desirable for LFPs because it can result in more isolated features that are more susceptible to focus issues. However, in some embodiments, a lower density of resist patterns may be undesirable for LFPs because the features may have shorter widths that can be considered hotspots.

[0054]

[0060] In some embodiments, the focus target sensitivity server 350 may include rules defining the characteristics of layout structures that make a layout structure acceptable and those that make it unacceptable. For example, the acceptability of a layout structure may be defined by the minimum or maximum dimensions, pitch, sidewall angle, etc. A resist pattern with a high ratio of acceptable to unacceptable layout structures is desirable for an LFP because it has a higher probability of adjusting the focus to a useful LFP during inspection. In some embodiments, the focus target sensitivity server 350 may include a threshold ratio for determining whether a resist pattern contains an LFP (for example, a resist pattern in which 90% or more of the layout structure is acceptable may be a candidate for an LFP).

[0055]

[0061] In some embodiments, resist patterns with smaller sidewall angles (e.g., steeper sidewalls) may be desirable for LFPs because the focus height along steep sidewalls can change abruptly (e.g., steep sidewalls may be more susceptible to focus sensitivity). In some embodiments, resist patterns with larger sidewall angles (e.g., less steep sidewalls) may be desirable for LFPs because the resist pattern during actual inspection may not have steep sidewalls. In some embodiments, the focus target sensitivity server 350 may include rules defining acceptable and unacceptable ranges of sidewall angles. For example, the rules may include a percentage difference (e.g., + / - 5%) from the nominal (e.g., average) sidewall angle. Resist patterns with a higher ratio of acceptable to unacceptable sidewall angles are desirable for LFPs because they are more likely to adjust focus to a useful LFP during inspection.

[0056]

[0062] In some embodiments, the sample charge may be affected during sample processing. For example, adjustments to the sample material or scanning speed or scanning direction may cause an imbalance in surface charge, which may affect the shape or surface area of ​​the resist pattern. These effects from surface charge imbalance may make focus adjustment more difficult and may make areas with surface charge imbalance undesirable for the LFP.

[0057]

[0063] In some embodiments, the system 300 may output LFPs used during the inspection as a list of coordinates on the sample. In some embodiments, LFPs may be determined by ranking them based on predetermined preferences. For example, the resulting LFPs may be evenly distributed on the sample based on preferences for susceptibility to focus, robust LFPs, or unknown target points on the sample.

[0058]

[0064] Next, refer to Figure 4, a schematic diagram showing an exemplary contour image of a resist pattern design consistent with the embodiments of this disclosure.

[0059]

[0065] As described above, the processor 332 may be configured to generate a contour map 401 of the selected resist pattern design, including the layout structure 403. In some embodiments, the processor 332 may be configured to run multiple process simulations using the selected resist pattern design. In some embodiments, the contour map 401 may show the effect of process variations on the resist pattern design.

[0060]

[0066] In some embodiments, the results of the performed process simulation may include the dimensions of features on the resist pattern. For example, a hotspot 405 may be defined based on the dimensions of features on the resist pattern (e.g., by the user). For example, a hotspot 405 may be determined to be a hotspot based on a width less than a threshold (e.g., 20 nm). As a result, the resist pattern associated with the contour image 401 may be excluded from the determined LFP.

[0061]

[0067] Next, refer to Figure 5, a schematic diagram showing an exemplary contour image of a resist pattern design consistent with the embodiments of this disclosure.

[0062]

[0068] As described above, the processor 332 may be configured to generate contour images 501, 503, 505, and 507 of the selected resist pattern design. In some embodiments, the processor 332 may be configured to perform multiple process simulations using the selected resist pattern design. For example, contour images 501 and 503 may show the effect of simulated etching of the relevant resist pattern and the relevant sample, while contour images 505 and 507 may show the effect of simulated development of the relevant resist pattern and the relevant sample.

[0063]

[0069] In some embodiments, the results of a performed process simulation may include the dimensions of features on the resist pattern. For example, a hotspot may be defined based on the dimensions of features on the resist pattern (e.g., by the user). For example, a hotspot may be determined to be a hotspot based on the width of a feature less than a threshold (e.g., 20 nm). For example, width 511 associated with contour image 501 and width 513 associated with contour image 503 may be below the hotspot threshold, thereby excluding the resist pattern associated with contour images 501 and 503 from the determined LFP. Width 515 associated with contour image 505 and width 517 associated with contour image 507 may exceed the hotspot threshold, thereby including the resist pattern associated with contour images 505 and 507 in the determined LFP.

[0064]

[0070] Next, refer to Figure 6, a schematic diagram showing a generated SEM image consistent with the embodiments of this disclosure.

[0065]

[0071] As described above, the processor 342 may be configured to generate SEM images (e.g., grayscale voltage contrast images) of the resist pattern design candidates. In some embodiments, the processor 342 may be configured to run multiple process simulations using the resist pattern design candidates. In some embodiments, the processor 342 may run multiple process simulations for each of the resist pattern design candidates and generate SEM images of each resist pattern based on the process simulations. The processor 342 may generate SEM images that show the effect of image parameter variations on each resist pattern.

[0066]

[0072] The resist pattern density can be the number of layout structures in the FOV. In some embodiments, denser resist patterns, such as those associated with the generated SEM image 601, may be desirable for LFPs because they can have a more stable focus during lithography. However, in some embodiments, denser resist patterns may be undesirable for LFPs because they can result in reduced resolution, coarser patterns, or defects unsuitable for image focusing. In some embodiments, less dense resist patterns, such as those associated with the generated SEM image 603, may be desirable for LFPs because they can have more isolated features that are more susceptible to focus issues. However, in some embodiments, less dense resist patterns may be undesirable for LFPs because features may have shorter widths that can be considered hotspots.

[0067]

[0073] Refer now to Figure 7, i.e., a flowchart illustrating an exemplary process 700 for determining the LFP on a sample, consistent with embodiments of the present disclosure. The steps of Method 700 can be performed by or using features of a computing device, e.g., a system run on the controller 109 in Figure 1 for illustrative purposes (e.g., system 300 in Figure 3). It will be understood that the illustrated Method 700 can be modified by changing the order of the steps and including additional steps.

[0068]

[0074] In step 701, the system (for example, using the processor 322 in Figure 3) may select a first plurality of resist pattern designs. For example, the system may be configured to receive one or more resist pattern designs (for example, from one or more users) to use for developing (e.g., lithography) a sample. The resist pattern design may include one or more layout structures (for example, layout structure 403 in Figure 4) that can be developed on the sample. In some embodiments, the resist pattern design may correspond to the field of view (FOV) of an inspection system (for example, inspection system 310 in Figure 3) (for example, the FOV of inspection system 310 may include one or more layout structures of the resist pattern design).

[0069]

[0075] The system can analyze one or more resist pattern designs and group them by pattern type (e.g., shape type of the resist pattern design). For example, the system can group resist pattern designs with shapes that include several contact holes in a sample with other resist pattern designs that include the same number of contact holes in a sample. Based on the grouped resist pattern designs, the system can sample one or more resist pattern designs from each group to determine the LFP. By selecting a representative number of resist pattern designs from each group, the system can reduce the number of resist pattern designs analyzed by the system, thereby lowering the likelihood of repeated analysis of resist pattern designs and, advantageously, increasing system throughput.

[0070]

[0076] In step 703, the system (e.g., the process response simulation server 330 in Figure 3) may perform multiple process simulations using a first plurality of resist pattern designs. The system (e.g., the processor 332 in Figure 3) may be configured to generate contour images of the selected resist pattern designs (e.g., contour image 401 in Figure 4, contour images 501, 503, 505, and 507 in Figure 5). The process simulation may include a set of process variations during sample (e.g., wafer) processing. In some embodiments, the process variations may include at least one of data defining a plurality of focus adjustments of light emitted onto the resist pattern on the sample (e.g., focus height between the objective lens and the sample such that the focal length ranges from negative to positive values) or data defining a plurality of adjustments related to the intensity of light emitted onto the resist pattern (e.g., light dose). In some embodiments, the process simulation using the set of process variations may be performed using at least one of the following: a resist model, a development (e.g., lithography) model, an etching model, a scanning model (e.g., a scanner lens model). For example, the model may use known parameters from physics-based models and materials.

[0071]

[0077] In some embodiments, the system may perform multiple process simulations for each of the selected resist pattern designs and generate contour images of each resist pattern design based on each process simulation (for example, in some embodiments, one contour image is generated for each resist pattern design in each process simulation). The system may generate contour images that show the effect of process variations on each of the resist pattern designs. For example, the generated contour images may show the effect of different focus heights on the resulting sharpness of the resist pattern during sample processing.

[0072]

[0078] In step 705, the system (e.g., processor 332 in Figure 3) may identify hotspots (e.g., hotspot 405 in Figure 4) corresponding to the resist pattern design based on the results of the performed process simulation. In some embodiments, the results of the performed process simulation may include the dimensions of features on the resist pattern design. In some embodiments, hotspots (e.g., defects) may be defined based on the dimensions of features on the resist pattern design (e.g., by the user). For example, a threshold (e.g., 20 nm) may be specified so that feature widths on the resist pattern design below the threshold are identified as hotspots (e.g., neckings) that should be excluded from the determined LFP. In some embodiments, one or more thresholds (e.g., ranges) for the sidewall angles of features may be specified so that the system determines that features with sidewall angles outside the threshold are hotspots. In some embodiments, the system may determine a plurality of resist pattern candidates based on the selected resist pattern design, and the plurality of resist pattern candidates exclude resist patterns containing hotspots.

[0073]

[0079] In step 707, the system (e.g., processor 342 in Figure 3) may identify focus-related characteristics corresponding to a plurality of resist pattern design candidates, the plurality of resist pattern design candidates being subsets of a first plurality of resist pattern designs, the subset being selected based on identified hotspots. The system may be configured to generate SEM images (e.g., grayscale voltage contrast images) (e.g., SEM images 601 or 603 in Figure 6) of the resist pattern design candidates. In some embodiments, the system may be configured to perform a plurality of process simulations using the resist pattern design candidates. For example, process simulations may include simulating the effects of image parameter variations during sample (e.g., wafer) processing. In some embodiments, process variations may include data defining the focusing of multiple electron beams directed at a resist pattern on a sample (e.g., adjustment of the focus height between the objective lens and the sample such that the focal lengths range from negative to positive), shifts in image-related measurements (e.g., brightness or contrast to represent samples containing different materials, shifts in the inspection tool, sample processing shifts, sample position shifts, noise, etc.), or at least one of the parameters used by the photolithography system when determining the exposure settings for a sample having one or more candidate resist pattern designs. For example, the system may simulate noise during inspection by varying the brightness level of the generated SEM image by a certain percentage. In some embodiments, process simulations simulating the effects of image parameter variations may be performed using at least one of the following: a resist model, a development (e.g., lithography) model, an etching model, a scanning model (e.g., a scanner lens model). For example, the models may use known parameters from physics-based models and materials.

[0074]

[0080] In some embodiments, the system may perform multiple process simulations for each of the candidate resist pattern designs and generate SEM images of each resist pattern design based on the process simulations. The system may generate SEM images that show the effect of image parameter variations on each resist pattern design. For example, the generated SEM images may show the effect of different focus heights on the resolution obtained as a result of the SEM image of the resist pattern design during sample processing.

[0075]

[0081] The system (for example, the processor 352 in Figure 3) may be configured to identify focus-related characteristics in multiple resist pattern design candidates based on the generated SEM images. In some embodiments, the focus-related characteristics may include at least one of the resist pattern density, the number of layout structures in the resist pattern design, the ratio of acceptable to unacceptable layout structures, the sidewall angle in the resist pattern design, the ratio of acceptable to unacceptable sidewall angles, or the charge effect.

[0076]

[0082] In step 709, the system (e.g., processor 352 in Figure 3) may be configured to determine multiple LFPs on multiple resist pattern design candidates based on identified focus-related characteristics. LFPs may be determined based on their location on the resist pattern design candidate that is robust and most susceptible to focus adjustment. In some embodiments, LFPs may be determined based on weight values ​​assigned to focus-related characteristics (e.g., more important focus-related characteristics are assigned larger weight values ​​than less important focus-related characteristics). In some embodiments, the LFPs used during inspection may be selected based on a predetermined number of LFPs (e.g., the top 10% of the highest-ranked LFPs) or one or more of the layout structure coverage on the sample (e.g., based on the number of layout structures in the resist pattern design, the ratio of acceptable to unacceptable layout structures, etc.).

[0077]

[0083] In some embodiments, the system may output LFPs used during the examination as a list of coordinates on the sample. In some embodiments, LFPs may be ranked and determined based on predetermined preferences. For example, the resulting LFPs may be evenly distributed on the sample based on preferences for susceptibility to focus, robust LFPs, or unknown target points on the sample.

[0078]

[0084] A non-temporary computer-readable medium storing processor instructions for a controller (e.g., controller 109 in Figure 1) for controlling a processor (e.g., processors 322, 332, 342, or 352 in Figure 3) of an electron beam tool or other system and server may be provided, consistent with embodiments of the present disclosure. These instructions may enable one or more processors to perform tasks such as image processing, data processing, beamlet scanning, database management, graphical display, operation of a charged particle beam apparatus or another imaging device. In some embodiments, a non-temporary computer-readable medium storing processor instructions for performing steps of process 700 may be provided. Common forms of non-temporary media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes, or any other magnetic data recording media, compact disk read-only memory (CD-ROM), any other optical data storage media, any physical media having a pattern of holes, random-access memory (RAM), programmable read-only memory (PROM), and erasable programmable read-only memory (EPROM), FLASH-EPROM, or any other flash memory, non-volatile random-access memory (NVRAM), caches, registers, any other memory chips or cartridges, and networked versions of the aforementioned.

[0079]

[0085] Embodiments may be further described using the following clauses: 1. A system for determining random access memory points (LFPs), comprising a controller including a circuit, the circuit includes, Selecting a first multiple resist pattern design, The first involves performing multiple process simulations using multiple resist pattern designs, Based on the results of the executed process simulation, hot spots corresponding to the resist pattern design are identified, Identifying focus-related characteristics corresponding to multiple resist pattern design candidates, wherein the multiple resist pattern design candidates are subsets of a first set of resist pattern designs, and the subsets are selected based on identified hotspots. Determining the locations of multiple LFPs based on the generated focus-related characteristics, A system configured to perform a certain action. 2. Selecting multiple resist pattern designs is possible. The second step is to analyze multiple resist pattern designs, Grouping multiple second resist pattern designs by pattern type, The method involves sampling a resist pattern design from each group of a second set of resist pattern designs, wherein the selection of the first set of resist pattern designs is based on the sampled resist pattern designs. The system described in Clause 1, including the system described in Clause 1. 3. Each pattern type is a system as described in Clause 2, including the shape type of the resist pattern design. 4. Performing multiple process simulations is a system described in any one of clauses 1 to 3, which includes generating contour images based on a first set of multiple resist pattern designs. 5. The circuit is further configured to allow the system to receive a set of process variations, and multiple process simulations are performed based on the received set of process variations, and contour images show the effect of the set of process variations on the sample features corresponding to the first multiple resist pattern designs, as described in Clause 4. 6. The system described in Clause 5, wherein the set of process variations includes any data specifying multiple optical focus adjustments corresponding to a first plurality of resist pattern designs or data specifying multiple optical intensity adjustments corresponding to a first plurality of resist pattern designs. 7. A system described in any one of Clauses 1-6, which includes performing multiple process simulations using a resist model, lithography model, etching model, or scanning model. 8. The results of the process simulation performed shall include the dimensions of features on the sample corresponding to the first multiple resist pattern designs, as described in any one of the systems described in Clauses 1 to 7. 9. The system as described in Clause 8, further configured to cause the system to identify hotspots in features where the dimensions of the features are below a threshold. 10. A hotspot is a system described in any one of Clauses 1 to 9, which includes an area where there is a high probability of defects being present in a sample feature corresponding to any of the first multiple resist pattern designs. 11. Identifying focus-related characteristics corresponding to multiple resist pattern design candidates is a system described in any one of clauses 1 to 10, which includes generating simulated scanning electron microscope (SEM) images of sample features corresponding to multiple resist pattern design candidates. 12. The circuit is further configured to allow the system to receive image parameter variations for use in multiple simulations that simulate the effects of image parameter variations, and the simulated SEM images show the effects of image parameter variations on sample features corresponding to multiple resist pattern design candidates, as described in Clause 11. 13. The system as described in Clause 12, wherein the image parameter variation includes any of the following: data defining multiple electron beam focus adjustments corresponding to multiple resist pattern design candidates, shifts in image-related measurements, or parameters used by the photolithography system when determining the exposure settings for a sample to include features corresponding to multiple resist pattern design candidates. 14. A system as described in any one of Clauses 1 to 13, in which the identified focus-related characteristics include any of the following: resist pattern density, number of layout structures in the resist pattern design, ratio of acceptable to unacceptable layout structures, sidewall angles corresponding to the resist pattern design, ratio of acceptable to unacceptable sidewall angles, or charge effect. 15. A system described in any one of Clauses 1 to 14, in which determining multiple LFPs based on identified focus-related characteristics corresponds to multiple resist pattern design candidates, includes identifying locations on the sample that are more susceptible to the effects of electron beam focusing adjustments to those locations, and selecting a set of identified locations as LFPs. 16. A method for determining a local focus (LFP) on a sample, Selecting a first multiple resist pattern design, The first involves performing multiple process simulations using multiple resist pattern designs, Based on the results of the executed process simulation, hot spots corresponding to the resist pattern design are identified, Identifying focus-related characteristics corresponding to multiple resist pattern design candidates, wherein the multiple resist pattern design candidates are subsets of a first set of resist pattern designs, and the subsets are selected based on identified hotspots. Determining the locations of multiple LFPs based on the generated focus-related characteristics, Methods that include... 17. The method according to Clause 16, wherein the selection of multiple resist pattern designs comprises analyzing a second set of resist pattern designs, grouping the second set of resist pattern designs by pattern type, and sampling a resist pattern design from each group of the second set of resist pattern designs, the selection of the first set of resist pattern designs comprising sampling based on the sampled resist pattern designs. 18. Each pattern type is as described in Clause 17, including the shape type of the resist pattern design. 19. Performing multiple process simulations is the method according to any one of the provisions of clauses 16 to 18, which includes generating contour images based on a first set of multiple resist pattern designs. 20. The method according to Clause 19, further comprising receiving a set of process variations, wherein multiple process simulations are performed based on the received set of process variations, and contour plots show the effect of the set of process variations on the sample features corresponding to the first multiple resist pattern designs. 21. The method according to Clause 20, wherein the set of process variations includes any data specifying multiple optical focus adjustments corresponding to a first plurality of resist pattern designs or data specifying multiple optical intensity adjustments corresponding to a first plurality of resist pattern designs. 22. Performing multiple process simulations is the method described in any one of the clauses 16-21, which includes using a resist model, a lithography model, an etching model, or a scanning model. 23. The results of the process simulation performed are as described in any one of clauses 16 to 22, including the dimensions of features on the sample corresponding to the first multiple resist pattern designs. 24. The method of the clause 23, further comprising identifying hotspots in features whose dimensions are below a threshold. 25. The method according to any one of the clauses 16 to 24, wherein a hotspot includes an area where there is a high probability of a defect being present in a sample feature corresponding to any of the first multiple resist pattern designs. 26. Identifying focus-related characteristics corresponding to multiple resist pattern design candidates, the method according to any one of clauses 16 to 25, comprising generating simulated scanning electron microscope (SEM) images of sample features corresponding to multiple resist pattern design candidates. 27. The method according to Clause 26, further comprising receiving image parameter variations to be used in multiple simulations to simulate the effects of image parameter variations, wherein the simulated SEM images show the effects of image parameter variations on sample features corresponding to multiple resist pattern designs. 28. The method according to Clause 27, wherein the image parameter variation includes any of the following: data defining multiple electron beam focus adjustments corresponding to multiple resist pattern design candidates, shifts in image-related measurements, or parameters used by the photolithography system when determining the exposure settings for a sample to include features corresponding to multiple resist pattern design candidates. 29. The method according to any one of Clauses 16 to 28, wherein the identified focus-related characteristics include any of the following: resist pattern density, number of layout structures in the resist pattern design, ratio of acceptable to unacceptable layout structures, sidewall angles corresponding to the resist pattern design, ratio of acceptable to unacceptable sidewall angles, or charge effect. 30. The method according to any one of Clauses 16 to 29, wherein determining multiple LFPs based on identified focus-related characteristics corresponds to multiple resist pattern design candidates and includes identifying locations on the sample that are more susceptible to the effects of electron beam focusing adjustments to those locations, and selecting a set of identified locations as LFPs. 31. A non-temporary computer-readable medium that is executable by at least one processor of a computing device and stores a set of instructions causing the computing device to execute a method for determining local foci (LFPs) on a sample, the method comprising: selecting a first plurality of resist pattern designs; performing a plurality of process simulations using the first plurality of resist pattern designs; identifying hotspots corresponding to the resist pattern designs based on the results of the performed process simulations; identifying focus-related properties corresponding to a plurality of candidate resist pattern designs, the plurality of candidate resist pattern designs being subsets of the first plurality of resist pattern designs, the subsets being selected based on the identified hotspots; and determining the locations of the plurality of LFPs based on the generated focus-related properties. 32. An instruction set that can be executed by at least one processor of a computing device, thereby causing the computing device to perform the following actions: analyzing a second plurality of resist pattern designs; grouping the second plurality of resist pattern designs by pattern type; and sampling a resist pattern design from each group of the second plurality of resist pattern designs, wherein the selection of the first plurality of resist pattern designs is based on the sampled resist pattern designs; and further performing sampling; a non-temporary computer-readable medium as described in Clause 31. 33. Each pattern type is a non-transient computer-readable medium as defined in Clause 32, including the shape type of the resist pattern design. 34. Performing multiple process simulations, including generating contour images based on a first multiple resist pattern design, in a non-temporary computer-readable medium as described in any one of clauses 31 to 33. 35. A non-transient computer-readable medium as described in Clause 34, which is executable by at least one processor of a computing device and thereby causes the computing device to further perform the task of receiving a set of process variations, a set of process simulations based on the received set of process variations, and contour images showing the effect of the set of process variations on the features of a sample corresponding to a first set of resist pattern designs. 36. A set of process variations, including any data specifying multiple optical focus adjustments corresponding to a first plurality of resist pattern designs or data specifying multiple optical intensity adjustments corresponding to a first plurality of resist pattern designs, in a non-temporary computer-readable medium as described in Clause 35. 37. Performing multiple process simulations, including using any of the resist models, lithography models, etching models, or scanning models, in a non-temporary computer-readable medium as described in any one of Clauses 31-36. 38. The results of the performed process simulation, including the dimensions of features on the sample corresponding to the first multiple resist pattern designs, are provided in a non-temporary computer-readable medium as described in any one of clauses 31 to 37. 39. An instruction set executable by at least one processor of a computing device, thereby causing the computing device to further perform the task of identifying hotspots in features whose dimensions are below a threshold, as described in Clause 38, in a non-temporary computer-readable medium. 40. A hotspot is a non-transient computer-readable medium as described in any one of the first multiple resist pattern designs, which includes an area of ​​high probability of a defect existing in a sample feature corresponding to any of the first multiple resist pattern designs. 41. Identifying focus-related characteristics corresponding to multiple resist pattern design candidates includes generating simulated scanning electron microscope (SEM) images of sample features corresponding to multiple resist pattern design candidates, in a non-temporary computer-readable medium as described in any one of Clauses 31 to 40. 42. An instruction set executable by at least one processor of a computing device, thereby causing the computing device to further perform the task of receiving image parameter variations for use in multiple simulations that simulate the effects of image parameter variations, the simulated SEM image showing the effects of image parameter variations on sample features corresponding to multiple resist pattern designs, in a non-temporary computer-readable medium as described in Clause 41. 43. Non-temporary computer-readable media as described in Clause 42, including any of the following: image parameter variations, which include data defining multiple electron beam focus adjustments corresponding to multiple resist pattern design candidates, shifts in image-related measurements, or parameters used by the photolithography system when determining the exposure settings for a sample to include features corresponding to multiple resist pattern design candidates. 44. Non-transient computer-readable media as described in any one of Clauses 31 to 43, wherein the identified focus-related characteristics include any of the following: resist pattern density, number of layout structures in the resist pattern design, ratio of acceptable to unacceptable layout structures, sidewall angles corresponding to the resist pattern design, ratio of acceptable to unacceptable sidewall angles, or charge effects. 45. Determining multiple LFPs based on identified focus-related characteristics, including identifying locations on a sample that are more susceptible to the effects of electron beam focusing adjustments to those locations, and selecting a set of identified locations as LFPs, in a non-temporary computer-readable medium as described in any one of Clauses 31 to 44, corresponding to multiple resist pattern design candidates. 46. ​​A system described in any one of clauses 1 to 15, wherein each of the first resist pattern designs includes a layout structure to be developed on a sample. 47. The first multiple resist pattern designs are stored in a layout file in the system described in any one of clauses 1 to 15 or 46. 48. The method according to any one of the first multiple resist pattern designs, each of which includes a layout structure to be developed on a sample. 49. The first multiple resist pattern designs are stored in a layout file, as described in any one of the methods of clauses 16-30 or 48. 50. Each of the first multiple resist pattern designs includes a layout structure to be developed on a sample, on a non-temporary computer-readable medium as described in any one of clauses 31 to 45. 51. The first multiple resist pattern designs are stored in a layout file on a non-temporary computer-readable medium as described in any one of clauses 31-45 or 50. 52. Identifying a hotspot includes identifying multiple hotspots, as described in any one of the systems in Clauses 1-15, 46, or 47. 53. A subset is a system as described in any one of clauses 1-15, 46, 47, or 52, selected so that the subset contains a limited number of hotspots. 54. Identifying a hotspot is the method described in any one of the clauses 16-30, 48, or 49, including identifying multiple hotspots. 55. A subset is selected such that the subset contains a limited number of hotspots, as described in any one of clauses 16-30, 48, 49, or 54. 56. Identifying a hotspot includes identifying multiple hotspots, as described in any one of Clauses 31-45, 50, or 51, on a non-temporary computer-readable medium. 57. A subset is a non-temporary computer-readable medium as described in any one of clauses 31-45, 50, 51, or 56, selected so that the subset contains a limited number of hotspots. 58. A resist pattern design in which hot spots are identified is a system described in any one of clauses 1-15, 46, 47, 52, or 53, which includes multiple resist pattern designs. 59. The method according to any one of the clauses 16-30, 48, 49, 54, or 55, wherein identifying hotspots corresponding to a resist pattern design includes identifying multiple hotspots corresponding to a resist pattern design, and identifying multiple hotspots corresponding to a resist pattern design includes identifying multiple hotspots corresponding to multiple resist pattern designs. 60. A hotspot that includes an area where the likelihood of a defect being present in a feature is higher is a system as described in Clause 10, which includes an area where the likelihood of a defect being present in a feature is above a threshold.

[0080]

[0086] The embodiments of this disclosure are not limited to those described above and illustrated in the accompanying drawings, and it will be understood that various modifications and changes can be made without departing from the scope of the present invention.

Claims

1. A system for determining the local focal point (LFP) on a sample, Includes a controller that includes a circuit, The circuit is configured in the system. Selecting a first multiple resist pattern design, Performing multiple process simulations using the first multiple resist pattern designs, Based on the results of the process simulation performed, hot spots corresponding to the resist pattern design are identified, Identifying focus-related characteristics corresponding to multiple resist pattern design candidates, The plurality of candidate resist pattern designs are a subset of the first plurality of resist pattern designs, and the subset is selected and identified based on the identified hotspots. Determining the locations of multiple LFPs based on the identified focus-related characteristics, A system configured to perform a certain action.

2. Selecting the aforementioned multiple resist pattern designs means The second step is to analyze multiple resist pattern designs, The second plurality of resist pattern designs are grouped by pattern type, The process involves sampling a resist pattern design from each group of the second plurality of resist pattern designs, wherein the selection of the first plurality of resist pattern designs is based on the sampled resist pattern designs. The system according to claim 1, including the following:

3. The system according to claim 1, wherein performing the plurality of process simulations includes generating contour images based on the first plurality of resist pattern designs.

4. The circuit is configured in the system. It is further configured to receive a set of process variations, and the multiple process simulations are based on the received set of process variations. The system according to claim 3, wherein the contour images show the effect of the set of process variations on the features of the sample corresponding to the first plurality of resist pattern designs.

5. The system according to claim 4, wherein the set of process variations includes arbitrary data defining a plurality of optical focus adjustments corresponding to the first plurality of resist pattern designs or data defining a plurality of optical intensity adjustments corresponding to the first plurality of resist pattern designs.

6. The system according to claim 1, wherein performing the aforementioned multiple process simulations includes using any of a resist model, a lithography model, an etching model, or a scanning model.

7. The system according to claim 1, wherein the results of the process simulation performed include dimensions of features on the sample corresponding to the first plurality of resist pattern designs.

8. The circuit is configured in the system. The system according to claim 7, further configured to identify hotspots in features where the dimensions of the features are below a threshold.

9. The system according to claim 1, wherein the hotspot includes an area where there is a high probability that a defect exists in a feature of the sample corresponding to any of the first plurality of resist pattern designs.

10. The system according to claim 1, wherein identifying focus-related characteristics corresponding to the plurality of resist pattern design candidates includes generating simulated scanning electron microscope (SEM) images of the sample features corresponding to the plurality of resist pattern design candidates.

11. The circuit is configured in the system. It is further configured to receive the image parameter variations used in multiple simulations that simulate the effects of image parameter variations, The system according to claim 10, wherein the simulated SEM image shows the effect of the image parameter variation on the features of the sample corresponding to the plurality of resist pattern design candidates.

12. The system according to claim 11, wherein the image parameter variation includes any of the following: data defining a plurality of electron beam focus adjustments corresponding to the plurality of resist pattern design candidates, a shift in image-related measurements, or parameters used by the photolithography system when determining the exposure settings for a sample to include features corresponding to the plurality of resist pattern design candidates.

13. The system according to claim 1, wherein the identified focus-related characteristics include any of the following: resist pattern density, number of layout structures in the resist pattern design, ratio of acceptable to unacceptable layout structures, sidewall angle corresponding to the resist pattern design, ratio of acceptable to unacceptable sidewall angles, or charge effect.

14. Determining the plurality of LFPs based on the identified focus-related characteristics is To identify locations on the sample that are more susceptible to the effects of electron beam focus adjustment, corresponding to the multiple candidate resist pattern designs, Selecting the aforementioned set of identified locations as the LFP, The system according to claim 1, including the following:

15. A non-temporary computer-readable medium that stores an instruction set that is executable by at least one processor of a computing device, thereby causing the computing device to execute a method for determining a local focus (LFP) on a sample, wherein the method is Selecting a first multiple resist pattern design, Performing multiple process simulations using the first multiple resist pattern designs, Based on the results of the process simulation performed, hot spots corresponding to the resist pattern design are identified, Identifying focus-related characteristics corresponding to multiple resist pattern design candidates, wherein the multiple resist pattern design candidates are a subset of the first multiple resist pattern designs, and the subset is selected based on the identified hotspots. A non-temporary computer-readable medium, comprising determining the locations of multiple LFPs based on the identified focus-related characteristics.

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