Methods for providing feedback on channel information, electronic devices, and computer-readable media.

Abstract

The present disclosure provides a method for feedback of channel information, including: determining a target basis vector, the target basis vector being a basis vector conforming to a vector construction rule, determining vector row identification bits, determining an extension vector based on the target basis vector and the vector row identification bits, constructing a codebook based on the extension vector, and performing channel information feedback using the codebook. The present disclosure further provides an electronic device and a computer-readable medium.

Description

[Technical Field]

[0001] The present disclosure relates to the technical field of channel information feedback, and in particular, to a method for feeding back channel information, an electronic device, and a computer-readable medium. [Background Art]

[0002] Distributed Multiple-Input Multiple-Output (Distributed MIMO) and Cell-Free Massive Multiple-Input Multiple-Output (CF-mMIMO) have attracted increasing attention as potential key technologies in the research direction of B5G / 6G (Beyond Fifth Generation Mobile Communication Technology / Sixth Generation Mobile Communication Technology) multi-antennas. One of the prominent features of this technology is that the spatial distribution of Access Points (APs) in a given area is more dispersed than that of centralized APs used in current New Radio (NR, fifth generation mobile communication technology), the number of APs is also relatively large, and multiple APs simultaneously provide services for multiple User Equipments (UEs).

[0003] However, in many cases, related technologies cannot meet the requirements for feeding back channel information. [Summary of Invention]

[0004] The present disclosure provides a method for feeding back channel information, an electronic device, and a computer-readable medium.

[0005] In a first aspect, embodiments of the present disclosure provide: determining a target basis vector that is a basis vector conforming to a vector construction rule; determining a vector row identification bit; Determining the extended vector based on the target basis vector and the vector row identification bit, Constructing a codebook based on the aforementioned extension vector, The present invention provides a method for providing feedback on channel information, which includes providing channel information feedback using the aforementioned codebook.

[0006] In some embodiments, before determining the target basis vector, the basis vector set is determined based on the vector construction rule, and the basis vector set includes at least one basis vector. Determining the target basis vectors includes selecting basis vectors from the set of basis vectors to be the target basis vectors.

[0007] In some embodiments, the vector construction rule is: This includes information about the dimensions of the basis vectors, the generation rules for the basis vectors, and the number of basis vectors in the basis vector set.

[0008] In some embodiments, the vector row identification bit is It includes at least one of the basis vector row identification bits and the extended vector row identification bits.

[0009] In some embodiments, the basis vector row identification bit displays the index of the row of the selected target basis vector, The aforementioned extended vector row identification bit displays the index of the selected extended vector row.

[0010] In some embodiments, determining the vector row identification bit is Determining the basis vector row identification bits based on bitmap signaling, Or, This includes determining the basis vector row identification bits based on a basis vector row identification bit variable and a basis vector row identification bit mapping function.

[0011] In some embodiments, the basis vector row identification bit mapping function is determined based on the vector construction rule. Or, The basis vector row-identification bit mapping function is configured by the base station.

[0012] In some embodiments, the basis vector row identification bit variable consists of one or more distinct elements, the elements being integers, and the integers of the distinct elements being consecutive or discontinuous.

[0013] In some embodiments, determining the basis vector row identification bit based on the basis vector row identification bit variable and the basis vector row identification bit mapping function is: Determining the basis vector row identification bits based on a group of basis vector row identification bit variables and a basis vector row identification bit mapping function, Determining the basis vector row identification bits based on a group of basis vector row identification bit variables and a plurality of different basis vector row identification bit mapping functions, Determining the basis vector row identification bits based on multiple groups of different basis vector row identification bit variables and one basis vector row identification bit mapping function, This includes any one of the following: determining the basis vector row identification bits based on multiple groups of different basis vector row identification bit variables and multiple different basis vector row identification bit mapping functions.

[0014] In some embodiments, the extended vector row identification bits are determined based on bitmap signaling. Or, The extended vector row identification bit is determined based on the extended vector row identification bit variable and the extended vector row identification bit mapping function.

[0015] In some embodiments, the extended vector row identification bit mapping function is determined by the vector construction rule. Or, The aforementioned extended vector row identification bit mapping function is deployed by the base station.

[0016] In some embodiments, the extended vector row identification bit variable consists of one or more distinct elements, the elements being integers, and the integers of the distinct elements being consecutive or discontinuous.

[0017] In some embodiments, determining the extended vector row identification bit based on the extended vector row identification bit variable and the extended vector row identification bit mapping function is: Determining the extended vector row identification bits based on one group of extended vector row identification bit variables and one extended vector row identification bit mapping function, Determining the extended vector row identification bits based on a group of extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions, Determining the extended vector row identification bit based on multiple groups of different extended vector row identification bit variables and one extended vector row identification bit mapping function, This includes any one of the following: determining the extended vector row identification bit based on multiple groups of different extended vector row identification bit variables and multiple different extended vector row identification bit mapping functions.

[0018] In some embodiments, determining the extended vector based on the target basis vector and the vector row identification bit is: The extension vector is determined based on the target basis vector, basis vector row identification bits, and basis vector row identification bit type, and the vector row identification bits include basis vector row identification bits. Or, determining an extended vector based on said target basis vector, basis vector row identification bit, basis vector row identification bit type, extended vector row identification bit, and extended vector row identification bit type, wherein said vector row identification bit includes said basis vector row identification bit and extended vector row identification bit.

[0019] In some embodiments, said determining an extended vector based on said target basis vector, basis vector row identification bit, and basis vector row identification bit type comprises: if said basis vector row identification bit type is a zero-setting type, zeroing elements of rows of said target basis vector corresponding to said basis vector row identification bit based on said target basis vector and said basis vector row identification bit to obtain an extended vector; and if said basis vector row identification bit type is a non-zero-setting type, zeroing elements of rows of said target basis vector not corresponding to said basis vector row identification bit based on said target basis vector and said basis vector row identification bit to obtain an extended vector.

[0020] In some embodiments, said determining an extended vector based on said target basis vector, basis vector row identification bit, basis vector row identification bit type, extended vector row identification bit, and extended vector row identification bit type comprises: if said basis vector row identification bit type is a zero-setting type and said extended vector row identification bit type is a zero-setting type, zeroing elements of rows of said target basis vector corresponding to said basis vector row identification bit to obtain a first vector, and zeroing elements of rows of said first vector corresponding to said extended vector row identification bit to obtain an extended vector; and if said basis vector row identification bit type is a zero-setting type and said extended vector row identification bit type is a non-zero-setting type, zeroing elements of rows of said target basis vector corresponding to said basis vector row identification bit to obtain a first vector, and zeroing elements of rows of said first vector not corresponding to said extended vector row identification bit to obtain an extended vector; If the base vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a zero setting type, then the elements of the rows of the target base vector that do not correspond to the base vector row identification bits are set to zero to obtain a second vector, and the elements of the rows of the second vector that correspond to the extended vector row identification bits are set to zero to obtain an extended vector. If the basis vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a non-zero setting type, the elements of the rows of the target basis vector that do not correspond to the basis vector row identification bits are set to zero to obtain a second vector, and the elements of the rows of the second vector that do not correspond to the extended vector row identification bits are set to zero to obtain an extended vector.

[0021] In some embodiments, the vector row identification bits can be dynamically adjusted over time.

[0022] In a second aspect, an embodiment of the present disclosure provides an electronic device comprising one or more memories and one or more processors, wherein the memories store a computer program to be executed by the processors, and when the computer program is executed by the processors, a method is provided for feeding back any one of the channel information in the embodiment of the present disclosure.

[0023] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored and which provides a method for feeding back any one of the channel information in the embodiment of the present disclosure when the computer program is executed by a processor.

[0024] In the embodiments of this disclosure, an extended vector is determined first based on a basis vector and a vector row identification bit, and then a codebook for channel information feedback is determined based on the extended vector. As a result, the codebook better conforms to the current channel information feedback requirements, enabling better channel information feedback and further improving communication quality. [Brief explanation of the drawing]

[0025] [Figure 1] Figure 1 is a flowchart of a method for feeding back channel information provided by an embodiment of the present disclosure. [Figure 2] Figure 2 is a flowchart of another method for feeding back channel information, as provided by an embodiment of the present disclosure. [Figure 3] Figure 3 is a block diagram of the configuration of an electronic device provided by an embodiment of the present disclosure. [Figure 4] Figure 4 is a block diagram of the configuration of a computer-readable medium provided by an embodiment of the present disclosure. [Modes for carrying out the invention]

[0026] To enable those skilled in the art to better understand the technical proposals of this disclosure, the methods for feeding back channel information, electronic devices, and computer-readable media provided by the embodiments of this disclosure will be described in detail below with reference to the drawings.

[0027] The present disclosure will be described in more detail below with reference to the drawings, but the embodiments presented may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments described below. Rather, these embodiments are provided to make the present disclosure thorough and complete, and to allow those skilled in the art to fully understand the scope of the present disclosure.

[0028] The drawings of the embodiments of this disclosure are provided to provide a further understanding of the embodiments of this disclosure, constitute part of the specification, and are used in conjunction with the detailed embodiments to interpret this disclosure, but do not constitute a limitation to this disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the drawings.

[0029] This disclosure can be described with reference to plan views and / or section views, with the help of the ideal schematic drawings of this disclosure. Accordingly, the examples and illustrations may be modified based on manufacturing technology and / or tolerances.

[0030] Each embodiment and each feature in the embodiment of this disclosure can be combined with one another, provided they do not contradict each other.

[0031] The terms used in this disclosure are for illustrative purposes only to describe specific embodiments and are not intended to limit this disclosure. The term “and / or” used in this disclosure includes any and all combinations of one or more related enumerations. The singular forms “one” and “the said” used in this disclosure are also intended to include the plural form unless otherwise clearly stated in the surrounding sentences. The terms “including” and “consisting of” used in this disclosure refer to the presence of the aforementioned features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0032] All terms used in this disclosure (including technical and scientific terms) shall have the same meaning as those generally understood by those skilled in the art, unless otherwise specified. Furthermore, such terms, as defined in common dictionaries, shall have the meaning consistent with their meaning in the context of the relevant technical invention and this disclosure, and shall not be interpreted as having an ideal or overly formal meaning unless explicitly defined so in this disclosure.

[0033] This disclosure is not limited to the embodiments shown in the drawings and includes modifications to the arrangement of configurations formed based on the manufacturing process. Accordingly, the areas illustrated in the drawings have illustrative attributes, and the shapes of the areas shown in the drawings illustrate, but are not intended to limit, the specific shapes of the areas of the elements.

[0034] In potential future application scenarios for CF-mMIMO, such as large gymnasiums, shopping malls, airports, and automated factories, the spatial distribution of UEs (Unified Element Users) is extremely complex. Some areas will have a high density and number of UEs, while others will have a low density and number, and still others will have an ideal balance of density and number. This will result in service requirements varying depending on the spatial location.

[0035] Therefore, under the circumstances described above, the channel situation becomes more complex, and related technologies find it difficult to meet the requirements for channel information feedback under these circumstances, which will affect communication quality.

[0036] In a first aspect, embodiments of the present disclosure provide a method for feeding back channel information.

[0037] The method of the embodiment of this disclosure is for a communication device (e.g., AP, UE, base station, etc.) to feed back information about the corresponding communication channel to the other party. Specifically, it involves first determining a feedback codebook for channel information feedback based on the current situation, and then feeding back the channel information based on the codebook.

[0038] Referring to Figure 1, the method for feeding back channel information in the embodiment of this disclosure includes the following steps:

[0039] S101: Determine the target basis vector. Here, the target basis vectors are basis vectors that conform to the vector construction rules.

[0040] S102: Determine the vector row identification bits. S103: Determine the extended vector based on the target basis vector and the vector row identification bit.

[0041] S104: Structure the codebook based on extended vectors. S105: Use the codebook to provide channel information feedback.

[0042] In the embodiments of this disclosure, first, one or more basis vectors (vectors) that conform to the requirements (vector construction rules) are determined as target basis vectors, vector row identification bits are determined, and an extended vector is obtained from the target basis vector based on the vector row identification bits (the specific method will be described later). Subsequently, a codebook is established based on the extended vector, and channel information feedback can be performed using the codebook.

[0043] Note that the numbering order and description order of steps S101 and S102 above do not indicate a necessary execution order for both; rather, it should be understood that it is sufficient as long as the target basis vector and vector row identification bits can be obtained before determining the extended vector.

[0044] In some embodiments, the vector row identification bits can be dynamically adjusted over time. In the embodiments of this disclosure, the vector row identification bit is determined according to the specific circumstances at the time of execution of the step. Therefore, if the execution process is different, the vector row identification bit may be different. In other words, the vector row identification bit may be dynamically adjusted over time, and the corresponding extended vectors and codebooks may also be different. Thus, the codebooks obtained in the embodiments of this disclosure are "adaptive" to the circumstances at the time they are obtained.

[0045] In the embodiments of this disclosure, an extended vector is determined first based on a basis vector and a vector row identification bit, and then a codebook for channel information feedback is determined based on the extended vector. As a result, the codebook better conforms to the current channel information feedback requirements, enabling better channel information feedback and further improving communication quality.

[0046] Here, there are various specific ways to construct a codebook based on vectors (extended vectors).

[0047]

number

[0048] In some embodiments, referring to Figure 2, the following steps are further included before determining the target basis vector (S101).

[0049] S100: Determine the basis vector set based on the vector construction rules. Here, the basis vector set contains at least one basis vector.

[0050] Determining the target basis vector (S101) involves the following steps: S1001: Select a basis vector from the basis vector set and use it as the target basis vector.

[0051] In embodiments of this disclosure, a vector construction rule, i.e., a rule for how to select a target basis vector, is established first, and then a basis vector set is constructed based on the vector construction rule, which may include one basis vector or multiple different basis vectors. Subsequently, when determining the target basis vector, a basis vector can be selected from the basis vector set to be the target basis vector.

[0052] In some embodiments, the vector construction rule includes information about the dimensions of the basis vectors, information about the generation rules for the basis vectors, and information about the number of basis vectors in the basis vector set.

[0053] In one embodiment of the present disclosure, the above vector construction rules may include information on the dimensions of the basis vectors (defining the dimensions of the basis vectors), information on the generation rules of the basis vectors (defining how the basis vectors should be generated), and information on the number of basis vectors in the basis vector set (defining how many basis vectors should be added to the basis vector set).

[0054] Here, the basis vectors can be N*1 vectors (where N is an integer greater than 1), that is, a vector with one row of N.

[0055] The basis vectors are, specifically, Constructed directly from a single DFT (Discrete Fourier Transform) vector, Obtained after weighting the elements of each row of a single DFT vector, This is obtained by calculating the Kronecker product for two DFT vectors. This is obtained by performing the Kronecker product calculation on two DFT vectors with weighted rows. It can be generated using one of the following methods.

[0056] In some embodiments, the vector row identification bit is It includes at least one of the basis vector row identification bits and the extended vector row identification bits.

[0057] In one embodiment of the present disclosure, the vector row identification bit may include a vector row identification bit for a basis vector, and may also include an extended vector row identification bit for an extended vector.

[0058] In some embodiments, the basis vector row identification bit displays the index of the row of the selected target basis vector, The extended vector row identification bit displays the index of the row in the selected extended vector.

[0059] In one embodiment of the embodiments of this disclosure, a vector row identification bit can characterize which "index" has been selected in the corresponding row of the vector.

[0060] In some embodiments, determining the vector row identification bit is Determining the row identification bits of a basis vector based on bitmap signaling. Or, This includes determining the basis vector row identification bits based on the basis vector row identification bit variables and the basis vector row identification bit mapping function.

[0061] In some embodiments, determining the vector row identification bit is Determining extended vector row identification bits based on bitmap signaling, Or, This includes determining the extended vector row identification bit based on the extended vector row identification bit variable and the extended vector row identification bit mapping function.

[0062] In one embodiment of the present disclosure, it is possible to determine the base vector row identification bits and the extended vector row identification bits by bitmap signaling.

[0063] For example, the number of bits in a bitmap may correspond to the number of rows in the basis vector, and the possible values ​​of each bit indicate whether or not the corresponding row has been selected.

[0064] For example, setting a bit to 1 indicates that the row of the basis vector corresponding to that bit has been selected, and setting a bit to 0 indicates that the row of the basis vector corresponding to that bit has been selected.

[0065] For example, suppose the basis vector is an 8*1 vector, and we want to select the 2nd and 5th rows of the basis vector.

[0066] Then, when determining the basis vector row identification bits based on the bitmap signaling, if the rule is that setting the value of a bit to 1 indicates that the corresponding basis vector row has been selected, then the bitmap signaling is 00010010, of which the 2nd and 5th bits can take values ​​of 1, and the remaining bits can take values ​​of 0. If the rule is that setting the value of a bit to 0 indicates that the corresponding basis vector row has been selected, then the bitmap signaling is 11101101, of which the 2nd and 5th bits can take values ​​of 0, and the remaining bits can take values ​​of 1.

[0067] For example, suppose the basis vector is an 8*1 vector, and we want to select the 3rd, 6th, and 7th rows of the basis vector.

[0068] Then, when determining the row identification bit of an extended vector based on bitmap signaling, if the rule is that setting the value of a bit to 1 indicates that the row of the extended vector corresponding to that bit has been selected, then the bitmap signaling is 01100100, of which the possible values ​​of the 3rd, 6th, and 7th bits are 1, and the possible values ​​of the remaining bits are 0. If the rule is that setting the value of a bit to 0 indicates that the row of the extended vector corresponding to that bit has been selected, then the bitmap signaling is 10011011, of which the possible values ​​of the 3rd, 6th, and 7th bits are 0, and the possible values ​​of the remaining bits are 1.

[0069] Alternatively, in another embodiment of the present disclosure, the basis vector row identification bits can be determined based on a basis vector row identification bit variable and a basis vector row identification bit mapping function, or the extended vector row identification bits can be determined based on an extended vector row identification bit variable and an extended vector row identification bit mapping function.

[0070] Specifically, we may define a basis / extension vector (representing either a basis vector or an extension vector, and the same applies hereafter) row-identification bit mapping function f(i), where i is the basis / extension vector row-identification bit variable, and the result of executing f(i) represents the basis / extension vector row-identification bits.

[0071] In some embodiments, the basis vector row identification bit variable consists of one or more distinct elements, where the elements are integers, and the integers of the distinct elements are either consecutive or discontinuous.

[0072] In some embodiments, the extended vector row identification bit variable consists of one or more distinct elements, where the elements are integers, and the integers of the distinct elements are either consecutive or discontinuous.

[0073] In one embodiment of the embodiments of this disclosure, the base / extension vector row identification bit variable may be one integer or multiple integers, specifically determined based on the row of choice.

[0074] Given multiple integers, they may be consecutive (i.e., form a continuous map), or they may be discontinuous (i.e., form a discontinuous map).

[0075] For example, if we assume that the basis vector is an 8*1 vector and we want to select the 2nd and 5th rows of the basis vector, we can define a basis vector row-identification bit mapping function f(i) = i and a basis vector row-identification bit variable i = {2, 5}. Alternatively, we can define a basis vector row-identification bit mapping function f(i) = i+1 and a basis vector row-identification bit variable i = {1, 4}.

[0076] For example, if we assume that the extended vector is an 8*1 vector and we want to select the 3rd, 4th, 5th, and 6th rows of the extended vector, we can define an extended vector row identification bit mapping function f(i) = i and an extended vector row identification bit variable i = {3, 4, 5, 6}. Alternatively, we can define an extended vector row identification bit mapping function f(i) = i + 2 and an extended vector row identification bit variable i = {1, 2, 3, 4}.

[0077] In some embodiments, the basis vector row-identification bit mapping function is determined based on the vector construction rule. Or, The basis vector row-identification bit mapping function is configured by the base station.

[0078] In some embodiments, the extended vector row-identification bit mapping function is determined by the vector construction rule. Or, The extended basis vector row-identification bit mapping function is configured by the base station.

[0079] In one embodiment of the embodiments of this disclosure, the basis / extended vector row identification bit mapping function may be determined by the above vector construction rules (rules for determining the basis vector set) and may be set by the base station (regardless of which side the method is performed on).

[0080] In some embodiments, determining the basis vector row identification bits based on the basis vector row identification bit variable and the basis vector row identification bit mapping function is, Determining the basis vector row-identity bits based on one group of basis vector row-identity bit variables and one basis vector row-identity bit mapping function, Determining the basis vector row identification bits based on one group of basis vector row identification bit variables and multiple different basis vector row identification bit mapping functions, Determining the basis vector row identification bits based on multiple sets of different basis vector row identification bit variables and one basis vector row identification bit mapping function. This includes any one of the following: determining the basis vector row identification bits based on multiple sets of different basis vector row identification bit variables and multiple different basis vector row identification bit mapping functions.

[0081] In some embodiments, determining the extended vector row identification bit based on the extended vector row identification bit variable and the extended vector row identification bit mapping function is, Determining the extended vector row identification bits based on one group of extended vector row identification bit variables and one extended vector row identification bit mapping function, Determining the extended vector row identification bit based on one group of extended vector row identification bit variables and multiple different extended vector row identification bit mapping functions, Determining the extended vector row identification bit based on multiple sets of different extended vector row identification bit variables and one extended vector row identification bit mapping function. This includes any one of the following: determining the extended vector row identification bit based on multiple sets of different extended vector row identification bit variables and multiple different extended vector row identification bit mapping functions.

[0082] In one embodiment of the present disclosure, when determining a basis / extended vector row identification bit based on a basis / extended vector row identification bit variable and a basis / extended vector row identification bit mapping function, the basis / extended vector row identification bit variable may consist of one or more groups, and the basis / extended vector row identification bit mapping function may consist of one or more groups.

[0083] Furthermore, multiple different combinations are possible based on the number of basis / extension vector row identification bit variables and basis / extension vector row identification bit mapping functions.

[0084] For example, if the basis vector is a 16*1 vector and we want to select the 2nd, 3rd, 4th, 5th, 8th, 9th, 10th, and 11th rows of the basis vector, we can define a basis vector row-identification bit mapping function f1(i)=i+1, f2(i)=i+7, and a basis vector row-identification bit variable i={1, 2, 3, 4}. Alternatively, we can define a basis vector row-identification bit mapping function f1(i)=i+1, f2(j)=j+2, and a basis vector row-identification bit variable i={1, 2, 3, 4}, j={6, 7, 8, 9}. Alternatively, we can define a basis vector row-identification bit mapping function f(i)=i, and a basis vector row-identification bit variable i={2, 3, 4, 5, 8, 9, 10, 11}.

[0085] For example, if we assume that the extended vector is a 16*1 vector and we want to select the 1st, 2nd, 9th, and 10th rows of the extended vector, we can define an extended vector row identification bit mapping function f1(i)=i, f2(i)=i+8, and an extended vector row identification bit variable i={1, 2}. Alternatively, we can define an extended vector row identification bit mapping function f1(i)=i+1, f2(j)=j*2+2, and an extended vector row identification bit variable i={0, 1, 8}, j={4}. Alternatively, we can define an extended vector row identification bit mapping function f(i)=i-1, and an extended vector row identification bit variable i={2, 3, 10, 11}.

[0086] In some embodiments, referring to Figure 2, determining the extended vector based on the target basis vector and the vector row identification bit (S103) includes the following steps:

[0087] S1031: Determine the extended vector based on the target basis vector, basis vector row identification bits, and basis vector row identification bit type.

[0088] Here, the vector row identification bits include the basis vector row identification bits. Or, S1032: Determine the extended vector based on the target basis vector, basis vector row identification bit, basis vector row identification bit type, extended vector row identification bit, and extended vector row identification bit type.

[0089] Here, the vector row identification bits include the base vector row identification bits and the extended vector row identification bits.

[0090] If the vector row identifier bits only contain basis vector row identifier bits, the target basis vector can be processed based on the basis vector row identifier bits and the basis vector row identifier bit type to obtain the extended vector.

[0091] If the vector row identification bits include both a base vector row identification bit and an extended vector row identification bit, the target base vector can be processed and the extended vector can be obtained based on the base vector row identification bit, the extended vector row identification bit and their types.

[0092] In some embodiments, determining the extended vector based on the target basis vector, basis vector row identification bits, and basis vector row identification bit type (S1031) includes the following steps:

[0093] S10311: If the basis vector row identification bit type is zero-setting type, the elements of the row of the target basis vector corresponding to the basis vector row identification bit are zero-set based on the target basis vector and the basis vector row identification bit, and the extended vector is obtained.

[0094] S10312: If the basis vector row identification bit type is a non-zero setting type, the elements of the rows of the target basis vector that do not correspond to the basis vector row identification bit are set to zero based on the target basis vector and the basis vector row identification bit, and the extended vector is obtained.

[0095] If the vector row identification bits consist only of basis vector row identification bits, and their type is set to zero, the elements of the row in the target basis vector corresponding to the basis vector row identification bits are set to zero, and the extended vector is obtained.

[0096] For example, if the target basis vector V0 is an 8*1 vector, and the basis vector row identification bits s={1,2,4}, and the basis vector row identification bit type is zero-setting, then the elements of the 1st, 2nd, and 4th rows of V0 are set to zero, and the elements of the other rows are kept as they are to obtain the extended vector V1, i.e., V1=P1*V0, P1=diag(0,0,1,0,1,1,1,1).

[0097] In response to this, if the type of the basis vector row identification bit is a non-zero type, the elements of the row in the target basis vector corresponding to the basis vector row identification bit are kept as they are, and the elements of the other rows that do not correspond to the basis vector row identification bit are set to zero to obtain the extended vector.

[0098] For example, if the target basis vector V0 is an 8*1 vector, and the basis vector row identification bits s={1,2,4}, and the basis vector row identification bit type is a non-zero setting type, then the 3rd, 5th, 6th, 7th, and 8th row elements of V0 are set to zero, and the elements of the other rows are kept as they are to obtain the extended vector V1, i.e., V1=P1*V0, P1=diag(1,1,0,1,0,0,0,0).

[0099] In some embodiments, determining the extended vector based on the target basis vector, basis vector row identification bit, basis vector row identification bit type, extended vector row identification bit, and extended vector row identification bit type (S1032) includes the following steps.

[0100] S10321: If the base vector row identification bit type is zero-setting type and the extended vector row identification bit type is zero-setting type, the elements of the row of the target base vector corresponding to the base vector row identification bit are set to zero to obtain the first vector, and the elements of the row of the first vector corresponding to the extended vector row identification bit are set to zero to obtain the extended vector.

[0101] S10322: If the base vector row identification bit type is a zero-setting type and the extended vector row identification bit type is a non-zero-setting type, the elements of the rows of the target base vector corresponding to the base vector row identification bits are set to zero to obtain the first vector, and the elements of the rows of the first vector that do not correspond to the extended vector row identification bits are set to zero to obtain the extended vector.

[0102] S10323: If the base vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a zero setting type, the elements of the target base vector rows that do not correspond to the base vector row identification bits are set to zero to obtain the second vector, and the elements of the rows of the second vector that correspond to the extended vector row identification bits are set to zero to obtain the extended vector.

[0103] S10324: If the base vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a non-zero setting type, the elements of the rows of the target base vector that do not correspond to the base vector row identification bits are set to zero to obtain the second vector, and the elements of the rows of the second vector that do not correspond to the extended vector row identification bits are set to zero to obtain the extended vector.

[0104] If the vector row identification bit includes both a base vector row identification bit and an extended vector row identification bit, first, based on whether the type of the base vector row identification bit is set to zero or not, the row in the target base vector corresponding to the base vector row identification bit, or other rows that do not correspond to the base vector row identification bit, is set to zero to obtain the first vector (obtained after setting the row corresponding to the base vector row identification bit to zero) or the second vector (obtained after setting the other rows that do not correspond to the base vector row identification bit to zero), which is then used as the intermediate vector.

[0105] Furthermore, based on whether the type of the extended vector row identification bit is set to zero or non-zero, the rows in the intermediate vector (first or second vector) corresponding to the extended vector row identification bit, or other rows that do not correspond to the extended vector row identification bit, can be set to zero to obtain the extended vector.

[0106] For example, if the target basis vector V0 is an 8*1 vector, the basis vector row identification bits s={1,2,4}, the basis vector row identification bit type is zero-setting type, and the extended vector row identification bits d={3}, the extended vector row identification bit type is zero-setting type, then first, based on V0, s, and the basis vector row identification bit type, the elements of the 1st, 2nd, and 4th rows of V0 are set to zero, and the elements of the other rows are left as they are to obtain the first vector T0, i.e., T0=P1*V0, P1=diag(0,0,1,0,1,1,1,1). Then, based on T0, d, and the extended vector row identification bit type, the element of the 3rd row of T0 is set to zero, and the elements of the other rows are left as they are to obtain the extended vector V1, i.e., V1=P2*T0, P2=diag(1,1,0,1,1,1,1,1).

[0107] Furthermore, if the target basis vector V0 is an 8*1 vector, the basis vector row identification bits s={1,2,4}, the basis vector row identification bit type is zero-setting type, and the extended vector row identification bits d={1,2,3,4,5}, the extended vector row identification bit type is non-zero-setting type, then first, based on V0, s, and the basis vector row identification bit type, the elements of the 1st, 2nd, and 4th rows of V0 are set to zero, and the elements of the other rows are left as they are to obtain the first vector T0, i.e., T0=P1*V0, P1=diag(0,0,1,0,1,1,1,1). Then, based on T0, d, and the extended vector row identification bit type, the elements of the 6th, 7th, and 8th rows of T0 are set to zero, and the elements of the other rows are left as they are to obtain the extended vector V1, i.e., V1=P2*T0, P2=diag(1,1,1,1,1,0,0,0).

[0108] Furthermore, for example, if the target basis vector V0 is a 12*1 vector, and the basis vector row identification bits s={1,2,3,4,7,11,12}, and the basis vector row identification bit type is a non-zero setting type, and the extended vector row identification bits d={2,5,7,11}, and the extended vector row identification bit type is a non-zero setting type, then first, based on V0, s, and the basis vector row identification bit type, we zero the 5th, 6th, 8th, 9th, and 10th row elements of V0, and leave the elements of the other rows as they are to obtain a second vector Q0, i.e., Q0=P1*V0, P1=diag(1,1,1,1,0,0,1,0,0,0,1,1). Then, based on Q0, d, and the extended vector row identification bit type, the 2nd, 5th, 7th, and 11th row elements of Q0 are set to zero, while the elements of the other rows remain unchanged to obtain the extended vector V1, i.e., V1 = P2 * Q0, P2 = diag(1,0,1,1,0,1,0,1,1,1,0,1).

[0109] Furthermore, for example, if the target basis vector V0 is a 16*1 vector, and the basis vector row identification bits s={2,3,4,5,6,7,8,9,10,11,12,13}, and the basis vector row identification bit type is a non-zero setting type, and the extended vector row identification bits d={1,2,4,8,12,13,14,15,16}, and the extended vector row identification bit type is a non-zero setting type, then first, based on V0, s, and the basis vector row identification bit type, we zero the elements of the first, 14, 15, and 16 rows of V0 and leave the elements of the other rows as they are to obtain a second vector Q0, i.e., Q0=P1*V0, P1=diag(0,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0). Then, based on Q0, d, and the extended vector row identification bit type, the 3rd, 5th, 6th, 7th, 9th, 10th, and 11th row elements of Q0 are set to zero, and the elements of the other rows are left as they are to obtain the extended vector V1, i.e., V1 = P2 * Q0, P2 = diag(1,1,0,1,0,0,0,1,0,0,0,1,1,1,1,1).

[0110] In a second aspect, referring to Figure 3, an embodiment of the present disclosure provides an electronic device comprising one or more memories and one or more processors, wherein the memories store a computer program executed by the processors, and when the computer program is executed by the processors, a method is provided for feeding back any one of the channel information in the embodiment of the present disclosure.

[0111] In a third aspect, referring to Figure 4, an embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored and which provides a method for feeding back any one of the channel information in the embodiment of the present disclosure when the computer program is executed by a processor.

[0112] In the embodiments of this disclosure, a processor is a device having data processing capabilities, and this includes, but is not limited to, a central processing unit (CPU). Memory is a device having data storage capabilities, and this includes, but is not limited to, random access memory (RAM; more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH). I / O interfaces (read / write interfaces) are connected between the processor and memory and enable information interaction between memory and the processor, and this includes, but is not limited to, data buses.

[0113] Those skilled in the art will understand that all or some of the functional modules / units among the steps, systems, and apparatus disclosed above may be performed as software, firmware, hardware, or a suitable combination thereof.

[0114] In hardware embodiments, the distinctions between functional modules / units mentioned above do not necessarily correspond to distinctions between physical components. For example, one physical component may have multiple functions, or one function or step may be performed by the cooperation of several physical components.

[0115] Some or all physical components may run as software executed by a processor such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or even as an integrated circuit such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-temporary media) and communication media (or temporary media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media that run in any way or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, random access memory (RAM; more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other magnetic disk memory, read-only optical disks (CD-ROM), digital multipurpose disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic memory, and any other media used to store desired information and accessible by a computer. In addition, it is known to those skilled in the art that communication media typically include computer-readable instructions, data structures, program modules, or other data within modulated data signals such as carrier waves or other carrier mechanisms, and may include any information distribution medium.

[0116] While examples and specific terminology have been disclosed in this disclosure, they are used only in a general descriptive sense and should be interpreted as such, and are not intended to be limiting. In some examples, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in combination with specific examples may be used alone or in combination with other features, characteristics, and / or elements described in combination with other examples, unless otherwise explicitly indicated. Accordingly, those skilled in the art will understand that various forms and details may be modified, as long as they do not deviate from the scope of this disclosure as revealed by the appended claims.

Claims

1. The process involves determining the target basis vectors, which are basis vectors that conform to the vector construction rules, Determining the vector row identification bit, Determining the extended vector based on the target basis vector and the vector row identification bit, Constructing a codebook based on the aforementioned extension vector, This includes providing Channel information feedback using the aforementioned codebook, Determining the aforementioned extension vector is The extension vector is determined based on the target basis vector, basis vector row identification bits, and basis vector row identification bit type, and the vector row identification bits include basis vector row identification bits. Or, The process includes determining an extended vector based on the target basis vector, basis vector row identification bits, basis vector row identification bit type, extended vector row identification bits, and extended vector row identification bit type, wherein the vector row identification bits include the basis vector row identification bits and extended vector row identification bits. How to provide feedback on channel information.

2. The method further includes determining a set of basis vectors based on the vector construction rules, prior to determining the target basis vectors, and ensuring that the set of basis vectors includes at least one basis vector. Determining the target basis vectors includes selecting basis vectors from the set of basis vectors to be the target basis vectors. The method according to claim 1.

3. The aforementioned vector construction rule is, This includes information on the dimensions of the basis vectors, the generation rules for the basis vectors, and the number of basis vectors in the basis vector set. The method according to claim 2.

4. The aforementioned vector row identification bit is, Includes at least one of the basis vector row identification bits and the extended vector row identification bits. The method according to claim 1.

5. The basis vector row identification bit displays the index of the row of the selected target basis vector. The aforementioned extended vector row identification bit displays the index of the selected extended vector row. The method according to claim 4.

6. Determining the aforementioned vector row identification bits means that Determining the basis vector row identification bits based on bitmap signaling, Or, This includes determining the basis vector row identification bits based on a basis vector row identification bit variable and a basis vector row identification bit mapping function. The method according to claim 4.

7. The basis vector row identification bit mapping function is determined based on the vector construction rule. Or, The basis vector row-identification bit mapping function is deployed by the base station. The method according to claim 6.

8. The basis vector row identification bit variable consists of one or more distinct elements, where the elements are integers, and the integers of the distinct elements are either consecutive or discontinuous. The method according to claim 6.

9. Determining the basis vector row identification bits based on the basis vector row identification bit variables and the basis vector row identification bit mapping function is: Determining the basis vector row identification bits based on one group of basis vector row identification bit variables and one basis vector row identification bit mapping function, Determining the basis vector row identification bits based on a group of basis vector row identification bit variables and a plurality of different basis vector row identification bit mapping functions, Determining the basis vector row identification bits based on multiple groups of different basis vector row identification bit variables and one basis vector row identification bit mapping function, This includes any one of the following: determining the basis vector row identification bits based on multiple groups of different basis vector row identification bit variables and multiple different basis vector row identification bit mapping functions. The method according to claim 6.

10. The extended vector row identification bits are determined based on bitmap signaling. Or, The extended vector row identification bit is determined based on the extended vector row identification bit variable and the extended vector row identification bit mapping function. The method according to claim 4.

11. The extended vector row identification bit mapping function is determined by the vector construction rule. Or, The aforementioned extended vector row discrimination bit mapping function is deployed by the base station. The method according to claim 10.

12. The extended vector row identification bit variable consists of one or more distinct elements, where the elements are integers, and the integers of the distinct elements are either consecutive or discontinuous. The method according to claim 10.

13. Determining the extended vector row identification bit based on the extended vector row identification bit variable and the extended vector row identification bit mapping function is: Determining the extended vector row identification bits based on one group of extended vector row identification bit variables and one extended vector row identification bit mapping function, Determining the extended vector row identification bit based on one group of extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions, Determining the extended vector row identification bit based on multiple groups of different extended vector row identification bit variables and one extended vector row identification bit mapping function, This includes any one of the following: determining the extended vector row identification bit based on multiple groups of different extended vector row identification bit variables and multiple different extended vector row identification bit mapping functions. The method according to claim 10.

14. Determining the extended vector based on the aforementioned target basis vector, basis vector row identification bit, and basis vector row identification bit type is: If the basis vector row identification bit type is a zero-setting type, then, based on the target basis vector and the basis vector row identification bit, the elements of the row of the target basis vector corresponding to the basis vector row identification bit are set to zero to obtain an extended vector. If the basis vector row identification bit type is a non-zero setting type, the process includes: zeroing out the elements of the rows of the target basis vector that do not correspond to the basis vector row identification bits, based on the target basis vector and the basis vector row identification bits, to obtain an extended vector. The method according to claim 1.

15. Determining the extended vector based on the aforementioned target basis vector, basis vector row identification bit, basis vector row identification bit type, extended vector row identification bit, and extended vector row identification bit type is: If the basis vector row identification bit type is a zero-setting type and the extended vector row identification bit type is a zero-setting type, then the elements of the row of the target basis vector corresponding to the basis vector row identification bit are set to zero to obtain a first vector, and the elements of the row of the first vector corresponding to the extended vector row identification bit are set to zero to obtain an extended vector. If the basis vector row identification bit type is a zero-setting type and the extended vector row identification bit type is a non-zero-setting type, then the elements of the rows of the target basis vector corresponding to the basis vector row identification bits are set to zero to obtain a first vector, and the elements of the rows of the first vector that do not correspond to the extended vector row identification bits are set to zero to obtain an extended vector. If the basis vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a zero setting type, then the elements of the rows of the target basis vector that do not correspond to the basis vector row identification bits are set to zero to obtain a second vector, and the elements of the rows of the second vector that correspond to the extended vector row identification bits are set to zero to obtain an extended vector. If the basis vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a non-zero setting type, the elements of the rows of the target basis vector that do not correspond to the basis vector row identification bits are set to zero to obtain a second vector, and the elements of the rows of the second vector that do not correspond to the extended vector row identification bits are set to zero to obtain an extended vector. The method according to claim 1.

16. The aforementioned vector row identification bits can be dynamically adjusted over time. The method according to claim 1.

17. The invention provides a method for feeding back channel information as described in any one of claims 1 to 16, comprising one or more memories and one or more processors, wherein the memories store computer programs executed by the processors, and when the computer programs are executed by the processors, the invention provides a method for feeding back channel information as described in any one of claims 1 to 16. Electronic devices.

18. A method for feeding back channel information according to any one of claims 1 to 16 is realized when a computer program is stored and the computer program is executed by a processor. Computer-readable media.

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